Magnetic tunnel junction device

Abstract

Embodiments of the invention provide a magnetic tunnel junction (MTJ) structure. The MTJ structure includes an MTJ stack including a tunnel barrier layer on a reference layer and a free layer on the tunnel barrier layer, where the free layer includes a plurality of sub-free layers, the plurality of sub-free layers being a plurality of ferromagnetic strips placed parallel to each other on the tunnel barrier layer, the plurality of ferromagnetic strips have respective first ends connected to the first electrode and respective second ends connected to the second electrode. A method of forming the MTJ structure is also provided.

Description

BACKGROUND OF THE INVENTION

[0001] This application relates to the manufacture of semiconductor integrated circuits. More specifically, the present invention relates to methods of forming magnetic tunnel junction devices and structures formed thereby.

[0002] Magnetic tunnel junction (MTJ) devices with programmable domain walls have been proposed for use in many advanced applications, such as, for example, analog artificial intelligence (AI) hardware. Generally, the weights of AI algorithms can be encoded into the conductance of MTJ devices. For example, by moving the position of a programmable domain wall in the free layer of an MTJ device, the conductance of the MTJ device can be tuned through a continuous range of conductance values.

[0003] However, in practice, moving the position of the domain wall is subject to significant variability. Depending on the size and shape of the free layer, as well as the variability of the external voltage applied to the device to adjust or move the domain wall, the position of the domain wall typically follows a statistical distribution with a standard deviation. In instances, it has been observed that the standard deviation of the domain wall position becomes so large that it hinders the ability to accurately program the MTJ device for any meaningful use or application. SUMMARY OF THE INVENTION

[0004] Embodiments of the present invention provide an MTJ structure. The MTJ structure includes an MTJ stack, and the MTJ stack includes a tunnel barrier layer over a reference layer and a free layer over the tunnel barrier layer, where the free layer includes a plurality of sub-free layers, the plurality of sub-free layers being a plurality of ferromagnetic strips placed parallel to each other over the tunnel barrier layer, the plurality of ferromagnetic strips having respective first ends connected to a first electrode and respective second ends connected to a second electrode. Using the plurality of sub-free layers of ferromagnetic strips reduces the statistical variation of the effective domain wall position of the free layer because the variation is reduced by an increase in the number of sub-free layers.

[0005] In one embodiment, the plurality of ferromagnetic strips are patterned to have notches formed along respective longitudinal directions of the plurality of ferromagnetic strips. In another embodiment, the notches of the plurality of ferromagnetic strips are substantially aligned with each other along the respective longitudinal directions. During operation of the MTJ structure, the notches increase the likelihood or certainty of the domain wall position by creating discrete positions where the domain wall position is more likely to be stable or in place.

[0006] In one embodiment, each of the plurality of ferromagnetic strips is covered by a spin-orbit coupling layer, the spin-orbit coupling layer being patterned to have the same shape as the ferromagnetic strip it covers. By using this spin-orbit coupling layer, the threshold current for driving the movement of the domain wall position is significantly reduced.

[0007] In another embodiment, the reference layer is a ferromagnetic layer that is perpendicularly overlapped with the plurality of sub-free layers via the tunnel barrier layer.

[0008] In one embodiment, the MTJ structure further includes a third electrode that contacts the reference layer at a substantially central position of the reference layer.

[0009] In another embodiment, multiple sub-free layers have respective domain wall positions defined by an applied voltage, where each domain wall position corresponds to a conductance value G having a standard deviation S1, and the free layer has an effective domain wall position defined by the applied voltage, the effective domain wall position corresponding to a G×N conductance value having a standard deviation of S2 = S1*sqrt(N), where N is the total number of sub-free layers. Clearly, using a larger number of sub-free layers results in a smaller standard deviation of the conductance.

[0010] Embodiments of the present invention provide a method of forming an MTJ structure. The method includes forming a capping tunnel barrier layer on top of a capping reference layer; forming a capping free layer on top of the capping tunnel barrier layer; patterning the capping free layer into a free layer having multiple sub-free layers, the multiple sub-free layers being multiple ferromagnetic stripes placed parallel to each other on top of the capping tunnel barrier layer; and forming a first electrode that contacts respective first ends of the multiple ferromagnetic stripes and a second electrode that contacts respective second ends of the multiple ferromagnetic stripes.

[0011] In one embodiment, patterning the capping free layer includes forming multiple ferromagnetic stripes having notches along respective longitudinal directions of the multiple ferromagnetic stripes. In another embodiment, the notches of the multiple ferromagnetic stripes are substantially aligned with each other along the respective longitudinal directions.

[0012] In another embodiment, the method further includes forming a capping spin-orbit coupling layer on top of the capping free layer, and patterning the capping free layer further includes patterning the capping spin-orbit coupling layer into multiple spin-orbit coupling stripes on top of the multiple ferromagnetic stripes.

[0013] In one embodiment, the method further includes, after patterning the capping free layer, patterning the capping tunnel barrier layer and the capping reference layer into a tunnel barrier layer and a reference layer, respectively.

[0014] In another embodiment, the method further includes depositing a dielectric layer to cover the multiple sub-free layers, the tunnel barrier layer, and the reference layer.

[0015] In yet another embodiment, the method further includes forming a capping reference layer on top of a conductive via, the conductive via being embedded in the dielectric layer and serving as a third electrode to the MTJ structure.

[0016] Embodiments of the present invention provide another method for forming an MTJ structure. The method includes forming a capping spin-orbit coupling layer on top of a substrate; forming a capping free layer on top of the capping spin-orbit coupling layer; patterning the capping free layer into a free layer, the free layer including a plurality of sub-free layers placed parallel to each other and on top of the capping spin-orbit coupling layer; depositing a capping tunneling barrier layer on top of the plurality of sub-free layers; depositing a capping reference layer on top of the capping tunneling barrier layer; patterning the capping tunneling barrier layer and the capping reference layer into a tunneling barrier layer and a reference layer respectively, the patterning exposing a first end and a second end of the plurality of sub-free layers; and forming a first electrode in contact with the first end of the plurality of sub-free layers and a second electrode in contact with the second end of the plurality of sub-free layers.

[0017] In one embodiment, the method further includes depositing a dielectric layer over the capping reference layer, the tunneling barrier layer, and the plurality of sub-free layers after patterning the capping reference layer and the capping tunneling barrier layer into the tunneling barrier layer and the reference layer.

[0018] In another embodiment, the method further includes patterning the dielectric layer to create first and second openings before forming the first and second electrodes in the first and second openings, the first and second openings exposing the first end and the second end of the plurality of sub-free layers.

[0019] In yet another embodiment, the method further includes patterning the dielectric layer to create a third opening that exposes a portion of the reference layer between the first opening and the second opening, and subsequently depositing a conductive material in the third opening to form a third electrode. Description of the Drawings

[0020] The present invention will be more fully understood and appreciated from the following detailed description of embodiments of the invention in conjunction with the accompanying drawings, in which:

[0021] Figure 1A 、 Figures 1B to 5A 、 Figure 5B is a schematic illustration of a cross-sectional view and a top view of an MTJ structure during its manufacturing process according to an embodiment of the present invention;

[0022] Figure 6A 、 Figures 6B to 10A 、 Figure 10B is a schematic illustration of a cross-sectional view and a top view of an MTJ structure during its manufacturing process according to another embodiment of the present invention;

[0023] Figure 11 is a schematic illustration of a flowchart of a method for manufacturing an MTJ structure according to an embodiment of the present invention;

[0024] Figure 12is a schematic illustration of a flowchart of a method of fabricating an MTJ structure according to another embodiment of the present invention; and

[0025] Figure 13 is a schematic illustration of the operation of an MTJ structure according to an embodiment of the present invention.

[0026] It should be understood that, for purposes of simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale. Further, and if applicable, in the various functional block diagrams, two connected devices and / or elements may not necessarily be shown as connected. In some other instances, the grouping of certain elements in the functional block diagrams may be for descriptive purposes only and may not necessarily imply that they are in a single physical entity or that they are embodied in a single physical entity. Detailed Description

[0027] In the following detailed description and the drawings, it should be understood that the various layers, structures, and regions shown in the drawings are illustrative and schematic and are not drawn to scale. Additionally, for ease of explanation, one or more layers, structures, and regions of the type typically used to form a semiconductor device or structure may not be explicitly shown in a given illustration or drawing. This does not mean that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure. Further, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with regard to semiconductor processing steps, it is emphasized that the description provided herein is not intended to include all processing steps that may be required to form a functional semiconductor integrated circuit device. Instead, for the sake of economy of description, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are purposefully not described herein.

[0028] It should be understood that the terms “about” or “substantially” as used herein with respect to thickness, width, percentage, range, etc. are intended to mean close to or approximate but not exact. For example, the terms “about” or “substantially” as used herein mean that there may be a small margin of error, e.g., as an example only, 1% or less of the stated amount. Similarly, the terms “on,” “above,” or “top” as used herein to describe the positional relationship between two layers or structures are intended to be broadly interpreted and should not be construed as excluding the presence of one or more intermediate layers or structures.

[0029] To provide a spatial context for the different structural orientations of the semiconductor structures shown in the drawings, XYZ Cartesian coordinates may be provided in some of the drawings. As used herein, the term “vertical” or “vertical direction” or “vertical height” refers to the Z direction of the Cartesian coordinates shown in the drawings, and the terms “horizontal” or “horizontal direction” or “lateral direction” as used herein refer to the X direction and / or Y direction of the Cartesian coordinates shown in the drawings.

[0030] In addition, although different reference numerals are used in different drawings, the same or similar reference numerals are used in all drawings to denote the same or similar features, elements or structures. Thus, for the sake of economy of description, for each drawing, the detailed description of the same or similar features, elements or structures may not be repeated. In some drawings, the reference numerals for the same or similar elements may also be omitted so as not to overcrowd the drawings.

[0031] Figure 1A and Figure 1B FIGS. (A) and (B) are schematic diagrams of a cross-sectional view and a top view, respectively, of an MTJ structure according to an embodiment of the present invention during its manufacturing steps. More specifically, when forming the MTJ structure 10, an embodiment of the present invention provides for forming a conductive via 111 in a support structure such as a dielectric layer 110, or alternatively, receiving a dielectric layer 110 in which a conductive via 111 has already been formed. In one embodiment, the dielectric layer 110 may be part of a substrate such as a semiconductor substrate. On the other hand, the conductive via 111 may be made of, for example, tantalum nitride (TaN), titanium nitride (TiN), copper (Cu), tungsten (W), or other suitable conductive materials, and may be used as an electrode (such as a third electrode) of the MTJ structure 10, the manufacturing of which is described in more detail below.

[0032] In addition, an embodiment of the present invention provides for forming a capping reference layer 120 on the conductive via 111 and the dielectric layer 110, forming a capping tunnel barrier layer 130 on the capping reference layer 120, forming a capping free layer 140 on the capping tunnel barrier layer 130, and forming a capping spin-orbit coupling layer 150 on the capping free layer 140.

[0033] In one embodiment, the capping reference layer 120 and the capping free layer 140 may be capping ferromagnetic layers. Each capping ferromagnetic layer may independently be a layer of a material based on cobalt (Co), iron (Fe), and boron (B) (CoFeB), such as an alloy of Co, Fe, and B, although other types of ferromagnetic materials, such as an alloy of Co and Fe (CoFe) or an alloy of nickel (Ni) and Fe (NiFe), may also be used. In some embodiments, the capping reference layer may include a combination of a ferromagnetic layer and a Co-based synthetic antiferromagnetic layer. The capping reference layer and the capping free layer may be formed to each have a thickness in the range of about 0.5 nm to about 30 nm.

[0034] In one embodiment, the capping tunnel barrier layer 130 may be magnesium oxide (MgO) or include, for example, aluminum oxide (Al 2 O 3 ) or titanium oxide (TiO 2a layer of other suitable materials, and can be formed to have a thickness generally in the range of about 0.5 nm to about 1.5 nm, although other thicknesses are also possible.

[0035] In one embodiment, the capping spin - orbit coupling layer 150 can be a spin - orbit torque material layer, which can include, for example, tantalum (Ta), platinum (Pt), or other suitable materials. The capping spin - orbit coupling layer 150 can be formed to have a thickness generally in the range of about 0.5 nm to about 5 nm.

[0036] Embodiments of the present invention can also provide for forming a hard mask layer 160 on top of the spin - orbit coupling layer 150. The hard mask layer 160 can then be patterned to form an etch mask and can be used in subsequent steps to pattern the capping free layer 140, as described in more detail below.

[0037] Figure 2A and Figure 2B is a schematic illustration of a cross - sectional view (A) and a top - view (B) of the MTJ structure in its manufacturing steps after the steps shown in Figure 1A and Figure 1B More specifically, embodiments of the present invention provide for patterning the hard mask layer 160 into a hard mask 161, the hard mask 161 including a plurality of hard mask stripes, such as hard mask stripes 1611, 1612, 1613, 1614, 1615, and 1616 that are parallel to each other. Although Figure 2B six (6) hard mask stripes are schematically shown in

[0038] Embodiments of the present invention may also provide for transferring the pattern of the hard mask 161 to the underlying covered spin - orbit coupling layer 150 and covered free layer 140, for example, by an anisotropic etching process. The anisotropic etching process may stop at the covered tunneling barrier layer 130. The transfer of the pattern of the hard mask 161 thereby forms a free layer 141 including a plurality of sub - free layers 1411, 1412, 1413, 1414, 1415, and 1416 that are parallel to each other. Since the covered free layer 140 is a ferromagnetic material layer, the plurality of sub - free layers 1411, 1412, 1413, 1414, 1415, and 1416 may be a plurality of ferromagnetic stripes. The plurality of sub - free layers 1411, 1412, 1413, 1414, 1415, and 1416 may each have a plurality of notches formed along their respective longitudinal directions. Creating notches along the sub - free layers helps to create discrete (or digital) conductance / resistance values of the MTJ structure or device, and during the operation of the device, the more the number of notches, the higher the resolution of the conductance / resistance that the MTJ device can provide.

[0039] In one embodiment, the notches of the plurality of sub - free layers may be substantially aligned with each other along their longitudinal directions. The notches may have a uniform pitch, and the pitch may be the same between the plurality of sub - free layers. However, embodiments of the present invention are not limited to this aspect. For example, the notches of the plurality of sub - free layers may not have the same pitch and / or may not be perpendicularly aligned with each other. However, by increasing the pitch and / or aligning the notches, it may help to increase the resolution of the conductance / resistance and / or the uniformity of the resolution during the operation of the MTJ device.

[0040] Similarly, the transfer of the pattern of the hard mask 161 may also form a spin - orbit coupling layer 151 including a plurality of spin - orbit coupling bands 1511, 1512, 1513, 1514, 1515, and 1516 that are parallel to each other. Since the transfer process is an anisotropic etching process, the hard mask 161, the spin - orbit coupling layer 151, and the free layer 141 have substantially the same shape. Figure 2B The hard mask 161, the spin - orbit coupling layer 151, and the free layer 141 are schematically shown in a top - view in

[0041] Figure 3A and Figure 3B is in accordance with an embodiment of the present invention in Figure 2A and Figure 2BSchematic illustrations of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown. More specifically, embodiments of the present invention provide patterning a capping tunnel barrier layer 130 and a capping reference layer 120 into a tunnel barrier layer 131 and a reference layer 121. For example, embodiments of the present invention provide forming an organic planarization layer (OPL) on top of the MTJ structure 10 in the case of manufacturing and forming an etch mask on top of the OPL. Subsequently, embodiments of the present invention provide using the etch mask to etch the OPL and the underlying capping tunnel barrier layer 130 and capping reference layer 120 in an anisotropic etching process, thereby creating or forming a tunnel barrier layer 131 and a reference layer 121. Since the capping reference layer 120 is a ferromagnetic material layer, the reference layer 121 formed therefrom is also a ferromagnetic layer. In one embodiment, etching of the capping reference layer 120 may place a conductive via 111 at a substantially central portion of the reference layer 121 thus formed. The conductive via 111 may form or act as a third electrode of the MTJ structure during manufacturing, as described in more detail below, and may also be referred to as the third electrode 111.

[0042] Figure 4A and Figure 4B are schematic illustrations of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown in accordance with an embodiment of the present invention in Figure 3A and Figure 3B More specifically, embodiments of the present invention provide depositing a dielectric layer 170 to encapsulate the MTJ structure 10 during manufacturing. For example, embodiments of the present invention provide forming the dielectric layer 170 to cover the sidewalls and / or side surfaces of the hard mask 161, the spin-orbit coupling layer 151, the free layer 141, the tunnel barrier layer 131, and the reference layer 121. The dielectric layer 170 may also cover the top surface of the exposed dielectric layer 110. The dielectric layer 170 may be formed to have a top surface coplanar with the top surface of the hard mask 161. For example, the dielectric layer 170 may be initially deposited above the hard mask 161 and cover the hard mask 161. Subsequently, the dielectric layer 170 may be planarized by a chemical mechanical polishing (CMP) process to have a top surface coplanar with the top surface of the hard mask 161.

[0043] Figure 5A and Figure 5B are schematic illustrations of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown in accordance with an embodiment of the present invention in Figure 4A and Figure 4B More specifically, embodiments of the present invention provide forming a first end of the free layer 141 (e.g., as shown in Figure 5A and Figure 5BThe first electrode 181 that contacts the left end in []. The first ends of the first ends of the free layer 141 may include a plurality of sub-free layers 1411, 1412, 1413, 1414, 1415, and 1416. Embodiments of the present invention also provide a second electrode 182 that forms in contact with the second end of the free layer 141. The second end is, for example, as shown in Figure 5A and Figure 5B the right end in []. The second ends of the free layer 141 may include the corresponding second ends of the plurality of sub-free layers 1411, 1412, 1413, 1414, 1415, and 1416.

[0044] In one embodiment, the first electrode 181 and the second electrode 182 may be formed by a selective metal growth process, such as, for example, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process, and may be made of, for example, tantalum nitride (TaN), titanium nitride (TiN), copper (Cu), tungsten (W), or other suitable conductive materials. In another embodiment, since the spin-orbit coupling layer 151 is in direct contact with the underlying free layer 141, the first electrode 181 and the second electrode 182 may only need to be formed to contact the first end and the second end of the spin-orbit coupling layer 151.

[0045] Figure 6A and Figure 6B are schematic diagrams of a cross-sectional view (A) and a top view (B) in the manufacturing steps of another MTJ structure according to an embodiment of the present invention. More specifically, when forming the MTJ structure 20, embodiments of the present invention provide receiving a dielectric layer 210, which may be a part of a substrate (such as a semiconductor substrate); forming a capping spin-orbit coupling layer 220 on the dielectric layer 210; and forming a capping free layer 230 on the capping spin-orbit coupling layer 220.

[0046] In one embodiment, the capping spin-orbit coupling layer 220 may be a spin-orbit torque material layer, which may include, for example, tantalum (Ta), platinum (Pt), or other suitable materials. The capping spin-orbit coupling layer 220 may be formed to have a thickness ranging from about 0.5 nm to about 5 nm, but other thicknesses are also possible and are fully expected.

[0047] In another embodiment, the capping free layer 230 may be a capping ferromagnetic layer, and the capping ferromagnetic layer may be a layer of a material based on Co, Fe, and B (CoFeB), such as an alloy of Co, Fe, and B. Although other types of ferromagnetic materials, such as an alloy of Co and Fe (CoFe) or an alloy of Ni and Fe (NiFe), may also be used. The capping ferromagnetic layer may be formed to have a thickness ranging from about 0.5 nm to about 30 nm, but other thicknesses are also possible and are fully covered herein.

[0048] Figure 7A and Figure 7B is a schematic illustration of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown in Figure 6A and Figure 6B According to an embodiment of the present invention. More specifically, an embodiment of the present invention provides patterning a capping free layer 230 into a free layer 231 including a plurality of sub-free layers (such as, for example, sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316 parallel to each other). Here, Figure 7B Six (6) sub-free layers are shown only as an example in

[0049] and a greater or fewer number of sub-free layers are possible and are fully contemplated by embodiments of the present invention. In another embodiment, the plurality of sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316 may optionally be formed to have a plurality of notches continuously formed along their respective longitudinal directions. Patterning of the capping free layer 230 can be performed (for example) by forming a hard mask on top of the capping free layer 230 through a photolithographic patterning process and then transferring the pattern of the hard mask to the capping free layer 230 through an anisotropic etching process. The hard mask can then be removed after the anisotropic etching process.

[0050] Figure 8A and Figure 8B is a schematic illustration of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown in Figure 7A and Figure 7B According to an embodiment of the present invention. More specifically, an embodiment of the present invention provides forming a capping tunnel barrier layer 240 on a free layer 231 including a plurality of sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316, and forming a capping reference layer 250 on the capping tunnel barrier layer 240. The capping tunnel barrier layer 240 and the capping reference layer 250 may cover the sidewalls or side surfaces of the free layer 231.

[0051] In one embodiment, the capping tunnel barrier layer 240 may be magnesium oxide (MgO) or other suitable materials (including, for example, aluminum oxide (Al 2 O 3 ) or titanium oxide (TiO 2) layer, and can be formed to have a thickness ranging from about 0.5 nm to about 1.5 nm, although other thicknesses are also possible. In another embodiment, the capping reference layer 250 can be a capping ferromagnetic layer, and the capping ferromagnetic layer can be a layer of a material based on Co, Fe, and B (CoFeB), such as an alloy of Co, Fe, and B, although other types of ferromagnetic materials, such as an alloy of Co and Fe (CoFe) or an alloy of Ni and Fe (NiFe), can also be used. The capping ferromagnetic layer can be formed to have a thickness in the range of, for example, from about 0.5 nm to about 30 nm.

[0052] Figure 9A and Figure 9B is a schematic illustration of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown in Figure 8A and Figure 8B according to an embodiment of the present invention. More specifically, embodiments of the present invention provide patterning the capping reference layer 250 and the capping tunnel barrier layer 240 into a reference layer 251 and a tunnel barrier layer 241. For example, embodiments of the present invention provide forming a hard mask on top of the capping reference layer 250 and then transferring the pattern of the hard mask onto the capping reference layer 250 and below the capping tunnel barrier layer 240 to form the reference layer 251 and the tunnel barrier layer 241. The transfer process of the pattern of the hard mask can be an anisotropic and selective etching process, which can stop at the free layer 231 and the capping spin-orbit coupling layer 220.

[0053] In one embodiment, patterning the capping reference layer 250 and the capping tunnel barrier layer 240 exposes the first end or the left end of the free layer 231 (as shown in Figure 9A and Figure 9B ) or the corresponding first ends of a plurality of sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316. The patterning process also exposes the second end or the right end of the free layer 231 (as shown in Figure 9A and Figure 9B ) or the corresponding second ends of a plurality of sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316.

[0054] Figure 10A and Figure 10B are according to an embodiment of the present invention as shown in Figure 9A and Figure 9BSchematic illustrations of a cross-sectional view (A) and a top view (B) of an MTJ structure in its manufacturing steps after the steps shown. More specifically, embodiments of the present invention provide for depositing a dielectric layer 270 to encapsulate the MTJ structure 20 during manufacturing. For example, the dielectric layer 270 may cover the exposed top surfaces of the reference layer 251, the free layer 231, and the spin-orbit coupling layer 220, and may cover the sidewalls or side surfaces of the reference layer 251, the tunnel barrier layer 241, and the free layer 231. Then, the dielectric layer 270 may be planarized by a CMP process.

[0055] Embodiments of the present invention further provide for forming a first electrode 261 through the dielectric layer 270 to contact a first end of the free layer 231 or corresponding first ends of the sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316; forming a second electrode 262 through the dielectric layer 270 to contact a second end of the free layer 231 or corresponding second ends of the sub-free layers 2311, 2312, 2313, 2314, 2315, and 2316; and forming a third electrode 263 through the dielectric layer 270 and between the first electrode 261 and the second electrode 262 to contact the reference layer 251. In one embodiment, the third electrode 263 may be made at a substantially central portion of the reference layer 251. The first, second, and third electrodes 261, 262, and 263 may be made of, for example, tantalum nitride (TaN), titanium nitride (TiN), copper (Cu), tungsten (W), or other suitable conductive materials, and may be made by, for example, ALD, CVD, or PVD processes.

[0056] Figure 11 Is a schematic illustration of a flowchart of a method for manufacturing an MTJ structure according to an embodiment of the present invention. The method includes (911) receiving a support structure, such as a dielectric layer having a conductive via or a third electrode embedded therein; (912) sequentially forming a capping reference layer, a capping tunnel barrier layer, a capping free layer, and a capping spin-orbit coupling layer on top of the dielectric layer and the conductive via; (913) patterning the capping free layer into a plurality of sub-free layers of ferromagnetic strips placed parallel to each other, and patterning the capping spin-orbit coupling layer into a spin-orbit coupling layer of a plurality of spin-orbit coupling strips on top of the plurality of sub-free layers, wherein the plurality of ferromagnetic strips may have a plurality of notches formed along their longitudinal directions; (914) patterning the capping tunnel barrier layer and the capping reference layer into a tunnel barrier layer and a reference layer; (915) depositing a dielectric layer covering the plurality of sub-free layers, the tunnel barrier layer, and the reference layer; (916) forming openings in the dielectric layer to expose corresponding first ends and corresponding second ends of the plurality of sub-free layers; and (917) filling the openings with a conductive material to form first and second electrodes respectively contacting the first and second ends of the plurality of sub-free layers.

[0057] Figure 12 is a schematic illustration of a flowchart of a method of manufacturing an MTJ structure according to an embodiment of the present invention. The method includes (921) forming a capping spin-orbit coupling layer on top of a substrate and forming a capping free layer on top of the capping spin-orbit coupling layer; (922) patterning the capping free layer into a free layer, wherein the free layer includes a plurality of sub-free layers placed or patterned parallel to each other. The sub-free layers may have a plurality of notches formed along their longitudinal directions; (923) depositing a capping tunneling barrier layer on top of the plurality of sub-free layers and depositing a capping reference layer on top of the capping tunneling barrier layer; (924) patterning the capping reference layer and the capping tunneling barrier layer into a reference layer and a tunneling barrier layer to expose first and second ends of the free layer or corresponding first and second ends of the plurality of sub-free layers; (925) depositing a dielectric layer to cover the reference layer, the tunneling barrier layer, and the plurality of sub-free layers; (926) forming first and second openings in the dielectric layer to expose the first and second ends of the free layer and creating a third opening in the dielectric layer between the first and second openings to expose a substantially central portion of the reference layer; and (927) depositing conductive material in the first, second, and third openings to form first, second, and third electrodes of the MTJ structure.

[0058] Figure 13 is a schematic illustration of the operation of an MTJ structure according to an embodiment of the present invention. For example, to explain how the use of a plurality of sub-free layers of a ferromagnetic strip helps to reduce the statistical variation of the domain wall positions of the free layer in an MTJ structure, Figure 13 a top view of the programming conditions of a plurality of sub-free layers 1411, 1412, 1413, 1414, 1415, and 1416 during the operation of the MTJ structure 10 is shown at the free layer 141 level. For example, a programming voltage such as a voltage pulse may be applied between the first electrode 181 and the second electrode 182 for a specific duration. The applied voltage may create domain walls at positions in the sub-free layers between a first portion whose magnetic direction (or polarization) has changed and a second portion whose magnetic direction (or polarization) remains unchanged.

[0059] For example, for Figure 13In the example shown, the magnetic directions (or polarizations) of the first portions 1421 (i.e., the first 5 notches) of the sub-free layers 1411, the first portions 1422 (i.e., the first 3 notches) of the sub-free layers 1412, the first portions 1423 (i.e., the first 4 notches) of the sub-free layers 1413, the first portions 1424 (i.e., the first 5 notches) of the sub-free layers 1414, the first portions 1425 (i.e., the first 3 notches) of the sub-free layers 1415, and the first portions 1426 (i.e., the first 4 notches) of the sub-free layers 1416 are changed under the applied programming voltage or voltage pulse. In other words, the domain wall positions of the sub-free layers 1411, 1412, 1413, 1414, 1415, and 1416 are located at the fifth notch (1421), the third notch (1422), the fourth notch (1423), the fifth notch (1424), the third notch (1425), and the fourth notch (1426) of the sub-free layers 1411, 1412, 1413, 1414, 1415, and 1416, respectively.

[0060] For all sub-free layers, it is assumed that the domain wall position of the programmed sub-free layer corresponds to the conductance value of G, and this domain wall position can vary statistically, resulting in the conductance value of G having a standard deviation of S1. The effective or combined domain wall position of the free layer 141 can correspond to the conductance value of G*N, and this conductance value of G*N can have a standard deviation S2 equal to S1*sqrt(N), where N is the total number of sub-free layers, i.e., the count of multiple sub-free layers. In other words, if the free layer 141 (with N sub-free layers) has the same conductance value as the conductance value of the sub-free layer, such as G, the conductance value of the free layer 141 can have a standard deviation smaller by sqrt(N) times than that of a single sub-free layer, i.e., S1 / sqrt(N). Additionally, the larger the number of sub-free layers, the smaller the standard deviation of the free layer 141. Moreover, the use of multiple sub-free layers allows for programming of partial conductance / resistance states that otherwise may not be accessible by a single free layer. For example, assuming a single free layer can reach 4 conductance / resistance states, using multiple sub-free layers will provide more discrete conductance / resistance states due to averaging of slightly different positioning of the domain walls of each sub-free layer.

[0061] It should be understood that the exemplary methods discussed herein can be readily combined with other semiconductor processing flows, semiconductor devices, and integrated circuits having various analog and digital circuits or mixed-signal circuits. In particular, integrated circuit dies can be fabricated with a variety of devices, such as field-effect transistors, bipolar transistors, metal-oxide semiconductor transistors, diodes, capacitors, inductors, etc. The integrated circuits according to the present invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention can include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid-state media storage devices, functional circuits, etc. Systems and hardware incorporating such integrated circuits are considered to be part of the embodiments described herein. Given the teachings of the present invention provided herein, those of ordinary skill in the art will be able to envision other implementations and applications of the technology of the present invention.

[0062] Accordingly, at least portions of one or more of the semiconductor structures described herein can be implemented in an integrated circuit. The resulting integrated circuit chips can be distributed by the fabricator in the form of an original wafer (i.e., as a single wafer having multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip can be mounted in a single-chip package (e.g., a plastic carrier having leads fixed to a motherboard or other high-level carrier) or a multi-chip package (such as a ceramic carrier having surface interconnects and / or buried interconnects). In any case, the chip can then be integrated with other chips, discrete circuit elements, and / or other signal processing devices, as part of an intermediate or final product such as a motherboard. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products having a display, keyboard, or other input device, and a central processing unit.

[0063] The description of the various embodiments of the present invention has been presented for purposes of illustration and is not exhaustive, and the present invention is not limited to the disclosed embodiments. The terms used herein have been chosen to best explain the principles of the embodiments, the practical application, or the improvement of the technology found in the marketplace, and to enable those of ordinary skill in the art to understand the embodiments disclosed herein. However, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modifications, and / or alternative embodiments can be made without departing from the scope of the present invention, and thus all such changes, modifications, and / or alternative embodiments are contemplated and considered to be within the scope of the present invention. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the present invention.

Claims

1. A magnetic tunnel junction (MTJ) structure, comprising: an MTJ stack including a tunnel barrier layer on a reference layer and a free layer on the tunnel barrier layer, wherein the free layer includes a plurality of sub-free layers, the plurality of sub-free layers being a plurality of ferromagnetic stripes placed parallel to each other on the tunnel barrier layer, the plurality of ferromagnetic stripes having respective first ends connected to a first electrode and respective second ends connected to a second electrode.

2. The MTJ structure according to claim 1, wherein the plurality of ferromagnetic stripes are patterned to have notches formed along respective longitudinal directions of the plurality of ferromagnetic stripes.

3. The MTJ structure according to claim 2, wherein the notches of the plurality of ferromagnetic stripes are substantially aligned with each other along the respective longitudinal directions.

4. The MTJ structure according to claim 1, wherein each of the plurality of ferromagnetic stripes is covered by a spin-orbit coupling layer, the spin-orbit coupling layer being patterned to have a shape identical to the shape of the ferromagnetic stripe covered by the spin-orbit coupling layer.

5. The MTJ structure according to claim 1, wherein the reference layer is a ferromagnetic layer perpendicularly overlapping the plurality of sub-free layers via the tunnel barrier layer.

6. The MTJ structure according to claim 1, further comprising a third electrode that contacts the reference layer at a substantially central position of the reference layer.

7. The MTJ structure according to claim 1, wherein the plurality of sub-free layers have respective domain wall positions defined by an applied voltage, wherein each domain wall position corresponds to a conductance value G having a standard deviation S1, and the free layer has an effective domain wall position defined by the applied voltage, the effective domain wall position corresponding to a conductance value G*N having a standard deviation S1*sqrt(N), where N is the count of the plurality of sub-free layers.

8. A method of forming an MTJ structure, the method comprising: forming a covered tunnel barrier layer on top of a covered reference layer; forming a covered free layer on top of the covered tunnel barrier layer; patterning the covered free layer into a free layer having a plurality of sub-free layers, the plurality of sub-free layers being a plurality of ferromagnetic stripes placed parallel to each other on top of the covered tunnel barrier layer; and forming a first electrode in contact with the respective first ends of the plurality of ferromagnetic stripes and a second electrode in contact with the respective second ends of the plurality of ferromagnetic stripes.

9. The method according to claim 8, wherein patterning the covered free layer includes forming the plurality of ferromagnetic stripes having notches along respective longitudinal directions of the plurality of ferromagnetic stripes.

10. The method according to claim 9, wherein the notches of the plurality of ferromagnetic stripes are substantially aligned with each other along the respective longitudinal directions.

11. The method according to claim 8, further comprising forming a covered spin-orbit coupling layer on top of the covered free layer, wherein patterning the covered free layer further includes patterning the covered spin-orbit coupling layer on top of the plurality of ferromagnetic stripes into a plurality of spin-orbit coupling stripes.

12. The method according to claim 8 further comprises, after patterning the covered free layer, patterning the covered tunnel barrier layer and the covered reference layer into a tunnel barrier layer and a reference layer, respectively.

13. The method according to claim 8 further comprises depositing a dielectric layer to cover the plurality of sub-free layers, the tunnel barrier layer, and the reference layer.

14. The method according to claim 8 further comprises forming the covered reference layer on top of a conductive via, the conductive via being embedded in a dielectric layer and serving as a third electrode of the MTJ structure.

15. A method of forming an MTJ structure, the method comprising: forming a covered spin-orbit coupling layer on top of a substrate; forming a covered free layer on top of the covered spin-orbit coupling layer; patterning the covered free layer into a free layer, the free layer comprising a plurality of sub-free layers on top of the covered spin-orbit coupling layer and placed parallel to each other; depositing a covered tunnel barrier layer on top of the plurality of sub-free layers; depositing a covered reference layer on top of the covered tunnel barrier layer; patterning the covered tunnel barrier layer and the covered reference layer into a tunnel barrier layer and a reference layer, respectively, the patterning exposing first and second ends of the plurality of sub-free layers; and forming a first electrode in contact with the first end of the plurality of sub-free layers and a second electrode in contact with the second end of the plurality of sub-free layers.

16. The method according to claim 15, wherein the covered free layer is a ferromagnetic material layer and the plurality of sub-free layers are a plurality of ferromagnetic stripes, and wherein patterning the covered free layer comprises forming the plurality of ferromagnetic stripes, each ferromagnetic stripe having a notch formed along a longitudinal direction of the ferromagnetic stripe.

17. The method according to claim 16, wherein the notches of the plurality of ferromagnetic stripes are substantially aligned with each other along respective longitudinal directions of the plurality of ferromagnetic stripes.

18. The method according to claim 15 further comprises, after patterning the covered tunnel barrier layer and the covered reference layer, depositing a dielectric layer covering the reference layer, the tunnel barrier layer, and the plurality of sub-free layers.

19. The method according to claim 18 further comprises patterning the dielectric layer to create a first opening and a second opening, the first opening and the second opening exposing the first and second ends of the plurality of sub-free layers, and after creating the first opening and the second opening, forming the first electrode and the second electrode in the first opening and the second opening.

20. The method according to claim 19 further comprises patterning the dielectric layer to create a third opening, the third opening exposing a portion of the reference layer between the first opening and the second opening, and subsequently depositing a conductive material in the third opening to form a third electrode.

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