Boost circuit and method for comparator circuit

Abstract

A voltage comparator includes a boost circuit configured to boost a direct current (DC) bias of the comparator. The boost circuit includes transistors of different sizes, one of which is configured to add a portion of the boost current to the bias current.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 18 / 045,050, filed on October 7, 2022, the disclosure of which is incorporated herein as if set forth in full below and for all applicable purposes. Technical field

[0003] This application relates to comparators, and more particularly to comparators with direct current (DC) bias boosting. Background art

[0004] Comparator circuits are used in many applications. For example, some protection circuits in battery - driven applications can include comparators that monitor over - voltage conditions. Such comparators can be used to respond quickly enough to ensure that high voltages within the system do not persist long enough to cause damage to integrated circuit devices. For example, IEC - 61000 - 4 - 5 imposes constraints on the reliability of connector pins and thus on the response time of the detection circuit to high - voltage events that may affect those connector pins. Additionally, since comparators can be considered auxiliary circuits, the design power requirements of comparators can be stringent.

[0005] There is a need in the art for comparators with increased performance and relatively low - power operation. Summary of the invention

[0006] In a specific embodiment, a voltage comparator includes: a first current mirror coupled to a first current source; a second current mirror coupled to the first current mirror; a first transistor and a second transistor coupled to the second current mirror and a first load, wherein the first transistor has a first voltage input and wherein the second transistor has a second voltage input, and an output terminal of the voltage comparator is coupled between the second transistor and the first load; and a third transistor and a fourth transistor coupled to a second current source, the third transistor coupled to a second load, and the fourth transistor coupled to the first current mirror, the third transistor having a third voltage input and receiving the same first voltage as the first voltage input, the fourth transistor having a fourth voltage input and receiving the same second voltage as the second voltage input, and further wherein the fourth transistor is larger than the third transistor.

[0007] In another specific implementation, a method for comparing a first voltage and a second voltage includes: mirroring a first current in a first current mirror to generate a second current in a second current mirror, the first current mirror being coupled to the second current mirror; applying the first voltage to a first transistor and the second voltage to a second transistor, wherein the first transistor and the second transistor are coupled to the second current mirror and a first load, and wherein the first transistor and the second transistor receive the second current; applying the first voltage to a third transistor and the second voltage to a fourth transistor, wherein the third transistor is coupled to a second load, and wherein the fourth transistor is larger than the third transistor and is coupled to the first current mirror, the third transistor and the fourth transistor shunt a boost current, and wherein the first current includes a portion of the boost current from the fourth transistor that is added to a bias current; and changing the state of an output terminal of a comparator at least partially based on a change in the value of the first voltage relative to the second voltage.

[0008] In another specific implementation, a wireless communication device includes: an application processor; an audio signal amplifier; a charging integrated circuit, wherein the application processor, the audio signal amplifier, and the charging integrated circuit are coupled to a set of wires through a multiplexing function; a data and charging plug, the data and charging plug being coupled to the set of wires; and a voltage comparator, the voltage comparator being coupled to at least one of the set of wires, wherein the voltage comparator includes: a boost circuit having a first transistor and a second transistor coupled to a first current source, wherein the gate of the first transistor is coupled to a reference voltage, and wherein the gate of the second transistor is coupled to the at least one of the set of wires, wherein the first transistor is configured to conduct a first portion of a first current of the first current source to a first current mirror; a second current source, the second current source being coupled to the first current mirror; a second current mirror, the second current mirror being coupled to the first current mirror; and a third transistor and a fourth transistor, the third transistor and the fourth transistor being coupled to the second current mirror, the gate of the third transistor being coupled to the at least one of the set of wires, and the gate of the fourth transistor being coupled to the reference voltage, further wherein the first transistor is larger than the second transistor, the third transistor, and the fourth transistor.

[0009] In yet another specific implementation, a wireless communication device includes: a comparator coupled to a reference voltage and to a wire configured to conduct direct current (DC) charging, audio signals, and data; components for biasing the comparator; and components for boosting the DC bias level of the comparator, including shunting a first current from a first current source at least partially based on a difference between the reference voltage and the voltage level of the wire, further including conductively superimposing a first portion of the first current to a second current in the components for biasing, and conducting a second portion of the first current to a load, wherein a first transistor configured to conduct the first portion of the first current is larger than a second transistor configured to conduct the second portion of the first current.

[0010] These advantages and additional advantages can be better understood through the following specific implementation manners. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Illustrates a block diagram of an example wireless device including an overvoltage protection (OVP) circuit according to one specific implementation.

[0012] Figure 2 Illustrates an example architecture for multiplexing audio signals, high-speed data signals, and charging while providing overvoltage protection in a device such as Figure 1 the device.

[0013] Figure 3 Illustrates an example voltage comparator that can be used in the Figure 2 specific implementation of

[0014] Figure 4 Illustrates a flowchart of an example method that can be performed by the Figure 2 overvoltage scheme of

[0015] The specific implementation of the present disclosure and its advantages can be best understood by referring to the following specific implementation manners. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. DETAILED DESCRIPTION

[0016] In one example, the comparator includes two current mirrors. A first current mirror is coupled to a first current source. A second current mirror is coupled to the first current mirror. The first current mirror is operable to mirror a bias current (Ibias). The second current mirror, due to its coupling to the first current mirror, also mirrors the bias current.

[0017] Continuing with the example, a second current mirror may be coupled to a first set of transistors, each of which is coupled from source to drain to a load from the second current mirror. The first set of transistors may be configured to receive a set of input voltages (e.g., INN, INP). The relative voltage levels of the set of input voltages determine how current is shunted between the first set of transistors. For example, the voltage level of INP may typically be lower than the voltage level of INN. The sizes of the first set of transistors and the load may be designed such that when the voltage level of INP increases to cross the voltage level of INN, this causes the ratio of the current flowing through the set of transistors to result in less current flowing through a first transistor of the transistors and more current flowing through a second transistor of the transistors. The additional current flowing through the second transistor of the transistors may raise the voltage level at the node between the transistor and the load, and the voltage level at that node may be used as an output voltage to indicate that the voltage level of INP is equal to or higher than the voltage level of INN.

[0018] However, some requirements for comparators are relatively fast operation to detect and act on overvoltage conditions (e.g., when INP rapidly increases). A comparator having an architecture as described above may include some capacitance at the load, where the capacitance takes time to charge. One way to increase the speed of the comparator is to charge the capacitance when INP rises but before INP crosses INN. The various specific implementations described herein include a bias boost circuit that operates to increase the speed of the comparator by charging the capacitance.

[0019] An example bias boost circuit may include a second current source that provides a boost current (Iboost). The second current source may supply the boost current to a second set of transistors controlled by the set of input voltages INN, INP. The second set of transistors may be replicas of the first set of transistors such that the second set of transistors includes a transistor controlled by INN, and that transistor is a replica of a transistor in the first set of transistors that is also controlled by INN. The second set of transistors may further include a transistor controlled by INP, and that transistor is a replica of a transistor in the first set of transistors that is also controlled by INP. Further in this example, the replica transistor controlled by INN may be larger than the replica transistor controlled by INP. In this example, a replica transistor is a transistor that is identical or similar in design to another transistor and is implemented on the same chip using the same process as that other transistor, but may be different in size.

[0020] As the voltage level of INP increases, this causes a greater proportion of the boost current Iboost to flow through the replica transistor controlled by INN. The boost circuit is arranged such that the replica transistor controlled by INN is coupled to a first current mirror and adds its corresponding proportion of the boost current Iboost to the bias current Ibias. The superimposed current (Itotal) is mirrored by the first current mirror and the second current mirror. In other words, as the proportion of the boost current Iboost corresponding to the replica transistor (controlled by INN) increases, this increases the amount of direct current (DC) bias at the first set of transistors, thereby charging the capacitance at the load. The larger relative size of the replica transistor controlled by INN increases the corresponding proportion of its boost current, which is further added to Itotal and the DC bias at the first set of transistors. Thus, the output voltage of the comparator can change more quickly from digital 0 to digital 1 during an overvoltage event.

[0021] Each particular implementation can be non-clock-controlled, i.e., provide continuous monitoring of the input voltage. As described above, even before the voltage level of INP crosses the voltage level of INN, the asymmetric nature of the second set of transistors can cause an increase in the DC bias current at the first set of transistors. This predictive action of the bias circuit is a form of hysteresis that helps avoid chatter near the trigger threshold, which might otherwise be associated with alternative techniques for changing the operating point of the transistors in the comparator. In other words, each particular implementation can provide speed, as well as avoid chatter at the trigger threshold. Additionally, the boost circuit can be implemented such that during normal operation, when INP is lower than INN, little or no additional current is used compared to a comparator that omits the boost circuit. In other words, the boost circuit can be implemented with little or no power loss and little or no area loss.

[0022] Figure 1 An example device 100 in which aspects of the present disclosure can be implemented is illustrated. Device 100 can be a battery-powered device such as a cellular phone, a handheld device, a wireless device, a laptop computer, a tablet computer, a smart phone, a wearable device, etc.

[0023] Device 100 can include a processor 104 that controls the operation of device 100. Processor 104 can also be referred to as a central processing unit (CPU). A memory 106 that can include both a read-only memory (ROM) and a random access memory (RAM) provides instructions and data to processor 104. A portion of memory 106 can also include a non-volatile random access memory (NVRAM). Processor 104 generally performs logical and arithmetic operations based on program instructions stored within memory 106.

[0024] In some aspects, device 100 may further include a housing 108, which may include a transmitter 110 and a receiver 112 to allow for sending and receiving data between device 100 and a remote location. For some aspects, transmitter 110 and receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise coupled to housing 108 and electrically connected to transceiver 114. Device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0025] Device 100 may also include a signal detector 118, which may be used to detect and quantify the signal level received by transceiver 114. Signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density, and other signal parameters. Device 100 may also include a digital signal processor (DSP) 120 for processing the signals.

[0026] Device 100 may also include a battery 122 for powering various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to various components of device 100. PMIC 124 may perform various functions for the device, such as direct current (DC) - to - DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In some aspects, PMIC 124 may include a battery charging circuit (e.g., a primary - secondary battery charging circuit) or other switched - mode power supplies. The various components of device 100 may be coupled together by a bus system 126, which may include, in addition to a data bus, a power bus, a control signal bus, and / or a status signal bus.

[0027] For some aspects, device 100 may have an input / output (I / O) module 128 for receiving and / or outputting data and / or power. In some aspects, I / O module 128 may include a connector 130, such as a Universal Serial Bus (USB) Type - A (USB - A) socket or a USB Type - C (USB - C) socket. The pins of connector 130 may be routed via bus system 126 and / or signal lines of I / O module 128 to processor 104 and / or PMIC 124, at least some of which may include over - voltage protection circuits, as further described herein. Moreover, as described herein, I / O module 128 may include an encoder - decoder (codec) chip, which includes an audio signal path and drivers and other hardware components to facilitate audio through connector 130.

[0028] Figure 2This is an illustration of an example hardware architecture 200, which provides more details on how some parts of device 100 can be implemented. For example, architecture 200 includes an application processor 210, which may include some or all of the functions of processor 104 and DSP 120. In some examples, application processor 210 may be a system-on-chip (SOC) that includes multiple processor cores, a digital signal processor (DSP), memory, and so on. For example, one or more of the processor cores may run an operating system with a kernel that provides functions for, for example, controlling multiplexing function 235. Architecture 200 also includes a charger integrated circuit 220, which may include some or all of the functions of PMIC 124.

[0029] Codec chip 230 may provide some or all of the functions of I / O module 128 and may also include a connector 130 for physically docking with plug 250. In this example, plug 250 is a USB-C plug, but the scope of the specific implementation may include any suitable plug, whether or not it conforms to a standard. Codec chip 230 interfaces with both the audio signal path and the USB data path. For example, codec chip 230 receives high-speed data from USB-C plug 250 on the DN and DP data lines. Codec chip 230 may then route this high-speed data to application processor 210.

[0030] In addition, the codec chip includes audio signal amplifiers 231, 232 for the left and right channels, respectively. The analog audio signal may be output to USB-C plug 250 for use with, for example, wired headphones. It is also worth noting that USB-C plug 250 can be used for charging, such that DC power can be provided from USB-C plug 250 to charger IC 220.

[0031] To facilitate sharing the connection, codec chip 230 includes a multiplexing function 235, which Figure 2are illustrated as multiple switches. For example, when an audio signal is being sent from audio signal amplifiers 231, 232 to the USB-C plug 250, the switches can be turned on to create a circuit path from the audio signal amplifiers 231, 232 to the USB-C plug 250, while other switches can be turned off to isolate the application processor 210 from the audio signal path and also isolate the charger IC 220 from the audio signal path. Similarly, when the application processor 210 is sending and receiving digital data through the DP and DN pins using the USB-C plug 250, the charger IC 220 and the audio signal amplifiers 231, 232 can be isolated from the USB-C plug through the multiplexing function 235. Moreover, when the charger IC 220 is receiving DC power through the DN and DP pins of the USB-C plug 250, the multiplexing function 235 can create an electrical connection from the charger IC 220 to the USB-C plug 250 while isolating the application processor 210 and the audio signal amplifiers 231, 232 from the DC charging power. The multiplexing function 235 can be controlled, for example, by the application processor 210 or some other suitable hardware or software logic within the architecture 200.

[0032] The codec chip 230 also includes an overvoltage protection circuit 236 that monitors the signal levels on lines DPR and DNL and can activate the voltage protection circuit 240 using the signal CMP_OUT.

[0033] A DC overvoltage fault condition can occur at one or more pins of a connector (such as a USB-A or USB-C socket) of a device (e.g., device 100). As illustrated in the architecture 200, an overvoltage protection (OVP) scheme can be employed to prevent electro-overstress (EOS) damage to a chipset integrated circuit (IC) having respective signal nodes for coupling to connector pins (such as the DN and DP pins). In this example, the OVP scheme is illustrated by the overvoltage protection circuit 236 and the voltage protection circuit 240. Specifically, the OVP scheme can be implemented between the DP and DN pins of the USB-C plug 250 and the pins (e.g., the corresponding DP and DN pins) of the application processor 210 that runs applications in the operating system. In an example overvoltage scenario, a USB-C cord (not shown) docked to the USB-C plug 250 has a static charge buildup. When the connector of the cord physically creates an electrical connection with the DN and DP pins of the USB-C plug 250, the static charge can be discharged. In the absence of overvoltage protection, current can surge through the codec chip 230 and the application processor 210 and potentially cause damage.

[0034] Figure 2The OVP scheme attempts to minimize the likelihood of damage to the codec chip 230 and the application processor 210 by using the overvoltage protection circuit 236 to detect surges and then signaling the voltage protection circuit 240 to take action. The actions of the voltage protection circuit 240 may include turning on a shunt transistor to feed the surge current to ground, closing switches to prevent the current surge from traveling from the USB-C plug 250 to the codec chip 230, and / or other appropriate measures.

[0035] Various embodiments herein include an improved comparator circuit within the overvoltage protection circuit 236. The improved comparator circuit can provide accurate detection of overvoltage conditions and provide rapid signaling to the voltage protection circuit 240.

[0036] Figure 3 is an illustration of a voltage comparator 300 that can be implemented within the overvoltage protection circuit 236 according to one embodiment. Figure 2 of the overvoltage protection circuit 236.

[0037] The voltage comparator 300 includes a first current mirror exemplified by transistors M5 and M6. The first current mirror is coupled to a first current source labeled Ibias. The voltage comparator 300 also includes a second current mirror exemplified by transistors M3 and M4, and the second current mirror is coupled to the first current mirror.

[0038] Now looking at transistors M1 and M2, they are coupled to the second current mirror and to a first load 303. Specifically, transistors M1 and M2 are arranged such that their sources are both coupled to the drain of transistor M4, and they each receive a respective portion of the current Icomp.

[0039] Transistor M1 has INP as its input, which is the voltage associated with the wire labeled DPR in Figure 2 . The wire labeled DPR can be used for analog audio signals, DC charging, or high-speed data, as explained above with respect to Figure 2 . Additionally or alternatively, INP can be the voltage associated with the wire labeled DNL in Figure 2 , and DNL can also be used for analog audio signals, DC charging, or high-speed data. Both DPR and DNL couple the multiplexer function 235 to the voltage protection circuit 240, and both DPR and DNL are monitored by the overvoltage protection circuit 236. In fact, some examples can implement two different voltage comparators 300 in the overvoltage protection circuit 236 - one voltage comparator 300 for monitoring the voltage level on the DPR wire, and a second voltage comparator 300 for monitoring the voltage level on the DNL wire.

[0040] Transistor M2 has INN as its input, which can be a reference voltage. The level of the reference voltage can be set to any appropriate value, which can be determined during simulation or testing to provide satisfactory overvoltage detection for a given application. The output terminal of voltage comparator 300 is labeled CMP_OUT, and it is taken from node 301 located between the drain of transistor M2 and load 303. The voltage from node 301 is provided to buffer 302, and the output terminal of buffer 302 is the comparator output terminal CMP_OUT.

[0041] Transistors M11 and M22 are coupled to current source Iboost. Transistor M11 is coupled to second load 304, and transistor M22 is coupled to a first current mirror through its drain. Specifically, transistor M22 is coupled to a second current mirror between current source Ibias and the drain of transistor M5. Transistor M11 is coupled to load 304 through its drain. Both transistors M11 and M22 are coupled to each other through their sources and to current source Iboost. Transistors M11 and M22 are configured to each conduct a respective portion of the current from current source Iboost, and transistor M22 adds its respective portion of the Iboost current to the current mirror including transistor M5.

[0042] In Figure 3 the example, transistor M11 is a replica of transistor M1, and transistor M22 is a replica of transistor M2. Further in this example, the replica transistors are transistors that are identical or similar in design to another transistor and are implemented on the same chip using the same process as that other transistor. Although transistors M11, M1, and M2 have the same size (e.g., the same number of fins), transistor M22 is five times larger. The increased size of transistor M22 allows transistor M22 to have a smaller on-state resistance and conduct more current at a given gate-source voltage.

[0043] Further in this example, transistors M1, M2, M3, M4, M11, and M22 are p-channel metal-oxide-semiconductor (PMOS) transistors, and transistors M5 and M6 are n-channel metal-oxide-semiconductor (NMOS) transistors. However, the scope of the specific implementation is not limited to any type of transistor, as other solutions may use different devices. Additionally, some implants may scale M11 and M22 such that M11 may have a size different from M1, and M22 may have a size scaled relative to M11 by a certain ratio. In other words, the scope of the specific implementation is not limited to transistors M11, M1, and M2 having the same size.

[0044] VDD is the voltage supply. The current Ibias is a DC bias current that is applied to the drain of transistor M5. The current Ibias is mirrored through a first current mirror including transistors M5 and M6 and a second current mirror including transistors M3 and M4. The comparator is not clock controlled and thus continuously monitors the voltages INP, INN.

[0045] Typically, the input voltage INP is lower than the input voltage INN, causing the comparator to output a low voltage (digital 0) at nodes 301 and CMP_OUT. When the input voltage INP is equal to or higher than the input voltage INN, the comparator shown here outputs a high voltage (digital 1) at nodes 301 and CMP_OUT. In a scenario where the input voltage INP is lower than the input voltage INN, transistor M1 is turned on and transistor M2 is off or mostly off, such that almost all of the current through M4 flows through transistor M1 to ground. As the level of INP approaches the level of INN, transistor M1 conducts less current and transistor M2 conducts more current, thus shunting the current between transistors M1 and M2. As more current conducts through M2, the voltage level at node 301 becomes higher and, if the input voltage INP is equal to or higher than the input voltage INN, this voltage level is decoded as a digital 1.

[0046] Current source Iboost and transistors M11, M22 are configured as a boost circuit to boost the bias current Itotal as the voltage level of INP increases and approaches the voltage level of the reference voltage INN. The current through transistor M22 is superimposed on the current Ibias to produce Itotal through transistor M5. When the input voltage INP is lower than the input voltage INN, the amount of current through transistor M22 is small, however as the voltage level of INP increases and approaches the voltage level of INN, more current flows through transistor M22. Since the current Itotal, which is the sum of Ibias and Iboost, is mirrored through transistors M5, M6, M3, and M4, this also increases the current through both transistors M1 and M2. In fact, as the voltage level of INP increases and approaches the voltage level of INN, transistor M1 conducts less current and transistor M2 conducts more current. Thus, as the voltage level of INP increases and approaches the voltage level of INN, the current boost brought about by the current through transistor M22 is mirrored (Icomp) through transistor M4 and causes the voltage at node 301 to rise faster and be decoded as a digital 1 more quickly.

[0047] In other words, as the current Itotal increases, it is mirrored as the current Icomp through the transistor M4, and it charges internal nodes that can be interpreted as parasitic capacitances, particularly at node 301. For example, there may be parasitic capacitances attributable to the transistor M2 as well as the load 303 at node 301, and this parasitic capacitance can be charged as the portion of Icomp passing through the transistor M2 increases. This charging effect at node 301 can allow the voltage at node 301 to rise more quickly and enable the digital 1 to be detected more quickly. In one example, when CMP_OUT is digital 0, this can turn on or off the switch at the voltage protection circuit 240

[0048] The voltage comparator 300 having transistors M11, M22 may include advantages over other comparators. For example, the voltage comparator 300 can allow for a faster transition from digital 0 to digital 1 at node 301. In applications where the voltage comparator 300 is used as a protection circuit to protect additional downstream devices from high voltages, the voltage comparator 300 can provide additional protection due to its fast switching speed. Moreover, compared to comparators without a boost circuit, the design of the voltage comparator 300 results in only a slightly increased silicon area and only a slightly increased power usage or no increase in power usage. Specifically, it is expected that the voltage level of INP is low enough during normal operation such that the proportion of the Iboost current carried by the transistor M11 is relatively large, and the proportion of the current carried by the transistor M22 is relatively small. Thus, during normal operation, the current Itotal is approximately equal to the current Ibias, and little or no additional current is mirrored at the transistors M1 and M2. In other words, when INP remains low compared to INN during normal operation, there may be little or no power waste

[0049] The scope of the specific implementation is not limited to Figure 3 the specific examples. For example, various designs can use different relative sizes of the transistor M22 relative to the other transistors M1, M2, and M11. The relative size of the transistor M22, as well as the magnitudes of the currents Iboost and Ibias and the impedances of the loads 304, 303, can be selected to provide an appropriate amount of predictive voltage rise at node 301 for a given application. Additionally, the buffer 302 can be designed to have a gain such that when the value of INP is equal to or higher than the value of INN, it can be interpreted as digital 1 by a downstream source (e.g., the voltage protection circuit 240)

[0050] Now, an example method for operating a comparator will be discussed with reference to Figure 4 the flowchart shown in Figure 2is performed during its operation to monitor and detect overvoltage conditions. The voltage comparator function may be performed by a voltage comparator (such as Figure 3 voltage comparator 300).

[0051] At operation 410, the method includes mirroring a first current (e.g., Itotal) in a first current mirror, thereby generating a second current (e.g., Icomp) in a second current mirror. In this example, the first current mirror is coupled to the second current mirror. Such an arrangement is illustrated in Figure 3 where the first current mirror includes transistors M5 and M6, and the second current mirror includes transistors M3 and M4.

[0052] At operation 420, the method includes applying a first voltage to a first transistor and applying a second voltage to a second transistor. An example is shown in Figure 3 where INP is applied to the gate of transistor M1 and a reference voltage INN is applied to the gate of transistor M2. Further in this example, the first transistor and the second transistor are coupled between the second current mirror and a first load, and the first transistor and the second transistor jointly receive the first current and split the first current into corresponding portions.

[0053] At operation 430, the method includes applying a first voltage to a third transistor and applying a second voltage to a fourth transistor. For example, as shown in Figure 3 transistor M11 receives voltage INP at its gate and transistor M22 receives voltage INN at its gate.

[0054] Continuing with operation 430, the third transistor and the fourth transistor split a boost current (e.g., Iboost), and the fourth transistor is coupled to the first current mirror such that its corresponding portion of the boost current is added to a bias current (e.g., Ibias) in the first current mirror. Thus, the current Ibias is added to the portion of the boost current attributable to the fourth transistor (e.g., M22) to provide a superimposed current (e.g., Itotal).

[0055] As described above, during normal operation, when INP has a voltage level lower than the reference voltage INN, the current Itotal is substantially equal to the current Ibias. However, as the proportion of Iboost attributable to transistor M22 increases, Itotal also increases, as does Icomp.

[0056] At operation 440, the method includes changing the state of the output of the comparator in response to a change in the value of the first voltage relative to the second voltage. For example, as voltage INP increases and approaches the voltage level of INN, the output state of the comparator can be digital 0. However, once voltage INP equals or is higher than the voltage level of reference voltage INN, the output of the comparator becomes digital 1. In Figure 3 the example of Figure 3 , buffer 302 applies gain to the voltage at node 301, and voltage comparator 300 is designed such that the voltage at node 301 is shown as digital 1 after the gain is applied. For example, the sizing of transistor M2, the impedance of load 303, and the sizing of Icomp can be designed such that when the voltage level of INP is greater than or equal to the voltage level of INN, the voltage level seen at CMP_OUT is at a level that is decoded as digital 1. However, the scope of the specific implementation is not limited to outputting digital 1 when the voltage level of INP crosses INN.

[0057] Each voltage comparator specific implementation can include predictive bias boosting such that when the voltage level of INP rises but has not yet reached the voltage level of INN, the proportion of the current attributable to transistor M22 increases, and the proportion of the current attributable to transistor M2 also increases. The increased proportion of the current attributable to transistor M2 can then charge the capacitance at the output of the comparator (e.g., at node 301). The charging of the capacitance allows the voltage level at the node to rise, but not necessarily to a level that would be decoded as a state change. Instead, the voltage comparator is designed such that when the voltage level of INP is greater than or equal to the voltage level of INN, the voltage at the node is associated with a state change.

[0058] The scope of the specific implementation is not limited to the series of operations Figure 4 described. Instead, other specific implementations can add, omit, rearrange, or modify one or more of these operations. For example, during the operation of the comparator, the changed state of the output of the comparator can be decoded as a digital 1 or digital 0 at a voltage protection circuit (such as Figure 2 voltage protection circuit 240 of Figure 2 ). In one example, voltage protection circuit 240 includes a shunt transistor (not shown) that receives CMP_OUT at its gate, and the changed state of the comparator turns on the shunt transistor such that a surge current at INP is directed to ground.

[0059] In another example, the voltage protection circuit 240 includes series transistors controlled by CMP_OUT such that they turn off upon a state change and prevent inrush current from reaching the codec chip 230. The scope of the specific implementation is not limited to any particular voltage protection circuit 240, as any suitable structure for protecting the application processor 210 and the codec chip 230 from overvoltage conditions can be used.

[0060] Furthermore, it is expected that the overvoltage condition only exists for a fraction of a second, and once that fraction of a second ends, the voltage level of INP will return to the normal operating range below the reference voltage level INN. When the voltage level of INP decreases such that it is less than the voltage level of INN, the state of the voltage comparator can change accordingly. For example, if the overvoltage condition results in a digital 1 state at CMP_OUT, the normal voltage condition where INP is below INN can result in a digital 0 state at CMP_OUT. Vice versa, this can also hold true in other specific implementations.

[0061] Some specific implementations can be part of a normally-on overvoltage protection scheme. For example, the voltage comparator 300 can be powered on as long as the reference voltage INN is provided and as long as the bias voltage Ibias and the boost voltage Iboost are provided. Additionally, the example specific implementation operates continuously rather than cautiously and thus does not consume clock resources.

[0062] As those skilled in the art will understand so far and depending on the particular application at hand, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of using the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific implementations illustrated and described herein (as they are only some examples of the present disclosure), but should be fully equivalent to the appended claims below and their functional equivalents.

[0063] Specific implementation examples are described in the following numbered clauses:

[0064] 1. A voltage comparator, the voltage comparator comprising:

[0065] A first current mirror coupled to a first current source;

[0066] A second current mirror coupled to the first current mirror;

[0067] A first transistor and a second transistor, the first transistor and the second transistor being coupled to the second current mirror and a first load, wherein the first transistor has a first voltage input, and wherein the second transistor has a second voltage input, an output terminal of the voltage comparator being coupled between the second transistor and the first load; and a third transistor and a fourth transistor, the third transistor and the fourth transistor being coupled to a second current source, the third transistor being coupled to a second load, and the fourth transistor being coupled to the first current mirror, the third transistor having a third voltage input and receiving a first voltage identical to the first voltage input, the fourth transistor having a fourth voltage input and receiving a second voltage identical to the second voltage input, and further wherein the fourth transistor is larger than the third transistor.

[0068] 2. The voltage comparator according to clause 1, wherein the second voltage input is coupled to a direct current (DC) reference voltage.

[0069] 3. The voltage comparator according to clause 2, wherein the first voltage input is coupled to an audio input transmission line.

[0070] 4. The voltage comparator according to any one of clauses 1 to 3, wherein the first voltage input is coupled to a data input transmission line.

[0071] 5. The voltage comparator according to any one of clauses 1 to 4, wherein a drain of the fourth transistor is coupled to a drain of another transistor in the first current mirror.

[0072] 6. The voltage comparator according to clause 5, wherein a total current through the drain of the another transistor is equal to a current through the drain of the fourth transistor plus a current of the first current source.

[0073] 7. The voltage comparator according to any one of clauses 1 to 6, wherein the third transistor is a replica of the first transistor, and wherein the fourth transistor is a replica of the second transistor.

[0074] 8. The voltage comparator according to any one of clauses 1 to 7, the voltage comparator further comprising a buffer coupled to the output terminal of the voltage comparator.

[0075] 9. A method of comparing a first voltage and a second voltage, the method comprising:

[0076] Mirroring a first current in a first current mirror so as to generate a second current in a second current mirror, the first current

[0077] mirror being coupled to the second current mirror;

[0078] Apply the first voltage to the first transistor and apply the second voltage to the second transistor, wherein the first transistor and the second transistor are coupled to the second current mirror and a first load, and wherein the first crys

[0079] tal transistor and the second transistor receive the second current;

[0080] Apply the first voltage to the third transistor and apply the second voltage to the fourth transistor, wherein the third transistor is coupled to a second load, and wherein the fourth transistor is larger than the third transistor and is coupled to the first current mirror, the third transistor and the fourth transistor shunt a boost current, and wherein the first current includes a portion of the boost current from the fourth transistor that is added to a bias current; and

[0081] Change the state of the output terminal of the comparator at least in part based on a change in the value of the first voltage relative to the second voltage.

[0082] 10. The method according to clause 9, the method further comprising charging a capacitor in the first load before changing the state of the output terminal of the comparator.

[0083] 11. The method according to any one of clauses 9 to 10, wherein a change in the value of the first voltage relative to the second voltage includes an increase in the first voltage and the first voltage crossing the second voltage, and further wherein during the increase in the first voltage and before the first voltage crosses the second voltage, a portion of the first current through the second transistor increases and charges a capacitor at the output terminal of the comparator.

[0084] 12. The method according to any one of clauses 9 to 11, wherein a change in the value of the first voltage relative to the second voltage

[0085] is associated with an overvoltage condition, the method further comprising:

[0086] Increase a proportion of the second current associated with the second transistor as the first voltage increases, wherein the state of the output terminal of the comparator is at least in part based on the proportion of the second current.

[0087] 13. The method according to clause 12, wherein the overvoltage condition includes an increase in the first voltage to become greater than or equal to the second voltage, and wherein the second voltage maintains a constant voltage level.

[0088] 14. The method according to clause 13, the method further comprising:

[0089] The shunt transistor is controlled at least in part based on the state of the output terminal of the comparator, including turning on the shunt transistor and conducting a surge current associated with the overvoltage condition to ground.

[0090] 15. The method according to any one of clauses 9 to 14, the method further comprising:

[0091] Measuring the output of the comparator at the drain of the second transistor.

[0092] 16. The method according to any one of clauses 9 to 15, wherein the change in the value of the first voltage includes the first voltage increasing at least in part based on a charging cable inserted into a wireless device including the comparator.

[0093] 17. A wireless communication device, the wireless communication device comprising:

[0094] An application processor;

[0095] An audio signal amplifier;

[0096] A charging integrated circuit, wherein the application processor, the audio signal amplifier, and the charging integrated circuit are coupled to a set of wires through a multiplexing function;

[0097] A data and charging plug, the data and charging plug being coupled to the set of wires; and

[0098] A voltage comparator, the voltage comparator being coupled to at least one of the set of wires, wherein the voltage comparator includes:

[0099] A boost circuit having a first transistor and a second transistor coupled to a first current source, wherein the gate of the first transistor is coupled to a reference voltage, and wherein the gate of the second transistor is coupled to at least one of the set of wires, wherein the first transistor is configured to conduct a first portion of a first current of the first current source to a first current mirror;

[0100] A second current source coupled to the first current mirror;

[0101] A second current mirror coupled to the first current mirror; and

[0102]

[0103]

[0104] ​​A third transistor and a fourth transistor, the third transistor and the fourth transistor being coupled to the second current mirror, the gate of the third transistor being coupled to at least one of the set of wires, and the gate of the fourth transistor being coupled to the reference voltage, and further wherein the first transistor is larger than the second transistor, the third transistor, and the fourth transistor.

[0105] 18. The wireless communication device according to clause 17, wherein the data and charging plug comprises a Universal Serial Bus (USB) plug.

[0106] 19. The wireless communication device according to any one of clauses 17 to 18, the wireless communication device further comprising:

[0107] A voltage protection circuit, the voltage protection circuit being coupled to the output of the voltage comparator and being coupled between the data and charging plug and the application processor.

[0108] 20. The wireless communication device according to clause 19, the wireless communication device further comprising:

[0109] A codec chip, the codec chip comprising the set of wires, the audio signal amplifier, and the multiplexing function, wherein the voltage protection circuit is coupled between the data and charging plug and the codec chip.

[0110] 21. The wireless communication device according to any one of clauses 17 to 20, wherein the sources of the first transistor and the second transistor are coupled to the first current source, and wherein the drain of the first transistor is coupled to the first current mirror.

[0111] 22. The wireless communication device according to clause 21, wherein the sources of the third transistor and the fourth transistor are coupled to the second current mirror and the drains are coupled to a load.

[0112] 23. The wireless communication device according to clause 22, wherein the first transistor is a replica of the fourth transistor, and wherein the second transistor is a replica of the third transistor.

[0113] 24. The wireless communication device according to clause 23, wherein the second transistor, the third transistor, and the fourth transistor have the same size.

[0114] 25. The wireless communication device according to any one of clauses 17 to 24, the wireless communication device further comprising a buffer coupled to the drain of the fourth transistor.

[0115] 26. A wireless communication device, the wireless communication device comprising:

[0116] A comparator, the comparator being coupled to a reference voltage and coupled to a wire, the wire being configured to conduct direct current (DC) charging, an audio signal, and data;

[0117] Components for biasing the comparator; and

[0118] Components for boosting the DC bias level of the comparator, including shunting a first current from a first current source at least partially based on a difference between the reference voltage and a voltage level of the wire, further including conductively superimposing a first portion of the first current to a second current in the components for biasing, and conducting a second portion of the first current to a load, wherein a first transistor configured to conduct the first portion of the first current is larger than a second transistor configured to conduct the second portion of the first current.

[0119] 27. The wireless communication device according to clause 26, wherein the components for biasing the comparator include:

[0120] A second current source, the second current source being coupled to a first current mirror, wherein the first current mirror is coupled to the

[0121] first transistor; and

[0122] A second current mirror, the second current mirror being coupled to the first current mirror and a first pair of transistors, wherein an output terminal of the comparator is coupled between the first pair of transistors and the load.

[0123] 28. The wireless communication device according to any one of clauses 26 to 27, the wireless communication device further including:

[0124] Components for multiplexing between the DC charging, the audio signal, and the data.

[0125] 29. The wireless communication device according to clause 28, wherein the comparator, the components for biasing the comparator, the components for boosting the DC bias level, and the components for multiplexing are implemented on an encoder-decoder (codec) chip.

[0126] 30. The wireless communication device according to clause 29, wherein the wire is coupled to a data and charging plug of the wireless communication device.

Claims

1. A voltage comparator, the voltage comparator comprising: a first current mirror coupled to a first current source; a second current mirror coupled to the first current mirror; a first transistor and a second transistor coupled to the second current mirror and a first load, wherein the first transistor has a first voltage input, and wherein the second transistor has a second voltage input, and an output terminal of the voltage comparator is coupled between the second transistor and the first load; and a third transistor and a fourth transistor coupled to a second current source, the third transistor coupled to a second load, and the fourth transistor coupled to the first current mirror, the third transistor having a third voltage input and receiving the same first voltage as the first voltage input, the fourth transistor having a fourth voltage input and receiving the same second voltage as the second voltage input, and further wherein the fourth transistor is larger than the third transistor.

2. The voltage comparator according to claim 1, wherein the second voltage input is coupled to a direct current (DC) reference voltage.

3. The voltage comparator according to claim 2, wherein the first voltage input is coupled to an audio input transmission line.

4. The voltage comparator according to claim 2, wherein the first voltage input is coupled to a data input transmission line.

5. The voltage comparator according to claim 1, wherein a drain of the fourth transistor is coupled to a drain of another transistor in the first current mirror.

6. The voltage comparator according to claim 5, wherein a total current through the drain of the another transistor is equal to a current through the drain of the fourth transistor plus a current of the first current source.

7. The voltage comparator according to claim 1, wherein the third transistor is a replica of the first transistor, and wherein the fourth transistor is a replica of the second transistor.

8. The voltage comparator according to claim 1, the voltage comparator further comprising a buffer coupled to the output terminal of the voltage comparator.

9. A method of comparing a first voltage and a second voltage, the method comprising: mirroring a first current in a first current mirror to generate a second current in a second current mirror, the first current mirror coupled to the second current mirror; applying the first voltage to a first transistor and applying the second voltage to a second transistor, wherein the first transistor and the second transistor are coupled to the second current mirror and a first load, and wherein the first transistor and the second transistor receive the second current; Apply the first voltage to the third transistor and the second voltage to the fourth transistor, where the third transistor is coupled to a second load, and where the fourth transistor is larger than the third transistor and is coupled to the first current mirror, the third transistor and the fourth transistor shunt a boost current, and where the first current includes a portion of the boost current from the fourth transistor that is added to a bias current; and change a state of an output terminal of a comparator at least partially based on a change in a value of the first voltage relative to the second voltage.

10. The method according to claim 9, the method further comprising charging a capacitance in the first load before changing the state of the output terminal of the comparator.

11. The method according to claim 9, where the change in the value of the first voltage relative to the second voltage includes an increase in the first voltage and the first voltage crossing the second voltage, further where during the increase in the first voltage and before the first voltage crosses the second voltage, a portion of the first current through the second transistor increases and charges a capacitance at the output terminal of the comparator.

12. The method according to claim 9, where the change in the value of the first voltage relative to the second voltage is associated with an overvoltage condition, the method further comprising: increasing a proportion of the second current associated with the second transistor as the first voltage increases, where the state of the output terminal of the comparator is at least partially based on the proportion of the second current.

13. The method according to claim 12, where the overvoltage condition includes the first voltage increasing to become greater than or equal to the second voltage, and where the second voltage maintains a constant voltage level.

14. The method according to claim 13, the method further comprising: controlling a shunt transistor at least partially based on the state of the output terminal of the comparator, including turning on the shunt transistor and conducting a surge current associated with the overvoltage condition to ground.

15. The method according to claim 9, the method further comprising: measuring the output of the comparator at a drain of the second transistor.

16. The method according to claim 9, where the change in the value of the first voltage includes the first voltage increasing at least partially based on a charging cable inserted into a wireless device including the comparator.

17. A wireless communication device, the wireless communication device comprising: an application processor; an audio signal amplifier; a charging integrated circuit, where the application processor, the audio signal amplifier, and the charging integrated circuit are coupled to a set of wires through a multiplexing function; a data and charging plug, the data and charging plug being coupled to the set of wires; and a voltage comparator, the voltage comparator being coupled to at least one of the set of wires, where the voltage comparator includes: A boost circuit having a first transistor and a second transistor coupled to a first current source, wherein the gate of the first transistor is coupled to a reference voltage and wherein the gate of the second transistor is coupled to at least one of the set of wires, wherein the first transistor is configured to conduct a first portion of a first current of the first current source to a first current mirror; A second current source coupled to the first current mirror; A second current mirror coupled to the first current mirror; and A third transistor and a fourth transistor coupled to the second current mirror, the gate of the third transistor coupled to at least one of the set of wires and the gate of the fourth transistor coupled to the reference voltage, further wherein the first transistor is larger than the second transistor, the third transistor, and the fourth transistor.

18. The wireless communication device according to claim 17, wherein the data and charging plug includes a Universal Serial Bus (USB) plug.

19. The wireless communication device according to claim 17, the wireless communication device further comprises: A voltage protection circuit coupled to the output of the voltage comparator and coupled between the data and charging plug and the application processor.

20. The wireless communication device according to claim 19, the wireless communication device further comprises: A codec chip including the set of wires, the audio signal amplifier, and the multiplexing function, wherein the voltage protection circuit is coupled between the data and charging plug and the codec chip.

21. The wireless communication device according to claim 17, wherein the source of the first transistor and the second transistor are coupled to the first current source, and wherein the drain of the first transistor is coupled to the first current mirror.

22. The wireless communication device according to claim 21, wherein the source of the third transistor and the fourth transistor are coupled to the second current mirror and the drain is coupled to a load.

23. The wireless communication device according to claim 22, wherein the first transistor is a replica of the fourth transistor, and wherein the second transistor is a replica of the third transistor.

24. The wireless communication device according to claim 23, wherein the second transistor, the third transistor, and the fourth transistor have the same size.

25. The wireless communication device according to claim 17, the wireless communication device further includes a buffer coupled to the drain of the fourth transistor.

26. A wireless communication device, the wireless communication device comprises: A comparator coupled to a reference voltage and coupled to a wire configured to conduct direct current (DC) charging, an audio signal, and data; Components for biasing the comparator; and A component for boosting the DC bias level of the comparator, including shunting a first current from a first current source at least partially based on the difference between the reference voltage and the voltage level of the wire, further including conductively superimposing a first portion of the first current to a second current in the component for biasing, and conducting a second portion of the first current to a load, wherein a first transistor configured to conduct the first portion of the first current is larger than a second transistor configured to conduct the second portion of the first current.

27. The wireless communication device according to claim 26, wherein the component for biasing the comparator comprises: A second current source coupled to a first current mirror, wherein the first current mirror is coupled to the first transistor; and A second current mirror coupled to the first current mirror and a first pair of transistors, wherein the output terminal of the comparator is coupled between the first pair of transistors and the load.

28. The wireless communication device according to claim 26, the wireless communication device further comprises: A component for multiplexing among the DC charging, the audio signal, and the data.

29. The wireless communication device according to claim 28, wherein the comparator, the component for biasing the comparator, the component for boosting the DC bias level, and the component for multiplexing are implemented on an encoder-decoder (codec) chip.

30. The wireless communication device according to claim 29, wherein the wire is coupled to the data and charging plug of the wireless communication device.

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