Nitride semiconductor device

Abstract

A nitride semiconductor device (10) is provided with a first nitride semiconductor layer (16), a second nitride semiconductor layer (18) formed on the first nitride semiconductor layer (16) and having a band gap larger than that of the first nitride semiconductor layer (16), and a gate electrode (32), a source electrode (24), and a drain electrode (26) formed above the second nitride semiconductor layer (18). The first nitride semiconductor layer (16) is a layer containing GaN. The first nitride semiconductor layer (16) has a half-value width of an X-ray rocking curve with respect to the (102) plane of from 1100 arcsec to 1400 arcsec (inclusive).

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device. Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) is underway. Patent Document 1 describes an example of an enhancement-mode HEMT using a nitride semiconductor.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-73506 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In a HEMT device using a nitride semiconductor, when the increase in the on-resistance during device operation is large, it may not be possible to ensure the given device characteristics. From the viewpoint of improving the reliability of HEMT products, it is required to suppress the increase in the on-resistance in either an enhancement-mode or depletion-mode HEMT device.

[0008] Means for Solving the Problems

[0009] A nitride semiconductor device according to one aspect of the present disclosure includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap larger than that of the first nitride semiconductor layer; and a gate electrode, a source electrode, and a drain electrode formed above the second nitride semiconductor layer. The first nitride semiconductor layer is a layer containing GaN. The full width at half maximum of the X-ray rocking curve of the first nitride semiconductor layer with respect to the (102) plane is 1100 arcsec or more and 1400 arcsec or less.

[0010] Effects of the Invention are as follows.

[0011] A nitride semiconductor device according to one aspect can suppress the increase in the on-resistance. Brief Description of the Drawings

[0012] Figure 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to an embodiment.

[0013] Figure 2 is a schematic cross-sectional view showing an exemplary structure of various nitride semiconductor layers formed on a semiconductor substrate in the Figure 1 nitride semiconductor device.

[0014] Figure 3 is a view schematically showing the (102) plane of the first nitride semiconductor layer.

[0015] Figure 4 is a view schematically showing screw dislocations.

[0016] Figure 5 is a view schematically showing edge dislocations.

[0017] Figure 6 is a graph showing the relationship between the XRC full width at half maximum of the first nitride semiconductor layer with respect to the (102) plane and the change rate of the on-resistance, which is measured for various nitride semiconductor devices including the first nitride semiconductor layer having different crystal defect densities. Detailed Embodiments

[0018] Hereinafter, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings.

[0019] In addition, in order to make the drawings and the description concise and clear, the constituent elements shown in the drawings are not necessarily drawn at a certain scale. For easy understanding, sometimes the characteristic parts are enlarged, and the dimensional ratios of the constituent elements are not necessarily the same in each drawing. The drawings are merely examples of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0020] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0021] [1. Overall Structure of Nitride Semiconductor Device]

[0022] Figure 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to an embodiment. The nitride semiconductor device 10 is, for example, a HEMT using GaN. The nitride semiconductor device 10 includes a semiconductor substrate 12, a buffer layer 14 formed on the semiconductor substrate 12, a first nitride semiconductor layer 16 formed on the buffer layer 14, and a second nitride semiconductor layer 18 formed on the first nitride semiconductor layer 16.

[0023] The semiconductor substrate 12 can be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. For example, the semiconductor substrate 12 is a Si substrate. The thickness of the semiconductor substrate 12 can be set to, for example, 200 μm or more and 1500 μm or less. In addition, Figure 1 the Z-axis direction of the mutually orthogonal XYZ axes shown is perpendicular to the main surface of the semiconductor substrate 12 ( Figure 1The direction orthogonal to the upper surface). In this specification, the term "top view" refers to observing the nitride semiconductor device 10 from above along the Z-axis direction unless otherwise specified explicitly.

[0024] The buffer layer 14 includes one or more nitride semiconductor layers. For example, the buffer layer 14 can be composed of any material that can suppress warping of the semiconductor substrate 12 and generation of cracks in the nitride semiconductor device 10 caused by the mismatch in the thermal expansion coefficients between the semiconductor substrate 12 and the first nitride semiconductor layer 16.

[0025] In some embodiments, the buffer layer 14 includes at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 can be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. The following refers to Figure 2 An exemplary structure of the buffer layer 14 will be described.

[0026] The first nitride semiconductor layer 16 is a layer containing GaN. In some embodiments, the first nitride semiconductor layer 16 includes a GaN composite layer in which a plurality of GaN layers are stacked. The thickness of the first nitride semiconductor layer 16 can be set to, for example, 0.5 μm or more and 2 μm or less. The following refers to Figure 2 An exemplary structure of the first nitride semiconductor layer 16 will be described.

[0027] The second nitride semiconductor layer 18 is composed of a nitride semiconductor having a larger bandgap than that of the first nitride semiconductor layer 16. The second nitride semiconductor layer 18 can be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the second nitride semiconductor layer 18 as an AlGaN layer has a larger bandgap than the first nitride semiconductor layer 16 including the GaN composite layer. In one example, the second nitride semiconductor layer 18 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably 0.1 < x < 0.3. The thickness of the second nitride semiconductor layer 18 can be set to, for example, 5 nm or more and 20 nm or less.

[0028] The first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 are made of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the first nitride semiconductor layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the second nitride semiconductor layer 18 form a lattice-mismatched heterojunction. Due to the spontaneous polarization of the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 and the piezoelectric polarization caused by the crystal strain near the heterojunction interface, the energy level of the conduction band of the first nitride semiconductor layer 16 near the heterojunction interface is lower than the Fermi level. As a result, in the position of the first nitride semiconductor layer 16 close to the heterojunction interface with the second nitride semiconductor layer 18 (e.g., within a range of about several nm from the interface), a two-dimensional electron gas (2DEG) 20 diffuses in the first nitride semiconductor layer 16.

[0029] The nitride semiconductor device 10 includes a gate structure 22, a source electrode 24, a drain electrode 2 formed on the second nitride semiconductor layer 18, and a passivation layer 28 formed on the second nitride semiconductor layer 18 and covering the gate structure 22. The passivation layer 28 includes a source-side opening 28A and a drain-side opening 28B that respectively expose a part of the upper surface of the second nitride semiconductor layer 18. The passivation layer 28 can be composed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 28 can be set, for example, to be 80 nm or more and 150 nm or less.

[0030] As Figure 1 shown, in some embodiments, the gate structure 22 includes a gate layer 30 and a gate electrode 32 formed on the gate layer 30. The gate layer 30 can be, for example, a GaN layer doped with acceptor-type impurities, that is, a p-type GaN layer. In this case, the acceptor-type impurities can be, for example, at least one of zinc (Zn), magnesium (Mg), and carbon (C). For example, the maximum concentration of the acceptor-type impurities in the gate layer 30 can be set to be 7×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0031] The gate layer 30 is located between the source-side opening 28A and the drain-side opening 28B of the passivation layer 28 in the Figure 1 shown X-axis direction. The gate layer 30 is separated from the source-side opening 28A and the drain-side opening 28B and is located at a position closer to the source-side opening 28A than the drain-side opening 28B.

[0032] The gate electrode 32 includes one or more metal layers. In some embodiments, the gate electrode 32 is formed of, for example, a titanium nitride (TiN) layer. In other embodiments, the gate electrode 32 is formed using a first metal layer made of Ti (titanium) and a second metal layer provided on the first metal layer and made of TiN. The gate electrode 32 and the gate layer 30 form a Schottky junction. The thickness of the gate electrode 32 can be set, for example, to be 50 nm or more and 200 nm or less.

[0033] The source electrode 24 and the drain electrode 26 include one or more metal layers. For example, the source electrode 24 and the drain electrode 26 can be formed of one or any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a part of the source electrode 24 is filled in the source-side opening 28A and is in ohmic contact with the 2DEG directly below the second nitride semiconductor layer 18 via the source-side opening 28A. Similarly, at least a part of the drain electrode 26 is filled in the drain-side opening 28B and is in ohmic contact with the 2DEG directly below the second nitride semiconductor layer 18 via the drain-side opening 28B. In Figure 1 the example of, the semiconductor substrate 12 is connected to the source electrode 24, and a voltage having the same potential as the source electrode 24 is applied to the semiconductor substrate 12.

[0034] [2. Exemplary gate structure]

[0035] As described above, in Figure 1 the example of, the gate structure 22 includes a gate layer 30 and a gate electrode 32. The gate layer 30 includes an upper surface where the gate electrode 32 is located and a bottom surface that abuts against the second nitride semiconductor layer 18. In some embodiments, the gate layer 30 includes: a gate layer main body 34 including the upper surface of the gate layer 30; and a source-side extension 36 and a drain-side extension 38 that are each thinner than the gate layer main body 34. The gate layer main body 34, the source-side extension 36, and the drain-side extension 38 all abut against the second nitride semiconductor layer 18.

[0036] The source-side extension 36 extends from the gate layer main body 34 toward the source-side opening 28A. A passivation layer 28 exists between the source electrode 24 embedded in the source-side opening 28A and the source-side extension 36. On the other hand, the drain-side extension 38 extends from the gate layer main body 34 toward the drain-side opening 28B. A passivation layer 28 exists between the drain electrode 26 embedded in the drain-side opening 28B and the drain-side extension 38.

[0037] The gate layer main body 34 is located between the source-side extension 36 and the drain-side extension 38 and is integrally formed with the source-side extension 36 and the drain-side extension 38. In Figure 1In the example, the main body portion 34 of the gate layer is formed to have a ridge-shaped cross section (a rectangular cross section). Among them, the cross-sectional shape of the main body portion 34 of the gate layer is not particularly limited. For example, it may also be a trapezoidal cross section or other cross-sectional shapes. Due to the existence of the source-side extension portion 36 and the drain-side extension portion 38, the bottom surface of the gate layer 30 has a larger area than the upper surface of the gate layer 30.

[0038] As Figure 1 shown, in some embodiments, the drain-side extension portion 38 extends longer than the source-side extension portion 36 toward the outside of the main body portion 34 of the gate layer in a top view. That is, the drain-side extension portion 38 may have a larger size than the source-side extension portion 36 in the X-axis direction. The size (length) of the source-side extension portion 36 in the X-axis direction may be, for example, 0.2 μm or more and 0.3 μm or less. The size (length) of the drain-side extension portion 38 in the X-axis direction may be, for example, 0.2 μm or more and 0.6 μm or less.

[0039] The main body portion 34 of the gate layer corresponds to the thicker portion of the gate layer 30. The thickness of the main body portion 34 of the gate layer can be set to, for example, 80 nm or more and 150 nm or less. The thickness of the main body portion 34 of the gate layer can be determined in consideration of various parameters including the gate threshold voltage. The source-side extension portion 36 and the drain-side extension portion 38 each have a smaller thickness than the main body portion 34 of the gate layer. For example, the source-side extension portion 36 and the drain-side extension portion 38 may each have a thickness of half or less of the main body portion 34 of the gate layer.

[0040] The source-side extension portion 36 and the drain-side extension portion 38 may each include a flat portion having a substantially constant thickness. The thickness of the flat portion of the source-side extension portion 36 and the thickness of the flat portion of the drain-side extension portion 38 can be set to, for example, 5 nm or more and 25 nm or less. In addition, in this specification, "substantially constant thickness" means that the thickness is within the range of manufacturing deviation (for example, 20%). And, as Figure 1 shown, in some embodiments, the source-side extension portion 36 and the drain-side extension portion 38 may each include an intermediate portion thicker than the flat portion between the flat portion and the main body portion 34 of the gate layer. In one example, the intermediate portion may have a thickness that gradually decreases away from the main body portion 34 of the gate layer.

[0041] In Figure 1In the gate structure 22, a gate layer 30 including acceptor-type impurities is provided directly below the gate electrode 32. In this structure, when the gate-source voltage exceeds a positive threshold voltage due to the gate input voltage applied to the gate electrode 32, a channel (current path) of 2DEG20 is formed in the region of the first nitride semiconductor layer 16 directly below the main body portion 34 of the gate layer, whereby conduction between the source and drain is established. On the other hand, when the gate-source voltage does not exceed the threshold voltage, 2DEG20 disappears in at least a part of the region of the first nitride semiconductor layer 16 directly below the main body portion 34 of the gate layer (see Figure 1 ). This is because, since the main body portion 34 of the gate layer includes acceptor-type impurities, the energy levels of the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 are raised, so that 2DEG20 is depleted. Thus, the nitride semiconductor device 10 is realized as an enhancement-mode HEMT.

[0042] [3. Exemplary field plate electrode structure]

[0043] As Figure 1 shown, in some embodiments, the nitride semiconductor device 10 includes a field plate electrode 40 formed on the passivation layer 28. In Figure 1 the example, the field plate electrode 40 is formed integrally with the source electrode 24 and covers the entire gate structure 22 in a top view. In this structure, the field plate electrode 40 can also be regarded as a part of the source electrode 24, and a voltage having the same potential as the source electrode 24 is applied to the field plate electrode 40. Here, the field plate electrode 40 may be provided separately from the source electrode 24, or a control voltage other than the source voltage may be applied to the field plate electrode 40.

[0044] The field plate electrode 40 is separated from the drain electrode 26. The field plate electrode 40 includes an end portion 40A that is located between the gate layer 30 (drain side extension portion 38) and the drain electrode 26 (drain side opening portion 28B) in a top view. The field plate electrode 40 functions as follows: when a drain voltage is applied to the drain electrode 26 in a zero bias state where no gate input voltage is applied to the gate electrode 32, the electric field concentration near the end portion of the gate electrode 32 and near the end portion of the gate layer 30 is alleviated.

[0045] [4. Exemplary structures of various nitride semiconductor layers on a semiconductor substrate]

[0046] Figure 2 is a schematic cross-sectional view showing an exemplary structure of various nitride semiconductor layers formed on the semiconductor substrate 12. As described above, a buffer layer 14, a first nitride semiconductor layer 16, a second nitride semiconductor layer 18, and a gate layer 30 (third nitride semiconductor layer) are sequentially formed on the semiconductor substrate 12. Hereinafter, the exemplary structures of the respective layers will be described in sequence.

[0047] [4-1. Buffer Layer]

[0048] First, an exemplary structure of the buffer layer 14 will be described. In some embodiments, the buffer layer 14 may include a first buffer layer 52 formed on the semiconductor substrate 12 and a second buffer layer 54 formed on the first buffer layer 52. The first buffer layer 52 may be, for example, an AlN layer. The thickness of the first buffer layer 52 can be set, for example, to be 100 nm or more and 300 nm or less.

[0049] The second buffer layer 54 may be, for example, an AlGaN composite layer in which a plurality of AlGaN layers are stacked. In some embodiments, the second buffer layer 54 may be a graded AlGaN layer in which a plurality of AlGaN layers having different aluminum (Al) compositions are stacked. In Figure 2 the example, the second buffer layer 54 is formed as a graded AlGaN layer in which three AlGaN layers, namely a first AlGaN layer 54A, a second AlGaN layer 54B, and a third AlGaN layer 54C, are sequentially stacked. The thicknesses of the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C can be set, for example, to be 100 nm or more and 300 nm or less.

[0050] The third AlGaN layer 54C is located at the uppermost layer of the second buffer layer 54 (buffer layer 14). In some embodiments, the third AlGaN layer 54C may have a lower Al composition and a larger thickness than the second AlGaN layer 54B. On the other hand, the second AlGaN layer 54B may have a lower Al composition than the first AlGaN layer 54A and can have the same thickness as the first AlGaN layer 54A. For example, the thicknesses of the first AlGaN layer 54A and the second AlGaN layer 54B may be about 100 nm, respectively, and the thickness of the third AlGaN layer 54C may be 2 times or more the thickness of the second AlGaN layer 54B, for example, 200 nm or more. Also, the ratios of the Al compositions in the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C may be about 80% (±5%), about 50% (±5%), and about 20% (±5%), respectively.

[0051] The third AlGaN layer 54C has a different Al composition from the second AlGaN layer 54B (in Figure 2In the example, the Al composition is lower than that of the second AlGaN layer 54B, and thus it is grown in a state strained with respect to the lattice constant of the second AlGaN layer 54B. Here, the thickness of the third AlGaN layer 54C is larger than the thickness of the second AlGaN layer 54B. Therefore, the generation of lattice relaxation (dislocations) is promoted in the third AlGaN layer 54C in order to relieve the internal stress (strain caused by lattice mismatch) accumulated as strain in the third AlGaN layer 54C. As a result, the density of crystal defects caused by lattice relaxation increases. Therefore, in some embodiments, in order to increase the density of crystal defects in the buffer layer 14 (and thus, in order to increase the density of crystal defects in the first nitride semiconductor layer 16), for example, the third AlGaN layer 54C is configured to have an Al composition lower than that of the second AlGaN layer 54B and a large thickness. Alternatively, in order to increase the density of crystal defects in the buffer layer 14, the number of AlGaN layers forming the second buffer layer 54 and the thickness of each layer are adjusted.

[0052] The buffer layer 14 may include impurities that form acceptor levels. The impurities in the buffer layer 14 may be at least one of carbon (C) and iron (Fe), for example. And the concentration of the impurities can be set to 4×10 16 cm -3 or more. In some embodiments, such impurities are introduced into a part of the buffer layer 14 to make the buffer layer 14 semi-insulating, so that leakage current in the buffer layer 14 can be suppressed and breakdown voltage can be improved. For example, in the second buffer layer 54, the impurities may be introduced only into the third AlGaN layer 54C, or only into the second AlGaN layer 54B and the third AlGaN layer 54C. Alternatively, the impurities may be introduced into all of the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C of the second buffer layer 54. The layer doped with impurities that form acceptor levels in the first AlGaN layer 54A to the third AlGaN layer 54C corresponds to the impurity-doped AlGaN layer.

[0053] [4-2. First Nitride Semiconductor Layer]

[0054] Next, an exemplary structure of the first nitride semiconductor layer 16 will be described. As described above, the first nitride semiconductor layer 16 may include a GaN composite layer in which a plurality of GaN layers are stacked. In some embodiments, the GaN composite layer may be formed by alternately stacking an impurity-doped GaN layer doped with impurities that form acceptor levels and an undoped GaN layer one or more times. The uppermost layer of the GaN composite layer is an undoped GaN layer. In addition, the term "undoped GaN layer" used in the present disclosure is defined as a GaN layer into which impurities are not intentionally introduced.

[0055] In the GaN composite layer, impurities in the impurity-doped GaN layer can be, for example, carbon (C). Moreover, the concentration of impurities in the impurity-doped GaN layer can be set to 5×10 17c m -3 or more and 5×10 19 cm -3 or less. In some embodiments, by introducing such impurities into a part of the first nitride semiconductor layer 16, at least locally outside the surface layer region of the first nitride semiconductor layer 16 becomes semi-insulating, and leakage current in the first nitride semiconductor layer 16 can be suppressed and breakdown voltage can be increased.

[0056] In Figure 2 an example, the first nitride semiconductor layer 16 is formed as a GaN composite layer having a three-layer structure in which three GaN layers, namely a first GaN layer 62, a second GaN layer 64, and a third GaN layer 66, are stacked in sequence. The first GaN layer 62 is an undoped GaN layer, the second GaN layer 64 is an impurity-doped GaN layer, and the third GaN layer 66 is an undoped GaN layer. The 2DEG 20 (see Figure 1 ) that becomes the channel of the HEMT is formed in the third GaN layer 66 located at the uppermost layer of the GaN composite layer (the first nitride semiconductor layer 16). The third GaN layer 66 that generates the 2DEG 20 is also functionally referred to as an electron transport layer.

[0057] The first GaN layer 62, the second GaN layer 64, and the third GaN layer 66 may have the same thickness, or may have different thicknesses. The thickness of the first GaN layer 62 can be, for example, 50 nm or more and 300 nm or less, the thickness of the second GaN layer 64 can be, for example, 300 nm or more and 600 nm or less. Moreover, the thickness of the third GaN layer 66 can be, for example, 200 nm or more and 500 nm or less. As described above, the thickness of the GaN composite layer, that is, the first nitride semiconductor layer 16 as a whole can be set to 0.5 μm or more and 2 μm or less.

[0058] In some embodiments, in order to increase the crystal defect density of the first nitride semiconductor layer 16, the number of layers and the thickness of each layer of one or more impurity-doped GaN layers (the second GaN layer 64 in Figure 2 the example) and / or one or more undoped GaN layers (in Figure 2In the example, the number of layers (the first GaN layer 62 and the third GaN layer 66) and the thickness of each layer. Crystal defects are formed as a plurality of dislocations (through dislocations) linearly extending in the stacking direction throughout both the impurity-doped GaN layer and the undoped GaN layer. The plurality of dislocations show a tendency to combine with each other and decrease during propagation in the undoped GaN layer located on the impurity-doped GaN layer (or the impurity-doped AlGaN layer of the buffer layer 14). Therefore, for example, thinning the undoped GaN layer formed on the impurity-doped GaN layer (or the impurity-doped AlGaN layer of the buffer layer 14) can suppress the reduction of dislocations in the undoped GaN layer and maintain the crystal defect density of the first nitride semiconductor layer 16. In addition, the significance of controlling the crystal defect density of the first nitride semiconductor layer 16 will be described below.

[0059] [4-3. Second Nitride Semiconductor Layer and Gate Layer (Third Nitride Semiconductor Layer)]

[0060] In Figure 2 the example, the second nitride semiconductor layer 18 is an AlGaN layer, and the gate layer 30 is a p-type GaN layer. The second nitride semiconductor layer 18 is also functionally referred to as an electron supply layer with respect to the electron transport layer (the third GaN layer 66) of the first nitride semiconductor layer 16. By providing a p-type GaN layer as the gate layer 30, the nitride semiconductor device 10 is configured as an enhancement-mode HEMT as described above.

[0061] [5. Acceptor Compensation Based on Crystal Defect Density Control]

[0062] Next, with reference to Figures 3 - 6 , acceptor compensation based on crystal defect density control will be described. In the nitride semiconductor device 10 configured as an HEMT, electron traps at relatively deep acceptor levels in the crystal of the first nitride semiconductor layer 16 or the buffer layer 14 are the main cause of the increase in on-resistance.

[0063] Specifically, when electrons are captured by acceptor levels in the crystal, the carrier (electron) concentration of the 2DEG 20 generated in the first nitride semiconductor layer 16 (in Figure 2 the example, the electron supply layer formed by the third GaN layer 66) decreases. As a result, the channel potential rises, and thus the on-resistance rises. In particular, electrons captured by relatively deep acceptor levels in the crystal are not easily released, so the on-resistance can be maintained at a high level. Such relatively deep acceptor levels can be formed, for example, by implanting impurities into the first nitride semiconductor layer 16 and / or the buffer layer 14.

[0064] In order to compensate for acceptors, which are the main cause of the above-mentioned electron traps, and suppress the increase in on-resistance, the first nitride semiconductor layer 16 is configured such that its crystal defect density is maintained within a predetermined range. Crystal defects caused by crystal strain contribute to the formation of donor energy levels. From this perspective, in order to form donor energy levels that compensate for acceptors, the crystal defect density in the crystal of the first nitride semiconductor layer 16 and / or the crystal of the buffer layer 14 is controlled.

[0065] Here, the evaluation of the crystal defect density is usually performed using X-ray Rocking Curve (XRC) measurement. The full width at half maximum (FWHM) of the XRC is used as an index value for quantifying the crystal strain, and thus has a correlation with the crystal defect density. More precisely, the full width at half maximum refers to the full width at half maximum (FWHM), but is hereinafter simply referred to as the full width at half maximum.

[0066] In some embodiments, the crystal defect density of the first nitride semiconductor layer 16 is controlled such that the XRC full width at half maximum of the first nitride semiconductor layer 16 for the (102) plane is 1100 arcsec or more and 1400 arcsec or less. Hereinafter, for the sake of simplicity of description, the "XRC full width at half maximum for the (102) plane" of the first nitride semiconductor layer 16 may sometimes be simply referred to as the "(102) full width at half maximum". By maintaining the (102) full width at half maximum within this range, it is possible to compensate for acceptors using donor energy levels brought about by crystal defects and suppress the increase in on-resistance. In addition, the relationship between the (102) full width at half maximum and the on-resistance change rate will be described below.

[0067] Figure 3 is a diagram schematically showing the (102) plane of the first nitride semiconductor layer 16. The (102) plane of the first nitride semiconductor layer 16 is a crystal plane with Miller indices (102) in the hexagonal crystal that is the unit lattice of GaN forming the first nitride semiconductor layer 16, corresponding to Figure 3 the crystal plane M102 of the hexagonal crystal HC shown. And the X-ray rocking curve for the (102) plane refers to the rocking curve obtained by X-ray diffraction for the (102) plane.

[0068] Here, the types of crystal defects (dislocations) include screw dislocations and edge dislocations as lattice arrangement offsets formed in the stacking direction of the crystal layer structure. A screw dislocation is a dislocation formed obliquely with respect to the direction perpendicular to the stacking plane of the crystal layer structure. Specifically, it is formed by the inclination of the crystal axis of the crystal growth orientation. An edge dislocation is a dislocation formed in the direction perpendicular to the stacking plane of the crystal layer structure. Specifically, it is formed by the torsion of the crystal axis in the plane.

[0069] Figure 4 is a diagram schematically showing a screw dislocation, Figure 5 is a diagram schematically showing an edge dislocation. In addition, Figure 4 and Figure 5 only shows one layer in a hexagonal crystal system having a crystal stacking structure in the X-axis direction, Figure 4 is a front view of a part of the crystal structure, Figure 5 is Figure 4 a top view of the crystal structure.

[0070] As Figure 4 shown, the screw dislocation is formed by the inclination of the c-axis C2 of the hexagonal crystal HC2 with respect to the c-axis C1 of the hexagonal crystal HC1 (and Figure 5 the c-axis C4 of the hexagonal crystal HC4). As Figure 5 shown, due to the inclination of the c-axis C2, a lattice arrangement shift D1 inclined with respect to the direction (Z-axis direction) perpendicular to the stacking plane of the crystal stacking structure is formed between the hexagonal crystal HC2 and the hexagonal crystals HC1 and HC4. This lattice arrangement shift D1 continues in the thickness direction (X-axis direction) of the first nitride semiconductor layer 16, thereby forming a crystal defect (through dislocation) caused by the screw dislocation.

[0071] On the other hand, as Figure 5 shown, the edge dislocation is formed by the torsion around the c-axis C3 of the hexagonal crystal HC3. Due to the torsion of the c-axis C3, a lattice arrangement shift D2 along the direction (Z-axis direction) perpendicular to the stacking plane of the crystal stacking structure is formed between the hexagonal crystal HC3 and the hexagonal crystals HC1 and HC4. This lattice arrangement shift D2 continues in the thickness direction (X-axis direction) of the first nitride semiconductor layer 16, thereby forming a crystal defect (through dislocation) caused by the edge dislocation.

[0072] The XRC full width at half maximum of the first nitride semiconductor layer 16 for the (102) plane becomes an index value reflecting both of the above lattice arrangement shifts D1 and D2, that is, both the crystal defect caused by the screw dislocation and the crystal defect caused by the edge dislocation.

[0073] Figure 6It is a graph showing the relationship between the XRC half-value width of the first nitride semiconductor layer 16 with respect to the (102) plane and the change rate of on-resistance ΔRon measured for various nitride semiconductor devices 10 including the first nitride semiconductor layer 16 with different crystal defect densities. In addition, the change rate of on-resistance ΔRon is derived by measuring the on-resistance before and after performing a High Temperature Reverse Bias (HTRB) test on the nitride semiconductor device 10 to be measured. And the HTRB test is performed by applying a stress voltage (e.g., 80% of the rated voltage (e.g., 150V)) for a predetermined time (e.g., 60 hours or more) to the drain electrode 26 of the HEMT in the off state in a high temperature environment (e.g., about 150°C).

[0074] As Figure 6 shown, the change rate of on-resistance ΔRon varies according to the XRC half-value width of the first nitride semiconductor layer 16 with respect to the (102) plane. Moreover, as the (102) half-value width increases, that is, as the crystal defect density of the first nitride semiconductor layer 16 increases, the change rate of on-resistance ΔRon decreases. In some embodiments, the allowable range of the change rate of on-resistance ΔRon is set to 40% or less. Figure 6 Among them, the (102) half-value width satisfying this allowable range is 1100 arcsec or more and 1250 arcsec or less.

[0075] Here, although not shown in Figure 6 even when the (102) half-value width is 1250 arcsec or more, as the (102) half-value width increases, the change rate of on-resistance ΔRon also decreases. Among them, if donor energy levels are excessively formed in the crystal of the first nitride semiconductor layer 16 or the buffer layer 14 due to the introduction of multiple crystal defects, the breakdown voltage of the first nitride semiconductor layer 16 may decrease due to leakage current passing through the crystal defects (through dislocations) as a path. Considering this, the (102) half-value width is set to 1100 arcsec or more and 1400 arcsec or less.

[0076] [6. Function of Nitride Semiconductor Device]

[0077] When a drain voltage is applied to the drain electrode 26 of the nitride semiconductor device 10 configured as a HEMT, electrons are trapped by acceptor levels present in the crystal of the first nitride semiconductor layer 16 or the buffer layer 14. This electron trapping is the main cause of the increase in the on-resistance. Therefore, the first nitride semiconductor layer 16 is configured to have a crystal defect density sufficient to provide donor levels that compensate for acceptors. Specifically, the crystal defect density of the first nitride semiconductor layer 16 is controlled so that the (102) full width at half maximum of the first nitride semiconductor layer 16, which is an index representing the crystal defect density, is 1100 arcsec or more and 1400 arcsec or less.

[0078] The first nitride semiconductor layer 16 may include a GaN composite layer in which one or more undoped GaN layers and one or more impurity-doped GaN layers are alternately stacked. In such a GaN composite layer, the crystal defect density of the first nitride semiconductor layer 16 can be controlled by adjusting the number of undoped GaN layers and the thickness of each layer, and / or the number of impurity-doped GaN layers and the thickness of each layer.

[0079] In Figure 2 the example, the first nitride semiconductor layer 16 includes a GaN composite layer in which a first GaN layer 62 (undoped GaN layer), a second GaN layer 64 (impurity-doped GaN layer), and a third GaN layer 66 (undoped GaN layer) are stacked. The thickness of the first GaN layer 62 is, for example, 50 nm or more and 300 nm or less, the thickness of the second GaN layer 64 is, for example, 300 nm or more and 600 nm or less, and the third GaN layer 66 is, for example, 200 nm or more and 500 nm or less.

[0080] Additionally or alternatively, the buffer layer 14 may include an AlGaN composite layer in which a plurality of AlGaN layers are stacked. In such an AlGaN composite layer, the crystal defect density of the buffer layer 14 can be controlled by adjusting the number of AlGaN layers and the thickness of each layer, and / or the ratio of the Al composition in each AlGaN layer. Thereby, the crystal defect density of the first nitride semiconductor layer 16 formed on the buffer layer 14 can be controlled.

[0081] In Figure 2In the example, the buffer layer 14 includes a first buffer layer 52 formed of an AlN layer and a second buffer layer 54 formed of an AlGaN composite layer in which a first AlGaN layer 54A, a second AlGaN layer 54B, and a third AlGaN layer 54C are stacked. The thicknesses of the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C are each, for example, 100 nm or more and 300 nm or less. In this case, the thickness of the third AlGaN layer 54C can be, for example, 2 times or more the thickness of the second AlGaN layer 54B, for example, 200 nm or more. The Al composition ratios of the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C are approximately 80% (±5%), approximately 50% (±5%), and approximately 20% (±5%), respectively.

[0082] Also, in Figure 2 the example, the third AlGaN layer 54C of the second buffer layer 54 (AlGaN composite layer) has a lower Al composition and a larger thickness than the second AlGaN layer 54B. Thereby, by promoting the generation of lattice relaxation (dislocation) in the third AlGaN layer 54C, the density of crystal defects caused by lattice relaxation increases. As a result, the density of crystal defects in the first nitride semiconductor layer 16 formed on the buffer layer 14 can be increased. In this way, by controlling the density of crystal defects in the buffer layer 14, the density of crystal defects in the first nitride semiconductor layer 16 can be controlled.

[0083] The nitride semiconductor device 10 of one embodiment has the following advantages.

[0084] (1) The nitride semiconductor device 10 is configured such that the full width at half maximum of the XRC for the (102) plane of the first nitride semiconductor layer 16 is 1100 arcsec or more and 1400 arcsec or less. According to this structure, the density of crystal defects in the first nitride semiconductor layer 16 can be maintained at a density of crystal defects sufficient to compensate for the donor levels of acceptors that are the main cause of electron traps. Thereby, a decrease in the carrier (electron) concentration of the 2DEG 20 generated in the first nitride semiconductor layer 16 can be suppressed, and an increase in the on-resistance can be suppressed.

[0085] (2) The full width at half maximum of the XRC for the (102) plane of the first nitride semiconductor layer 16 is an index indicating the density of crystal defects reflecting both crystal defects caused by edge dislocations and crystal defects caused by screw dislocations. Thereby, the density of crystal defects in the first nitride semiconductor layer 16 can be controlled with high precision.

[0086] (3) The first nitride semiconductor layer 16 includes a GaN composite layer in which a first GaN layer 62, a second GaN layer 64, and a third GaN layer 66 are stacked. The first GaN layer 62 and the third GaN layer 66 are undoped GaN layers, and the second GaN layer 64 is an impurity-doped GaN layer doped with carbon (C) as an impurity. In this structure, by adjusting the respective thicknesses of the first GaN layer 62, the second GaN layer 64, and the third GaN layer 66, the crystal defect density of the first nitride semiconductor layer 16 can be controlled. Further, since the first nitride semiconductor layer 16 includes an impurity-doped GaN layer (the second GaN layer 64), the leakage current in the first nitride semiconductor layer 16 can be suppressed and the breakdown voltage can be increased.

[0087] (4) The buffer layer 14 includes an AlGaN composite layer (the second buffer layer 14) in which a first AlGaN layer 54A, a second AlGaN layer 54B, and a third AlGaN layer 54C are stacked. The third AlGaN layer 54C is located at the uppermost layer of the AlGaN composite layer and has an Al composition lower than that of the second AlGaN layer 54B directly below it and a large thickness. For example, in this structure, by adjusting the respective thicknesses and / or the ratio of the Al composition of the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C, the crystal defect density of the buffer layer 14 can be controlled. Thereby, the crystal defect density of the first nitride semiconductor layer 16 formed on the buffer layer 14 can be controlled.

[0088] (5) In the buffer layer 14, at least one of the first AlGaN layer 54A, the second AlGaN layer 54B, and the third AlGaN layer 54C is an impurity-doped AlGaN layer doped with at least one of carbon (C) and iron (Fe) as an impurity. According to this structure, since the buffer layer 14 includes an impurity-doped AlGaN layer, the leakage current in the buffer layer 14 can be suppressed and the breakdown voltage can be increased.

[0089] (6) In the nitride semiconductor device 10, the gate structure 22 includes a gate layer 30 formed on the second nitride semiconductor layer 18 and a gate electrode 32 formed on the gate layer 30. The gate layer 30 is formed of a GaN layer including an acceptor-type impurity, that is, a p-type GaN layer. By providing such a gate layer 30, the nitride semiconductor device 10 can be configured as an enhancement-mode HEMT.

[0090] [Modification Example]

[0091] Each of the above embodiments can be implemented with the following modifications. Further, the above embodiments and the following modification examples can be implemented in combination with each other within a range where no technical contradiction occurs.

[0092] · The nitride semiconductor device 10 is not limited to the reference Figure 1Regarding the structure of the above-described embodiment, for example, the nitride semiconductor device 10 of the above-described embodiment is configured as an enhancement-mode HEMT. However, the structure of the present disclosure is not limited to an enhancement-mode HEMT and can also be applied to a depletion-mode HEMT. For example, by omitting the gate layer 30 from the nitride semiconductor device 10 (or forming the gate layer 30 as a nitride semiconductor layer that does not include acceptor-type impurities), the nitride semiconductor device 10 can be configured as a depletion-mode HEMT.

[0093] · The first nitride semiconductor layer 16 is not limited to the structure of the above-described embodiment described with reference to Figure 2 Regarding the structure of the above-described embodiment. The first nitride semiconductor layer 16 only needs to be a layer including GaN and is not necessarily limited to a structure including a GaN composite layer. Of course, the number of layers and the structure of the GaN composite layer are not particularly limited either. For example, in addition to the GaN layer, the first nitride semiconductor layer 16 may also include other nitride semiconductor layers (such as an AlN layer, etc.), and the crystal defect density of the first nitride semiconductor layer 16 can also be adjusted by other layer structures.

[0094] · The buffer layer 14 is not limited to the structure of the above-described embodiment described with reference to Figure 2 Regarding the structure of the above-described embodiment and may also include other nitride semiconductor layers. Of course, the number of layers and the structure of the AlGaN composite layer are not particularly limited either.

[0095] · The gate layer 30 is not limited to a structure including the source-side extension 36 and the drain-side extension 38 and may also be a structure including only the gate layer main body 34. Also, the structures and shapes of the source electrode 24 and the drain electrode 26 are not limited to Figure 1 The structures and shapes shown.

[0096] In the present disclosure, the term "on ~" includes the meanings of "on ~" and "above ~" unless it is clearly indicated otherwise according to the context. Therefore, for example, the expression "the first element is mounted on the second element" means in one embodiment that the first element can be directly disposed in contact with the second element on the second element, but in other embodiments it means that the first element can be disposed above the second element without contacting the second element. That is, the term "on ~" does not exclude a structure in which other elements are formed between the first element and the second element.

[0097] In the present disclosure, the Z-axis direction used is not necessarily the vertical direction and does not need to be exactly the same as the vertical direction. Therefore, the various structures of the present disclosure are not limited to the "above" and "below" in the Z-axis direction described in this specification being the "above" and "below" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0098] In the present disclosure, numerals such as "first ~" and "second ~" are used only to clearly distinguish the constituent components, and it is not necessary to have the constituent components in order.

[0099] [Supplementary Note]

[0100] The technical ideas that can be grasped from the above-described embodiments and modification examples are described below. In addition, the symbols of the constituent elements of the embodiments corresponding to the constituent elements described in each supplementary note are shown as examples for assisting understanding, and the constituent elements described in each supplementary note should not be limited to the constituent elements indicated by the symbols.

[0101] (Supplementary Note A1)

[0102] A nitride semiconductor device 10 includes:

[0103] A first nitride semiconductor layer 16;

[0104] A second nitride semiconductor layer 18 formed on the first nitride semiconductor layer 16 and having a band gap larger than that of the first nitride semiconductor layer 16; and

[0105] A gate electrode 32, a source electrode 24, and a drain electrode 26 formed above the second nitride semiconductor layer 18,

[0106] The first nitride semiconductor layer 16 is a layer containing GaN,

[0107] The full width at half maximum of the X-ray rocking curve of the first nitride semiconductor layer 16 with respect to the (102) plane is 1100 arcsec or more and 1400 arcsec or less.

[0108] (Supplementary Note A2)

[0109] The nitride semiconductor device 10 according to Supplementary Note A1, wherein

[0110] The first nitride semiconductor layer 16 includes a GaN composite layer in which a plurality of GaN layers 62, 64, and 66 are stacked,

[0111] The GaN composite layer is formed by alternately stacking an impurity-doped GaN layer 64 doped with impurities forming an acceptor level and undoped GaN layers 62 and 66,

[0112] The uppermost layer of the GaN composite layer is formed of the undoped GaN layer 66,

[0113] The second nitride semiconductor layer 18 is formed on the undoped GaN layer 66 located at the uppermost layer of the GaN composite layer.

[0114] (Supplementary Note A3)

[0115] The nitride semiconductor device 10 according to Supplementary Note A2, wherein,

[0116] It further includes a semiconductor substrate 12 and a buffer layer 14 formed on the semiconductor substrate 12,

[0117] The GaN composite layer has a three-layer structure including a first GaN layer 62 located on the buffer layer 14, a second GaN layer 64 located on the first GaN layer 62, and a third GaN layer 66 located on the second GaN layer 64,

[0118] The first GaN layer 62 and the third GaN layer 66 are respectively formed of the undoped GaN layer,

[0119] The second GaN layer 64 is formed of the impurity-doped GaN layer,

[0120] The second nitride semiconductor layer 18 is formed on the third GaN layer 66.

[0121] (Supplementary Note A4)

[0122] The nitride semiconductor device 10 according to Supplementary Note A3, wherein,

[0123] The first GaN layer 62 has a thickness of 50 nm or more and 300 nm or less.

[0124] (Supplementary Note A5)

[0125] The nitride semiconductor device (10) according to any one of Supplementary Notes A2 to A4, wherein,

[0126] The impurity in the impurity-doped GaN layer 64 is carbon (C).

[0127] (Supplementary Note A6)

[0128] The nitride semiconductor device 10 according to Supplementary Note A1, wherein,

[0129] It further includes a semiconductor substrate 12 and a buffer layer 14 formed on the semiconductor substrate 12,

[0130] The first nitride semiconductor layer 16 is formed on the buffer layer 14,

[0131] The buffer layer 14 includes an AlGaN composite layer 54 in which a plurality of AlGaN layers 54A, 54B, 54C are stacked,

[0132] The uppermost AlGaN layer 54C among the multiple AlGaN layers 54A, 54B, 54C has an aluminum composition lower than that of the AlGaN layer 54B directly below the uppermost AlGaN layer 54C and a larger thickness.

[0133] (Appendix A7)

[0134] The nitride semiconductor device 10 according to Appendix A6, wherein,

[0135] At least one of the multiple AlGaN layers 54A, 54B, 54C is an impurity-doped AlGaN layer 54A; 54B; 54C doped with impurities that form acceptor levels.

[0136] (Appendix A8)

[0137] The nitride semiconductor device 10 according to Appendix A7, wherein,

[0138] The impurity in the impurity-doped AlGaN layer 54A; 54B; 54C is at least one of carbon (C) and iron (Fe).

[0139] (Appendix A9)

[0140] The nitride semiconductor device 10 according to any one of Appendices A6 to A8, wherein,

[0141] The first nitride semiconductor layer 16 includes a GaN composite layer in which multiple GaN layers 62, 64, 66 are stacked,

[0142] The multiple GaN layers 62, 64, 66 include:

[0143] A first GaN layer 62, which is located on the AlGaN composite layer 54 and is formed of an undoped GaN layer;

[0144] A second GaN layer 64, which is located on the first GaN layer 62 and is formed of an impurity-doped GaN layer doped with impurities that form acceptor levels; and

[0145] A third GaN layer 66, which is located on the second GaN layer 64 and is formed of an undoped GaN layer,

[0146] The second nitride semiconductor layer 18 is formed on the third GaN layer 66.

[0147] (Appendix A10)

[0148] The nitride semiconductor device 10 according to any one of Appendices A1 to A9, wherein,

[0149] Further, there is provided a third nitride semiconductor layer 30 formed on the second nitride semiconductor layer 18 and including an acceptor-type impurity.

[0150] The gate electrode (32) is formed on the third nitride semiconductor layer 30.

[0151] (Appendix B1)

[0152] A nitride semiconductor device 10 includes:

[0153] A semiconductor substrate 12;

[0154] A buffer layer 14 formed on the semiconductor substrate 12;

[0155] A first nitride semiconductor layer 16 formed on the buffer layer 14;

[0156] A second nitride semiconductor layer 18 formed on the first nitride semiconductor layer 16 and having a band gap larger than that of the first nitride semiconductor layer 16; and

[0157] A gate electrode 32, a source electrode 24, and a drain electrode 26 formed above the second nitride semiconductor layer 18,

[0158] The buffer layer 14 includes an AlGaN composite layer 54 in which a plurality of AlGaN layers 54A, 54B, 54C are stacked.

[0159] The first nitride semiconductor layer 16 includes a GaN composite layer in which a plurality of GaN layers 62, 64, 66 are stacked.

[0160] The GaN composite layer is formed by alternately stacking an impurity-doped GaN layer 64 doped with an impurity that forms an acceptor level and undoped GaN layers 62; 66.

[0161] The uppermost layer of the GaN composite layer is formed by the undoped GaN layer 66.

[0162] The second nitride semiconductor layer 18 is formed on the undoped GaN layer 66 that is the uppermost layer of the GaN composite layer.

[0163] The uppermost AlGaN layer 54C among the plurality of AlGaN layers 54A, 54B, 54C has a lower aluminum composition and a larger thickness than the AlGaN layer 54B directly below the uppermost AlGaN layer 54C.

[0164] (Appendix B2)

[0165] The nitride semiconductor device 10 according to Appendix B1, wherein

[0166] The above-mentioned GaN composite layer has a three-layer structure including a first GaN layer 62 located on the above-mentioned buffer layer 14, a second GaN layer 64 located on the above-mentioned first GaN layer 62, and a third GaN layer 66 located on the above-mentioned second GaN layer 64.

[0167] The above-mentioned first GaN layer 62 and the above-mentioned third GaN layer 66 are respectively formed of the above-mentioned undoped GaN layer.

[0168] The above-mentioned second GaN layer 64 is formed of the above-mentioned impurity-doped GaN layer.

[0169] The above-mentioned second nitride semiconductor layer 18 is formed on the above-mentioned third GaN layer 66.

[0170] (Supplementary Note B3)

[0171] The nitride semiconductor device 10 according to Supplementary Note B1 or B2, wherein

[0172] At least one of the above-mentioned plurality of AlGaN layers 54A, 54B, 54C is an impurity-doped AlGaN layer 54A; 54B; 54C doped with impurities that form acceptor levels.

[0173] The above description is only an example. Those skilled in the art can recognize that, in addition to the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure, more possible combinations and permutations can also be made. The present disclosure aims to include all substitutions, deformations, and changes within the scope of the present disclosure including the claims.

[0174] Symbol Explanation

[0175] 10 - Nitride semiconductor device, 12 - Semiconductor substrate, 14 - Buffer layer, 16 - First nitride semiconductor layer, 18 - Second nitride semiconductor layer, 20 - Two-dimensional electron gas (2DEG), 22 - Gate structure, 24 - Source electrode, 26 - Drain electrode, 30 - Gate layer (third nitride semiconductor layer), 32 - Gate electrode, 52 - First buffer layer, 54 - Second buffer layer (AlGaN composite layer), 54A - First AlGaN layer, 54B - Second AlGaN layer, 54C - Third AlGaN layer, 62 - First GaN layer, 64 - Second GaN layer, 66 - Third GaN layer.

Claims

1. A nitride semiconductor device, characterized in that, comprising: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap larger than that of the first nitride semiconductor layer; and a gate electrode, a source electrode, and a drain electrode formed above the second nitride semiconductor layer, wherein the first nitride semiconductor layer is a layer containing GaN, and the full width at half maximum of the X-ray rocking curve of the first nitride semiconductor layer with respect to the (102) plane is 1100 arcsec or more and 1400 arcsec or less.

2. The nitride semiconductor device according to claim 1, characterized in that, the first nitride semiconductor layer includes a GaN composite layer in which a plurality of GaN layers are stacked, the GaN composite layer is formed by alternately stacking an impurity-doped GaN layer doped with an impurity that forms an acceptor level and an undoped GaN layer, the uppermost layer of the GaN composite layer is formed of the undoped GaN layer, and the second nitride semiconductor layer is formed on the undoped GaN layer that is the uppermost layer of the GaN composite layer.

3. The nitride semiconductor device according to claim 2, characterized in that, it further includes a semiconductor substrate and a buffer layer formed on the semiconductor substrate, the GaN composite layer has a three-layer structure including a first GaN layer on the buffer layer, a second GaN layer on the first GaN layer, and a third GaN layer on the second GaN layer, the first GaN layer and the third GaN layer are each formed of the undoped GaN layer, the second GaN layer is formed of the impurity-doped GaN layer, and the second nitride semiconductor layer is formed on the third GaN layer.

4. The nitride semiconductor device according to claim 3, characterized in that, the first GaN layer has a thickness of 50 nm or more and 300 nm or less.

5. The nitride semiconductor device according to any one of claims 2 to 4, characterized in that, the impurity in the impurity-doped GaN layer is carbon (C).

6. The nitride semiconductor device according to claim 1, characterized in that, it further includes a semiconductor substrate and a buffer layer formed on the semiconductor substrate, the first nitride semiconductor layer is formed on the buffer layer, the buffer layer includes an AlGaN composite layer in which a plurality of AlGaN layers are stacked, and the uppermost AlGaN layer among the plurality of AlGaN layers has a lower aluminum composition and a larger thickness than the AlGaN layer directly below the uppermost AlGaN layer.

7. The nitride semiconductor device according to claim 6, characterized in that, at least one of the plurality of AlGaN layers is an impurity-doped AlGaN layer doped with an impurity that forms an acceptor level.

8. The nitride semiconductor device according to claim 7, characterized in that, the impurity in the impurity-doped AlGaN layer is at least one of carbon (C) and iron (Fe).

9. The nitride semiconductor device according to any one of claims 6 to 8, characterized in that, The above-mentioned first nitride semiconductor layer includes a GaN composite layer in which a plurality of GaN layers are stacked, The above-mentioned plurality of GaN layers include: A first GaN layer located on the above-mentioned AlGaN composite layer and formed of an undoped GaN layer; A second GaN layer located on the above-mentioned first GaN layer and formed of an impurity-doped GaN layer doped with impurities that form acceptor levels; and A third GaN layer located on the above-mentioned second GaN layer and formed of an undoped GaN layer, The above-mentioned second nitride semiconductor layer is formed on the above-mentioned third GaN layer.

10. The nitride semiconductor device according to any one of claims 1 to 9, characterized in that, It further includes a third nitride semiconductor layer formed on the above-mentioned second nitride semiconductor layer and including acceptor-type impurities, The above-mentioned gate electrode is formed on the above-mentioned third nitride semiconductor layer.

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