A Simulation Verification Method for Improving the Clamping Effect of ESD Devices

Abstract

The present invention relates to the technical field of data simulation, and particularly to a method for simulating and verifying the clamping effect of an improved ESD device. This method obtains the clamping voltage, pulse current, and device temperature of the device; calculates the temperature influence coefficient according to the correlation between the clamping voltage and temperature in device testing; analyzes the rising degree of the clamping voltage under different pulse events to determine the conduction moment; evaluates the degree of device performance degradation according to the variation characteristics of the pulse current and capacitance after the conduction moment; corrects the clamping voltages of different times based on the degree of device performance degradation and the temperature influence coefficient to obtain the corrected clamping voltages; compares the corrected clamping voltages with the calibrated clamping voltages, and combines the conduction duration to determine the stability effect value of the clamping voltage. The present invention improves the accuracy of data simulation of the clamping voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of data simulation, and particularly to a method for simulating and verifying the clamping effect of an improved ESD device. Background Art

[0002] The negative resistance type ESD device is a kind of device used to protect circuits from damage caused by Electro-Static Discharge (ESD). The main function of the ESD device is to provide efficient electrostatic discharge protection and reduce circuit failures or damages caused by electrostatic release. When an electrostatic discharge occurs instantaneously, the negative resistance characteristic in the ESD device can quickly absorb or disperse charges, and rapidly convert the overvoltage into current. The voltage of the device will be clamped at a specific value, and this voltage is the clamping voltage. Therefore, the stability of the clamping voltage is an important index to characterize the protection performance of the ESD device.

[0003] Currently, when simulating and verifying the clamping voltage of an ESD device, generally an external pulse voltage source is connected to conduct repeated pulse discharge tests on the ESD device by simulating the instantaneous high voltage of the ESD event. However, with the occurrence of clamping during multiple discharges, the ESD protection device will absorb energy, heat gradually accumulates, the temperature rises, resulting in changes in the electrical characteristics of the device, causing the clamping voltage of the device to gradually shift and rise, and the clamping voltage gradually deviates, affecting the accuracy of the simulation effect, reducing the accuracy of judging the stable state of the clamping voltage, and making it difficult to evaluate the protection performance of the ESD device. Summary of the Invention

[0004] In order to solve the technical problem that heat gradually accumulates, and then the clamping voltage gradually shifts and rises, affecting the accuracy of judging the stable state of the clamping voltage, the purpose of the present invention is to provide a method for simulating and verifying the clamping effect of an improved ESD device, and the specific technical solution adopted is as follows:

[0005] In a first aspect, an embodiment of the present invention provides a method for simulating and verifying the clamping effect of an improved ESD device, and the method includes:

[0006] Obtain the clamping voltage, pulse current, and device temperature of the device;

[0007] Calculate the temperature influence coefficient according to the correlation between the clamping voltage and the device temperature during device testing;

[0008] Analyze the rising degree of the clamping voltage under different high-voltage pulses, and determine the conduction moment; evaluate the degree of device performance degradation according to the change characteristics of the pulse current and capacitance after the conduction moment;

[0009] Based on the degree of device performance degradation and the temperature influence coefficient, correct the clamping voltages of different times to obtain the corrected clamping voltages;

[0010] Compare the clamped voltage after correction with the calibrated clamped voltage, and combine the conduction duration to determine the stability effect value of the clamped voltage.

[0011] Further, calculating the temperature influence coefficient according to the correlation between the clamped voltage and the device temperature in the device test includes:

[0012] Determine the heat accumulation weight after each high-voltage pulse according to the proportion of the test duration corresponding to each high-voltage pulse and the change in the clamped voltage of adjacent high-voltage pulses;

[0013] Combine the device temperature after each high-voltage pulse and the heat accumulation weight after the high-voltage pulse to determine the temperature influence coefficient after each high-voltage pulse.

[0014] Further, determining the heat accumulation weight after each high-voltage pulse according to the proportion of the test duration corresponding to each high-voltage pulse and the change in the clamped voltage of adjacent high-voltage pulses includes:

[0015] Calculate the slope value corresponding to the clamped voltage of the current high-voltage pulse and the previous high-voltage pulse; take the product of the slope value and the proportion of the test duration corresponding to the current high-voltage pulse as the heat accumulation weight after the current high-voltage pulse.

[0016] Further, analyzing the rising degree of the clamped voltage under different high-voltage pulses to determine the conduction moment includes:

[0017] Take any moment as the target moment, use the target moment as the segmentation point, and divide the clamped voltage sequence into two sequences, including: the left clamped voltage sequence and the right clamped voltage sequence;

[0018] Determine the voltage rising degree of the left clamped voltage sequence according to the difference between adjacent values in the left clamped voltage sequence; calculate the difference between adjacent values in the right clamped voltage sequence to determine the voltage rising degree of the right clamped voltage sequence;

[0019] Take the absolute value of the difference in the voltage rising degrees of the left clamped voltage sequence and the right clamped voltage sequence as the rising difference value at the corresponding target moment; when the rising difference value is greater than the preset normal threshold for the first time, take the corresponding moment as the conduction moment.

[0020] Further, evaluating the performance degradation degree of the device according to the change characteristics of the pulse current and the capacitor after the conduction moment includes:

[0021] Compare the pulse current of the pulse event after the conduction moment with the pulse current corresponding to the calibrated clamped voltage to obtain the first degradation degree;

[0022] Compare the capacitance value of the device capacitor after the pulse event after the conduction moment with the capacitance value of the device capacitor in all previous pulse events before the conduction moment to obtain the second degree of decline;

[0023] Combine the first degree of decline and the second degree of decline to obtain the degree of performance decline of the device.

[0024] Further, the correction factors for correcting different clamping voltages include:

[0025] Before and at the conduction moment, use the normalized value of the temperature influence coefficient as the correction factor for the clamping voltage;

[0026] After the conduction moment, combine the degree of performance decline and the temperature influence coefficient to determine the correction factor for the clamping voltage.

[0027] Further, the method of correcting different clamping voltages based on the degree of performance decline of the device and the temperature influence coefficient to obtain the corrected clamping voltage includes:

[0028] Take the product between the clamping voltage and the correction factor as the correction value of the clamping voltage;

[0029] Reduce the clamping voltage by the correction value to obtain the corrected clamping voltage.

[0030] Further, the method of reducing the clamping voltage by the correction value to obtain the corrected clamping voltage includes:

[0031] Calculate the difference between the clamping voltage and the correction value as the corrected clamping voltage.

[0032] Further, the method of comparing the corrected clamping voltage with the calibrated clamping voltage and combining the conduction duration to determine the stability effect value of the clamping voltage includes:

[0033] Compare the difference between the corrected clamping voltage of each pulse event after the first pulse event and the calibrated clamping voltage as the voltage fluctuation effect value;

[0034] Obtain the proportion of the conduction duration of the device; use the proportion of the conduction duration as the weight to weight the negative correlation mapping value of the voltage fluctuation effect value to obtain the stability effect value of the clamping voltage.

[0035] Further, after determining the stability effect value of the clamping voltage, it further includes: when the stability effect value of the clamping voltage is less than the preset stability threshold, adjust the package and materials of the device.

[0036] In a second aspect, an improved ESD device clamping effect simulation verification system is provided, and the system includes the following modules:

[0037] A data acquisition module, configured to acquire the clamping voltage, pulse current, and device temperature of the device;

[0038] A temperature analysis module, configured to calculate the temperature influence coefficient according to the correlation between the clamping voltage and the device temperature during device testing;

[0039] A performance analysis module, configured to analyze the rising degree of the clamping voltage under different high-voltage pulses to determine the conduction moment; and evaluate the performance degradation degree of the device according to the change characteristics of the pulse current and capacitance after the conduction moment;

[0040] A voltage correction module, configured to correct the clamping voltages of different times based on the performance degradation degree and temperature influence coefficient of the device to obtain the corrected clamping voltage;

[0041] An effect simulation module, configured to compare the corrected clamping voltage with the calibrated clamping voltage, and determine the stable effect value of the clamping voltage in combination with the conduction duration.

[0042] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor. An executable code is stored in the memory. When the processor executes the executable code, the methods in all possible implementation embodiments of the first aspect are implemented.

[0043] In a fourth aspect, an embodiment of the present invention provides a computer program product, including: computer program code. When the computer program code runs on a computer, the computer is caused to execute the method in the first aspect or any possible implementation manner of the first aspect.

[0044] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute the methods in all possible implementation embodiments of the first aspect.

[0045] The embodiments of the present invention have at least the following beneficial effects:

[0046] First, calculate the real-time temperature influence coefficient based on the correlation between the clamping voltage and temperature during the ESD device test. Since multiple frequent high-voltage pulses will cause the temperature of this ESD device to gradually increase and the internal resistance to become larger, resulting in an increase in the clamping voltage, the deviation of the clamping voltage can be more intuitively measured through the degree of temperature influence. Subsequently, the clamping voltage can be modified in combination with the temperature influence coefficient. Then, analyze the current conduction and capacitance change characteristics under different pulses to evaluate the performance degradation degree of the device. Because the increase in temperature will also cause local overheating of the device, leading to possible degradation of the internal crystal structure, material properties, or internal electrodes, affecting the working performance of the device and indirectly affecting the magnitude of the clamping voltage. Therefore, the electrical performance degradation situation still needs to be considered when correcting the clamping voltage; and the clamping voltages of different times are corrected according to the performance degradation characteristics caused by the temperature increase of this ESD device under multiple pulses. Finally, verify the effect based on the multi-clamping voltages of the corrected ESD device to determine the stable effect value of the clamping voltage. By correcting the clamping voltage, the present invention avoids the problem of deviation in the clamping effect verification caused by the gradual accumulation of heat and the gradual offset and increase of the clamping voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0048] Figure 1 FIG. is a flowchart of a method for simulating and verifying the clamping effect of an improved ESD device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following, in combination with the accompanying drawings and preferred embodiments, will describe in detail a method for simulating and verifying the clamping effect of an improved ESD device according to the present invention, its specific implementation manner, structure, features, and effects.

[0050] In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. In addition, the specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0051] Among them, in the description of the embodiments of the present invention, unless otherwise specified, " / " means "or". For example, A / B may mean A or B. The "and / or" in the text is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "a plurality of" means two or more than two.

[0052] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as implying or suggesting relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0054] The embodiments of the present invention will be described below with reference to the accompanying drawings. As is known to those of ordinary skill in the art, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.

[0055] The specific solution of a method for simulating and verifying the clamping effect of an improved ESD device provided by the present invention will be specifically described below with reference to the accompanying drawings.

[0056] Please refer to Figure 1 , which shows a flowchart of the steps of a method for simulating and verifying the clamping effect of an improved ESD device provided by an embodiment of the present invention. The method includes the following steps:

[0057] Step S100, obtain the clamping voltage, pulse current, and device temperature of the device.

[0058] Since the traditional array-type ESD device does not have a negative resistance function, the internal structure is a wire bonding process, with a large parasitic capacitance, a high clamping voltage, and a small current; the ESD effect protection is poor. The improved ESD device described in this embodiment uses the negative resistance function to achieve a low clamping. Thus, it can better protect high-speed signals. The internal structure is a FAN-OUT process, reducing the parasitic capacitance, and performing a flyback through the conduction of the triode to solve the high clamping problem.

[0059] The clamping voltage is a key parameter for measuring the performance of ESD devices. It represents the voltage level at which the device begins to effectively suppress overvoltage and prevent further increase of this voltage. The level of the clamping voltage directly affects the protection effect of electronic components during electrostatic discharge. Currently, when simulating and modeling the clamping voltage of ESD devices, it is generally based on the IEC 61000-4-2 standard. A pulse voltage source is connected to the conductive part of the device to generate an instantaneous high-voltage current pulse to simulate the discharge situation that the device withstands in the actual usage environment. In this embodiment, the discharge voltage is set to 10 kV, the discharge waveform is usually a unipolar pulse, and the number of discharges during the test process is 500 times.

[0060] Then, collect the real-time clamping voltage of the ESD device, the pulse current when the clamping voltage is reached, and the device temperature after each discharge during each discharge process. A clamping voltage - pulse current curve can also be established based on the clamping voltage and pulse current data.

[0061] Since each discharge event releases a certain amount of electrical energy, and this energy is absorbed by the protection device, most of the electrical energy is converted into heat energy. If the device discharges frequently in a short period of time, heat will accumulate. This heat accumulation may cause changes in the resistance and conduction characteristics of the internal materials of the device, and then be manifested as a gradual increase in the clamping voltage. Thus, it leads to errors in the simulation verification effect of the clamping voltage. Therefore, in this embodiment, the clamping voltage is corrected by analyzing the temperature increase degree and performance degradation characteristics of the device under multiple pulses to ensure the reliability of the verification effect.

[0062] Step S200, calculate the temperature influence coefficient according to the correlation between the clamping voltage and the device temperature during device testing.

[0063] Regarding the problem that the temperature accumulation caused by multiple high-voltage pulse simulations will cause the clamping voltage to gradually deviate from the calibrated value, in this step, first calculate the real-time temperature influence coefficient based on the correlation between the clamping voltage and the temperature during the ESD device testing process. Then, combine the performance degradation characteristics of this ESD device under multiple pulse events to correct the clamping voltages of different times. Finally, verify the clamping effect based on the multiple clamping voltages of the corrected ESD device.

[0064] Since multiple frequent high-voltage pulses will cause the temperature of this ESD device to gradually increase and the internal resistance to become larger, which in turn leads to an increase in the clamping voltage, while in this embodiment, the real-time clamping voltage is corrected. Then, the degree of influence of temperature can more intuitively measure the deviation or increase of the clamping voltage. Therefore, in this step, first determine the temperature influence coefficient based on the relationship between the temperature and the clamping voltage after each pulse event.

[0065] First, establish a corresponding correlation curve based on the device temperature and the clamping voltage after each pulse event.

[0066] As the test progresses, the device temperature and the clamping voltage gradually increase. However, different temperature ranges have different degrees of influence on the device characteristics. At lower temperatures, the influence on the clamping voltage may be relatively small, but as the temperature accumulates, the influence may increase sharply. Therefore, it is unreasonable to simply correct the clamping voltage based on the real-time temperature change. In this step, different weights need to be set for the temperatures under different pulse events to improve its accuracy.

[0067] Here, different weights are set for the device temperatures after different pulses. Since the temperature gradually accumulates with the test time, that is, the test duration is positively correlated with the temperature, and at the same time, the real-time temperature growth rate also represents the degree of influence on the device.

[0068] In some embodiments, the method for obtaining the temperature influence coefficient is as follows:

[0069] Determine the heat accumulation weight after each high-voltage pulse according to the ratio of the test duration corresponding to each high-voltage pulse and the change in the clamping voltage of adjacent high-voltage pulses.

[0070] Then, combine the device temperature after each high-voltage pulse and the heat accumulation weight after the high-voltage pulse to determine the temperature influence coefficient after each high-voltage pulse.

[0071] The ratio of the test duration corresponding to the high-voltage pulse here represents the timing weight of the current high-voltage pulse. As the number of high-voltage pulses gradually increases, the high-voltage pulse time also gradually increases, then the corresponding heat accumulation increases, and the corresponding timing weight is larger. The greater the change in the clamping voltage of adjacent high-voltage pulses, the more obvious the rise in the clamping voltage after this high-voltage pulse, the more serious the heat accumulation, and the larger the corresponding real-time weight.

[0072] In some embodiments, the change in the clamping voltage of adjacent high-voltage pulses is taken as the slope value of the clamping voltage of the device in the current high-voltage pulse and the clamping voltage of the device in the previous high-voltage pulse. The calculation method of this slope value is the ratio of the difference in the clamping voltage of the device in the current high-voltage pulse and the previous high-voltage pulse to the time difference between the two high-voltage pulses.

[0073] Furthermore, by weighting the device temperature at the corresponding moment of the device with the heat accumulation weight after the high-voltage pulse to obtain the real-time temperature influence coefficient, the actual working conditions of the device can be more accurately matched, and unreasonable corrections under certain temperature conditions can be avoided.

[0074] In some embodiments, the product value of the device temperature after each high-voltage pulse and the heat accumulation weight after the high-voltage pulse is used as the temperature influence coefficient after each high-voltage pulse.

[0075] The greater the temperature influence coefficient corresponding to a certain high-voltage pulse, the greater the influence of the temperature at this moment on the clamping voltage of the device, so as to improve the reliability of subsequent clamping voltage correction.

[0076] Step S300: Analyze the rising degree of the clamping voltage under different high-voltage pulses, and determine the conduction moment; according to the change characteristics of the pulse current and capacitance after the conduction moment, evaluate the degree of device performance degradation.

[0077] According to step S200, the temperature influence coefficient is obtained based on the temperature change of the device. However, it should be noted that the increase in temperature will also cause local overheating of the device, resulting in possible degradation of the internal crystal structure, material properties or internal electrodes, affecting the working performance of the device, and indirectly affecting the magnitude of the clamping voltage. Therefore, the electrical performance degradation situation still needs to be considered during the correction process. This step analyzes the electrical performance degradation situation of the device and combines the temperature influence coefficient to correct the clamping voltage.

[0078] As the device is tested under high temperature and high voltage conditions for a long time, the metal electrodes may age, and the semiconductor material may reach the conduction state, resulting in gradual changes in the electrical characteristics of the device. This aging effect will cause a significant increase in the clamping voltage of the device. That is, the greater the performance degradation of the device, the greater the influence on the clamping voltage, and the greater the corresponding clamping voltage correction degree. Since the effect of temperature on the clamping voltage is divided into two aspects: direct and indirect. Among them, the direct manifestation is temperature accumulation, and the indirect manifestation is performance degradation. And the performance of the device will accelerate degradation after reaching the conduction state, and its influence on the clamping voltage is more significant. Therefore, the influence of the device's performance degradation characteristics on the clamping voltage still needs to be considered after conduction.

[0079] First, determine the conduction moment of the device during the test. Generally, there is a difference in the rising amplitude of the clamping voltage before and after the conduction moment of the device, that is, the rising amplitude of the clamping voltage after conduction is relatively larger. Here, the rising degree of the clamping voltage under different high-voltage pulse events can be analyzed. If the difference in the rising degree of the clamping voltage before and after a certain pulse event is the largest, the corresponding moment is more likely to be the conduction moment.

[0080] Take any moment as the target moment, and use the target moment as the segmentation point to divide the clamping voltage sequence into two sequences, including: the left clamping voltage sequence and the right clamping voltage sequence.

[0081] For example, take the clamping voltage corresponding to any moment , and use it as the boundary to divide the clamping voltages on both sides of this point into two sequences and . Where A is the left clamping voltage sequence and B is the right clamping voltage sequence. In the embodiment of the present invention, the value of N is 500.

[0082] Then, according to the differences between adjacent values in the left clamping voltage sequence, determine the voltage rising degree of the left clamping voltage sequence; calculate the differences between adjacent values in the right clamping voltage sequence, and determine the voltage rising degree of the right clamping voltage sequence.

[0083] In some embodiments, the method for obtaining the voltage rising degrees of the two-side clamping voltage sequences is as follows: calculate the mean value of the differences between adjacent values in the left clamping voltage sequence to determine the voltage rising degree of the left clamping voltage sequence; calculate the mean value of the differences between adjacent values in the right clamping voltage sequence to determine the voltage rising degree of the right clamping voltage sequence.

[0084] Take the absolute value of the difference between the voltage rising degrees of the left clamping voltage sequence and the right clamping voltage sequence as the rising difference value corresponding to the target moment. Calculate the rising difference values at all moments.

[0085] In the order of time, when the rising difference value is greater than the preset normal threshold for the first time, take the corresponding moment as the conduction moment, which is also the conduction moment of the device. In the embodiments of the present invention, the value of the preset normal threshold is 0.9, and in other embodiments, the implementer adjusts this value according to the actual situation.

[0086] So far, the conduction moment of this device is determined. Since the electrical performance of the device deteriorates after conduction, making the deviation of the clamping voltage more serious, it is necessary to analyze the electrical performance deterioration of the device after the conduction moment for convenient correction.

[0087] Generally, in the conduction state, the pulse current corresponding to the device when reaching or approaching the clamping voltage will increase significantly, and at the same time, the increase in temperature will cause the capacitance value in the device to decrease. Then, the performance deterioration degree of the device can be evaluated according to the change characteristics of the pulse current and capacitance after the conduction moment. More specifically: compare the pulse current of the pulse event after the conduction moment with the pulse current corresponding to the calibrated clamping voltage to obtain the first deterioration degree; compare the capacitance value of the device of the pulse event after the conduction moment with the capacitance values of the device of all previous pulse events before the conduction moment to obtain the second deterioration degree; combine the first deterioration degree and the second deterioration degree to obtain the performance deterioration degree of the device.

[0088] In some embodiments, the first deterioration degree is the difference between the pulse current of the pulse event after the conduction moment and the pulse current corresponding to the device when reaching the calibrated clamping voltage; the second deterioration degree is the difference between the mean value of the capacitance values of the device of all previous pulse events before the conduction moment and the capacitance value of the device of the pulse event after the conduction moment; the performance deterioration degree is the product value of the first deterioration degree and the second deterioration degree. The larger the value of the performance deterioration degree, the more serious the electrical performance deterioration of the device during the corresponding pulse event, and the more serious the deviation of the corresponding clamping voltage.

[0089] In some embodiments, for a certain high-voltage pulse event i after the turn-on moment, the degree of electrical performance degradation can be expressed as: ; where is the degree of electrical performance degradation of the device after a certain high-voltage pulse event after the turn-on moment. is the pulse current corresponding to the high-voltage pulse event , is the pulse current corresponding to the device when it reaches the calibrated clamping voltage, is the capacitance value of the device at the time of the high-voltage pulse event , is the average capacitance value of all previous high-voltage pulses before the turn-on moment of the device.

[0090] Step S400, based on the degree of performance degradation of the device and the temperature influence coefficient, correct different clamping voltages to obtain the corrected clamping voltages.

[0091] So far, for this simulation test, before the device enters the on state, the direct cumulative effect of temperature plays a major role in the deviation of the clamping voltage. After the on state, the deviation of the clamping voltage is jointly determined by temperature accumulation and the degree of electrical performance degradation. Therefore, when determining the correction factor for the clamping voltage at different stages, two factors need to be combined.

[0092] The correction factors for correcting different clamping voltages include: before and at the turn-on moment, the normalized value of the temperature influence coefficient is used as the correction factor for the clamping voltage; after the turn-on moment, combining the degree of performance degradation and the temperature influence coefficient, determine the correction factor for the clamping voltage, where both the degree of performance degradation and the temperature influence coefficient are positively correlated with the clamping voltage, and the correction factors are all normalized values.

[0093] In some embodiments, after the turn-on moment, the normalized value of the product of the degree of performance degradation and the temperature influence coefficient is used as the correction factor for the clamping voltage.

[0094] It should be noted that the stabilities of ESD devices with different designs are different. There may be some devices with better stability that do not conduct during the test. Then, the influence of the electrical performance degradation on the clamping voltage can be ignored compared with the temperature accumulation, and only correction through the temperature influence coefficient is required.

[0095] For the clamping voltage corresponding to any pulse event during the simulation test, the greater the increase in its clamping voltage, the greater the corresponding correction factor. Therefore, the clamping voltage can be corrected through the correction factor to improve its accuracy.

[0096] Use the product of the clamping voltage and the correction factor as the corrected value of the clamping voltage; reduce the clamping voltage by the corrected value to obtain the corrected clamping voltage. The specific method for reducing the clamping voltage is: calculate the difference between the clamping voltage and the corrected value as the corrected clamping voltage.

[0097] Since the clamping voltage gradually increases, it is necessary to correct it in a decreasing trend during correction.

[0098] Step S500: Compare the corrected clamping voltage with the calibrated clamping voltage, and combine the conduction duration to determine the stability effect value of the clamping voltage.

[0099] Through the above method, more accurate clamping voltages of different pulse events during the ESD device simulation test can be obtained. Since the stability of the device clamping voltage can represent the protection ability of this device for the circuit, and there is a calibrated clamping voltage value for reference for different ESD devices, that is, there is a calibrated clamping voltage for reference, so the clamping voltage effect of this device can be verified in combination with the calibrated value.

[0100] Generally, during the simulation test, the smaller the deviation of the real-time clamping voltage from the calibrated clamping voltage, the higher the consistency of this device, and vice versa, the more unstable it is. At the same time, the conduction moment of the device represents its stability. If the conduction moment of this device is later, the corresponding stability is greater.

[0101] Therefore, first, compare the difference between the corrected clamping voltage of each pulse event after the first pulse event and the calibrated clamping voltage as the voltage fluctuation effect value.

[0102] Then, obtain the proportion of the conduction duration of the device; use the proportion of the conduction duration as the weight to weight the negative correlation mapping value of the voltage fluctuation effect value to obtain the stability effect value of the clamping voltage.

[0103] In some embodiments, for the ESD device, the stability effect value of its clamping voltage The calculation formula is: ; where is the clamping voltage of the kth high-voltage pulse event after the first pulse event; is the calibrated clamping voltage of the device; N is the number of high-voltage pulse events after the first pulse event; is the total test duration, is the conduction moment when conduction occurs, is the starting moment of the test. It should be noted that for the convenience of calculation, it is necessary to unify the units of the total test duration, the moment of conduction, and the starting moment of the test. Each moment can be sorted in chronological order, and the calculation can be carried out according to the serial number corresponding to each moment. For example, the total test duration here is the largest serial number after sorting, the starting moment of the test is 0, and the conduction moment is the serial number corresponding to the conduction moment.

[0104] characterizes the proportion of the conduction duration of the device. The larger its value, the slower the conduction of this device. If it is not conducted, this item is 0. At the same time, combined with the voltage fluctuation effect value characterizing the deviation of the real-time clamping voltage to determine the stability effect value of the clamping voltage. The smaller the deviation, the larger the stability effect value of the corresponding clamping voltage.

[0105] Generally, the deviation of the clamping voltage is the result of the action of temperature. However, in the embodiments of the present invention, the clamping voltage is only theoretically corrected to ensure the accuracy of the verification result. But if there are frequent pulse events during the actual operation of the device, the temperature rise is an inevitable event, and the sampling result of the clamping voltage cannot be corrected.

[0106] Therefore, if the clamping voltage stability of a certain ESD device is small, such as when the stability effect value of the clamping voltage is less than the preset stability threshold, it means that this device is more affected by temperature. Appropriate packaging and materials can be selected and the circuit topology can be optimized to further reduce the influence of temperature and ensure the stability and reliability of this device. Here, the appropriate packaging and materials include ceramic packaging and metal oxide packaging. In the embodiments of the present invention, the value of the preset stability threshold is 0.6. In other embodiments, the implementer can adjust this threshold according to the actual situation. For example, when the implementer has a high demand for the stability of the clamping voltage, the preset stability threshold can be appropriately increased. When the implementer has a low demand for the stability of the clamping voltage, the preset stability threshold can be appropriately decreased.

[0107] The embodiments of the present invention provide a simulation verification system for improving the clamping effect of an ESD device, and the system includes:

[0108] A data acquisition module for acquiring the clamping voltage, pulse current, and device temperature of the device;

[0109] A temperature analysis module for calculating the temperature influence coefficient according to the correlation between the clamping voltage and the device temperature during the device test;

[0110] A performance analysis module for analyzing the rising degree of the clamping voltage under different high-voltage pulses to determine the conduction moment; and evaluating the performance degradation degree of the device according to the change characteristics of the pulse current and capacitance after the conduction moment;

[0111] A voltage correction module, configured to correct different clamping voltages based on the performance degradation degree of the device and the temperature influence coefficient to obtain the corrected clamping voltage;

[0112] An effect simulation module, configured to compare the corrected clamping voltage with the calibrated clamping voltage, and determine the stability effect value of the clamping voltage in combination with the conduction duration.

[0113] Optionally, the transmission medium may be a wired link, such as but not limited to, coaxial cable, optical fiber, digital subscriber line, etc., or a wireless link, such as but not limited to, Wireless Fidelity (WIFI), Bluetooth, mobile device network, etc.

[0114] It should be noted that: for the device provided in the above embodiment, only the division of the above functional modules is used for illustration. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the computer device is divided into different functional modules to complete all or part of the functions described above.

[0115] A schematic structural diagram of a computer device provided by an embodiment of the present invention. Exemplarily, the computer device includes: a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, the computer device can execute any one of the improved ESD device clamping effect simulation verification methods introduced above.

[0116] In addition, an embodiment of the present invention also protects a device, which may include a memory and a processor. Among them, an executable program code is stored in the memory, and the processor is used to call and execute the executable program code to execute an improved ESD device clamping effect simulation verification method provided by an embodiment of the present invention.

[0117] The embodiment of the present invention can divide the functions of the device according to the above method examples. For example, it can correspond to each functional module, or integrate two or more functions into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is illustrative, only a logical function division, and there may be other division methods in actual implementation.

[0118] In the case of dividing each module according to the corresponding functions, the device may further include a signal uploading module, a determination module, an adjustment module, etc. It should be noted that all relevant contents of each step involved in the above method embodiment can be cited in the function description of the corresponding functional module, and will not be repeated here.

[0119] It should be understood that the device provided by the embodiments of the present invention is used to execute the above method for simulating and verifying the clamping effect of an improved ESD device, so the same effect as the above implementation method can be achieved.

[0120] In the case of adopting an integrated unit, the device may include a processing module and a storage module. Among them, when the device is applied to a device, the processing module may be used to control and manage the actions of the device. The storage module may be used to support the device to execute mutual program codes, etc. Among them, the processing module may be a processor or a controller, which can implement or execute various exemplary logic blocks, modules and circuits described in combination with the disclosure of the present invention. The processor may also be a combination for implementing computing functions, such as including a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module may be a memory.

[0121] In addition, the device provided by the embodiments of the present invention may specifically be a chip, a component or a module. The chip may include a connected processor and a memory; among them, the memory is used to store instructions. When the processor calls and executes the instructions, the chip can execute an improved method for simulating and verifying the clamping effect of an ESD device provided by the above embodiments.

[0122] The embodiments of the present invention also provide a computer-readable storage medium, in which computer program code is stored. When the computer program code runs on a computer, the computer is enabled to execute the above relevant method steps to implement an improved method for simulating and verifying the clamping effect of an ESD device provided by the above embodiments.

[0123] The embodiments of the present invention also provide a computer program product. When the computer program product runs on a computer, the computer is enabled to execute the above relevant steps to implement an improved method for simulating and verifying the clamping effect of an ESD device provided by the above embodiments.

[0124] Among them, the device, computer-readable storage medium, computer program product or chip provided by the embodiments of the present invention are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be elaborated here. Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the above division of each functional module is used as an example for illustration. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by the present invention, it should be understood that the disclosed device and method can be implemented in other ways.

[0125] The device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed among each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical or other forms.

[0126] It should also be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or terminal device including the said element.

[0127] It should be noted that the above-mentioned order of the embodiments of the present invention is only for description and does not represent the superiority or inferiority of the embodiments. The processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0128] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments.

[0129] The above content is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention.

Claims

1. A simulation verification method for improving the clamping effect of an ESD device, characterized in that, The method includes the following steps: Obtain the clamping voltage, pulse current, and device temperature of the device; Calculate the temperature influence coefficient according to the correlation between the clamping voltage and the device temperature during device testing; Analyze the rising degree of the clamping voltage under different high-voltage pulses to determine the conduction moment; evaluate the degree of device performance degradation according to the change characteristics of the pulse current and capacitance after the conduction moment; Based on the degree of device performance degradation and the temperature influence coefficient, correct different clamping voltages to obtain the corrected clamping voltage; Compare the corrected clamping voltage with the calibrated clamping voltage, and combine the conduction duration to determine the stability effect value of the clamping voltage; Among them, the method for obtaining the stability effect value is: compare the difference between the corrected clamping voltage and the calibrated clamping voltage of each pulse event after the first pulse event as the voltage fluctuation effect value; obtain the proportion of the conduction duration of the device; use the proportion of the conduction duration as the weight to weight the negative correlation mapping value of the voltage fluctuation effect value to obtain the stability effect value of the clamping voltage.

2. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 1, wherein The calculating the temperature influence coefficient according to the correlation between the clamping voltage and the device temperature during device testing includes: Determine the heat accumulation weight after each high-voltage pulse according to the proportion of the test duration corresponding to each high-voltage pulse and the change in the clamping voltage of adjacent high-voltage pulses; Combine the device temperature after each high-voltage pulse and the heat accumulation weight after the high-voltage pulse to determine the temperature influence coefficient after each high-voltage pulse.

3. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 2, wherein The determining the heat accumulation weight after each high-voltage pulse according to the proportion of the test duration corresponding to each high-voltage pulse and the change in the clamping voltage of adjacent high-voltage pulses includes: Calculate the slope value corresponding to the clamping voltage of the current high-voltage pulse and the previous high-voltage pulse; take the product of the slope value and the proportion of the test duration corresponding to the current high-voltage pulse as the heat accumulation weight after the current high-voltage pulse.

4. The simulation verification method for improving the clamping effect of the ESD device according to claim 1, characterized in that, The analyzing the rising degree of the clamping voltage under different high-voltage pulses to determine the conduction moment includes: Take any moment as the target moment, use the target moment as the segmentation point, and divide the clamping voltage sequence into two sequences, including: the left clamping voltage sequence and the right clamping voltage sequence; Determine the voltage rising degree of the left clamping voltage sequence according to the difference between adjacent values in the left clamping voltage sequence; calculate the difference between adjacent values in the right clamping voltage sequence to determine the voltage rising degree of the right clamping voltage sequence; Take the absolute value of the difference in the voltage rising degree of the left clamping voltage sequence and the right clamping voltage sequence as the rising difference value of the corresponding target moment; when the rising difference value is greater than the preset normal threshold for the first time, take the corresponding moment as the conduction moment.

5. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 1, wherein The evaluating the degree of device performance degradation according to the change characteristics of the pulse current and capacitance after the conduction moment includes: Compare the pulse current of the pulse event after the conduction moment with the pulse current corresponding to the calibrated clamping voltage to obtain the first degradation degree; Compare the device capacitance value of the pulse event after the conduction moment with the device capacitance values of all previous pulse events before the conduction moment to obtain the second degradation degree; Combining the first degree of degradation and the second degree of degradation, the degree of performance degradation of the device is obtained.

6. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 1, characterized in that, The correction factors for correcting different clamping voltages include: Before and at the conduction moment, the normalized value of the temperature influence coefficient is used as the correction factor for the clamping voltage; After the conduction moment, combining the degree of performance degradation and the temperature influence coefficient, the correction factor for the clamping voltage is determined.

7. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 6, wherein, The method of correcting different clamping voltages based on the degree of performance degradation and the temperature influence coefficient of the device to obtain the corrected clamping voltage includes: Taking the product between the clamping voltage and the correction factor as the correction value of the clamping voltage; Reducing the clamping voltage by the correction value to obtain the corrected clamping voltage.

8. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 7, wherein The method of reducing the clamping voltage by the correction value to obtain the corrected clamping voltage includes: Calculating the difference between the clamping voltage and the correction value as the corrected clamping voltage.

9. The method for simulating and verifying the clamping effect of the improved ESD device according to claim 1, wherein After determining the stable effect value of the clamping voltage, it further includes: when the stable effect value of the clamping voltage is less than the preset stable threshold, adjusting the package and materials of the device.

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