Power supply drop detection system and method

Abstract

The invention relates to the technical field of power supply detection, and discloses a power supply drop detection system and method, the system is used for detecting a target power supply node in a to-be-detected power supply network, and the system comprises a reference generation module and a level comparison module; the level comparison module is respectively connected with the target power supply node and the reference generation module; the reference generation module is used for generating a reference voltage according to the imbalance control code corresponding to the target power supply node; the level comparison module is used for comparing the node voltage of the target power supply node with a reference voltage and generating a detection signal according to a comparison result; the detection signal is used for representing whether the target power supply node has power supply drop or not. The reference voltage is dynamically adjusted through the imbalance control code, the inherent imbalance of the level comparison module is compensated, and the detection precision is remarkably improved; and reference voltages can be independently configured for different power supply nodes, so that diversified tolerance requirements can be flexibly met.

Description

Technical Field

[0001] The present application relates to the technical field of power supply detection, and in particular to a power supply drop detection system and method. Background Art

[0002] As the complexity of modern electronic systems increases, their power supply networks often contain multiple independent power supply nodes, and the dynamic range of load changes has expanded (such as the start and stop of high-current equipment, high-frequency signal switching, etc.), resulting in frequent power supply voltage drop (VoltageDroop) events. Such events include both persistent voltage anomalies (such as long-term low voltage caused by overload) and transient drops in nanoseconds (such as instantaneous current spikes). If not detected in time, data errors may occur at the least, and hardware damage may occur at the worst. The current mainstream power drop detection solutions have significant deficiencies in detection accuracy, detection mode, and detection efficiency, and are difficult to adapt to diverse detection needs.

[0003] Therefore, there is an urgent need for a high-precision, multi-mode power drop detection solution that can overcome the defects of the existing technology. Summary of the invention

[0004] In view of this, the present application provides a power drop detection system and method to address the deficiencies of existing solutions in terms of detection accuracy, detection mode, and detection efficiency. The technical solution is as follows.

[0005] In a first aspect, the present application provides a power drop detection system for detecting a target power node in a power network to be tested, the system comprising a reference generation module and a level comparison module; the level comparison module is connected to the target power node and the reference generation module respectively;

[0006] The reference generation module is used to generate a reference voltage according to an offset control code corresponding to the target power supply node;

[0007] The level comparison module is used to compare the node voltage of the target power node with the reference voltage and generate a detection signal according to the comparison result; the detection signal is used to indicate whether a power drop occurs at the target power node.

[0008] The power drop detection system provided in this application has the following advantages:

[0009] The power supply drop detection system of the present application includes a reference generation module and a level comparison module, dynamically generates a reference voltage through an offset control code, and realizes the comparison between the node voltage and the reference voltage. The reference voltage is adjusted in real time through the offset control code to compensate for the inherent offset of the comparator, which can eliminate detection errors and significantly improve detection accuracy; and it supports independently configuring reference voltages for different power supply nodes to flexibly adapt to diverse tolerance requirements; the complex global detection scheme in the traditional solution is removed, reducing system complexity and hardware costs.

[0010] In an alternative embodiment, the level comparison module includes: a comparison unit, a gating unit, and a latching unit;

[0011] The comparison unit is configured to generate a detection signal according to the magnitude relationship between the node voltage and the reference voltage; the detection signal includes a first level signal or a second level signal; the first level signal is greater than the second level signal; the first level signal is used to indicate that no power supply drop occurs at the target power supply node; the second level signal is used to indicate that a power supply drop occurs at the target power supply node;

[0012] The latching unit is configured to latch the first level signal to obtain a latched signal; the latched signal is used to indicate that a transient power supply drop occurs at the target power supply node;

[0013] The gating unit is configured to select and output the detection signal or the latched signal according to the type of the received power supply drop detection requirement.

[0014] The power supply drop detection system of the present application switches the output signal through the gating unit, is compatible with continuous drop detection and transient drop detection, and covers all-scenario power supply abnormal events; and the latching unit latches the pulse drop as short as the nanosecond level to avoid missed detection caused by response delay in the traditional solution; users can flexibly select the detection mode according to actual needs (for example, industrial control scenarios focus on continuous detection, and communication devices focus on transient detection).

[0015] In an alternative embodiment, the comparison unit is specifically configured to:

[0016] When the node voltage is greater than the reference voltage, generate a first level signal; when the node voltage is less than the reference voltage, generate a second level signal;

[0017] When the type of the power supply drop detection requirement is continuous detection, the gating unit outputs the detection signal; when the type of the power supply drop detection requirement is transient detection, the gating unit outputs the latched signal and locks the output of the latching unit after outputting the latched signal.

[0018] The power supply drop detection system of the present application uses a high level to directly represent "no drop" and a low level to represent "drop occurs", simplifying the backend processing logic; it can quickly switch between continuous detection and transient detection without hardware reconstruction or system restart; it multiplexes the same comparison unit to implement multi-mode detection, reducing the volume of redundant modules.

[0019] In an optional implementation, the level comparison module further includes a control unit and a reset unit; the control unit is configured to control the reset unit to issue a reset signal to clear the output lock of the latch unit after the gating unit outputs the second power supply drop detection signal.

[0020] The power supply drop detection system of the present application realizes reset by controlling the reset unit to issue a reset signal through the control unit after outputting the latch signal, ensuring the continuity of subsequent detections and avoiding manual intervention; it can also eliminate false latches (such as false drop marks caused by noise) through reset.

[0021] In an optional implementation, the system further includes:

[0022] A calibration control module, connected to the reference generation module, for controlling the adjustment of the reference voltage and generating the offset control code during the calibration process;

[0023] An offset storage module, respectively connected to the calibration control module and the reference generation module, for storing the offset control code.

[0024] The power supply drop detection system of the present application can complete calibration in real time without interrupting the system operation or relying on external devices by setting up a calibration control module, ensuring the continuity of detection. The calibration data is retained through an offset storage module (such as a non-volatile memory) to ensure the threshold consistency after the system is powered off and restarted; and it can uniformly manage the offset calibration codes of multiple nodes.

[0025] In an optional implementation, the calibration control module is specifically configured to:

[0026] Responding to the received calibration signal, controlling the level comparison module to be calibrated to output a detection signal, and controlling the power supply network to be measured to enter a no-load static state;

[0027] Obtaining the first node voltage of the power supply node connected to the level comparison module to be calibrated;

[0028] Controlling the reference generation module to generate an initial reference voltage; the initial reference voltage is greater than the first node voltage;

[0029] Controlling the reference generation module to gradually adjust the reference voltage and monitoring the duty cycle of the detection signal in real time;

[0030] When the duty cycle reaches a preset threshold, an offset control code corresponding to the current reference voltage is obtained.

[0031] The power supply drop detection system of the present application is dynamically calibrated based on duty cycle statistics (such as the threshold point corresponding to a 50% duty cycle), eliminates the interference of single measurement noise, and can be applied to level comparison modules of different process nodes.

[0032] In an optional implementation manner, the reference generation module is further configured to:

[0033] Generate a control code according to the offset control code and a preset drop amplitude of the target power supply node;

[0034] Generate a reference voltage according to the control code.

[0035] The power supply drop detection system of the present application dynamically configures the detection sensitivity through a preset drop amplitude (such as 5% or 10%) to adapt to different scenario requirements in industries, consumer electronics, etc.; a tolerance offset is superimposed on the basis of the offset calibration code, and threshold fine-tuning can be achieved.

[0036] In an optional implementation manner, the number of the level comparison modules is multiple, and each level comparison module is respectively connected to different power supply nodes in the power supply network to be measured.

[0037] The power supply drop detection system of the present application supports distributed deployment of multiple power supply nodes, realizes full coverage of the power supply network, and the abnormal positioning accuracy reaches the node level; each node is independently calibrated and the threshold is set to avoid mutual interference between nodes; moreover, it supports adding or reducing detection nodes as needed (such as expanding from 8 nodes to 32 nodes), reducing the modification cost.

[0038] In an optional implementation manner, the system further includes:

[0039] A gating module for gating the output signals of multiple level comparison modules.

[0040] The power supply drop detection system of the present application uniformly polls and schedules the detection results of multiple nodes to meet the real-time requirements of high-speed systems.

[0041] In a second aspect, the present application provides a power supply drop detection method, which is applied to the power supply drop detection system as described in the first aspect or any corresponding implementation manner thereof. The method is executed by a level comparison module, and the method includes:

[0042] In response to the received power supply drop detection requirement, obtain the power supply node to be measured and the corresponding offset control code;

[0043] Obtain the current node voltage of the power supply node to be measured, and control the reference generation module to generate a reference voltage according to the offset control code;

[0044] Compare the current node voltage with the reference voltage, and generate a detection signal according to the comparison result; the detection signal is used to characterize whether a power sag has occurred at the target power supply node.

[0045] In a third aspect, the present application provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the power sag detection method according to the second aspect or any corresponding embodiment thereof.

[0046] In a fourth aspect, the present application provides a computer-readable storage medium, on which computer instructions are stored. The computer instructions are used to cause a computer to execute the power sag detection method according to the second aspect or any corresponding embodiment thereof.

[0047] In a fifth aspect, the present application provides a computer program product, including computer instructions, which are used to cause a computer to execute the power sag detection method according to the second aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 is a structural block diagram of a power sag detection system according to an embodiment of the present application;

[0050] Figure 2 is a schematic flowchart of a power sag detection method according to an embodiment of the present application;

[0051] Figure 3 is a schematic diagram of a typical chip power network;

[0052] Figure 4 is a schematic diagram of a power sag of a typical chip power network;

[0053] Figure 5 is a schematic diagram of detecting the chip power supply with an ADC;

[0054] Figure 6 is a schematic diagram of testing the chip power supply with test pins;

[0055] Figure 7It is a schematic diagram showing the difference between the signal detected in the chip power supply using test pins and the original signal;

[0056] Figure 8 It is a schematic structural diagram of a chip power supply drop detection circuit according to an embodiment of the present application;

[0057] Figure 9 It is a schematic structural diagram of a level comparison module according to an embodiment of the present application;

[0058] Figure 10 It is a schematic diagram of signal levels according to an embodiment of the present application;

[0059] Figure 11 It is a schematic hardware structure diagram of a computer device according to an embodiment of the present application. Detailed implementation manners

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0061] In modern electronic systems, the stability of the power network directly determines the reliability of device operation. Therefore, power supply drop detection technology has become a core requirement in the design of electronic systems. The current mainstream power supply drop detection solutions mainly rely on two types of technical solutions: the fixed threshold comparator solution and the programmable reference voltage solution.

[0062] The fixed threshold comparator solution compares the divided power supply voltage signal with a fixed reference voltage through a comparator and outputs a high / low level as the detection signal. However, the inherent offset and temperature drift of the comparator cause the actual trigger threshold to deviate from the designed value, resulting in insufficient detection accuracy. Moreover, it can only output real-time level signals and cannot latch short-time pulse drops, resulting in the failure of detecting transient events. In addition, the tolerance requirements of different power supply nodes vary, but the fixed threshold cannot be dynamically adjusted, and a separate circuit needs to be designed for each node, resulting in high hardware costs.

[0063] The programmable reference voltage solution uses a digital-to-analog converter (DAC) to generate a reference voltage and configures the threshold through software. However, it is necessary to interrupt the system operation and rely on external devices to measure the comparator offset, and online self-calibration cannot be achieved. The operation is complex and inefficient. Moreover, when distributedly deployed, the offset errors of each node exist independently, lacking a unified calibration strategy, resulting in poor consistency of detection thresholds. In addition, no dedicated latching mechanism is designed, and short-time drop events still cannot be reliably captured.

[0064] Therefore, the existing solutions have significant deficiencies in terms of detection accuracy, detection mode, and detection efficiency, and it is difficult to adapt to diverse detection requirements.

[0065] In view of the above problems, the embodiments of the present application provide a power supply drop detection system, which dynamically adjusts the reference voltage through the offset control code to compensate for the inherent offset of the level comparison module, significantly improving the detection accuracy; and supports independent configuration of the reference voltage for different power supply nodes, flexibly adapting to diverse tolerance requirements.

[0066] The structure of the power supply drop detection system provided by this embodiment is as Figure 1 shown, and is used to detect the target power supply node in the power supply network to be measured. The system includes a reference generation module 101 and a level comparison module 102; the level comparison module is respectively connected to the target power supply node and the reference generation module.

[0067] The reference generation module 101 is configured to generate a reference voltage according to the offset control code corresponding to the target power supply node.

[0068] Specifically, the reference generation module 101 generates a control code according to the offset control code and the preset drop amplitude of the target power supply node; and generates a reference voltage according to the control code. By dynamically configuring the detection sensitivity through the preset drop amplitude (such as 5% or 10%), it adapts to the requirements of different scenarios such as industry and consumer electronics; and by superimposing a tolerance offset on the offset calibration code, threshold fine-tuning can be achieved.

[0069] In addition, the system can independently configure the reference voltage for different power supply nodes according to requirements, and adjust the reference voltage in real time through the corresponding offset control code to compensate for the inherent offset of the comparator, which can eliminate detection errors and significantly improve the detection accuracy.

[0070] The level comparison module 102 is configured to compare the node voltage of the target power supply node with the reference voltage, and generate a detection signal according to the comparison result; the detection signal is used to indicate whether a power supply drop has occurred at the target power supply node.

[0071] By real-time monitoring of the node voltage and comparing it with the reference voltage, it can be determined whether a power supply drop event has occurred at the node voltage according to the comparison result.

[0072] Optionally, the number of the level comparison modules 102 can be multiple, and each level comparison module is respectively connected to different power supply nodes in the power supply network to be measured. By supporting the distributed deployment of multiple power supply nodes, full coverage of the power supply network is achieved, and the abnormal positioning accuracy reaches the node level; each node is independently calibrated and the threshold is set to avoid mutual interference between nodes; and it also supports adding or reducing detection nodes as needed (such as expanding from 8 nodes to 32 nodes), reducing the modification cost.

[0073] Optionally, the system is further provided with a calibration control module 103 and an offset storage module 104. The calibration control module 103 is connected to the reference generation module 101 and is used to control the adjustment of the reference voltage and generate the offset control code during the calibration process. The offset storage module 104 is respectively connected to the calibration control module 103 and the reference generation module 101 and is used to store the offset control code. By setting the calibration control module 103, calibration can be completed in real time without interrupting the system operation or relying on external devices, ensuring the continuity of detection. The calibration data is retained by the offset storage module 104 (such as a non-volatile memory) to ensure the threshold consistency after the system is powered off and restarted, and the offset calibration codes of multiple nodes can be uniformly managed.

[0074] In addition, the offset storage module 104 can also be used to detect the temperature of each power supply node and store the offset control code values obtained by calibration at different temperatures, realizing the temperature drift management of the offset voltage of each power supply node and being able to solve the problem of threshold drift of each power supply node.

[0075] The above-mentioned calibration process is executed by the calibration control module 103. Specifically, the calibration control module 103 responds to the received calibration signal, controls the level comparison module 102 to be calibrated to output a detection signal, and controls the power supply network to be measured to enter a no-load static state; obtains the first node voltage of the power supply node connected to the level comparison module 103 to be calibrated; controls the reference generation module 101 to generate an initial reference voltage, where the initial reference voltage is greater than the first node voltage; controls the reference generation module 101 to gradually adjust the reference voltage and monitors the duty cycle of the detection signal in real time; when the duty cycle reaches a preset threshold, the offset control code corresponding to the current reference voltage is obtained. Dynamic calibration is based on duty cycle statistics (such as the 50% duty cycle corresponding to the threshold point) to eliminate the noise interference of single measurement and is applicable to the level comparison modules of different process nodes.

[0076] Optionally, the system is further provided with a gating module 105 for gating the output signals of multiple level comparison modules. The gating module polls and schedules the detection results of multiple nodes uniformly to meet the real-time requirements of a high-speed system.

[0077] In an optional implementation manner, the above-mentioned level comparison module 102 includes: a comparison unit, a gating unit, and a latching unit;

[0078] The comparison unit is configured to generate a detection signal according to the magnitude relationship between the node voltage and the reference voltage; the detection signal includes a first level signal or a second level signal; the first level signal is greater than the second level signal; the first level signal is used to indicate that no power supply drop has occurred at the target power supply node; the second level signal is used to indicate that a power supply drop has occurred at the target power supply node; the latching unit is configured to latch the first level signal to obtain a latched signal; the latched signal is used to indicate that a transient power supply drop has occurred at the target power supply node; the gating unit is configured to select and output the detection signal or the latched signal according to the type of the received power supply drop detection requirement.

[0079] By switching the output signal through the gating unit, it is compatible with continuous drop detection and transient drop detection, covering all-scenario power supply abnormal events; and the latching unit latches the pulse drop as short as the nanosecond level, avoiding missed detection caused by response delay in the traditional scheme; users can flexibly select the detection mode according to actual needs (for example, industrial control scenarios focus on continuous detection, and communication devices focus on transient detection).

[0080] Specifically, when the node voltage is greater than the reference voltage, a first level signal is generated; when the node voltage is less than the reference voltage, a second level signal is generated; when the type of the power supply drop detection requirement is continuous detection, the gating unit outputs the detection signal; when the type of the power supply drop detection requirement is transient detection, the gating unit outputs the latched signal and locks the output of the latching unit after outputting the latched signal. By directly representing "no drop" with a high level and "drop occurred" with a low level, the backend processing logic is simplified; it can quickly switch between continuous detection and transient detection without hardware reconstruction or system restart; the same comparison unit is reused to implement multi-mode detection, reducing the volume of redundant modules.

[0081] It should be noted that the situation where the node voltage is equal to the reference voltage does not need to be considered here. The specific reasons are as follows: On the one hand, the system is provided with a calibration process. By gradually adjusting the reference voltage and observing the duty cycle of the detection signal, that is, the system will record the offset control code corresponding to the 0 / 1 alternation point of the detection signal. This process is essentially to determine the actual threshold point of the level comparison module, so that the relationship between the node voltage and the reference voltage can be clearly determined as greater than or less than in subsequent detections, without considering the theoretically equal state. On the other hand, in a real system, due to factors such as noise and process deviation, the probability that the node voltage is exactly equal to the reference voltage is very small. Even if a short-term equality occurs, it will quickly transition to a state where the node voltage is greater than the reference voltage or the node voltage is less than the reference voltage due to dynamic characteristics. Therefore, there is no need to specifically handle the equal situation in the design.

[0082] Optionally, the level comparison module 102 is further provided with a control unit and a reset unit; the control unit is configured to control the reset unit to send a reset signal to clear the output lock of the latch unit after the gating unit outputs the second power supply drop detection signal. After the output latch signal is sent, the reset unit is controlled by the control unit to send a reset signal to achieve reset, avoiding manual intervention; false latch (such as a false drop mark caused by noise) can also be eliminated through reset.

[0083] Based on the above embodiments, an embodiment of the present application further provides a power supply drop detection method, which is executed by the level comparison module, and the method flow is as Figure 2 shown, including the following steps.

[0084] S201. In response to the received power supply drop detection requirement, obtain the power supply node to be measured and the corresponding offset control code.

[0085] Specifically, after receiving the power supply drop detection requirement, determine the power supply node to be detected from the detection requirement, and obtain the corresponding offset control code from the offset storage module.

[0086] S202. Obtain the current node voltage of the power supply node to be measured, and control the reference generation module to generate a reference voltage according to the offset control code.

[0087] Specifically, collect the node voltage of the power supply node to be detected. Generate a control code according to the offset control code and the preset drop amplitude of the power supply node to be detected; generate a corresponding reference voltage according to the control code. The drop amplitude can be set according to specific needs, such as 5% or 10%.

[0088] S203. Compare the current node voltage with the reference voltage, and generate a detection signal according to the comparison result; the detection signal is used to indicate whether a power supply drop has occurred at the target power supply node.

[0089] Specifically, when the node voltage is greater than the reference voltage, it indicates that no power supply drop has occurred at this node; when the node voltage is less than the reference voltage, it indicates that a power supply drop has occurred at this node.

[0090] In summary, the power supply drop detection system provided by the embodiments of the present application has achieved a breakthrough improvement in the field of power supply drop detection through the collaborative design of a dynamic calibration mechanism and a multi-mode detection architecture. Based on the linkage control of a reference generation module and a level comparison module, the system effectively compensates for the inherent offset of the comparator by dynamically generating reference voltages adapted to each power supply node, solving the problem of threshold drift caused by process deviation and temperature drift in traditional solutions. Combining the configuration of a latch unit and a strobe unit, it synchronously supports continuous drop detection and transient event capture, covering the requirements of high-dynamic scenarios. Through the integration of a self-calibration process and an offset storage module, the system can complete multi-node threshold calibration and support dynamic configuration of detection sensitivity according to a preset drop amplitude, adapting to diverse tolerance requirements. The modular design with distributed deployment allows multiple detection nodes to be densely arranged in the power network. Combining the time-division multiplexing mechanism of the strobe module, while achieving global monitoring and anomaly localization (node-level accuracy), the hardware resource occupancy is significantly reduced. In addition, the introduction of a reset unit and a standardized detection process ensures the anti-interference ability and cross-platform compatibility of the system in a complex noise environment, providing a full-scenario solution for high-reliability power management.

[0091] Those skilled in the art can apply the solution to integrated circuits, chip design, or other electronic systems based on the specific implementation of the power supply drop detection system provided in the above embodiments without departing from the core idea of the present application.

[0092] The following will use the preferred example of chip design to illustrate the power supply drop detection system and method provided in the above embodiments.

[0093] In chip design, the power supply quality of the power network inside the chip directly affects the chip performance and even the functions it is intended to implement. When the chip is working, the power supply is affected by load changes, and its level will drop to a certain extent. If the duration of this drop is short, it is very difficult to be detected outside the chip. In order to timely detect the problem of power supply drop, a monitoring circuit that can detect rapid power supply drops is needed. This is of great significance for chip problem localization, monitoring the power supply quality inside the chip, and judging whether the chip power supply quality meets the IP requirements. At the same time, since there are generally multiple sets of power supplies inside the chip and multiple nodes need to be detected, if all nodes' power supply quality needs to be comprehensively detected, multiple detection modules are required. This requires the control of the detection modules to be as simple as possible, avoiding too much wiring consuming routing resources, and the area should be small, suitable for multi-point layout.

[0094] Such as Figure 3In the typical scenario shown, VDD0 / VDD1 are the power pins of the chip, and GND0 / GND1 are the ground pins of the chip. They form two power supply networks. An actual chip may have more power supply networks. It should be noted that the connection lines from the chip pins to each internal module are not ideal conductors and have a certain resistance. When the switch SW inside Module 1 conducts and turns off quickly, due to the influence of the instantaneous large current and the resistance of the internal connection lines of the chip, the level at point A on the VDD0 connection line will experience a rapid drop and recovery, as Figure 4 shown. This drop may cause functional or performance problems in Module 2, which is sensitive to power supply, and it is not easy to detect. In a chip, there may be multiple points such as A to F that need to be monitored.

[0095] Regarding the above Figure 3 shown typical scenario, one method is to use an ADC to detect the internal power supply. Figure 5 is the internal power supply detection circuit of the ADC. Among them, point A and point B are the sites to be detected. Points A and B are introduced into the two input terminals in0 and in1 of the multiplexer MUX through leads, and one of them is selected as the input signal vin of the ADC. The ADC performs analog-to-digital conversion on the input signal vin, generates a digital signal, and outputs it to the outside of the chip through other modules of the chip, so as to obtain the levels of points A and B. The disadvantages of this method are: The ADC can only sample the input signal vin at the moment specified by the clock signal clk, and the power supply drop does not necessarily occur at the sampling moment of the ADC, so transient power supply drops may be missed or not captured. The area of the ADC is relatively large, occupying too much chip area. Due to the large area of the ADC, it is impossible to arrange multiple points. If the signal is introduced into the input terminal of the ADC through long traces, the signal will be filtered and distorted due to the long traces.

[0096] Another method is as Figure 6 shown. The internal power supply is tested with a test pin. Points A and B of the internal power supply are tested through the test pin TEST; after being selected by the multiplexer MUX, the DC level on the TEST pin is equal to the DC level of point A or point B. By testing TEST, the level of A or B can be known. The disadvantages of this method are: The connection lines from point A or point B to the TEST pin are non-ideal and have a certain resistance, and the TEST pin itself has a certain parasitic capacitance (the external detection device also has a certain input capacitance); the connection line resistance and the parasitic capacitance of the TEST pin (and the input capacitance of the external detection device) will form an RC low-pass filter network, and the filter network makes the measured level drop much lower than the original drop at point A or B, resulting in inaccurate testing of the power supply drop. The difference between the measured signal and the original signal is as Figure 7 shown.

[0097] Therefore, based on the power supply drop detection system and method provided in the above embodiments, this example provides a chip power supply drop detection circuit, the structure of which is as shown in Figure 8 shown. The main components of this circuit include: a calibration and control module, an offset storage module, a reference generation module, a digital signal gating mux, and multiple level comparison modules.

[0098] In this chip power supply drop detection circuit, different level comparison modules are placed at different power supply nodes inside the chip. The level comparison module can compare the divided voltage value of the power supply level at different nodes with the corresponding reference voltage and generate a digital signal, and different level comparison modules can work in a time-sharing manner. The calibration and control module can control the calibration of each level comparison module and call the corresponding offset level when it is working properly. The offset storage module can store the offset control codes of different level comparison modules and control the reference generation module to generate the corresponding reference voltage. Each of the level comparison modules is characterized by a simple structure and a small area, and can be placed where detection is needed without occupying too much chip area. The digital signal gating mux can select the comparison results of different nodes for output.

[0099] In the chip power supply drop detection circuit provided in this example, the reference generation module generates a reference level vref for level comparison. Its internal main circuit is a DAC. By transmitting the control code to the DAC, different reference levels vref can be generated. The level comparison module is placed at the power supply node to be detected, and the power supply node is connected to its in port.

[0100] The specific structure of the level comparison module is as shown in Figure 9 shown, and it is composed of a voltage division circuit, an amplifier, a shaping buffer, a latch module (such as a D flip-flop), and a gating mux.

[0101] The voltage division circuit generates a voltage signal v_div that is proportional to its in port, so that voltage signals in different power domains can be compressed into the same power domain. For example, the 3.3V power supply is divided into 1.1V, which avoids the delay and risk of direct comparison of high voltages, and at the same time maintains the dynamic characteristics of the original signal.

[0102] The amplifier is used to amplify the difference between the divided voltage signal (v_div) and the reference voltage (vref) to generate the analog signal V_ana. The gain of the amplifier is designed to be high enough to quickly respond to small voltage changes. The shaping buffer converts the analog signal V_ana into a digital signal V_A (0 or 1). The hysteresis characteristic of the shaping buffer (similar to a Schmitt trigger) can suppress noise and ensure that only real power supply drop events trigger signal transitions. The shaping buffer converts the analog comparison result into a digital signal V_A, reducing the impact of analog noise on subsequent logic. The voltage division circuit can use high-precision, low-temperature-drift resistors (such as laser-trimmed or thin-film resistors) to ensure the stability of the linear relationship between v_div and the original power supply voltage. The circuit design of the amplifier and the shaping buffer (such as low transmission delay and high bandwidth) ensures a fast conversion from voltage change to digital signal output (in the nanosecond range), capable of capturing transient drops as short as dozens of nanoseconds. In addition, an RC filter circuit can be added to the amplifier or buffer to suppress high-frequency noise while maintaining sensitivity to short-term drops.

[0103] The above reference voltage (vref) is dynamically adjustable. Specifically, the reference generation module dynamically adjusts vref through a DAC, enabling flexible setting of the detection threshold. For example, when the normal voltage is 1.0V, set vref = 0.9V to detect a 10% drop; by adjusting the DAC control code, vref can be adapted to different power supply domains or different drop sensitivity requirements. Combined with the calibration control module, it can compensate for temperature drift or process variations to ensure the accuracy of the comparison threshold and avoid missed detections or false alarms.

[0104] Moreover, since each power supply node in the chip belongs to the same power supply domain and has the same voltage characteristics, unified detection of multiple power supply nodes can be achieved by sharing VREF and offset correction codes. In addition, if it is necessary to detect power supply nodes that do not belong to the same power supply domain, if a certain error (such as ±5%) is allowed for power supply drop detection and the offset differences of each level comparison module are within the allowable range, VREF and offset correction codes can also be shared.

[0105] It should be noted that the generation of vref is dynamically adjusted by a DAC (Digital-to-Analog Converter) through a digital control code, rather than a simple resistor voltage division or a fixed reference source. This requires a high-precision and low-noise DAC design. The accuracy and stability of the DAC directly depend on the purity of its power supply. If there is noise or fluctuation in the power supply, it will cause deviation in the vref output, which in turn affects the detection accuracy of the level comparison module. Therefore, the above-mentioned level comparison module reserves an external vref input pin, and the external vref signal can be injected through the multiplexed in port or the independent test interface. If the internal DAC fails, the detection function can be maintained through the external vref input, improving the system's fault tolerance and ensuring the flexibility of detection. In addition, the externally input vref can also be routed to the level comparison module to be compared with the vref generated by the internal DAC, thereby verifying the DAC accuracy.

[0106] When v_div > vref, the V_ana level is high, and after passing through the shaping buffer, V_A = 1, which indicates that the node voltage of the power supply node to be measured is in a normal state; when v_div < vref, the V_ana level is low, and after passing through the shaping buffer, V_A = 0, which indicates that a power supply voltage drop has occurred at the power supply node to be measured. At this time, the V_A signal can be directly output as the power supply drop detection result, and continuous power supply drop events can be detected.

[0107] In addition, transient power supply drop events can also be detected through a D Flip-Flop (DFF). Specifically.

[0108] A transient power supply drop refers to a voltage disturbance (such as switching noise, electromagnetic interference) with an extremely short duration (such as from sub-nanoseconds to microseconds) and possibly a small amplitude. The D Flip-Flop (DFF) samples and latches the V_A signal when a transition from 1 to 0 occurs in V_A, and outputs V_B. Even if the power supply drop event has an extremely short duration (such as a transient glitch), as long as a transition from 1 to 0 occurs in V_A, V_B will immediately be latched to a high level. For example, assuming a clock frequency of 100 MHz (period 10 ns), even if the power supply drop only lasts for 5 ns, as long as a transition from 1 to 0 occurs in V_A, the DFF can capture this event, that is, latch and output V_B = 1. The total delay from the occurrence of the voltage drop to the DFF latching and output is extremely short, which can cover the vast majority of transient events. Even if the power supply drop event has ended (V_A returns to 0), the V_B latched by the DFF still remains at 1 until the next sampling or reset, ensuring that the subsequent logic circuit has enough time to process. In addition, the latched state can be cleared through a reset signal, and after resetting the latching module, transient power supply drop events can be detected again.

[0109] In addition, another method can be used to latch the V_A signal. The V_A signal is inverted and connected to the clock port of the D flip-flop, and the data port of the D flip-flop is connected to a fixed high-level signal. In this way, latching can be performed without a clock.

[0110] According to the specific detection requirements, the use of a gate mux allows only one detection type to be selected at the same time (such as real-time level detection V_A or transient event latch V_B). Although this design sacrifices parallel detection capabilities, it has significant advantages for chip design. Specifically, the gate merges two types of detection signals (V_A and V_B) into the same output channel, reducing the input port requirements of the back-end processing module (such as a microcontroller, state machine, or alarm unit). For example, in resource-constrained embedded systems, if multiple signals need to be processed simultaneously, complex arbitration logic may be required, and the gate simplifies this process through hardware selection. Sharing output channels can also save routing space on the chip or PCB, which is especially important in high-density integrated circuits. By activating only the signal path selected by the gate (such as turning off the power supply of the unselected module), dynamic power consumption caused by the simultaneous transmission of multiple signals is avoided. The transmission paths of V_A and V_B are isolated by the gate to prevent the two types of signals from interfering with each other during transmission (such as crosstalk caused by level jumps). The electromagnetic compatibility design of a single signal path is simpler, avoiding the noise coupling problem introduced by multiple parallel signals. The detection type can be dynamically selected according to system requirements. For example, V_A is used for real-time monitoring during normal operation, and V_B is switched to record the fault waveform when an abnormality occurs.

[0111] Since the level comparison modules are distributed near multiple power supply nodes, the detection result outputs of different nodes are switched by digital signal selection MUX in time-sharing mode. Each level comparison module is polled and read within the selection cycle, forming periodic sampling of multiple nodes, thereby realizing continuous coverage monitoring of the entire power supply network. If each node is polled multiple times within a unit time, the frequency of IR drop (voltage drop) can be calculated by counting the number of triggering node voltage drop events and combining the polling cycle. Continuous detection of IR drop frequency is achieved.

[0112] The level comparison module, voltage division, amplification, and shaping circuit design optimizes the signal processing speed. DFF "freezes" transient events in digital signals to avoid loss due to short event duration. The DAC-controlled vref supports dynamic adjustment of detection sensitivity to adapt to different application scenarios. Through the three-level processing of high-speed level comparison, digital shaping, and DFF latching, reliable detection of short-term power drop events is achieved.

[0113] The following will Figure 9 On this basis, the calibration process and the detection process are explained in detail.

[0114] The calibration process specifically includes the following steps.

[0115] First, the calibration and control module controls the level comparison module to be calibrated to select the V_A signal (the original unlatched comparison result) as the output. This can ensure that the power supply domain to be measured is in a stable state of being powered on but not working, avoiding interference from dynamic power fluctuations during calibration.

[0116] Subsequently, the calibration and control module controls the reference generation module (with an internal DAC) to generate a lower-level vref, so that the V_A signal of the level comparison module always remains "1" (i.e., v_div > vref). Gradually increase the level of the vref signal, which can be achieved by incrementing the DAC control code, so that the V_A signal changes from 1 to 0 (i.e., v_div < vref).

[0117] Monitor the change of the V_A signal in real time. When vref drops to a value close to the divided voltage value (v_div) of the actual power supply voltage, the V_A will alternate between 0 and 1 due to noise or offset. When the 0 and 1 ratios of the V_A signal are basically equal (i.e., the comparator is in a critical state), record the DAC control code at this time as the offset control code code0.

[0118] Store code0 in the offset storage module. Each level comparison module corresponds to an independent code0, supporting the multi-point detection requirement. Repeat the above steps for other level comparison modules in turn to complete the full-system calibration.

[0119] Through the above calibration to compensate for the offset, it is allowed to use a smaller-area level comparison module. Through dynamic reference voltage adjustment and offset code storage, efficient calibration of multi-node power detection is achieved.

[0120] After completing the above calibration process, the power supply drop event detection can be carried out, which specifically includes the following steps.

[0121] The calibration and control module reads the offset control code code0 of the corresponding level comparison module from the offset storage module. According to the power supply drop amplitude to be detected, perform an offset adjustment on the basis of code0 (for example, reduce the value of code0 to lower the reference voltage vref). Finally, generate a new control code code (for example, code0 ± Δ), and input it into the DAC of the reference generation module. The reference generation module generates the corresponding vref according to the adjusted code as the detection threshold.

[0122] According to the detection requirements, the output signal is selected through the digital signal gating mux. The V_A signal (continuous detection mode) is the original digital signal (0 / 1) directly output after the amplifier comparison, which is used to detect continuous power dips. The logic of the V_A signal is: when v_div < vref, V_A = 0, indicating that the power supply voltage is lower than the threshold (a dip is detected); when v_div > vref, V_A = 1, indicating that the power supply is normal. The V_B signal (transient detection mode) is the signal latched by the output DFF, which is used to detect transient power dips (such as short-time pulse interference). The logic of the V_B signal is: if the pulse with V_A = 1 is latched by the DFF to V_B = 1, it indicates that a transient dip has been detected (even if V_A then returns to 0). The signal levels are as Figure 10 shown. If the V_B signal is used, the DFF latching module needs to be reset after each detection to clear the historical state and prepare for the next transient event capture.

[0123] The calibration and control module sequentially switches the level comparison modules of different power nodes through the gating MUX to achieve multi-node time-sharing detection. According to the gated V_A or V_B signal, the system outputs a digital alarm signal (such as an interrupt signal or a status register flag bit). If dips of different amplitudes need to be detected, the code value can be adjusted in real time to dynamically change the vref threshold.

[0124] The chip power dip detection circuit provided in this embodiment has a small area of the level comparison module, which can be distributed at multiple power nodes. Time-sharing detection is achieved through the gating MUX, covering complex power networks, and can significantly improve the detection speed in complex power networks. The two detection modes are complementary. The V_A mode is suitable for continuously monitoring whether the power supply voltage is lower than the threshold (such as long-term undervoltage). The V_B mode captures short-time dips (such as ns-level glitches) through the latching function to avoid missing transient events. Combined with the calibrated offset code code0, the detection threshold can be flexibly set according to actual needs to adapt to the safety margins of different power domains.

[0125] The embodiment of this application also provides a computer device having the above Figure 1 shown power dip detection system.

[0126] Please refer to Figure 11 , Figure 11 which is a schematic structural diagram of a computer device provided by an alternative embodiment of this application, as Figure 11As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting the components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if needed, multiple processors and / or multiple buses can be used together with multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (such as an array of servers, a set of blade servers, or a multi-processor system). Figure 11 In [example], a single processor 10 is taken as an example.

[0127] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device can be a complex programmable logic device, a field-programmable gate array, a generic array logic, or any combination thereof.

[0128] Among them, the memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0129] The memory 20 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device. In addition, the memory 20 can include a high-speed random access memory and can also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 can optionally include a memory remotely set relative to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0130] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 can also include a combination of the above types of memories.

[0131] Embodiments of the present application also provide a computer-readable storage medium. The methods according to the embodiments of the present application can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the methods described herein can be stored in such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0132] Although embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A power drop detection system, characterized in that: Used to detect a target power supply node in a power supply network to be tested, the system comprises a reference generation module and a level comparison module; the level comparison module is connected to the target power supply node and the reference generation module respectively; The reference generation module is used to generate a reference voltage according to an offset control code corresponding to the target power supply node; The level comparison module is used to compare the node voltage of the target power node with the reference voltage and generate a detection signal according to the comparison result; the detection signal is used to indicate whether a power drop occurs at the target power node.

2. The system according to claim 1, characterized in that The level comparison module comprises: a comparison unit, a gating unit and a latch unit; The comparison unit is used to generate a detection signal according to the magnitude relationship between the node voltage and the reference voltage; the detection signal includes a first level signal or a second level signal; the first level signal is greater than the second level signal; the first level signal is used to indicate that the target power node has not experienced a power drop; the second level signal is used to indicate that the target power node has experienced a power drop; The latch unit is used to latch the first level signal to obtain a latch signal; the latch signal is used to indicate that a transient power drop has occurred at the target power node; The gating unit is used to select an output detection signal or a latch signal according to the type of the received power drop detection requirement.

3. The system according to claim 2, characterized in that The comparison unit is specifically used for: When the node voltage is greater than the reference voltage, a first level signal is generated; when the node voltage is less than the reference voltage, a second level signal is generated; When the power drop detection requirement type is continuous detection, the gating unit outputs a detection signal; when the power drop detection requirement type is transient detection, the gating unit outputs a latch signal and locks the output of the latch unit after outputting the latch signal.

4. The system according to claim 3, characterized in that The level comparison module also includes a control unit and a reset unit; The control unit is used to control the reset unit to send a reset signal to clear the output lock of the latch unit after the selection unit outputs the second power drop detection signal.

5. The system according to claim 4, characterized in that The system further comprises: A correction control module, connected to the reference generation module, for controlling the adjustment of the reference voltage and generating the offset control code in the correction process; The offset storage module is connected to the correction control module and the reference generation module respectively, and is used to store the offset control code.

6. The system according to claim 5, characterized in that The correction control module is specifically used for: In response to the received correction signal, the level comparison module to be corrected is controlled to output a detection signal, and the power supply network to be tested is controlled to enter a no-load static state; Acquire a first node voltage of a power supply node connected to the level comparison module to be corrected; Controlling the reference generation module to generate an initial reference voltage; The initial reference voltage is greater than the first node voltage; Controlling the reference generation module to gradually adjust the reference voltage, and monitoring the duty cycle of the detection signal in real time; When the duty cycle reaches a preset threshold, an offset control code corresponding to the current reference voltage is obtained.

7. The system according to claim 6, characterized in that The benchmark generation module is further used for: Generate a control code according to the offset control code and a preset drop amplitude of a target power supply node; A reference voltage is generated according to the control code.

8. The system according to any one of claims 1 to 7, characterized in that: There are multiple level comparison modules, and each level comparison module is respectively connected to a different power supply node in the power supply network to be tested.

9. The system according to claim 8, characterized in that The system further comprises: The gating module is used to gating the output signals of multiple level comparison modules.

10. A power drop detection method, characterized in that: Applied to the power drop detection system according to any one of claims 1 to 9, the method is performed by a level comparison module, and the method comprises: In response to the received power drop detection requirement, obtaining a power node to be tested and a corresponding imbalance control code; Acquire the current node voltage of the power node to be tested, and control the reference generation module to generate a reference voltage according to the offset control code; The current node voltage is compared with the reference voltage, and a detection signal is generated according to the comparison result; the detection signal is used to indicate whether a power drop occurs at the target power node.

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