Discrete magnitude rapid configuration method supporting hardware verification and control system

Abstract

The invention discloses a discrete magnitude rapid configuration method supporting hardware verification and a control system, an FPGA searches a corresponding discrete magnitude configuration value in a preset discrete magnitude lookup table according to a configuration starting signal and a required discrete magnitude working mode, and after the discrete state of each discrete magnitude group is configured, the discrete magnitude is configured to be a discrete magnitude set; writing a logic level signal in the configuration completion flag bit; when the configuration completion signal is a high level, triggering the FPGA to obtain the actual discrete magnitude state of each discrete magnitude group on the current hardware, inputting the current actual discrete magnitude state and a discrete magnitude configuration value when the hardware is configured according to the discrete magnitude lookup table into a verification algorithm for verification to obtain a verification result; a logic level signal written in the check completion flag bit; and the upper computer judges whether to correctly configure the discrete magnitude working mode of the hardware according to the read verification result. By reducing the number of register interfaces, the FPGA undertakes most work to improve the control and debugging efficiency of discrete magnitude.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic communication and control, and particularly relates to a method and control system for fast configuration of discrete quantities supporting hardware verification. Background Art

[0002] Discrete quantities include switch signals, enable signals, etc. The most important feature is that they have a definite level state (high level or low level) at a definite moment. With the increasing complexity of modern electronic systems, there are usually a large number of discrete quantities in a system (for example, there may be dozens of electronic switches in a spectrum analyzer). Using an FPGA with rich I / O resources to implement the control of these discrete quantities has become a common solution in the industry. The specific implementation is usually to store these discrete quantities in several registers on the internal bus defined by the logic in the FPGA first, and then let the host computer (such as a CPU, DSP, etc.) read and write and configure these registers to achieve the purpose of controlling the corresponding discrete quantities. The general block diagram of this solution is as Figure 1 .

[0003] It can be found from the block diagram that the biggest feature of this solution is that each group of discrete quantities requires a corresponding register, which leads to an increase in the number of register interfaces between the FPGA and the host computer as the number of discrete quantities increases. And at a definite moment, the host computer can only configure one register, that is, only the control of a group of discrete quantities can be realized at a definite moment. As Figure 1 shown, the discrete quantity control has the following defects:

[0004] 1. There are many register interfaces, and only one group of discrete quantities can be controlled at a definite moment, resulting in low control efficiency;

[0005] 2. The FPGA actually only provides a forwarding function, only responsible for forwarding the configuration value sent by the host computer to the logic to the corresponding discrete quantity, and the specific configured value is still determined by the host computer. This means that the software in the host computer must know what state the discrete quantity needs at the current moment, increasing the workload of the host computer software engineer and also reducing the debugging efficiency of the test engineer.

[0006] 3. There is a lack of substantial verification at the hardware level, and it is impossible to judge from the software level whether each discrete quantity on the hardware is controlled correctly. Only by using instruments such as a multimeter to measure the level states of each group of discrete quantities on the hardware can it be judged, which is very inconvenient.

[0007] Therefore, there is still a great room for improvement in the current control of discrete quantities, and it is necessary to further improve the configuration and debugging efficiency. Summary of the Invention

[0008] The object of the present invention is to provide a method for quickly configuring discrete quantities with hardware verification support and its FPGA implementation. By migrating the execution processes of configuration and verification into the FPGA, the number of register interfaces between the FPGA and the host computer is greatly reduced. The host computer only needs to give a start configuration signal, the working modes of current discrete quantities, and a start verification signal, and can complete the quick control of each group of discrete quantities on the hardware when polling the configuration completion signal. At the same time, the host computer only needs to read the verification result when polling the verification completion signal, and can judge whether each discrete quantity on the hardware is correctly controlled from the software level, so as to realize the substantial verification of each discrete quantity.

[0009] To achieve the above object, the present application provides the following solutions:

[0010] On the one hand, the present application provides a method for quickly configuring discrete quantities with hardware verification support, and the host computer executes the following steps:

[0011] S1. Send the discrete quantity working modes required for each group of discrete quantities on the current hardware and a configuration start signal to the FPGA;

[0012] S2. Poll the configuration completion signal given by the FPGA. The configuration completion signal is: after the FPGA searches for the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the current required discrete quantity working mode, and configures the discrete states of each group of discrete quantities on the hardware, the logic level signal written in the configuration completion flag bit.

[0013] S3. When polling that the configuration completion signal of the FPGA is at a high level, send a verification start signal to the FPGA;

[0014] S4. Poll the verification completion signal given by the FPGA. The verification completion signal is: after triggering the FPGA to obtain the actual discrete quantity states of each group of discrete quantities on the current hardware according to the verification start signal, inputting the current actual discrete quantity states and the discrete quantity configuration values found in step S2 into the verification algorithm for verification to obtain the verification result, the logic level signal written in the verification completion flag bit.

[0015] S5. After polling that the verification completion signal is at a high level, judge whether each group of discrete quantities on the hardware is in the configured working mode according to the read verification result.

[0016] In some specific implementation schemes, in step S2, the specific process of obtaining the configuration completion signal in the FPGA is as follows:

[0017] S21. Write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration;

[0018] S22. When the FPGA reads a logic high level from the configuration start register, clear the configuration completion signal of the previous configuration cached in the configuration completion register defined within the FPGA logic;

[0019] S23. The FPGA looks up the corresponding discrete quantity configuration value in a preset discrete quantity lookup table according to the discrete quantity working mode, and configures the discrete quantity states of each discrete quantity group on the hardware according to the discrete quantity configuration value;

[0020] S24. When the configuration of the discrete quantity states of each discrete quantity group on the hardware is completed, write the configuration completion signal of this configuration into the configuration completion register.

[0021] In some specific implementation manners, the specific process of obtaining the verification completion signal in the FPGA is as follows:

[0022] S41. Write a logic high level into the verification start register defined within the FPGA logic to start this verification;

[0023] S42. When the FPGA reads the logic high level in the verification start register, clear the verification completion signal of the previous verification cached in the verification completion register defined within the FPGA logic;

[0024] S43. Obtain the actual discrete quantity states of each discrete quantity group on the current hardware, call the verification algorithm implemented within the FPGA logic to verify the actual discrete quantity states and the discrete quantity configuration values when configuring the hardware according to the discrete quantity lookup table, and write the verification result into the verification result register defined within the FPGA logic after obtaining the verification result;

[0025] S44. When the verification is completed, write the verification completion signal of this verification into the verification completion register.

[0026] In some specific implementation manners, the verification algorithm in step S43 adopts bitwise exclusive OR verification or parity verification or CRC verification. The bitwise exclusive OR verification is: perform a bitwise exclusive OR operation on the actual discrete quantity states on the hardware and the discrete quantity configuration values configured by the host computer in parallel.

[0027] In some specific implementation manners, the preset discrete quantity lookup table is a truth table, and the configuration values required for each group of discrete quantities on the hardware in various working modes are solidified in the discrete quantity lookup table.

[0028] In some specific implementation manners, when polling the verification completion register, if the verification completion signal is read, read the verification result from the verification result register;

[0029] Judge whether the actual discrete quantity status on the hardware is consistent with the discrete quantity configuration value configured by the host computer according to the verification result. If it is consistent, judge that each discrete quantity group on the current hardware works in the discrete quantity working mode specified by the host computer; if it is inconsistent, judge that there is a discrete quantity group on the current hardware that does not work in the discrete quantity working mode specified by the host computer, and find out the discrete quantity group that does not work in the discrete quantity working mode specified by the host computer according to the verification result.

[0030] In a second aspect, the present application provides a control system for fast configuration of discrete quantities supporting hardware verification, including an FPGA and a host computer. The FPGA communicates with the host computer through its internal logic bus. Among them,

[0031] The host computer is used to send the discrete quantity working mode and the configuration start signal required for each current discrete quantity group to the FPGA.

[0032] It is also used to poll the configuration completion signal given by the FPGA. When the polled configuration completion signal of the FPGA is at a high level, send a verification start signal to the FPGA;

[0033] It is also used to poll the verification completion signal given by the FPGA. After polling that the verification completion signal is at a high level, judge whether each discrete quantity group on the hardware is in the configured working mode according to the read verification result;

[0034] The FPGA is used to find the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the current required discrete quantity working mode, and after configuring the discrete states of each discrete quantity group on the hardware, write the logic level signal into the configuration completion flag bit;

[0035] It is also used to trigger the FPGA to obtain the actual discrete quantity status of each discrete quantity group on the current hardware according to the verification start signal, input the current actual discrete quantity status and the discrete quantity configuration value when configuring the hardware according to the discrete quantity lookup table into the verification algorithm for verification, and after obtaining the verification result, write the logic level signal into the verification completion flag bit.

[0036] In some specific implementation schemes, the FPGA includes a configuration module, a configuration start register, a working mode register, and a configuration completion register. Among them,

[0037] The configuration module is used to write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration;

[0038] When a logic high level is read from the configuration start register, clear the configuration completion signal of the previous configuration cached in the configuration completion register defined in the FPGA logic;

[0039] Look up the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the discrete quantity working mode, and configure the discrete quantity states of each discrete quantity group on the hardware according to the discrete quantity configuration value;

[0040] When the discrete quantity states of each discrete quantity group on the hardware are configured, write the configuration completion signal of this configuration into the configuration completion register.

[0041] In some specific implementation schemes, the FPGA further includes a verification module, a verification start register, a verification completion register, and a verification result register, where,

[0042] The verification module is used to write a logic high level into the verification start register defined in the FPGA logic to start this verification;

[0043] When the logic high level in the verification start register is read, clear the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic;

[0044] Obtain the actual discrete quantity states of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity states and the discrete quantity configuration values when configuring the hardware according to the discrete quantity lookup table, and write the verification result into the verification result register defined in the FPGA logic;

[0045] When the verification is completed, write the verification completion signal of this verification into the verification completion register.

[0046] In some specific implementation schemes, the verification algorithm adopts bitwise exclusive OR verification or parity verification or CRC verification. The bitwise exclusive OR verification is: perform a bitwise exclusive OR operation on the actual discrete quantity states on the hardware and the discrete quantity configuration values configured by the host computer in parallel.

[0047] The beneficial effects of the present invention are:

[0048] 1. The configuration operation proposed in this application is convenient and fast. This is due to the fact that the number of interfaces between the FPGA and the host computer during configuration is very small. Different from the common solutions in the current industry, in this application, the number of register interfaces in the FPGA logic does not increase as the number of discrete quantities to be controlled increases. The host computer only needs to access 3 registers in total for one configuration or one verification. Whether it is one configuration or one verification, only 3 steps are required, namely, giving the start signal of the configuration or verification, giving the working mode of the discrete quantity or reading out the substantial verification result at the hardware level, and polling the completion flag bit of the configuration or verification. The operation is very simple;

[0049] 2. This application has a high encapsulation level. In this application, the actual control execution authority of discrete quantities is transferred from the host computer to the FPGA. During a single configuration process, the host computer software engineer only needs to know the working mode of the discrete quantities at the current moment, and does not need to know the specific configuration values corresponding to this working mode, because the specific configuration values will be automatically obtained by the discrete quantity lookup table in this method. For the host computer software engineer, the control of discrete quantities becomes a "black box", and only the input needs to be provided and then wait for the output result, which greatly improves the work and debugging efficiency of the host computer software engineer and the test engineer.

[0050] 3. This application realizes true hardware verification. By enabling the verification function, the host computer can monitor the actual true level status of each group of discrete quantities on the hardware at any time, so as to judge whether there are errors in discrete quantities at the hardware level, and can further know which specific discrete quantities are in error. When an error occurs, there is no need to rely on instruments such as multimeters to judge, which greatly improves the troubleshooting efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a system block diagram implemented by the prior art;

[0052] Figure 2 is a system block diagram implemented by the discrete quantity fast configuration method supporting hardware verification provided by the embodiment of the present invention;

[0053] Figure 3 is a state transition schematic diagram of the configuration state machine provided by the embodiment of the present invention;

[0054] Figure 4 is a state transition schematic diagram of the verification state machine provided by the embodiment of the present invention;

[0055] Figure 5 is a flowchart of the discrete quantity fast configuration method supporting hardware verification provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0057] Unless otherwise specifically stated, the relative arrangements, numerical expressions and values of the components and steps described in these embodiments do not limit the scope of the present invention.

[0058] Meanwhile, it should be understood that, for the sake of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0059] In addition, for the sake of clarity and conciseness, the description of well-known structures, functions and configurations may be omitted. Those of ordinary skill in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0060] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be regarded as part of the authorization specification.

[0061] In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.

[0062] As Figure 1 shown, generally in a control system, for the control of discrete quantities, each group of discrete quantities needs to correspond to a register, which results in an increase in the number of register interfaces between the FPGA and the host computer as the number of discrete quantities increases, and at a determined moment, the host computer can only configure one register, that is, only the control of a group of discrete quantities can be achieved at a determined moment. In today's control systems with numerous discrete quantities, the control efficiency is undoubtedly very low;

[0063] In addition, it can be seen that in this control mode, the FPGA actually only provides a forwarding function, only responsible for sending the configuration values issued by the host computer to the corresponding discrete quantities through the corresponding registers in the logic internal bus, and the specific configuration is still determined by the host computer, which means that the software in the host computer must know what state the discrete quantity needs at the current moment. As mentioned above, the state value of the discrete quantity at a determined moment is nothing but simply "0" or "1", and does not involve complex software calculations at all. Therefore, letting the host computer determine the configuration will increase the workload of the host computer software engineer and also reduce the debugging efficiency of the test engineer. For example, if a certain discrete quantity needs to be configured in mode A at a certain moment, and the configuration value corresponding to mode A is "0x3c", then both the host computer software engineer and the test engineer not only need to know that the discrete quantity needs to work in mode A at this time, but also need to send "0x3c" to the FPGA to complete the control.

[0064] After the control is completed, the existing solution lacks substantial verification at the hardware level, that is, the host computer can only confirm whether the configuration value has been correctly sent to the FPGA by reading back the value of the corresponding register. It is impossible to determine whether the actual discrete quantity in the hardware is controlled correctly. If a hardware error occurs (for example, a discrete quantity is forced to be pulled up or down in the hardware), it is impossible to locate which discrete quantity has a problem from the software level. It can only be located by using instruments such as multimeters to measure the level state of the discrete quantity, which is very inconvenient.

[0065] In view of this, this application proposes the following solutions:

[0066] Example 1

[0067] like Figure 2 As shown, this embodiment provides a control system that supports fast configuration of discrete quantities with hardware verification, which is implemented by FPGA and includes FPGA and a host computer. The FPGA communicates with the host computer through its logical internal bus, wherein:

[0068] The host computer is used to send the discrete quantity working mode required by each discrete quantity group and configure the start signal to the FPGA.

[0069] It is also used to poll the configuration completion signal given by the FPGA. When the configuration completion signal of the FPGA is at a high level, a verification start signal is sent to the FPGA.

[0070] It is also used to poll the verification completion signal given by FPGA. When the verification completion signal is high level, it is judged whether each discrete quantity group on the hardware is in the configured working mode according to the read verification result.

[0071] FPGA, used to find the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the currently required discrete quantity working mode, and after configuring the discrete state of each discrete quantity group on the hardware, write the logic level signal in the configuration completion flag bit;

[0072] It is also used to trigger the FPGA to obtain the actual discrete quantity status of each discrete quantity group on the current hardware according to the verification start signal, input the current actual discrete quantity status and the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table into the verification algorithm for verification, and after obtaining the verification result, write the logic level signal to the verification completion flag.

[0073] Specifically, the FPGA includes a configuration module, a configuration start register, an operating mode register, and a configuration completion register, wherein:

[0074] A configuration module is used to write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration;

[0075] When a logic high level is read from the configuration start register, clear the configuration completion signal of the previous configuration cached in the configuration completion register defined in the FPGA logic;

[0076] Look up the corresponding discrete quantity configuration value in the preset discrete quantity look-up table according to the discrete quantity working mode, and configure the discrete quantity states of each discrete quantity group on the hardware according to the discrete quantity configuration value;

[0077] When the discrete quantity states of each discrete quantity group on the hardware are configured, write the configuration completion signal of this configuration into the configuration completion register.

[0078] Specifically, the FPGA further includes a verification module, a verification start register, a verification completion register, and a verification result register, where

[0079] The verification module is used to write a logic high level into the verification start register defined in the FPGA logic to start this verification;

[0080] When a logic high level is read from the verification start register, clear the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic;

[0081] Obtain the actual discrete quantity states of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity states and the discrete quantity configuration values when configuring the hardware according to the discrete quantity look-up table, and write the verification result into the verification result register defined in the FPGA logic;

[0082] The verification algorithm adopts bitwise exclusive OR verification or parity verification or CRC verification. The bitwise exclusive OR verification is: perform a bitwise exclusive OR operation on the actual discrete quantity states on the hardware and the discrete quantity configuration values configured by the host computer in parallel.

[0083] When the verification is completed, write the verification completion signal of this verification into the verification completion register.

[0084] From Figure 2 、 Figure 3 And Figure 4It can be seen that the FPGA control logic mainly includes a configuration module and a verification module. The configuration module is responsible for realizing the rapid control of discrete quantities, and the verification module is responsible for realizing the substantial verification of the controlled state of discrete quantities at the hardware level. The configuration module contains two parts: a discrete quantity lookup table and a configuration state machine. The discrete quantity lookup table is essentially a truth table. The truth table is implemented by combinational logic resources such as LUT in FPGA. It solidifies the configuration values ​​of each group of discrete quantities in the entire electronic system under various working modes. These configuration values ​​are directly sent to the discrete quantities by FPGA, and the sending process is scheduled by the logic control flow formed by the configuration state machine. The verification module contains two parts: a verification algorithm core and a verification state machine. The verification algorithm core implements a specific verification algorithm. The verification algorithm used in this article is XOR verification. Other verification algorithms (such as parity check, CRC check, etc.) can also be integrated into the verification algorithm core as needed. The calculation process of the algorithm core is scheduled by the logic control flow formed by the verification state machine.

[0085] In order to reduce the register connection interface with the host computer and the configuration and verification calculation amount of the host computer, the FPGA in this application undertakes most of the work, and there are only 6 register interfaces between the host computer, which are defined on the logical internal bus.

[0086] When each group of discrete quantities needs to be controlled at a certain moment, the host computer first needs to write the working mode of each group of discrete quantities at this time into the working mode register. At this time, the FPGA logic will input the value in the working mode register into the discrete quantity lookup table. The discrete quantity lookup table will obtain the corresponding discrete quantity configuration value according to the working mode. Then the host computer needs to write "1" to the configuration start register to indicate the configuration trigger. At this time, the FPGA logic will generate a configuration trigger signal to the configuration state machine, and then start the configuration of each group of discrete quantities. According to the discrete quantity configuration value obtained from the discrete quantity lookup table, each group of discrete quantities is controlled in parallel. After the control is completed, the FPGA logic will write "1" to the configuration completion register to indicate that the configuration is completed as a configuration completion flag. The configuration completion flag will be cleared at the beginning of the next configuration. When the host computer polls and the flag is set, the configuration ends. The configuration state machine is divided into 4 states, namely IDLE state, CLR state, PROGRAM state and DONE state. The state transition diagram is shown as follows Figure 3As shown, the IDLE state is responsible for waiting for the configuration trigger signal, that is, waiting for the host computer to start the configuration process. When the configuration state machine reads a "1" from the configuration start register, it changes from the IDLE state to the CLR state. The CLR state is responsible for clearing the configuration completion flag generated by the previous configuration. When changing from the IDLE state to the CLR state, the value of the configuration completion flag in the configuration completion register is cleared. After the clearing is completed, it changes to the PROGRAM state. The PROGRAM state is responsible for configuring each group of discrete quantities. When the configuration is completed, it jumps to the DONE state. The DONE state is responsible for setting the configuration completion flag for this time and ending this configuration process.

[0087] In this application, the verification module can immediately verify the configured result after each configuration is completed, or can separately start the verification module when verification is desired to be started.

[0088] When hardware verification of each group of discrete quantities is required, the host computer first needs to write a "1" to the verification start register to indicate verification trigger. At this time, the FPGA logic will generate a verification trigger signal to the verification state machine. At this time, this protocol starts verification. The FPGA logic will parallelly input the states of the current groups of discrete quantities into the verification algorithm core. The verification algorithm core will parallelly perform a bitwise exclusive OR operation on the states of each group of discrete quantities and the discrete quantity configuration values maintained in the current discrete quantity look-up table, and store the verification result in the verification result register (if a certain group of discrete quantities is incorrect, the corresponding bit in the verification result register will be set to "1"). After the verification is completed, the FPGA logic will write a "1" to the verification completion register as the verification completion flag. This flag will be cleared at the start of the next verification. When the host computer polls and finds that this flag is set, this protocol ends. The verification state machine also has 4 states, namely the IDLE state, the CLR state, the CHECK state, and the DONE state. Its state transition diagram is as Figure 4 As shown, the IDLE state is responsible for waiting for the verification trigger signal, that is, waiting for the host computer to start verification. When the verification state machine reads a "1" from the verification start register, it changes from the IDLE state to the CLR state; the CLR state is responsible for clearing the verification completion flag generated by the previous verification; when changing from the IDLE state to the CLR state, the value of the verification completion flag in the verification completion register is cleared. After the clearing is completed, it changes to the CHECK state. The CHECK state is responsible for performing hardware verification on the current states of each group of discrete quantities; when the verification is completed, it jumps to the DONE state. The DONE state is responsible for setting the verification completion flag for this time and ending this verification.

[0089] Embodiment 2

[0090] As Figure 5As shown in the figure, this embodiment provides a method for quickly configuring discrete quantities that supports hardware verification. For the above control system, the host computer performs the following steps:

[0091] S1. Send the discrete quantity working mode and configuration start signal required for each discrete quantity group on the current hardware to the FPGA;

[0092] S2. Poll the configuration completion signal given by the FPGA. The configuration completion signal is: According to the configuration start signal and the current required discrete quantity working mode, the FPGA looks up the corresponding discrete quantity configuration value in the preset discrete quantity lookup table, and after configuring the discrete states of each discrete quantity group on the hardware, the logic level signal written in the configuration completion flag bit (this signal is high level when the configuration is completed);

[0093] At this time, the following process is executed in the FPGA:

[0094] S21. Write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration;

[0095] S22. When the FPGA reads a logic high level from the configuration start register, clear the configuration completion signal of the previous configuration cached in the configuration completion register defined in the FPGA logic;

[0096] S23. The FPGA looks up the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the discrete quantity working mode, and configures the discrete quantity states of each discrete quantity group on the hardware according to the discrete quantity configuration value;

[0097] S24. When the configuration of the discrete quantity states of each discrete quantity group on the hardware is completed, write the configuration completion signal of this configuration into the configuration completion register.

[0098] S3. When polling that the configuration completion signal of the FPGA is high level, send a verification start signal to the FPGA;

[0099] S4. Poll the verification completion signal given by the FPGA. The verification completion signal is: According to the verification start signal, trigger the FPGA to obtain the actual discrete quantity states of each discrete quantity group on the current hardware, input the current actual discrete quantity states and the discrete quantity configuration values in step S2 into the verification algorithm for verification to obtain the verification result, and then the logic level signal written in the verification completion flag bit, this signal is high level when the verification is completed;

[0100] At this time, the following process is executed in the FPGA:

[0101] S41. Write a logic high level to the check start register defined within the FPGA logic to start this check;

[0102] S42. When the FPGA reads the logic high level in the check start register, clear the check completion signal of the previous check cached in the check completion register defined within the FPGA logic;

[0103] S43. Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the check algorithm implemented within the FPGA logic to check the actual discrete quantity status against the discrete quantity configuration value when configuring the hardware according to the discrete quantity look-up table, and write the check result into the check result register defined within the FPGA logic after obtaining the check result;

[0104] S44. When the check is completed, write the check completion signal of this check into the check completion register.

[0105] S5. After polling and finding that the check completion signal is at a high level, determine whether each discrete quantity group on the hardware is in the configured working mode according to the read check result. It is possible to determine whether the hardware is indeed in the working mode issued by the host computer based on the status of each discrete group read on the hardware, and whether there is a situation where the configuration is successful but each discrete group on the hardware does not work in the correct working mode.

[0106] When polling the check completion register, if the check completion signal is read, read the check result from the check result register;

[0107] Judge whether the actual discrete quantity status on the hardware is consistent with the discrete quantity configuration value configured by the host computer according to the check result. If they are consistent, it is judged that each discrete quantity group on the current hardware is working in the discrete quantity working mode specified by the host computer; if they are inconsistent, it is judged that there is a discrete quantity group on the current hardware that is not working in the discrete quantity working mode specified by the host computer, and find out the discrete quantity group that is not working in the discrete quantity working mode specified by the host computer according to the check result.

[0108] The above is only a preferred embodiment of the present invention, and does not impose any form of limitation on the present invention. Based on the technical essence of the present invention, any simple modification, equivalent replacement, and improvement made to the above embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A discrete quantity fast configuration method supporting hardware verification, characterized in that: The host computer performs the following steps: S1, sending the discrete quantity working mode and configuration start signal required by each discrete quantity group on the current hardware to the FPGA; S2, polling the configuration completion signal given by FPGA, wherein the configuration completion signal is: FPGA searches for the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the currently required discrete quantity working mode, and configures the discrete state of each discrete quantity group on the hardware, and then writes a logic level signal to the configuration completion flag; S3, when the configuration completion signal of the FPGA is polled to be high level, a verification start signal is sent to the FPGA; S4, polling the verification completion signal given by FPGA, wherein the verification completion signal is: triggering FPGA to obtain the actual discrete quantity state of each discrete quantity group on the current hardware according to the verification start signal, inputting the current actual discrete quantity state and the discrete quantity configuration value found in step S2 into the verification algorithm for verification to obtain the verification result, and then writing the logic level signal in the verification completion flag; S5. When the check completion signal is polled to be at a high level, it is determined whether each discrete quantity group on the hardware is in the configured working mode according to the read check result.

2. A discrete quantity fast configuration method supporting hardware verification according to claim 1, characterized in that: In step S2, the specific process of obtaining the configuration completion signal in the FPGA is as follows: S21, writing the discrete quantity working mode into the working mode register defined in the FPGA logic, and writing a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration; S22, when the FPGA reads a logic high level from the configuration start register, clear the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic; S23, FPGA searches for the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the discrete quantity working mode, and configures the discrete quantity state of each discrete quantity group on the hardware according to the discrete quantity configuration value; S24. When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, a configuration completion signal of this configuration is written into the configuration completion register.

3. A discrete quantity fast configuration method supporting hardware verification according to claim 1, characterized in that: The specific process of obtaining the verification completion signal in FPGA is: S41, write a logic high level into the verification start register defined in the FPGA logic to start this verification; S42, when the FPGA reads the logic high level in the verification start register, the verification completion signal of the last verification cached in the verification completion register defined in the FPGA logic is cleared; S43, obtaining the actual discrete quantity state of each discrete quantity group on the current hardware, calling the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity state with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and writing the verification result into the verification result register defined in the FPGA logic after obtaining it; S44. When the verification is completed, a verification completion signal of this verification is written into the verification completion register.

4. A discrete quantity fast configuration method supporting hardware verification according to claim 3, characterized in that: In step S43, the check algorithm adopts bitwise XOR check, parity check or CRC check. The bitwise XOR check is: performing bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

5. The method for fast discrete quantity configuration supporting hardware verification according to claim 1, characterized in that: The preset discrete quantity lookup table is a truth table, and the discrete quantity lookup table solidifies the configuration values ​​required for each group of discrete quantities on the hardware in various working modes.

6. A discrete quantity fast configuration method supporting hardware verification according to claim 1, characterized in that: In step S5, when polling the verification completion register, if a verification completion signal is read, the verification result is read from the verification result register; According to the verification result, it is judged whether the actual discrete quantity state on the hardware is consistent with the discrete quantity configuration value configured by the host computer. If consistent, it is judged that each discrete quantity group on the current hardware works in the discrete quantity working mode specified by the host computer; if inconsistent, it is judged that there are discrete quantity groups on the current hardware that do not work in the discrete quantity working mode specified by the host computer, and the discrete quantity groups that do not work in the discrete quantity working mode specified by the host computer are found out according to the verification result.

7. A control system for fast configuration of discrete quantities supporting hardware verification, characterized in that: It includes FPGA and host computer. FPGA communicates with the host computer through its internal logic bus. The host computer is used to send the discrete quantity working mode required by each discrete quantity group and configure the start signal to the FPGA. It is also used to poll the configuration completion signal given by the FPGA. When the configuration completion signal of the FPGA is at a high level, a verification start signal is sent to the FPGA. It is also used to poll the verification completion signal given by FPGA. When the verification completion signal is high level, it is judged whether each discrete quantity group on the hardware is in the configured working mode according to the read verification result. FPGA, used to find the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the currently required discrete quantity working mode, and after configuring the discrete state of each discrete quantity group on the hardware, write the logic level signal in the configuration completion flag bit; It is also used to trigger the FPGA to obtain the actual discrete quantity status of each discrete quantity group on the current hardware according to the verification start signal, input the current actual discrete quantity status and the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table into the verification algorithm for verification, and after obtaining the verification result, write the logic level signal to the verification completion flag.

8. A control system for discrete quantity rapid configuration supporting hardware verification according to claim 7, characterized in that: FPGA includes a configuration module, a configuration start register, an operating mode register, and a configuration completion register, among which: A configuration module, used for writing a discrete quantity operation mode into an operation mode register defined in the FPGA logic, and writing a logic high level into a configuration start register defined in the FPGA logic according to a configuration start signal to start the configuration; When a logic high level is read from the configuration start register, the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic is cleared; According to the discrete quantity working mode, the corresponding discrete quantity configuration value is searched in the preset discrete quantity lookup table, and the discrete quantity state of each discrete quantity group on the hardware is configured according to the discrete quantity configuration value; When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, the configuration completion signal of this configuration is written into the configuration completion register.

9. A control system for discrete quantity rapid configuration supporting hardware verification according to claim 7, characterized in that: The FPGA also includes a verification module, a verification start register, a verification completion register, and a verification result register, wherein: The verification module is used to write a logic high level into the verification start register defined in the FPGA logic to start this verification; When a logic high level is read in the verification start register, the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic is cleared; Get the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the verification result into the verification result register defined in the FPGA logic after obtaining it; When the verification is completed, the verification completion signal of this verification is written into the verification completion register.

10. A control system for discrete quantity rapid configuration supporting hardware verification according to claim 7, characterized in that: The verification algorithm adopts bitwise XOR verification or parity verification or CRC verification. The bitwise XOR verification is: performing bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

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