Hardware Component Connection Recovery Method, Device, Storage Medium and Program Product

Abstract

The present application discloses a method, device, storage medium and program product for restoring the connection of a hardware component, relating to the field of computer technology. After detecting the insertion of a hardware component, it detects whether the connection between the hardware component and the target slot is abnormal. In the case of an abnormal connection, a stop transmission instruction is sent to the controller associated with the hardware component to prevent the controller from transmitting data with the hardware component, and the target slot is restarted to attempt to restore the connection with the hardware component. In the case of a failure to restore, the hardware component is powered off and then powered on, and the process of restarting the target slot is executed again to restore the connection with the hardware component. If the connection is still abnormal, the slot restart and the power on / off of the hardware component are repeated. Since the controller is prevented from transmitting data with the hardware component, it is possible to prevent data corruption, data loss and hardware damage, and by enabling the slot after failure and powering on / off the hardware component, the effect of active recovery in the case of an abnormal connection is achieved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a method, device, storage medium, and program product for restoring the connection of hardware components. Background Art

[0002] In order to transfer data at a faster speed, hardware components such as graphics cards, solid-state drives, and network cards are usually connected to a computer through PCIe (Peripheral Component Interconnect Express) slots.

[0003] Currently, some hardware components have multiple interfaces, and multiple slots need to be used simultaneously to connect multiple controllers, and hot plugging is required during use.

[0004] However, when current hardware components perform hot plugging, there may be a lack of a method to actively repair anomalies, and data processing errors may occur in the controller when the hardware components are connected to multiple slots. Summary of the Invention

[0005] Embodiments of this application provide a method, device, storage medium, and program product for restoring the connection of hardware components, so as to actively repair anomalies generated during hot plugging of hardware components and avoid data processing errors when hardware components are connected to multiple slots.

[0006] An embodiment of this application provides a method for restoring the connection of hardware components, including: if it is detected that a target slot inserts a hardware component, detecting whether the hardware component is abnormally connected; if the hardware component is abnormally connected, determining a target controller associated with the hardware component; sending a stop transmission instruction to the target controller so that the target controller stops data transmission with the hardware component according to the stop transmission instruction; setting a connection failure bit of a connection control register of the target slot to a first preset value to disable the target slot and start timing to obtain a first timing duration; if the first timing duration is greater than or equal to a first preset duration, setting the connection failure bit of the connection control register to a second preset value to enable the target slot; detecting again whether the hardware component is abnormally connected; if the hardware component is still abnormally connected, powering off the hardware component and then delaying power-on, and repeating the steps of disabling the target slot to detecting whether the hardware component is abnormally connected; if the hardware component is abnormally connected, repeating the steps of disabling the target slot to powering off the hardware component and then delaying power-on until the hardware component is normally connected or repeating n times, where n is a positive integer.

[0007] An embodiment of the present application provides a hardware component connection recovery device, including: an abnormality detection module, configured to detect whether a hardware component is abnormally connected if it is detected that the hardware component is inserted into a target slot; a controller determination module, configured to determine a target controller associated with the hardware component if the hardware component is abnormally connected; an instruction sending module, configured to send a stop transmission instruction to the target controller, so that the target controller stops data transmission with the hardware component according to the stop transmission instruction; a slot failure module, configured to set a connection failure bit of a connection control register of the target slot to a first preset value, so that the target slot fails and starts timing to obtain a first timing duration; a slot enabling module, configured to set the connection failure bit of the connection control register to a second preset value if the first timing duration is greater than or equal to a first preset duration, so that the target slot is enabled; the abnormality detection module is further configured to detect again whether the hardware component is abnormally connected; a power-on / off control module, configured to power off the hardware component and then delay power-on if the hardware component is still abnormally connected, and repeatedly execute the steps from making the target slot fail to detecting whether the hardware component is abnormally connected; a repeated repair module, configured to repeatedly execute the steps from making the target slot fail to powering off the hardware component and then delaying power-on if the hardware component is abnormally connected, until the hardware component is normally connected or the steps are repeatedly executed n times, where n is a positive integer.

[0008] An embodiment of the present application provides a hardware component connection recovery device, including: a memory, a processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementation manners of the first aspect.

[0009] An embodiment of the present application provides a computer-readable storage medium, in which computer execution instructions are stored, and when the computer execution instructions are executed by a processor, they are used to implement the above first aspect and / or various possible implementation manners of the first aspect.

[0010] An embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the above first aspect and / or various possible implementation manners of the first aspect.

[0011] The hardware component connection recovery method, device, storage medium and program product provided by the embodiments of the present application, by detecting whether the hardware component is abnormally connected after detecting the insertion of the hardware component, preventing the controller associated with the hardware component from transmitting data to the hardware component in the case of abnormal connection, thereby preventing data corruption, data loss and hardware damage, restarting the target slot, attempting to restore the connection with the hardware component, powering off and then powering on the hardware component in the case of failed recovery, and repeatedly executing the process of restarting the target slot to restore the connection with the hardware component, so as to achieve the effect of active recovery in the case of abnormal connection and protecting the data correctness. Brief Description of the Drawings

[0012] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 It is a schematic diagram of the scenario for the connection recovery of hardware components provided by the present application;

[0014] Figure 2 It is a schematic flowchart of the method for the connection recovery of hardware components provided by the present application;

[0015] Figure 3 It is a schematic structural diagram of the device for the connection recovery of hardware components provided by the present application;

[0016] Figure 4 It is a schematic structural diagram of the device for the connection recovery of hardware components provided by the present application. Detailed Description of the Embodiments

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0018] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0019] Hardware components such as graphics cards, solid-state drives, and network cards usually use PCIe (Peripheral Component Interconnect Express) slots to connect to the computer motherboard to achieve efficient data transmission. As a new generation of high-speed serial computer expansion bus standard, PCIe provides data bandwidth far exceeding that of traditional interfaces for various hardware components through a point-to-point serial connection method.

[0020] For some hardware components with multiple physical interfaces, when in use, they need to occupy multiple PCIe slots simultaneously and configure controllers for each slot separately. Some hardware components support hot plugging operations in a non-stop state. However, during the hot plugging process, anomalies may occur. After anomalies occur, there is a lack of active repair methods and it is easy to cause data processing errors.

[0021] To address the above technical problems, the inventor proposed the following technical concept: by disabling and then enabling the slots, and performing power-on and power-off operations on the hardware components connected to the slots to restore the connection to normal, and terminating the data transfer between the controller associated with the hardware component and the hardware component before performing the recovery process.

[0022] Figure 1 This is a schematic diagram of the scenario for restoring the connection of the hardware components provided in this application. As Figure 1 shown, the specific application scenario of this application includes:

[0023] Processor 101, controller 102, connection control register 103, CPIe slot 104, hardware component 105.

[0024] Processor 101 may include: CPU (central processing unit, central processor), programmable logic device (PLD, programmable logic device), control board, ECU (Electronic Control Unit, electronic control unit), etc.

[0025] Controller 102 may include a switch controller, an endpoint controller, a bridge controller, a root port controller, etc.

[0026] Connection control register 103 may include any type of register.

[0027] CPIe slot 104 may include a slot applicable to the high-speed serial computer expansion bus standard.

[0028] Hardware component 105 may include hardware such as a hard disk, a graphics card, a network card, etc.

[0029] Processor 101 is communicatively connected to controller 102, connection control register 103 and controller 102 are communicatively connected to CEIe slot 104, and hardware component 105 is pluggably installed on CEIe slot 104.

[0030] The processor 101 is used to obtain the connection status of the hardware component 105 after it is installed in the CPIe slot 104. In the case of an abnormal connection, by changing the bit of the connection control register 103, the slot is disabled and then enabled, so that the state machine of the root port returns to the default exploration state, and the normal connection between the hardware component 105 and the CPIe slot 104 is restored. If the connection is still abnormal, the hardware component 105 is powered off and then powered on, and the connection is detected again for abnormality. If it is still abnormal, the process of disabling and then enabling the slot and the power-on and power-off processes are repeated until the connection is restored to normal or remains abnormal after repeating the preset number of times.

[0031] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0032] Figure 2 It is a schematic flowchart of the hardware component connection recovery method provided by the present application. As Figure 2 shown, the method includes:

[0033] S201: If it is detected that a hardware component is inserted into the target slot, it is detected whether the hardware component is abnormally connected.

[0034] In this step, detecting that a hardware component is inserted into the target slot may include obtaining the presence information of the hardware component from the PCIe bus in-band. If there is presence information, it is determined that a hardware component is inserted into the target slot. It may also include detecting the high level or low level of a certain pin to determine that a hardware component is inserted into the target slot. Detecting whether the hardware component is abnormally connected may include: detecting whether the connection to the hardware component is disconnected, whether the bandwidth or transmission rate has decreased. If the connection is disconnected, the bandwidth has decreased, or the transmission rate has decreased, it is determined that the hardware component is abnormally connected.

[0035] S202: If the hardware component is abnormally connected, the target controller associated with the hardware component is determined.

[0036] In this step, it may include looking up the correspondence between the hardware component identifier and the controller to obtain the target controller associated with the hardware component; it may also include sending hardware identifier query information to each controller to obtain the hardware identifier returned by the controller. If the hardware identifier returned by any controller is the same as the identifier of the hardware component, this controller is determined as the target controller.

[0037] S203: Send a stop transmission instruction to the target controller so that the target controller stops data transmission with the hardware component according to the stop transmission instruction.

[0038] In this step, the stop transmission instruction can be pre-set, and the target controller stops data transmission after receiving the stop transmission instruction.

[0039] S204: Set the connection failure bit of the connection control register of the target slot to a first preset value to disable the target slot and start timing to obtain a first timing duration.

[0040] In this step, the connection failure bit can be the fourth bit of the connection control register, and the first preset value is, for example, 1. The first timing duration can be the duration obtained by subtracting the start time from the current time.

[0041] S205: If the first timing duration is greater than or equal to a first preset duration, set the connection failure bit of the connection control register to a second preset value to enable the target slot.

[0042] In this step, the first preset duration can be pre-set by the staff according to experimental data or experience, such as 10ms, 20ms, 30ms, etc.

[0043] S206: Detect again whether the hardware components are abnormally connected.

[0044] This step is the same as the way of detecting whether the hardware components are abnormally connected in the above step S201 and will not be elaborated here.

[0045] S207: If the hardware components are still abnormally connected, power off the hardware components and then delay power-on, and execute the steps from disabling the target slot to detecting whether the hardware components are abnormally connected again.

[0046] In this step, powering off the hardware components can include sending a power-on / off signal to the CPLD (Complex Programmable Logic Device) to enable the CPLD to control the hardware components to power off and then power on. There can be a time interval between power off and power on, such as 100ms, 150ms, 200ms, etc. The steps from disabling the target slot to detecting whether the hardware components are abnormally connected can include the above steps S204 to S206.

[0047] S208: If the hardware components are abnormally connected, repeat the steps from disabling the target slot to powering off the hardware components and then delaying power-on until the hardware components are normally connected or repeat n times, where n is a positive integer.

[0048] In this step, the steps from disabling the target slot to powering off the hardware components and then delaying power-on can include steps S204 to S207.

[0049] Among them, n is, for example, 2, 3, 4, etc.

[0050] From the description of the above embodiments, it can be seen that in the embodiments of the present disclosure, after detecting the insertion of a hardware component, it is detected whether the hardware component is abnormally connected. In the case of abnormal connection, the controller associated with the hardware component is prevented from transmitting data to the hardware component, thereby preventing data corruption, data loss, and hardware damage, and restarting the target slot to attempt to restore the connection with the hardware component. In the case of failure to restore, the hardware component is powered off and then powered on, and the process of restarting the target slot is executed again to restore the connection with the hardware component, so as to achieve the effect of active recovery in the case of abnormal connection and protect the data correctness.

[0051] In a possible implementation manner, after the above step S208, if the hardware component is normally connected, the hot plugging process is normally executed.

[0052] In a possible implementation manner, in the above step S201, if it is detected that a hardware component is inserted into the target slot, it is detected whether the hardware component is abnormally connected, including: step S2011 and step S2012.

[0053] S2011: In response to detecting that a hardware component is inserted into the target slot, obtain the bandwidth and transmission rate stored in the connection status register of the target slot.

[0054] In this step, each slot has a corresponding connection status register, which is used to store various information related to the connection of the slot. By reading the data stored in the connection status register, the bandwidth and transmission rate are obtained.

[0055] S2012: Determine whether the hardware component is abnormally connected according to the bandwidth and transmission rate.

[0056] In this step, it may include determining whether the hardware component is abnormally connected according to the change amount of the bandwidth, whether the bandwidth is the same as the preset bandwidth, or the change of the transmission rate.

[0057] From the description of the above embodiments, it can be seen that in the embodiments of the present disclosure, after a hardware component is inserted into the slot, the bandwidth and transmission rate stored in the connection status register of the target slot are obtained, and whether there is an abnormal connection is judged by the bandwidth and transmission rate, so as to quickly judge whether the hardware component is abnormal and reduce the time cost of troubleshooting.

[0058] In a possible implementation manner, the bandwidth and transmission rate are obtained by periodic detection.

[0059] In the above step S2012, determining whether the hardware component is abnormally connected according to the bandwidth and transmission rate includes: steps S12A1 to S12A4.

[0060] S12A1: Determine the number of target detection cycles whose transmission rate is lower than the preset transmission rate threshold.

[0061] In this step, it may include calculating the average value of the transmission rate within each detection cycle and determining the cycle with the average value lower than the preset transmission rate threshold as the target detection cycle; it may also include determining the cycle with the lowest transmission rate lower than the preset transmission rate threshold as the target detection cycle.

[0062] For example, if the average transmission rate corresponding to cycle A is 4 GB / s and the preset transmission rate threshold is 6 GB / s, then cycle A is determined as the target detection cycle. Another example, if the minimum value of the transmission rate corresponding to cycle B is 1 GB / s and the preset transmission rate threshold is 4 GB / s, then cycle B is determined as the target detection cycle.

[0063] S12A2: Divide the number of target detection cycles by the total number of detection cycles to obtain a cycle ratio.

[0064] In this step, the total number of detection cycles may be the number of detection cycles included within a period of time.

[0065] For example, if the number of target detection cycles is 5 and the total number of detection cycles is 10, then the cycle ratio is 0.5. Another example, if the number of target detection cycles is 4 and the total number of detection cycles is 20, then the cycle ratio is 0.2.

[0066] S12A3: If the cycle ratio is greater than the preset cycle ratio threshold, determine that the connection of the hardware component is abnormal.

[0067] In this step, the cycle ratio threshold may be preset by the staff according to experimental data or empirical parameters.

[0068] For example, if the cycle ratio is 0.9 and the cycle ratio threshold is 0.8, then determine that the connection of the hardware component is abnormal. Another example, if the cycle ratio is 0.8 and the cycle ratio threshold is 0.6, then determine that the connection of the hardware component is abnormal.

[0069] S12A4: If the bandwidth detected in any detection cycle is different from the preset bandwidth, determine that the connection of the hardware component is abnormal.

[0070] In this step, the preset bandwidth may be calibrated in advance by the staff, may correspond to the model of the hardware component, or may be jointly determined by the rated bandwidth of the hardware component and the rated bandwidth of the slot.

[0071] As can be seen from the description of the above embodiments, in the embodiments of the present disclosure, by periodically detecting the bandwidth and the transmission rate, by counting the number of detection periods in which the transmission rate is lower than the preset rate threshold and dividing by the total number of detection periods, a period ratio is obtained. When the period ratio is greater than the preset period ratio threshold, the time with a lower transmission rate is longer, and it is determined that the connection of the hardware component is abnormal. Or when the bandwidth within the detection period is inconsistent with the preset bandwidth, it is determined that the connection of the hardware component is abnormal, achieving the effect of accurately determining whether the connection of the hardware component is abnormal.

[0072] In a possible implementation manner, in the above step S2012, determining whether the hardware component is abnormally connected according to the bandwidth and the transmission rate includes steps S12B1 to S12B4.

[0073] S12B1: Determine the minimum value and the average value of the transmission rate.

[0074] In this step, it may include obtaining the minimum value of the transmission rate of the hardware component within a period of time and calculating the average value of the transmission rate within this period of time.

[0075] S12B2: Calculate the difference between the average value and the minimum value.

[0076] In this step, subtract the minimum value from the average value to obtain the difference.

[0077] For example, if the average value is 4 GB / s and the minimum value is 1.5 GB / s, the difference is 2.5 GB / s. Another example, if the average value is 3 GB / s and the minimum value is 1 GB / s, the difference is 2 GB / s.

[0078] S12B3: If the difference is greater than the preset transmission rate difference threshold, determine that the connection of the hardware component is abnormal.

[0079] In this step, the transmission rate difference threshold can be preset by the staff according to experimental data or empirical parameters.

[0080] S12B4: If the bandwidth decreases, determine that the connection of the hardware component is abnormal.

[0081] In this step, for example, if the bandwidth decreases from PCIe 5.0 to PCIe 4.0, it is determined that the connection of the hardware component is abnormal. Another example, if the bandwidth decreases from PCIe 6.0 to PCIe 3.0, it is determined that the connection of the hardware component is abnormal.

[0082] As can be seen from the description of the above embodiments, in the embodiments of the present disclosure, when the difference between the minimum value and the average value of the transmission rate is greater than the preset transmission rate difference threshold or when the bandwidth decreases, it is determined that the connection of the hardware component is abnormal, achieving the effect of accurately determining whether the connection of the hardware component is abnormal and reducing the abnormal detection time.

[0083] In a possible implementation, determining whether a hardware component is abnormally connected according to the bandwidth and transmission rate includes: step S12C1 and step S12C2.

[0084] S12C1: If the bandwidth decreases, it is determined that the hardware component is abnormally connected.

[0085] This step is similar to step S12B4 above and will not be elaborated here.

[0086] S12C2: If the transmission rate decreases and the decrease amplitude is greater than a preset amplitude threshold, it is determined that the hardware component is abnormally connected.

[0087] In this step, the amplitude threshold can be preset by the staff according to experimental data or empirical parameters. Determining whether the decrease amplitude is greater than the preset amplitude threshold may include obtaining the minimum value and average transmission rate of the transmission rate, calculating the difference between the minimum value and the transmission rate, determining the ratio of the difference to the average transmission rate as the decrease amplitude, comparing the decrease amplitude with the preset amplitude threshold, and obtaining the judgment result of whether the decrease amplitude is greater than the preset amplitude threshold.

[0088] From the description of the above embodiments, it can be seen that the embodiments of the present disclosure determine that the hardware component is abnormally connected when the bandwidth decreases or the transmission rate decreases and the decrease amplitude is greater than the preset amplitude threshold, achieving the effects of accurately determining whether the hardware component is abnormally connected and reducing the abnormal detection time.

[0089] In a possible implementation, in the above step S202, determining the target controller associated with the hardware component includes:

[0090] S2021: Obtain the identifier of the hardware component and the component identifiers associated with each controller.

[0091] In this step, obtaining the identifier of the hardware component can access the configuration space of the hardware component to read the identifier of the hardware component, or receive the identifier of the hardware component during the hardware initialization process, or obtain the identifier of the hardware component using a driver.

[0092] S2022: Determine the controller whose associated component identifier is the same as the identifier of the hardware component as the target controller.

[0093] In this step, for example, if the component identifier associated with controller A is a and the hardware component identifier is also a, then controller A is determined as the target controller. Another example is that if the component identifier associated with controller B is "A00101" and the hardware component identifier is also "A00101", then controller B is also determined as the target controller. There can be one or more target controllers.

[0094] As can be seen from the description of the above embodiments, the embodiments of the present disclosure find the target controller associated with the hardware component by obtaining the identifier of the hardware component and the component identifiers associated with each controller, thereby facilitating the unified control of the controller associated with the hardware component.

[0095] In a possible implementation manner, in step S201 above, if it is detected that a hardware component is inserted into the target slot, it is detected whether the hardware component is abnormally connected, including: step S2011.

[0096] S2011: If it is detected that the occupancy register of the target slot stores a preset field, it is determined that a hardware component is inserted into the target slot, and it is detected whether the hardware component is abnormally connected.

[0097] In this step, if the field stored in the occupancy register of the target slot is detected as "1" or "1xFF", it is determined that a hardware component is inserted into the target slot. If the field stored in the occupancy register of the target slot is detected as "0" or "0xFF", it is determined that no hardware component is inserted into the target slot. The preset field can also be other fields pre-calibrated by the staff, which will not be elaborated here. The method for detecting whether the hardware component is abnormally connected is similar to that in step S201 above, which will not be elaborated here.

[0098] As can be seen from the description of the above embodiments, the embodiments of the present disclosure determine whether a hardware component is inserted into the slot by detecting the field in the occupancy register, so as to determine whether various types of hardware components are inserted into the slot. After detecting that the hardware component is inserted into the slot, it is detected whether the hardware component is abnormally connected, so as to determine the connection status at the first time when the hardware component is connected.

[0099] In a possible implementation manner, in step S208 above, if the hardware component is abnormally connected, the steps of disabling the target slot until powering off the hardware component and then delaying power-on are repeatedly executed until the hardware component is normally connected or after repeating n times, further including: step S210 to step S212.

[0100] S210: If the hardware component is abnormally connected, determine an alternative hardware component.

[0101] In this step, the method for determining an alternative hardware component may include using other idle hardware components as the alternative hardware component, or may include determining other hardware components that are not operating at full load as the alternative hardware component.

[0102] S211: Obtain the data to be transmitted.

[0103] In this step, the data to be transmitted may include data that needs to be transmitted to the hardware component but has not been transmitted yet.

[0104] S212: Send the data to be transmitted to the alternative hardware component so that the alternative hardware component processes the data to be transmitted.

[0105] In this step, the data to be transmitted can be transmitted to the alternative hardware component in formats such as messages and data packets.

[0106] As can be seen from the description of the above embodiments, the embodiments of the present disclosure maintain the normal processing of data by determining the alternative hardware component and transmitting the data to be transmitted to the alternative hardware component.

[0107] In a possible implementation manner, in the above step S210, if the connection of the hardware component is abnormal, determining the alternative hardware component includes: step S2101 and step S2102

[0108] S2101: If the connection of the hardware component is abnormal, obtain the real-time transmission rate of the remaining hardware components.

[0109] In this step, the method for obtaining the real-time transmission rate of the remaining hardware components includes obtaining the real-time transmission rate of the remaining hardware components by reading the log file, and can also obtain the real-time transmission rate of the remaining hardware components through tools such as network testing tools and performance testing tools.

[0110] For example, currently there are 5 hardware components, and if the connection of hardware component A is abnormal, the remaining 4 hardware components are the remaining hardware components, and the real-time transmission rates of the remaining 4 hardware components are obtained.

[0111] S2102: Determine the remaining hardware component with the lowest real-time transmission rate as the alternative hardware component.

[0112] In this step, for example, among the remaining 4 hardware components, if the real-time transmission rate of hardware component C is the lowest, then hardware component C is determined as the alternative hardware component.

[0113] As can be seen from the description of the above embodiments, the embodiments of the present disclosure determine the remaining hardware component with the lowest real-time transmission rate as the alternative hardware component by obtaining the real-time transmission rate of the remaining hardware components, so as to select a component with a lower load as the alternative and maintain the load balance between the hardware components.

[0114] In a possible implementation manner, after the above step S2101, it further includes: step S2103 and step S2104.

[0115] S2103: Obtain the real-time transmission rate and the rated transmission rate of each hardware component.

[0116] In this step, the manner of obtaining the real-time transmission rate of each hardware component can be similar to the above step S2101, which will not be elaborated here. The rated transmission rate can be preset for the hardware component.

[0117] S2104: Determine the hardware component with the largest difference between the real-time transmission rate and the rated transmission rate as the alternative hardware component.

[0118] In this step, it includes calculating the difference between the real-time transmission rate and the rated transmission rate, sorting the differences, and obtaining the hardware component with the largest difference.

[0119] As can be seen from the description of the above embodiments, in the embodiments of the present disclosure, by determining the hardware component with the largest difference between the real-time transmission rate and the rated transmission rate as the alternative hardware component, the alternative hardware component is selected by comprehensively considering the real-time transmission rate and the data processing ability of the hardware component itself.

[0120] In a possible implementation manner, in the above step S208, if the connection of the hardware component is abnormal, then repeat the steps from making the target slot invalid to delaying the power-on after powering off the hardware component until the connection of the hardware component is normal or after repeating n times, it further includes: step S220.

[0121] S220: If the connection of the hardware component is normal, send a data transmission recovery instruction to the target controller to enable the target controller to resume data transmission with the hardware component.

[0122] In this step, the data transmission recovery instruction can also be preset. The manner of sending the data transmission recovery instruction to the target controller is similar to the manner of sending the notification transmission instruction in the above step S203, and will not be elaborated here.

[0123] After the connection of the hardware component is restored, send a data transmission recovery instruction to the target controller.

[0124] As can be seen from the description of the above embodiments, in the embodiments of the present disclosure, after the connection of the hardware component is restored to normal, a data transmission recovery instruction is sent to the target controller to resume normal data transmission to the hardware component.

[0125] In a possible implementation manner, before the above step S201, if it is detected that a hardware component is inserted into the target slot and then it is detected whether the connection of the hardware component is abnormal, it further includes: step S230 to step S234.

[0126] S230: Obtain the presence information of the target slot.

[0127] In this step, it can be similar to the above step S2011 to read the information stored in the presence register of the target slot to obtain the presence information.

[0128] S231: If it is determined according to the in-place information that the hardware component has been unplugged, set the connection failure bit of the connection control register of the target slot to a first preset value to disable the target slot, and start timing to obtain a second timing duration.

[0129] In this step, if the in-place information indicates that no hardware component is inserted, the hardware component has been unplugged.

[0130] S232: If it is detected that the hardware component is inserted into the slot and the second timing duration is greater than or equal to a second preset duration threshold, set the fourth bit of the connection control register to a second preset value to enable the target slot.

[0131] In this step, detecting that the hardware component is inserted into the slot may include detecting that the in-place information stored in the in-place register of the target slot changes to inserted. The second preset duration threshold may be pre-set by the staff, such as 10ms, 15ms, 20ms, etc. The second preset value is, for example, 1, or other values set by the staff.

[0132] S233: Power on the hardware component through the controller and start timing to obtain a third timing duration.

[0133] In this step, it may include sending a power-on instruction to the controller to cause the controller to power on the hardware component.

[0134] S234: If the third timing duration is greater than or equal to a third preset duration threshold, detect whether the hardware component is abnormally connected.

[0135] In this step, the third preset duration threshold may also be pre-set by the staff, such as 10ms, 20ms, 100ms, etc. The steps for detecting whether the hardware component is abnormally connected are similar to the above step S201 and will not be elaborated here.

[0136] As can be seen from the description of the above embodiments, the embodiments of the present disclosure update the slot status by disabling the slot after detecting that the hardware component is manually unplugged and enabling the slot after detecting that the hardware component is manually inserted into the slot, power on the hardware component to make the hardware component run, and determine whether the hardware component is abnormally connected, so as to actively judge whether the connection is normal after manually unplugging and inserting the hardware component, reducing the manual judgment time.

[0137] In a possible implementation manner, in the above step S208, if the hardware component is abnormally connected, the steps of disabling the target slot until delaying power-on after powering off the hardware component are repeatedly executed until the hardware component is normally connected or after being repeatedly executed n times, further including: step S240 and step S241.

[0138] S240: If the hardware component is abnormally connected, obtain the identifier of the hardware component.

[0139] In this step, the method of obtaining the identifier of the hardware component can be similar to that in step S2021, which will not be elaborated here.

[0140] S241: Output an error message according to the identifier of the hardware component.

[0141] In this step, it may include writing the identifier of the hardware component into an error template to obtain an error message, and displaying or sending the error message to a control terminal.

[0142] As can be seen from the description of the above embodiments, the embodiments of the present disclosure obtain the identifier of the hardware component when the connection of the hardware component is abnormal, and output an error message according to the identifier of the hardware component.

[0143] Figure 3 is a schematic structural diagram of a hardware component connection recovery device provided by the present application. As Figure 3 shown, the hardware component connection recovery device 300 provided in this embodiment includes:

[0144] An abnormality detection module 301, configured to detect whether the hardware component is abnormally connected if it detects that a hardware component is inserted into a target slot;

[0145] A controller determination module 302, configured to determine a target controller associated with the hardware component if the hardware component is abnormally connected;

[0146] An instruction sending module 303, configured to send a stop transmission instruction to the target controller, so that the target controller stops data transmission with the hardware component according to the stop transmission instruction;

[0147] A slot failure module 304, configured to set a connection failure bit of a connection control register of the target slot to a first preset value, so that the target slot fails and starts timing to obtain a first timing duration;

[0148] A slot enabling module 305, configured to set the connection failure bit of the connection control register to a second preset value if the first timing duration is greater than or equal to a first preset duration, so that the target slot is enabled;

[0149] The abnormality detection module 301 is further configured to detect whether the hardware component is abnormally connected again;

[0150] A power on / off control module 306, configured to power off the hardware component with a delay and then power it on again, and repeatedly execute the steps from making the target slot fail to detecting whether the hardware component is abnormally connected if the hardware component is still abnormally connected;

[0151] A repeat repair module 307, configured to, if the connection of a hardware component is abnormal, repeatedly execute the steps from invalidating the target slot to powering on the hardware component after powering it off until the connection of the hardware component is normal or the steps are repeatedly executed n times, where n is a positive integer.

[0152] The hardware component connection recovery device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0153] In a possible implementation manner, the abnormal detection module 301 is specifically configured to, in response to detecting that a hardware component is inserted into the target slot, obtain the bandwidth and transmission rate stored in the connection status register of the target slot; and determine whether the connection of the hardware component is abnormal according to the bandwidth and transmission rate.

[0154] In a possible implementation manner, the bandwidth and transmission rate are detected periodically; the abnormal detection module 301 is specifically configured to determine the number of target detection periods in which the transmission rate is lower than a preset transmission rate threshold; divide the number of target detection periods by the total number of detection periods to obtain a period ratio; if the period ratio is greater than a preset period ratio threshold, determine that the connection of the hardware component is abnormal; if the bandwidth detected in any detection period is different from the preset bandwidth, determine that the connection of the hardware component is abnormal.

[0155] In a possible implementation manner, the abnormal detection module 301 is specifically configured to determine the minimum value and average value of the transmission rate; calculate the difference between the average value and the minimum value; if the difference is greater than a preset transmission rate difference threshold, determine that the connection of the hardware component is abnormal; if the bandwidth decreases, determine that the connection of the hardware component is abnormal.

[0156] In a possible implementation manner, the abnormal detection module 301 is specifically configured to, if the bandwidth decreases, determine that the connection of the hardware component is abnormal. If the transmission rate decreases and the decrease amplitude is greater than a preset amplitude threshold, determine that the connection of the hardware component is abnormal.

[0157] In a possible implementation manner, the controller determination module 302 is specifically configured to obtain the identifier of the hardware component and the component identifiers associated with each controller; and determine the controller whose associated component identifier is the same as the identifier of the hardware component as the target controller.

[0158] In a possible implementation manner, the abnormal detection module 301 is specifically configured to, if it is detected that a preset field is stored in the occupancy register of the target slot, determine that a hardware component is inserted into the target slot and detect whether the connection of the hardware component is abnormal.

[0159] In a possible implementation manner, the hardware component connection recovery device 300 further includes: a data transmission module 308.

[0160] The data transmission module 308 is configured to determine an alternative hardware component if the connection of the hardware component is abnormal; obtain the data to be transmitted; and send the data to be transmitted to the alternative hardware component so that the alternative hardware component processes the data to be transmitted.

[0161] In a possible implementation manner, the data transmission module 308 is specifically configured to, if the connection of the hardware component is abnormal, obtain the real-time transmission rate of the remaining hardware components; and determine the remaining hardware component with the lowest real-time transmission rate as the alternative hardware component.

[0162] In a possible implementation manner, the hardware component connection recovery device 300 further includes: a transmission recovery module 309.

[0163] The transmission recovery module 309 is configured to send a data transmission recovery instruction to the target controller if the connection of the hardware component is normal, so that the target controller resumes data transmission with the hardware component.

[0164] In a possible implementation manner, the abnormality detection module 301 is further configured to obtain the presence information of the target slot; if it is determined according to the presence information that the hardware component has been removed, set the connection failure bit of the connection control register of the target slot to a first preset value to disable the target slot, and start timing to obtain a second timing duration; if it is detected that the hardware component is inserted into the slot and the second timing duration is greater than or equal to a second preset duration threshold, set the fourth bit of the connection control register to a second preset value to enable the target slot; power on the hardware component through the controller, and start timing to obtain a third timing duration; if the third timing duration is greater than or equal to a third preset duration threshold, detect whether the connection of the hardware component is abnormal.

[0165] In a possible implementation manner, the hardware component connection recovery device 300 further includes: an information output module 310.

[0166] The information output module 310 is configured to obtain the identifier of the hardware component if the connection of the hardware component is abnormal; and output an error message according to the identifier of the hardware component.

[0167] The hardware component connection recovery device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0168] Figure 4 This is a schematic structural diagram of the hardware component connection recovery device provided in the present application. As Figure 4As shown, the hardware component connection recovery device 40 provided in this embodiment includes at least one processor 401 and a memory 402. Optionally, the hardware component connection recovery device 40 further includes a communication component 403. Among them, the processor 401, the memory 402, and the communication component 403 are connected through a bus 404.

[0169] In the specific implementation process, at least one processor 401 executes the computer-executable instructions stored in the memory 402, so that at least one processor 401 executes the above-mentioned hardware component connection recovery method.

[0170] For the specific implementation process of the processor 401, reference can be made to the above method embodiment, and its implementation principle and technical effects are similar, so they will not be elaborated here in this embodiment.

[0171] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as being completed by a hardware processor, or by a combination of hardware and software modules in the processor.

[0172] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0173] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0174] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is set to execute the steps in any one of the above XX method embodiments when running.

[0175] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media that can store computer programs, such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), external hard drives, magnetic disks, or optical discs.

[0176] The embodiments of the present application also provide a computer program product. The computer program product includes a computer program. When the computer program is executed by a processor, the steps in any of the above embodiments of the hardware component connection recovery method are implemented.

[0177] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps in any of the above embodiments of the hardware component connection recovery method are implemented.

[0178] Those skilled in the art can further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0179] The above has introduced in detail a hardware component connection recovery method, device, storage medium, and program product provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for restoring the connection of a hardware component, characterized in that, It includes: If it is detected that a hardware component is inserted into the target slot, it is detected whether the hardware component is abnormally connected based on the bandwidth and transmission rate; If the hardware component is abnormally connected, the target controller associated with the hardware component is determined; A stop transmission instruction is sent to the target controller, so that the target controller stops data transmission with the hardware component according to the stop transmission instruction; The connection failure bit of the connection control register of the target slot is set to a first preset value, so that the target slot fails, and timing starts to obtain a first timing duration; If the first timing duration is greater than or equal to a first preset duration, the connection failure bit of the connection control register is set to a second preset value, so that the target slot is enabled; It is detected again whether the hardware component is abnormally connected; If the hardware component is still abnormally connected, the hardware component is powered off and then powered on after a delay, and the steps of making the target slot fail to the steps of detecting whether the hardware component is abnormally connected are executed again; If the hardware component is abnormally connected, the steps of making the target slot fail to powering off the hardware component and then powering on after a delay are repeatedly executed until the hardware component is normally connected or repeated n times, where n is a positive integer; If the hardware component is normally connected, a hot plugging process is executed.

2. The method according to claim 1, wherein The step of if it is detected that a hardware component is inserted into the target slot, it is detected whether the hardware component is abnormally connected based on the bandwidth and transmission rate includes: In response to detecting that a hardware component is inserted into the target slot, the bandwidth and transmission rate stored in the connection status register of the target slot are obtained; Based on the bandwidth and transmission rate, it is determined whether the hardware component is abnormally connected.

3. The method according to claim 2, wherein The bandwidth and transmission rate are obtained by periodic detection; The step of based on the bandwidth and transmission rate, it is determined whether the hardware component is abnormally connected includes: Determine the number of target detection periods in which the transmission rate is lower than a preset transmission rate threshold; The number of the target detection periods is divided by the total number of detection periods to obtain a period ratio; If the period ratio is greater than a preset period ratio threshold, it is determined that the hardware component is abnormally connected; If the bandwidth detected in any detection period is different from the preset bandwidth, it is determined that the hardware component is abnormally connected.

4. The method according to claim 2, characterized in that The step of based on the bandwidth and transmission rate, it is determined whether the hardware component is abnormally connected includes: Determine the minimum value and average value of the transmission rate; Calculate the difference between the average value and the minimum value; If the difference is greater than a preset transmission rate difference threshold, it is determined that the hardware component is abnormally connected; If the bandwidth decreases, it is determined that the hardware component is abnormally connected.

5. The method according to claim 2, wherein Based on the bandwidth and transmission rate, it is determined whether the hardware component is abnormally connected includes: If the bandwidth decreases, it is determined that the hardware component is abnormally connected; If the transmission rate decreases and the decrease amplitude is greater than a preset amplitude threshold, it is determined that the hardware component is abnormally connected.

6. The method according to claim 1, characterized in that, The step of determining the target controller associated with the hardware component includes: Obtain the identifier of the hardware component and the component identifiers associated with each controller; Determine the controller whose associated component identifier is the same as the identifier of the hardware component as the target controller.

7. The method according to claim 1, characterized in that, If it is detected that a hardware component is inserted into the target slot, then detect whether the hardware component is abnormally connected, including: If it is detected that the in-position register of the target slot stores a preset field, then determine that a hardware component is inserted into the target slot and detect whether the hardware component is abnormally connected.

8. The method according to any one of claims 1 to 7, characterized in that, If the hardware component is abnormally connected, then repeatedly execute the steps from invalidating the target slot to delaying power-on after powering off the hardware component until the hardware component is normally connected or after repeating n times, further including: If the hardware component is abnormally connected, then determine an alternative hardware component; Obtain data to be transmitted; Send the data to be transmitted to the alternative hardware component so that the alternative hardware component processes the data to be transmitted.

9. The method according to claim 8, wherein The step of determining an alternative hardware component if the hardware component is abnormally connected includes: If the hardware component is abnormally connected, then obtain the real-time transmission rate of the remaining hardware components; Determine the remaining hardware component with the lowest real-time transmission rate as the alternative hardware component.

10. The method according to any one of claims 1 to 7, characterized in that, If the hardware component is abnormally connected, then repeatedly execute the steps from invalidating the target slot to delaying power-on after powering off the hardware component until the hardware component is normally connected or after repeating n times, further including: If the hardware component is normally connected, then send a data transmission recovery instruction to the target controller so that the target controller resumes data transmission with the hardware component.

11. The method according to any one of claims 1 to 7, characterized in that Before the step of detecting whether the hardware component is abnormally connected if it is detected that a hardware component is inserted into the target slot, further including: Obtain the in-position information of the target slot; If it is determined according to the in-position information that the hardware component has been removed, then set the connection failure bit of the connection control register of the target slot to the first preset value to invalidate the target slot and start timing to obtain a second timing duration; If it is detected that the hardware component is inserted into the slot and the second timing duration is greater than or equal to the second preset duration threshold, then set the fourth bit of the connection control register to the second preset value to enable the target slot; Power on the hardware component through the controller and start timing to obtain a third timing duration; If the third timing duration is greater than or equal to the third preset duration threshold, detect whether the hardware component is abnormally connected.

12. The method according to any one of claims 1 to 7, characterized in that, If the hardware component is abnormally connected, then repeatedly execute the steps from invalidating the target slot to delaying power-on after powering off the hardware component until the hardware component is normally connected or after repeating n times, further including: If the hardware component is abnormally connected, then obtain the identifier of the hardware component; Output an error message according to the identifier of the hardware component.

13. A hardware component connection recovery device, characterized in that, Including: A memory and a processor; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory, so that the processor executes the method according to any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, Computer execution instructions are stored in the computer-readable storage medium, and when the computer execution instructions are executed by a processor, they are used to implement the method according to any one of claims 1 to 12.

15. A computer program product, characterized in that, Comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 12.

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