Multi-plane cache transfer enhancements

Abstract

The invention relates to multi-plane cache transfer enhancements. Portions of pages associated with different subsets of planes may be transmitted between subsets of latches at offset times such that a portion of a page may be transmitted while a portion of another page is received or transmitted. For a write operation, a portion of the page may be transferred from the gateway latch to the buffer latch while another portion of the page is received from the outside. For a read operation, a portion of the page may be transferred from the buffer latch to the gateway latch while another portion of the page is transmitted to the outside. This may allow external reception and transmission of the pages to be performed without delay between the pages.

Description

[0001] Cross-reference

[0002] This patent application claims the benefit of priority of U.S. Patent Application No. 18 / 949,612, filed Nov. 15, 2024, entitled "Multi-Plane Cache Transfer Enhancement," and U.S. Patent Application No. 63 / 604,710, filed Nov. 30, 2023, entitled "Multi-Plane Cache Transfer Enhancement," both of which are assigned to its assignee and each of which is hereby incorporated by reference in its entirety.

[0003] The technical field relates to multi-plane cache transfer enhancement. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) the state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of an external power supply. Memory cells configured in a volatile configuration lose their stored state when disconnected from an external power supply. Summary of the Invention

[0006] Describe a memory device. The memory device may include: a plurality of planes, including a first subset of planes and a second subset of planes; a plurality of latches, including a first set of latches and a second set of latches; and a controller coupled to the plurality of planes and the plurality of latches and configured to cause the memory device to: receive, at the memory device, a write command associated with a plurality of pages and the plurality of planes; load a first set of data associated with a first page of the plurality of pages and the first subset of planes into a first subset of the first set of latches during a first duration; load a second set of data associated with the first page and the second subset of planes into a second subset of the first set of latches during a second duration; transfer the first set of data from the first subset of the first set of latches to a first subset of the second set of latches during the second duration; load a third set of data associated with a second page of the plurality of pages and the first subset of planes into the first subset of the first set of latches during a third duration; transfer the second set of data from the second subset of the first set of latches to a second subset of the second set of latches during the third duration; load a fourth set of data associated with the second page and the second subset of planes into the second subset of the first set of latches during a fourth duration; and program the first, second, third, and fourth sets of data into memory cells of the memory device.

[0007] Describe a memory device. The memory device may include: a plurality of planes, including a first subset of planes and a second subset of planes; a plurality of latches, including a first set of latches and a second set of latches; and a controller coupled to the plurality of planes and the plurality of latches and configured to cause the memory device to: receive at the memory device a read memory command associated with a plurality of pages and the plurality of planes; obtain from the memory of the memory device a first set of data associated with a first page of the plurality of pages and the first subset of planes and a second set of data associated with the first page and the second subset of planes, the obtaining the first set of data including loading the first set of data into a first subset of the first set of latches and loading the second set of data into a second subset of the first set of latches; receive a command to transfer the first page; transfer the first set of data from the first subset of the first set of latches to a first subset of the second set of latches and transfer the second set of data from the second subset of the first set of latches to a second subset of the second set of latches; transfer the first set of data from the first subset of the second set of latches within a first duration and in response to receiving the command to transfer the first page; transfer the second set of data from the second subset of the second set of latches within a second duration; after transferring the first and second sets of data from the first and second subsets of the first set of latches to the first and second subsets of the second set of latches, obtain from the memory of the memory device a third set of data associated with a second page of the plurality of pages and the first subset of planes and a fourth set of data associated with the second page and the second subset of planes, wherein the obtaining the third set of data includes loading the third set of data into the first subset of the first set of latches and the second subset of planes and loading the fourth set of data into the second subset of the first set of latches; transfer the third set of data from the first subset of the first set of latches to the first subset of the second set of latches during the second duration; receive a command to transfer the second page; transfer the third set of data from the first subset of the second set of latches within a third duration; transfer the fourth set of data from the second subset of the first set of latches to the second subset of the second set of latches during the third duration; and transfer the fourth set of data from the second subset of the second set of latches within a fourth duration.

[0008] Describe an apparatus. The apparatus may include: a controller configured to be coupled to a memory device, wherein the controller is configured to cause the apparatus to: transmit write commands associated with a plurality of pages and a plurality of planes to the memory device; transmit a first set of data associated with a first page of the plurality of pages and a first subset of the plurality of planes to the memory device during a first duration; transmit a change plane command to the memory device; transmit a second set of data associated with the first page and a second subset of the plurality of planes to the memory device during a second duration; transmit a command to write a second page of the plurality of pages to the memory device; and transmit a third set of data associated with the second page and the first subset of the plurality of planes to the memory device during a third duration, wherein the third duration is directly consecutive with the second duration.

[0009] Describe an apparatus. The apparatus may include: a controller configured to be coupled to a memory device, wherein the controller is configured to cause the apparatus to: transmit a memory read command associated with a plurality of pages and a plurality of planes to the memory device; transmit a command to send data associated with a first page of the plurality of pages to the memory device; receive a first set of data associated with the first page and a first subset of planes of the plurality of planes from the memory device during a first duration; receive a second set of data associated with the first page and a second subset of planes of the plurality of planes from the memory device during a second duration; transmit a command to send data associated with a second page of the plurality of pages to the memory device; and receive a third set of data associated with the second page and the first subset of planes of the plurality of planes from the memory device during a third duration, wherein the third duration is directly consecutive with the second duration. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Shows an example of a system supporting multi-plane cache transfer enhancement according to an example disclosed herein.

[0011] Figure 2 Shows an example of a system supporting multi-plane cache transfer enhancement according to an example disclosed herein.

[0012] Figure 3 AND 4 is a timing diagram illustrating examples of write and read operations supporting multi-plane cache transfer enhancement according to an example disclosed herein.

[0013] Figure 5 Shows a block diagram of a memory device supporting multi-plane cache transfer enhancement according to an example disclosed herein.

[0014] Figure 6 A block diagram showing a memory system supporting multi-plane cache transfer enhancement according to the examples disclosed herein.

[0015] Figures 7 to 10 A flowchart showing a method supporting multi-plane cache transfer enhancement according to the examples disclosed herein. DETAILED DESCRIPTION

[0016] Memory devices may use latches to read and write data. For example, a memory device may include at least two types of latches: a gateway latch for transferring data to the outside (e.g., to and from a memory system controller) and a buffer latch for transferring data internally on the memory device (e.g., to and from a memory array). Memory may be associated with different planes and the gateway latch and buffer latch may be associated with various planes. If cache transfer is involved, data may be transferred between the two types of latches before being saved or transmitted. It takes a specific amount of time (latency time) to transfer data associated with a page between the gateway latch and the buffer latch. The latency time may include, for example, the time for data to stabilize, the time to perform data latching, etc. and may be about 2 microseconds or more.

[0017] In current memory systems, a wait time may be introduced between the transfer of each data page to account for the latency time and ensure that the internal transfer of the page is completed between the latches. This latency time may be exacerbated between multi-plane operations. For the purposes of this application, a multi-plane operation may be defined as a memory operation (e.g., a memory read or write) associated with multiple memory planes. A data page associated with a multi-plane operation may be referred to herein as a multi-plane page or a page. A page may include a portion of the data associated with each plane of the operation, which may be referred to herein as the associated page of the plane. For example, for a multi-plane data page associated with a two-plane operation, one portion of the page may be associated with one of the planes (e.g., the associated page of the plane) and another portion of the page may be associated with the other plane (e.g., the associated page of the other plane). Reducing or eliminating the wait time between multi-plane pages will allow for faster data transfer and higher throughput, especially in multi-plane operations.

[0018] Techniques for multi-plane cache transfer enhancement are described. In some examples, portions of each multi-plane data page may be transferred between a subset of latches at an offset time such that a portion of a page may be transferred while a portion of another page is received or transmitted from the outside (e.g., from a memory system controller). This may result in the data transfer between latches being completed (including the wait time) during the reception or transmission of other data from the outside. In many cases, this may allow the reception or transmission of pages to be performed without latency between the pages, as discussed herein.

[0019] During a write operation, a portion of a multi-plane page associated with a subset of planes can be transferred from a subset of gateway latches to a subset of buffer latches, while a portion of a multi-plane page (the same page or a next page) associated with a different subset of planes is received from the outside (e.g., from a memory system controller) and stored in a different subset of gateway latches. For example, a first portion of the multi-plane page can be transferred from a first subset of gateway latches to a first subset of buffer latches, while a second portion of the page is received from the memory system controller and stored in a second subset of gateway latches. Similarly, a second portion of the multi-plane page can be transferred from a second subset of gateway latches to a second subset of buffer latches, while a first portion of the next page is received from the memory system controller and stored in a first subset of gateway latches.

[0020] By transferring portions of the multi-plane page at different times, the latency associated with the transfer between the subsets of the gateway and buffer latches can occur while another subset of the gateway latches is receiving data from the outside. This can cause the transfer of a portion of the page from a subset of the gateway latches to a subset of the buffer latches to complete before another portion of the page has been fully received in another subset of the gateway latches. Thus, the subset of the gateway latches can become free to receive the next page (or a portion thereof) without delay. Accordingly, the latency associated with the data transfer between the latches does not delay the reception of additional data pages during the write operation. That is, external pages can be received without delay between pages.

[0021] During a read operation, a portion of a multi-plane page associated with a subset of planes can be transferred from a subset of buffer latches to a subset of gateway latches, while a portion of a multi-plane page (the same page or a previous page) associated with a different subset of planes is transferred from a different subset of gateway latches to the outside (e.g., to a memory system controller). For example, while a first portion of the multi-plane page is transferred from a first subset of gateway latches to the memory system controller, a second portion of the page can be transferred from a second subset of buffer latches to a second subset of gateway latches. Similarly, while a second portion of the multi-plane page is transferred from a second subset of gateway latches to the memory system controller, a first portion of the next page can be transferred from a first subset of buffer latches to a first subset of gateway latches.

[0022] By transmitting portions of a multi-plane page at different times, the latency associated with the transfer between a subset of buffer and gateway latches can occur while another subset of gateway latches is transferring data to the outside. This can cause the transfer of portions of the page from a subset of buffer latches to a subset of gateway latches to complete before the previous portion of the page has been fully transferred from another subset of gateway latches. Thus, the portions of the page in the subset of gateway latches are ready to be transferred immediately after the previous portion has been transferred from another subset of gateway latches. Accordingly, the latency associated with the data transfer between latches does not delay the external transfer of additional data pages during a read operation. That is, pages can be transferred to the outside without delay between pages.

[0023] First described in the context of the systems, apparatuses, and circuits of Figure 1 and 2 The features of the present disclosure are described. Further described in the context of the timing diagrams of Figure 3 and 4 The features of the present disclosure are described. Further illustrated and described in the context of the device diagrams and flowcharts related to multi-plane cache transfer enhancement of Figures 5 to 10 These and other features of the present disclosure.

[0024] Figure 1 FIG. 17 shows an example of a system 100 that supports multi-plane cache transfer enhancement according to examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110. System 100 may be included in a computing device such as a desktop computer, laptop computer, network server, mobile device, vehicle (such as an airplane, drone, train, car, or other transportation vehicle), Internet of Things (IoT) enabled device, embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or any other computing device that includes memory and processing means.

[0025] Memory system 110 may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other devices.

[0026] System 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations in accordance with the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to and read data from the memory system 110. Although Figure 1 a memory system 110 is shown, the host system 105 may be coupled to any number of memory systems 110.

[0027] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of the physical host interface may include (but are not limited to) a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some instances, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0028] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 two memory devices 130-a and 130-b are shown in the example of

[0029] Memory system 110 may include any number of memory devices 130. Additionally, if memory system 110 includes more than one memory device 130, then the different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0030] Memory system controller 115 may be coupled to and communicate with host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause memory system 110 to perform various operations in accordance with the examples described herein. Memory system controller 115 may also be coupled to and communicate with memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130 and other such operations, which may be collectively referred to as access operations. In some cases, memory system controller 115 may receive commands from host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at the memory arrays within the one or more memory devices 130). For example, memory system controller 115 may receive commands or operations from host system 105 and may convert the commands or operations into instructions or appropriate commands to effect the desired access of memory devices 130. In some cases, memory system controller 115 may exchange data with host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from host system 105). For example, memory system controller 115 may convert a response (e.g., a data packet or other signal) associated with a memory device 130 into a corresponding signal for host system 105.

[0031] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic for performing the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0032] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) executable by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, e.g., internal storage or computations related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when read from or written to the memory device 130, and the data may be used within the local memory 120 for subsequent retrieval or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130). Further, data received by the memory system controller 115 from the memory device 130 or written to the memory device 130 may be temporarily stored in the local memory 120 while data verification and error control are performed thereon.

[0033] Although Figure 1 the example of the memory system 110 in has been illustrated as including the memory system controller 115, in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be implemented within the memory device 130, respectively, to perform the functions attributed to the memory system controller 115 herein. Generally, in some cases, one or more of the functions attributed to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0035] In some instances, the memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the corresponding memory device 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions ascribed herein to the memory system controller 115. For example, as Figure 1 illustrated, the memory device 130-a may include a local controller 135-a and the memory device 130-b may include a local controller 135-b.

[0036] In some cases, the memory device 130 may be or include a NAND device (e.g., a NAND flash device). The memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, the memory device 130 may be a package that includes one or more dies 160. In some instances, the die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0037] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLCs).

[0038] Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple information bits, which may be referred to as multi-level cells (MLCs) when configured to each store two information bits, triple-level cells (TLCs) when configured to each store three information bits, quad-level cells (QLCs) when configured to each store four information bits, or more generally as multi-level memory cells. The multi-level memory cells may provide a greater storage density relative to single-level cell (SLC) memory cells, but in some cases may involve narrower read or write margins or greater complexity for the support circuitry.

[0039] In some cases, a plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, the concurrent operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d that are respectively in planes 165-a, 165-b, 165-c, and 165-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes that include memory devices 130-a and 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations on different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0040] In some cases, a block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., be coupled to a common word line), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line).

[0041] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level or a portion thereof) but erased at a second granularity level (e.g., at a block granularity level). That is, page 175 can be the smallest unit (e.g., a group of memory cells) of the memory that can be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., a group of memory cells) of the memory that can be independently erased (e.g., concurrently erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing the page 175 is erased.

[0042] System 100 can include any number of non-transitory computer-readable media that support multi-plane cache transfer enhancements. For example, host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135) can include or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed herein to host system 105, memory system 110, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135), can cause host system 105, memory system 110, or memory device 130 to perform the associated functions described herein.

[0043] In addition to being applied to the memory systems described herein, the techniques for multi-plane cache transfer enhancements can generally be implemented to support increased connectivity of electronic systems. As the use of systems that rely on interconnected electronic devices increases, the connectivity of these electronic devices becomes an increasingly relevant factor in system operation. For example, as critical systems become more reliant on connectivity, as systems use a larger number of interconnected devices, or if the number and complexity of the signals communicated between devices increase, the latency associated with the signals communicated between devices becomes increasingly relevant. Implementing the techniques described herein can support techniques for increasing connectivity in electronic systems by improving data transfer between devices and other benefits.

[0044] Figure 2 An example of a memory system 200 that supports multi-plane cache transfer enhancements in accordance with the examples disclosed herein is shown. Memory system 200 can be a reference Figure 1An example of the described memory system 110 or an aspect thereof. Memory system 200 may include a memory system controller 205 coupled to one or more memory devices 210 (e.g., memory devices 210-1 to 210-n) via one or more communication channels (e.g., one or more ONFI channels). Memory system controller 205 may have a cache memory 220, for example, for temporarily storing data transferred between a host system and memory devices 210. Memory system controller 205 may be an example of memory system controller 115 as Figure 1 discussed. Cache memory 220 may be an example of local memory 120 as Figure 1 discussed or may be included in local memory 120.

[0045] Memory devices 210 may be an example of memory devices 130 as Figure 1 discussed. Memory system 200 may improve performance (e.g., speed and throughput) associated with reading and writing data to multiple planes. For a write operation, the timing of transferring data from a gateway latch associated with a subset of planes to a buffer latch may be offset from the timing of transferring data from a gateway latch associated with another subset of planes to a buffer latch, such that data associated with one subset of planes may be transferred between latches while external data is received and stored into a gateway latch associated with another subset of planes. This may allow external pages to be received without delay between pages.

[0046] For a read operation, the timing of transferring data from a buffer latch associated with a subset of planes to a gateway latch may be offset from the timing of transferring data from a buffer latch associated with another subset of planes to a gateway latch, such that data associated with one subset of planes may be transferred between latches while data is transferred externally from a gateway latch associated with another subset of planes. This may allow pages to be transferred externally without delay between pages.

[0047] Memory system 200 may be configured to store data received from a host system and send data to the host system in response to a request issued by the host system using an access command (e.g., a read command or a write command). Memory system controller 205 may execute commands (e.g., access commands) received from the host system and control the movement of information (e.g., data, address mapping information) within memory system 200. For example, memory system controller 205 may manage the transfer of information to and from memory devices 210, such as for storing information, retrieving information, and determining the memory locations where information is stored and from which it is retrieved.

[0048] The memory device 210 may store data transmitted between the memory system 200 and the host system, for example, in response to an access command received from the host system. The memory device 210 may include N planes 225 (e.g., 4 planes, labeled as plane 1 to plane 4 in the depicted example). The planes 225 may be organized into subsets that can be used independently of each other for reading and writing data groups, as discussed herein. One or more of the planes may together form a first subset of the planes and one or more other planes may together form a second subset of the planes. For example, in the depicted example, planes 1 and 2 may form a first subset 250-a of the planes and planes 3 and 4 may form a second subset 250-b of the planes. The first and second subsets of the planes may be disjoint subsets. In some instances, each subset of the planes may include at least two planes. In some instances, the subsets may have the same number of planes. In some instances, one of the subsets of the planes may include a single plane. For example, the first subset 250-a of the planes may include a single plane (e.g., plane 1) and the second subset 250-b of the planes may include 3 planes (e.g., planes 2 to 4).

[0049] Each plane 225 may have one or more associated latch circuits 230 (labeled as L1 to L5 in the depicted embodiment). The latch circuits 230 may facilitate access operations (e.g., read operations, write operations) by temporarily storing data involved in the access operations. Each of the latch circuits 230 may include a plurality of latch circuits each capable of storing a single bit, such that each of the latch circuits 230 may store a certain number of bits corresponding to a page of the corresponding plane 225. The latch circuits may be implemented as level-triggered (e.g., transparent latches) or edge-triggered (e.g., flip-flops) in the memory device. Although described as having 5 latch circuits 230 associated with each plane, some memory devices may have fewer or more latch circuits 230 associated with the planes. In some cases, each memory device 210 may include m + 1 latch circuits 230 associated with the planes, where m may represent the number of bits stored in the memory cells at the highest supported density (e.g., the highest number of bits stored in each of the multi-level memory cells). For example, for a plane 225 having QLC memory cells, there may be 5 latch circuits, and for a plane 225 having TLC memory cells, there may be 4 latch circuits.

[0050] In some instances, one or more of the latches 230 associated with plane 225 (e.g., latch L5) can be used as a gateway latch 230-a to transfer data back and forth between the memory system controller 205. In some instances, one or more of the latches 230 associated with the plane (e.g., one or more of latches L1 to L4) can each be used as a buffer latch 230-b to transfer data back and forth between the memory cells of the plane. In some instances, the gateway latch 230-a and the buffer latch 230-b can be coupled such that data sent to or received from the memory system controller is routed through the gateway latch 230-a and the buffer latch 230-b.

[0051] Data transferred from the memory system controller 205 to the memory cells associated with plane 225 (e.g., as part of a write command) can be sequentially routed through the gateway latch 230-a and the buffer latch 230-b associated with the plane before being written to the memory cells of the plane. Conversely, data transferred from the memory cells of plane 225 to the memory system controller 205 (e.g., as part of a read command) can be sequentially routed through the buffer latch 230-b and the gateway latch 230-a before being transmitted to the memory system controller 205.

[0052] The latches 230 associated with plane 225 can be organized into latch groups 255. For example, all of the latches L5 of plane 225 can together form a group of latches 255-a, all of the latches L1 of plane 225 can together form another group of latches 255-b, all of the latches L2 of plane 225 can together form another group of latches 255-c, and so on.

[0053] Each group of latches 255 can be further organized into subsets based on the corresponding subsets 250 of the planes associated with each latch. For example, each of the latches in latch group 255-a associated with the first subset 250-a of the plane can include a first subset 260-a of latch group 255-a (e.g., latches L5 associated with planes 1 and 2) and each of the latches in latch group 255-a associated with the second subset 250-b of the plane can include a second subset 260-b of latch group 255-a (e.g., latches L5 associated with planes 3 and 4). Similarly, each of the latches in latch group 255-b associated with the first subset 250-a of the plane can include a first subset 265-a of latch group 255-b (e.g., latches L1 associated with planes 1 and 2) and each of the latches in latch group 255-b associated with the second subset 250-b of the plane can include a second subset 265-b of latch group 255-b (e.g., latches L1 associated with planes 3 and 4).

[0054] In some instances, as disclosed herein, during write and read operations involving multiple multi-level cell pages and multiple planes of a memory device, portions of the pages may be transferred between subsets 260, 265, 270 of the latch bank 255 at different times (e.g., offset from each other) to move pages between the memory system controller 205 and the memory with reduced latency between the pages.

[0055] During write and read operations of pages associated with multiple planes, portions of the pages associated with each plane may be received or transmitted one plane at a time. For example, during a write operation, portions of a page associated with a first plane may be transmitted to the memory system controller before portions associated with a second plane, and so on.

[0056] In some instances, the memory device 210 may include logic 240 for determining which planes and subsets of planes to use during different portions of write and read operations. In some instances, the logic 240 may track when planes 225 and subsets of planes 250 are being used (e.g., using write indicator 275 and read indicator 276) and may determine when to change planes 225 and subsets of planes 250 during an operation based thereon. For example, during a write operation, upon receiving a command from the memory system controller 205 to change or advance planes, the logic 240 may determine that a first subset 250-a of planes is currently being used to receive data from the memory system controller and may determine to change to a second subset 250-b of planes to receive data, e.g., based on the next plane being associated with a second subset of planes. The logic 240 may also determine which gateways and buffer latches to apply to transfer data and when the data should be transferred based on the tracking of planes and subsets of planes, as discussed herein. In some instances, the logic 240 may determine to transfer data based on a command received from the memory system controller. For example, in addition to changing planes, a command received from the memory system controller may also indicate to transfer data.

[0057] In some instances, the logic 240 may determine which planes and subsets of planes to use based on a command received from the memory system controller. For example, a particular command received from the memory system controller may indicate a subset of planes for transmitting or receiving data.

[0058] When writing data to multi-level cells (e.g., MLC, TLC, or QLC) on multiple planes, more than one data page can be received and stored in different buffer latches 230-b before the page is programmed to the multi-level cells. For example, a page can include a lower page (LP), an upper page (UP), and an extra page (XP) of a TLC memory operation or a combination thereof. Each page can be transferred between the memory system controller 205 and the memory device 210 one plane at a time, and multiple pages can be transferred consecutively. In some instances, the latency between pages can be avoided by transferring a portion of a page between latches associated with a subset of planes while receiving or transferring a portion of a page associated with another subset of planes from the outside.

[0059] For a write (e.g., program) operation, the memory device 210 can receive data from the memory system controller 205 one plane at a time into a gateway latch 230-a associated with each page (e.g., LP, UP, XP, or a combination thereof) of the write operation. The memory device 210 can transfer the received data from the gateway latch 230-a to the buffer latch 230-b for temporary storage until the data can be programmed to the plane.

[0060] Transferring data from the gateway latch 230-a to the buffer latch 230-b can be offset between different subsets 250 of the plane. For example, a portion of a first data page (e.g., a first set of data) associated with a first subset 250-a of the plane can be transferred from a first subset of the gateway latch group 230-a (e.g., a first subset 260-a of latch L5) to a first subset of the buffer latch group 230-b (e.g., a first subset 265-a of latch L1) at a time when another portion of the first data page (e.g., a second set of data) associated with a second subset 250-b of the plane is transferred from a second subset of a set of gateway latches 230-a (e.g., a second subset 260-b of latch L5) to a second subset of a set of buffer latches 230-b (e.g., a second subset 265-b of latch L1). This offset can allow a set of data associated with a subset of the plane to be transferred to the buffer latch 230-b while a set of data associated with another subset of the plane is received into the gateway latch 230-a from the memory system controller, thereby improving latency, as further discussed herein.

[0061] In some instances, the write indicator 275 may indicate which subset of planes is associated with the next set of data received from the memory system controller. Logic 240 may direct the gateway latch 230-a and buffer latch 230-b associated with the indicated subset of planes for the data set. For example, if the write indicator 275 indicates the first subset 250-a of planes, then the next set of data received from the memory system controller may be loaded into a subset of the gateway latch associated with the first subset of planes and may subsequently be transferred to a subset of the buffer latch associated with the first subset of planes; and if the write indicator 275 indicates the second subset 250-b of planes, then the next set of data received from the memory system controller may be loaded into a subset of the gateway latch associated with the second subset of planes and may subsequently be transferred to a subset of the buffer latch associated with the second subset of planes.

[0062] In some instances, the write indicator 275 may be maintained by the memory device. For example, the write indicator 275 may be set by logic 240 to indicate a first set of planes or a second set of planes, at least in part, based on a write command or a change plane command received from the memory system controller. In some instances, the write indicator 275 may be changed by the memory device after a set of data is loaded into a subset of the latches. For example, the write indicator 275 may be changed by logic 240 to indicate (i) the second subset 250-b of planes after the first set of data is loaded into the first subset 230-a of the gateway latch or (ii) the first subset 250-a of planes after the second set of data is loaded into the second subset 230-b of the gateway latch.

[0063] In some instances, the write indicator 275 may be changed based on a command received from the memory system controller (e.g., a command to advance a plane (e.g., opcode 11h in ONFI) or a command to change a plane (e.g., a command to switch planes (e.g., opcode 15h in ONFI))).

[0064] In some instances, the memory device may determine which subset of planes is associated with a data group based on an indication received from the memory system controller. For example, the indication may be sent by the memory system controller in a set of data that indicates the first or second subset of planes associated with the data group. For example, a write command may include a field (e.g., one or more bits) having a value that foreshadows a first set of planes and another value that foreshadows a second set of planes. In some instances, the memory device may determine when to transfer data between latches based on an indication received from the memory system controller. In some instances, the command itself may be the indication. For example, one type of command (e.g., opcode 13h in ONFI) may be used to change planes and trigger a data transfer from a gateway latch associated with a first subset of planes to a buffer latch, and another type of command (e.g., opcode 17h in ONFI) may be used to change planes and trigger a data transfer from a gateway latch associated with a second subset of planes to a buffer latch. Logic 240 may determine which subset to use and when to trigger the data transfer based on these indications.

[0065] For a read operation, the memory device may read data from plane 225 into buffer latch 230-b. The memory device may transfer the data from buffer latch 230-b to gateway latch 230-a for temporary storage until the data can be transferred to the memory system controller one plane at a time.

[0066] Transferring the data from buffer latch 230-b to gateway latch 230-a may be offset between different subsets 250 of the planes. For example, a portion of a first data page (e.g., a first set of data) associated with a first subset 250-a of the planes may be transferred from a first subset of the set of buffer latches 230-b (e.g., the second subset 265-b of latch L1) to a first subset of the set of gateway latches 230-a (e.g., the second subset 260-b of latch L5) at a time offset from when another portion of the first data page (e.g., a second set of data) associated with a second subset 250-b of the planes is transferred from a second subset of the set of buffer latches 230-b (e.g., the second subset 265-b of latch L1) to a second subset of the set of gateway latches 230-a (e.g., the second subset 260-b of latch L5). This offset may allow data groups associated with subsets of the planes to be transferred to gateway latch 230-a while data groups associated with another subset of the planes are read into buffer latch 230-b, thus improving latency, as further discussed herein.

[0067] In some instances, the read indicator 276 may indicate which subset of planes is associated with the data transmitted to the memory system controller. The logic 240 may direct the data to be transferred from the buffer latch 230-b to the gateway latch 230-a associated with the indicated plane for transmission to the memory system controller. For example, if the read indicator 276 indicates the first subset 250-a of planes, the data stored in the subset of the buffer latch associated with the first subset of planes may be transferred to the subset of the gateway latch associated with the first subset of planes; and if the read indicator 276 indicates the second subset 250-b of planes, the data stored in the subset of the buffer latch associated with the second subset of planes may be transferred to the subset of the gateway latch associated with the second subset of planes.

[0068] In some instances, the read indicator 276 may be maintained by the memory device. For example, the read indicator 276 may be set by the logic 240, such as at least in part based on a read command or a change plane command received from the memory system controller, to indicate the first subset of planes or the second subset of planes. In some instances, the read indicator 276 may be changed by the logic 240 after the data associated with each subset of planes is transmitted to the memory system controller. In some instances, the read indicator 276 may be changed by the logic 240 after a set of data is transferred to the subset of the gateway latch 230-a.

[0069] In some instances, the read indicator 276 may be changed based on a read-related command received from the memory system controller (e.g., opcode 31h in ONFI for performing a read operation or opcode 06h in ONFI for advancing a plane).

[0070] In some instances, the memory device may determine which subset of planes to use based on an indication received from the memory system controller. For example, the indication may be sent by the memory system controller in combination with a read command indicating the first or second subset of planes for a data set. For example, the read command may include a field (e.g., one or more bits) having a value indicating a first set of planes and another value indicating a second set of planes. In some instances, the memory device may determine when to transfer data between latches based on an indication received from the memory system controller. In some instances, the command itself may be the indication. For example, one type of command (e.g., opcode 1Ah in ONFI) may be used to change a plane and trigger the transfer of data from the buffer latch associated with the first subset of planes to the gateway latch, and another type of command (e.g., opcode 1Bh in ONFI) may be used to change a plane and trigger the transfer of data from the buffer latch associated with the second subset of planes to the gateway latch. The logic 240 may determine which subset to use and when to trigger the data transfer based on these indications.

[0071] In some instances, the write indicator 275 and the read indicator 276 can be the same indicator.

[0072] Figure 3 and 4 are timing diagrams 300 and 400 respectively illustrating examples of write and read operations that support multi-plane cache transfer enhancements according to the examples disclosed herein. The write and read operation examples are based on Figure 2 system 200. Thus, for timing diagrams 300 and 400, subsets 260, 265, and 270 of latch groups 255-a (gateway latch L5), 255-b (buffer latch L1), and 255-c (buffer latch L2) can be used to transfer data pages between subsets of planes (subsets 250-a (planes 1 and 2) and 250-b (planes 3 and 4)) and the memory system controller 205.

[0073] The write and read operations can correspond to data associated with multi-level cells. For example, timing diagram 300 can correspond to a write cache command sequence for transferring a first page (e.g., upper page UP) and a second page (e.g., extra page XP) of TLC (in the depicted example, the lower page LP may have been transferred) to the memory device for programming to multiple planes. In some instances, the write and read operations can correspond to data associated with SLC.

[0074] Turning Figure 3 to the write operation illustrated in timing diagram 300 of

[0075] : At A, the memory device can receive a write command from the memory system controller. The write command can include one or more operation codes associated with a page and one or more planes. For example, operation codes 80h or 81h corresponding to a write memory command can be received by the memory device via the ONFI command bus for each plane 225.

[0076] When the first and second sets of data are received, they may be stored in first and second subsets of a set of gateway latches, respectively. For example, starting with D, when the first set of data 315-a is received from a memory system controller, the first set of data 315-a may be stored in the first subset 260-a of the gateway latch L5 associated with planes 1 and 2; and starting with E, when the second set of data 315-b is received from the memory system controller, the second set of data 315-b may be stored in the second subset 260-b of the gateway latch L5 associated with planes 3 and 4.

[0077] In some instances, the memory system controller may send commands to the memory device to indicate when data for the first or next plane will be received. For example, opcodes 80h and 11h may be received by the memory device via the ONFI command bus to select a plane and indicate that the transfer of a portion of the data associated with the plane has been completed; and opcode 15h may be received by the memory device to indicate that the transfer of a portion of the data associated with a multi-plane page has been completed. Thus, at D, the first set of data may begin to be stored in the first subset 260-a of the gateway latch L5 based on opcode 80h, and starting with E, the second set of data may begin to be stored in the second subset 260-b of the gateway latch L5 based on a second opcode 80h received after opcode 11h. In some instances, the opcode itself may indicate that the next portion of data is associated with the opposite subset of the plane.

[0078] After the first set of data is received and stored in the first subset of the gateway latch set (e.g., after a first duration), the first set of data may be transferred from there to the first subset of a set of buffer latches. For example, at F, the first set of data 315-a associated with planes 1 and 2 may be transferred from the first subset 260-a of the gateway latch L5 to the first subset 265-a of the buffer latch L1. After a latency (e.g., t PBSY ) for completing the transfer, the first subset 260-a of the gateway latch set L5 may be free to receive other data. In some instances, the first set of data may begin to be transferred from the first subset of the gateway latch to the first subset of the buffer latch before the data has been fully received and stored in the first subset of the gateway latch. That is, the first set of data may begin to be transferred at any time during the first duration.

[0079] In some instances, to help determine when to perform a transfer between a gateway and a buffer latch, a memory device may keep track of the plane associated with the data currently received from a memory system controller. The transfer may be triggered by the memory device based on determining that a new plane belongs to a different plane group than a previous plane when changing the plane associated with the received data (e.g., in response to receiving a write page or change plane command from the memory system controller). For example, the transfer at F may be triggered in response to receiving opcode 11h that changes the plane at time C (which results in changing from plane 2 to plane 3 associated with the received data).

[0080] In some instances, the transfer may be triggered by the memory device based on receiving a specific command from the memory system controller. For example, the transfer at F may be triggered in response to receiving opcode 13h at time C that indicates, in addition to changing the plane, that the memory device will perform a transfer between the gateway and the buffer latch associated with a first subset 250-a of the plane.

[0081] When a second set of data is received from the memory system controller into a different subset of the gateway latch, a transfer of a first set of data from a subset of the gateway latch to a subset of the buffer latch may be performed and completed. For example, a first set of data 315-a may be fully transferred (including latency t PBSY ) to a first subset 265-a of buffer latch L1 during a second duration. Thus, the latency associated with the data transfer between the gateway and the buffer latch does not delay the receipt of additional data pages from the memory system controller during a write operation. That is, external pages may be received without delay between external pages.

[0082] After the first and second sets of data have been received via the data bus, a third and fourth set of data associated with a second multi-plane page may be received. In some instances, a command (e.g., opcode 15h) may be received by the memory device to indicate a new page. The third and fourth sets of data may be associated with first and second subsets 250-a, 250-b of the plane, respectively, and may be received without delay between the data sets. The third set of data may be received during a third duration that is directly after (e.g., directly contiguous with) the second duration, and the fourth set of data may be received during a fourth duration that is directly after (e.g., directly contiguous with) the third duration. For example, starting at G, a third set of data 315-c associated with planes 1 and 2 may start to be received and may continue to be received during the third duration, and starting at H, a fourth set of data 315-d associated with planes 3 and 4 may start to be received and may continue to be received directly thereafter during the fourth duration.

[0083] Since the transfer of the first set of data to the first subset of the buffer latch set can be completed before the end of the second duration, the first subset of the gateway latch set is free to receive other data at the start of the third duration. Thus, when the third set of data is received during the third duration, it can be stored in the now-free first subset of the gateway latch set. For example, starting with I, when the third set of data 315-c is received from the memory system controller during the third duration, the third set of data 315-c associated with planes 1 and 2 can be stored in the first subset 260-a of the gateway latch L5 associated with planes 1 and 2.

[0084] In some instances, the storage of the third set of data in the first subset 260-a of the gateway latch L5 can be based on a command (such as opcode 15h). In some instances, the opcode can indicate that the next portion of the received data is associated with the first subset of the plane.

[0085] After the second set of data is received and stored in the second subset of the gateway latch set (e.g., after the second duration), the second set of data can be transferred from there to the second subset of the buffer latch set. For example, at J, the second set of data 315-b associated with planes 3 and 4 can be transferred from the second subset 260-b of the gateway latch L5 to the second subset 265-b of the buffer latch L1. After the latency (e.g., t PBSY ) used to complete the transfer, the second subset 260-b of the gateway latch set L5 is free to receive other data. In some instances, the second set of data can start being transferred from the second subset of the gateway latch to the second subset of the buffer latch before the data has been fully received and stored in the second subset of the gateway latch. That is, the second set of data can start being transferred at any time during the second duration.

[0086] When the third set of data is received from the memory system controller into another subset of the gateway latch, the transfer of the second set of data from the subset of the gateway latch to the buffer latch can be executed and completed. For example, the second set of data 315-b can be fully transferred (including the latency t PBSY ) to the second subset 265-b of the buffer latch L1 during the third duration. Thus, the latency associated with the data transfer between the gateway and the buffer latch does not delay the receipt of additional data pages from the memory system controller during a write operation. That is, external pages can be received without delay between external pages.

[0087] In some instances, the transfer at J can be triggered based on the receipt of a command (such as opcode 15h to complete the page transfer started at B).

[0088] Since the transfer of the second set of data to the second subset of the buffer latch set can be completed before the end of the third duration, the second subset of the gateway latch set is free to receive other data at the start of the fourth duration. Thus, when the fourth set of data is received during the fourth duration, it can be stored in the now-free second subset of the gateway latch set. For example, starting with K, when the fourth set of data 315-d is received from the memory system controller during the fourth duration, the fourth set of data 315-d associated with planes 3 and 4 can be stored in the second subset 260-b of the gateway latch L5 associated with planes 3 and 4.

[0089] In some instances, the storage of the fourth set of data in the second subset 260-b of the gateway latch L5 can be based on a command (e.g., the second opcode 80h after G). In some instances, the opcode can indicate that the next part of the received data is associated with the first subset of the plane.

[0090] After the third set of data is received and stored in the first subset of the gateway latch set (e.g., after the third duration), the third set of data can be transferred from there to the first subset of another set of buffer latches. For example, at L, the third set of data 315-c associated with planes 1 and 2 can be transferred from the first subset 260-a of the gateway latch L5 to the first subset 270-a of the buffer latch L2. After the latency (e.g., t PBSY ) used to complete the transfer, the first subset 260-a of the gateway latch set L5 is free to receive other data. In some instances, the third set of data can start being transferred from the first subset of the gateway latch to the first subset of the buffer latch before the data has been fully received and stored in the first subset of the gateway latch. That is, the third set of data can start being transferred at any time during the third duration.

[0091] When the fourth set of data is received from the memory system controller into a different subset of the gateway latch, the transfer of the third set of data from the subset of the gateway latch to the subset of the buffer latch can be performed and completed. For example, the third set of data 315-c can be fully transferred to the first subset 270-a of the buffer latch L2 during the fourth duration. Thus, the latency associated with the data transfer between the gateway and the buffer latch does not delay the receipt of additional data pages from the memory system controller during a write operation. That is, external pages can be received without delay between pages.

[0092] In some instances, the transfer at L may be triggered based on receiving a command (e.g., the second opcode 11h after G). In some instances, the transfer may be triggered based on receiving a specific command (e.g., opcode 13h) that indicates not only a change in plane but also that the memory device will perform a transfer between the gateway and the buffer latch associated with the first subset 250-a of the plane.

[0093] After the fourth set of data is received and stored in the second subset of the gateway latch group (e.g., after the fourth duration), the fourth set of data may be transferred from this to the second subset of another set of buffer latches. For example, at M, the fourth set of data 315-d associated with planes 3 and 4 may be transferred from the second subset 260-b of the gateway latch L5 to the second subset 270-b of the buffer latch L2. After the latency (e.g., t PBSY ) for completing the transfer, the second subset 260-b of the gateway latch group L5 may be free to receive other data. In some instances, the fourth set of data may begin to be transferred from the second subset of the gateway latch to the second subset of the buffer latch before the data has been fully received and stored in the second subset of the gateway latch. That is, the fourth set of data may begin to be transferred at any time during the fourth duration.

[0094] In some instances, the transfer at M may be triggered based on receiving a command (e.g., opcode 15h for completing the page transfer initiated at G).

[0095] After the transfer of the fourth set of data to the second subset of another set of buffer latches is complete, the memory cells of the first and second subsets of the plane may be programmed using the data sets stored in the buffer latch group. For example, at N, after the latency (e.g., t PBSY ) for completing the transfer of the fourth set of data 315-d to the second subset 270-b of the buffer latch L2, the memory cells of planes 1 to 4 associated with the first and second multi-plane pages may be programmed using the data sets 315-a to 315-d stored in the buffer latch groups L1 and L2 associated with planes 1 to 4.

[0096] Although the depicted example shows two multi-plane data pages associated with a write command, additional pages may also be received. The additional pages may be handled in a manner similar to the first and second pages. That is, for each additional page, the transfer of the data set from the gateway latch group to the additional buffer latch group may be offset for different subsets 250 of the plane. For example, steps G to M may be repeated for each additional page, where the programming of the memory (step N) is performed after the last page.

[0097] Turning Figure 4The read operation illustrated in timing diagram 400: At A, the memory device may receive a read memory command from the memory system controller. The read memory command may include one or more opcodes associated with a page and one or more planes. For example, the opcode 30h or 32h corresponding to the read memory command may be received by the memory device via the ONFI command bus.

[0098] In response to receiving the read memory command, the memory device may obtain a first multi-plane data page from the planes that may include different portions from each plane. Portions from a first subset of the planes may be considered a first set of data and portions from a second subset of the planes may be considered a second set of data. The first and second sets of data associated with the first page may be obtained from the first and second subsets of the planes, respectively, and stored in the first and second subsets of a set of buffer latches. For example, at B, the first set of data 415-a may be obtained from planes 1 and 2 and stored in the first subset 265-a of buffer latch L1; and the second set of data 415-b may be obtained from planes 3 and 4 and stored in the second subset 265-b of buffer latch L1. This may be done concurrently for the first and second sets of data.

[0099] The memory device may then receive a command from the memory system controller to transfer the first multi-plane page to the memory system controller. For example, at C, the opcode 31h may be received by the memory device via the ONFI command bus to indicate that the memory device initiates the next read operation and prepares the previous multi-plane page for transfer to the memory system controller.

[0100] In response to receiving the command, the first and second subsets of the data may be transferred from the first and second subsets of the buffer latch set to the first and second subsets of a set of gateway latches, respectively. For example, at D, the first set of data 415-a may be transferred from the first subset 265-a of buffer latch L1 to the first subset 260-a of gateway latch L5 associated with planes 1 and 2; and the second set of data 415-b may be transferred from the second subset 265-b of buffer latch L1 to the second subset 260-b of gateway latch L5 associated with planes 3 and 4. The transfer may be done concurrently for the first and second sets of data. After a latency (e.g., t RCBSY ) for completing the transfer, the first and second subsets 265-a and 265-b of buffer latch set L1 may be free to receive other data.

[0101] After the first and second sets of data are transferred to the first and second subsets of the gateway latch set, the first and second sets of data can be transferred from these latches to the memory system controller one plane at a time, with no latency between planes. For example, starting with E, the portion of the data associated with planes 1 and 2 (first set of data 415-a) can be transferred from the first subset 260-a of gateway latch L5 to the memory system controller via the data bus during a first duration, and starting with F, the portion of the data associated with planes 3 and 4 (second set of data 415-b) can be transferred from the second subset 260-b of gateway latch L5 to the memory system controller via the data bus during a second duration that is directly after (e.g., directly consecutive with) the first duration. In some instances, there may be no latency between the transfers of each set of data.

[0102] In some instances, the transfer of data associated with each plane can be based on a command received from the memory system controller to do so. In some instances, the memory system controller can send a command to the memory device when the data for the first or next plane is to be transferred. For example, the opcode 06h can be received by the memory device via the ONFI command bus to select the plane for transfer. Thus, at E, the first set of data can be transferred to the memory system controller based on the first opcode 06h received after C, and at F, the second set of data can be transferred to the memory system controller based on the third opcode 06h received after C. In some instances, the opcode can indicate that the data set to be transferred is associated with a particular subset of planes. For example, opcodes 1Ah and 1Bh can indicate that the next sets of data to be transferred are associated with the first and second subsets of planes, respectively. For example, at E, the transfer of the first set of data from the first subset 260-a of gateway latch L5 to the memory system controller can be based on the opcode 1Ah received after C, and at F, the transfer of the second set of data from the second subset 260-b of gateway latch L5 to the memory system controller can be based on the opcode 1Bh received after C.

[0103] After the first and second subsets of the buffer latch set become free, the memory device can obtain a second multi-plane data page from the planes. For example, the third and fourth sets of data associated with the second page can be obtained from the first and second subsets of the planes, respectively, and stored in the first and second subsets of the buffer latch set. For example, at G, the third set of data 415-c can be obtained from planes 1 and 2 and stored in the first subset 265-a of buffer latch L1; the fourth set of data 415-d can be obtained from planes 3 and 4 and stored in the second subset 265-b of buffer latch L1.

[0104] After the first set of data is transferred to the memory system controller (e.g., after the first duration), the first subset of the gateway latch group becomes available to receive other data from the buffer latches. Thus, the third set of data can be transferred from the first subset of the buffer latch group to the first subset of the gateway latch group after the first duration. For example, starting with H, the third set of data 415-c can be transferred from the first subset 265-a of buffer latch L1 to the first subset 260-a of gateway latch L5 associated with planes 1 and 2. The transfer can be executed and completed when the second set of data is transferred to the memory system controller (i.e., during the second duration). Thereafter, the first subset 265-a of buffer latch group L1 becomes available to receive other data.

[0105] In some instances, the transfer at H can be triggered by the memory device based on determining that the new plane belongs to a different plane group than the previous plane when changing the plane used to transfer data to the memory system controller (e.g., in response to receiving a command to change the plane from the memory system controller). For example, the transfer at H can be triggered in response to receiving the third opcode 06h received after C to indicate that the memory device will transfer data associated with plane 3.

[0106] In some instances, the transfer can be triggered by the memory device based on receiving a specific command from the memory system controller. For example, the transfer at H can be triggered in response to receiving opcode 1Ah (instead of or in combination with opcode 06h) to indicate that in addition to transferring data associated with the new plane, the memory device will also perform a transfer associated with the first subset 250-a of the plane.

[0107] Since the transfer can be executed concurrently with transferring the second set of data to the memory system controller, the latency associated with performing the transfer of the third set of data between the buffer and gateway latches (e.g., t RCBSY ) does not delay the transfer of data groups over the data bus during a read operation. Thus, data pages can be transferred externally without delay between them.

[0108] The memory device can receive a command from the memory system controller to transfer a second multi-plane page to the memory system controller. For example, at I, another opcode 31h can be received by the memory device over the ONFI command bus to indicate that the memory device starts the read operation of the next multi-plane page and prepares the previous multi-plane page for transfer to the memory system controller.

[0109] In response to receiving a command, a third set of data stored in a first subset of a gateway latch group can be transferred to a memory system controller without delay between groups after a second set of data has been transferred. For example, starting with J, a third set of data 415-c associated with planes 1 and 2 can be transferred from a first subset 260-a of gateway latch L5 to the memory system controller within a third duration that is directly after (e.g., directly consecutive with) a second duration.

[0110] In some instances, the transfer of the third set of data from the first subset 260-a of gateway latch L5 to the memory system controller can be based on a command received after I (e.g., a first opcode 06h or opcode 1Bh).

[0111] After a second set of data has been transferred to the memory system controller (e.g., after a second duration), a second subset of the gateway latch group can be freed up to receive other data from a buffer latch. Thus, a fourth set of data can be transferred from a second subset of a buffer latch group to a second subset of the gateway latch group after the second duration. For example, starting with K, a fourth set of data 415-d can be transferred from a second subset 265-b of buffer latch L1 to a second subset 260-b of gateway latch L5 associated with planes 3 and 4. The transfer can be performed and completed when the third set of data is transferred to the memory system controller (i.e., during the third duration). Thereafter, the second subset 265-b of buffer latch group L1 can be freed up to receive other data.

[0112] In some instances, the transfer at K can be triggered in response to receiving a first opcode 06h received after I to indicate that the memory device will transfer data associated with plane 1. In some instances, the transfer can be triggered in response to receiving opcode 1Bh to indicate that in addition to transferring data associated with a new plane, the memory device will also perform a transfer associated with a second subset 250-b of planes.

[0113] Because the transfer can be performed concurrently with transferring the third set of data to the memory system controller, the latency associated with performing the transfer of the fourth set of data between the buffer and gateway latches (e.g., t RCBSY ) does not delay the transfer of data groups over the data bus during a read operation. Thus, pages can be transferred to the outside without delay between them.

[0114] After the fourth set of data is transferred to the second subset of the gateway latch group, the fourth set of data can be transferred from these latches to the memory system controller without delay between groups after the third set of data has completed its transfer. For example, starting with L, a portion of the fourth set of data 415-d associated with planes 3 and 4 can be transferred from the second subset 260-b of the gateway latch L5 to the memory system controller within a fourth duration that is directly after (e.g., directly consecutive with) the third duration.

[0115] In some instances, at L, the transfer of the fourth set of data from the second subset 260-b of the gateway latch L5 to the memory system controller can be based on a command received after I (e.g., the third opcode 06h or opcode 1Ah).

[0116] After the first and second subsets of the buffer latch group become free, the memory device can obtain a third multi-plane data page from the plane. For example, the fifth and sixth sets of data associated with the third page can be obtained from the first and second subsets of the plane, respectively, and stored in the first and second subsets of the buffer latch group. For example, at M, the fifth set of data 415-e can be obtained from planes 1 and 2 and stored in the first subset 265-a of the buffer latch L1; the sixth set of data 415-f can be obtained from planes 3 and 4 and stored in the second subset 265-b of the buffer latch L1.

[0117] After the third set of data is transferred to the memory system controller (e.g., after the third duration), the first subset of the gateway latch group can be free for receiving other data from the buffer latch. Thus, the fifth set of data can be transferred from the first subset of the buffer latch group to the first subset of the gateway latch group after the third duration. For example, starting with N, the fifth set of data 415-e can be transferred from the first subset 265-a of the buffer latch L1 to the first subset 260-a of the gateway latch L5 associated with planes 1 and 2. The transfer can be executed and completed when the fourth set of data is transferred to the memory system controller (i.e., during the fourth duration). After a latency (e.g., t RCBSY ) for completing the transfer, the first subset 265-a of the buffer latch group L1 can be free for receiving other data.

[0118] In some instances, the transfer at N can be triggered in response to receiving a command (e.g., the third opcode 06h or opcode 1Ah received after I) to indicate that the memory device will transfer data associated with plane 3.

[0119] Since the transfer can be executed concurrently with transferring the fourth set of data to the memory system controller, the latency (e.g., t RCBSY)There is no delay in transferring data groups through the data bus during a read operation. Thus, pages can be transferred externally without delay between them.

[0120] The memory device may receive a command from the memory system controller to transfer a third multi-plane page to the memory system controller. For example, at P, another opcode 31h may be received by the memory device via the ONFI command bus to instruct the memory device to initiate a read operation of the next multi-plane page and prepare the previous multi-plane page for transfer to the memory system controller.

[0121] In response to receiving the command, the fifth group of data stored in the first subset of the gateway latch group can be transferred to the memory system controller without delay between groups after the fourth group of data has completed its transfer. For example, starting at Q, the fifth group of data 415-e associated with planes 1 and 2 can be transferred from the first subset 260-a of the gateway latch L5 to the memory system controller within a fifth duration directly after (e.g., directly consecutive with) the fourth duration.

[0122] In some instances, the transfer of the fifth group of data from the first subset 260-a of the gateway latch L5 to the memory system controller can be based on a command received after P (e.g., the first opcode 06h or opcode 1Bh).

[0123] After the fourth group of data is transferred to the memory system controller (e.g., after the fourth duration), the sixth group of data can be transferred from the second subset of the buffer latch group to the second subset of the gateway latch group after the fourth duration. For example, starting at R, the sixth group of data 415-f can be transferred from the second subset 265-b of the buffer latch L1 to the second subset 260-b of the gateway latch L5 associated with planes 3 and 4. The transfer can be executed and completed when the fifth group of data is transferred to the memory system controller (i.e., during the fifth duration). Thereafter, the second subset 265-b of the buffer latch group L1 can be freed up to receive other data.

[0124] In some instances, the transfer at R can be triggered in response to receiving a command (e.g., the first opcode 06h or opcode 1Bh received after P) to instruct the memory device to transfer data associated with plane 1.

[0125] Because the transfer can be executed concurrently with transferring the fifth group of data to the memory system controller, the latency associated with performing the transfer of the sixth group of data between the buffer and gateway latches (e.g., t RCBSY )There is no delay in transferring data groups through the data bus during a read operation. Thus, pages can be transferred externally without delay between pages.

[0126] After the sixth set of data is transferred to the second subset of the gateway latch group, the sixth set of data can be transferred from these latches to the memory system controller without delay between groups after the fifth set of data has completed its transfer. For example, starting with S, a portion of the sixth set of data 415-f associated with planes 3 and 4 can be transferred from the second subset 260-b of the gateway latch L5 to the memory system controller via the data bus during a sixth duration that is directly after (e.g., directly consecutive with) the fifth duration.

[0127] In some instances, at S, the transfer of the sixth set of data from the second subset 260-b of the gateway latch L5 to the memory system controller can be based on a command received after P (e.g., the third opcode 06h or opcode 1Ah).

[0128] Although the depicted example shows three multi-plane data pages associated with a read command, two pages can be transferred instead. For example, steps M to S can be omitted. More than three pages can also be transferred. Each additional page can be handled in a manner similar to the first, second, and third pages. That is, for each additional page, the transfer of data groups from the buffer latch group to the gateway latch group can be offset for different subsets 250 of the planes. For example, steps M to S can be repeated for each additional page.

[0129] Figure 5 FIG. 500 is a block diagram showing a memory device 520 that supports multi-plane cache transfer enhancements according to an example disclosed herein. The memory device 520 can be an example of aspects of the memory device described in Figures 1 to 4 reference. The memory device 520 or its various components can be examples of components for performing various aspects of the multi-plane cache transfer enhancements described herein. For example, the memory device 520 can include a receiver 525, a data loader 530, a latch manager 535, a programmer 540, a reader 545, a transmitter 550, an indicator manager 555, or any combination thereof. Each of these components can communicate directly or indirectly with each other (e.g., via one or more buses).

[0130] The receiver 525 may be configured to or otherwise support components for receiving write commands associated with multiple pages and multiple planes at the memory device. The data loader 530 may be configured to or otherwise support components for loading a first set of data associated with a first page of the multiple pages and a first subset of planes of the multiple planes into a first subset of a first set of latches during a first duration. In some instances, the data loader 530 may be configured to or otherwise support components for loading a second set of data associated with the first page and a second subset of planes of the multiple planes into a second subset of the first set of latches during a second duration. The latch manager 535 may be configured to or otherwise support components for transferring the first set of data from the first subset of the first set of latches to a first subset of a second set of latches during the second duration.

[0131] In some instances, the data loader 530 may be configured to or otherwise support components for loading a third set of data associated with a second page of the multiple pages and the first subset of planes into a first subset of the first set of latches during a third duration. In some instances, the latch manager 535 may be configured to or otherwise support components for transferring the second set of data from the second subset of the first set of latches to a second subset of the second set of latches during the third duration. In some instances, the latch manager 535 may be configured to or otherwise support components for loading a fourth set of data associated with the second page and the second subset of planes into a second subset of the first set of latches during a fourth duration. The programmer 540 may be configured to or otherwise support components for programming the first, second, third, and fourth sets of data into memory cells of the memory device.

[0132] In some instances, the third duration may be directly consecutive with the second duration.

[0133] In some instances, the memory device may include an indicator indicating one of the first subset of planes or the second subset of planes, and the indicator manager 555 may be configured to or otherwise support components for determining that the indicator indicates the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches are at least partially based on determining that the indicator indicates the first subset of planes. In some instances, the memory device may include an indicator indicating one of the first subset of planes or the second subset of planes, and the indicator manager 555 may be configured to or otherwise support components for determining that the indicator indicates the second subset of planes, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches are at least partially based on determining that the indicator indicates the second subset of planes.

[0134] In some instances, the indicator manager 555 may be configured to or otherwise support components for setting a first subset of an indicator indication plane at least in part based on receiving a write command, wherein determining the first subset of the indicator indication plane is at least in part based on setting the first subset of the indicator indication plane. In some instances, the receiver 525 may be configured to or otherwise support components for receiving a second command to change a plane. In some instances, the indicator manager 555 may be configured to or otherwise support components for setting a second subset of the indicator indication plane at least in part based on the first subset of the indicator indication plane when the second command is received, wherein determining the second subset of the indicator indication plane is at least in part based on setting the second subset of the indicator indication plane.

[0135] In some instances, the indicator manager 555 may be configured to or otherwise support components for changing an indicator to indicate a second subset of a plane after loading a second set of data into a first subset of a first set of latches. In some instances, the indicator manager 555 may be configured to or otherwise support components for changing an indicator to indicate a first subset of a plane after loading a fourth set of data into a second subset of a first set of latches.

[0136] In some instances, the receiver 525 may be configured to or otherwise support components for receiving a first indication along with first and second sets of data, the first indication indicating a first subset of a plane, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches are at least in part based on receiving the first indication. In some instances, the receiver 525 may be configured to or otherwise support components for receiving a second indication along with third and fourth sets of data, the second indication indicating a second subset of a plane, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches are at least in part based on receiving the second indication.

[0137] In some instances, to support receiving the first indication, the receiver 525 may be configured to or otherwise support components for receiving a first command that triggers a first data transfer using a first subset of a plane, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches are at least in part based on receiving the first command. In some instances, to support receiving the second indication, the receiver 525 may be configured to or otherwise support components for receiving a second command that triggers a second data transfer using a second subset of a plane, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches are at least in part based on receiving the second command.

[0138] In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a third set of data from a first subset of the first set of latches to a first subset of the third set of latches during a fourth duration.

[0139] In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a fourth set of data from a second subset of the first set of latches to a second subset of the third set of latches after the fourth duration, wherein programming the first, second, third, and fourth sets of data is at least partially based on transferring the fourth set of data to the second subset of the third set of latches.

[0140] In some instances, to support programming the first, second, third, and fourth sets of data into memory cells, the programmer 540 may be configured to or otherwise support components for programming the first, second, third, and fourth sets of data using the first and second sets of data loaded in the first and second subsets of the second set of latches and the third and fourth sets of data loaded in the first and second subsets of the third set of latches.

[0141] In some instances, the data loader 530 may be configured to or otherwise support components for loading a fifth set of data associated with a third page and a first subset of planes of multiple pages into a first subset of the first set of latches during a fifth duration, wherein loading the fifth set of data is at least partially based on transferring the third set of data to the first subset of the third set of latches. In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a fourth set of data from a second subset of the first set of latches to a second subset of the third set of latches during the fifth duration. In some instances, the data loader 530 may be configured to or otherwise support components for loading a sixth set of data associated with the third page and a second subset of planes into a second subset of the first set of latches during a sixth duration.

[0142] In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a fifth set of data from a first subset of the first set of latches to a first subset of the fourth set of latches during the sixth duration. In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a sixth set of data from a second subset of the first set of latches to a second subset of the fourth set of latches after the sixth duration. In some instances, the programmer 540 may be configured to or otherwise support components for programming the fifth and sixth sets of data into memory cells of the memory device.

[0143] In some instances, the first and second pages may correspond to pages of multi-level cells of the memory device.

[0144] In some examples, the first subset of planes and the second subset of planes can be disjoint subsets each including at least two planes.

[0145] In some examples, the receiver 525 can be configured to or otherwise support components for receiving read memory commands associated with multiple pages and multiple planes at a memory device. The reader 545 can be configured to or otherwise support components for obtaining from the memory of the memory device a first set of data associated with a first page of the multiple pages and a first subset of planes of the multiple planes and a second set of data associated with the first page and a second subset of planes of the multiple planes, where obtaining the first set of data includes loading the first set of data into a first subset of a first set of latches and loading the second set of data into a second subset of the first set of latches.

[0146] In some examples, the receiver 525 can be configured to or otherwise support components for receiving a command to transfer a first page. In some examples, the latch manager 535 can be configured to or otherwise support components for transferring the first set of data from a first subset of the first set of latches to a first subset of a second set of latches and transferring the second set of data from a second subset of the first set of latches to a second subset of the second set of latches. The transmitter 550 can be configured to or otherwise support components for transferring the first set of data from the first subset of the second set of latches within a first duration and in response to receiving the command to transfer the first page.

[0147] In some examples, the transmitter 550 can be configured to or otherwise support components for transferring a second set of data from a second subset of the second set of latches within a second duration. In some examples, the reader 545 can be configured to or otherwise support components for obtaining from the memory of the memory device a third set of data associated with a second page of the multiple pages and a first subset of planes and a fourth set of data associated with the second page and a second subset of planes after transferring the first and second sets of data from the first and second subsets of the first set of latches to the first and second subsets of the second set of latches, where obtaining the third set of data includes loading the third set of data into the first subset of the first set of latches and the second subset of planes and loading the fourth set of data into the second subset of the first set of latches.

[0148] In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a third set of data from a first subset of the first set of latches to a first subset of the second set of latches during a second duration. In some instances, the receiver 525 may be configured to or otherwise support components for receiving a command to transfer a second page. In some instances, the transmitter 550 may be configured to or otherwise support components for transferring a third set of data from a first subset of the second set of latches during a third duration.

[0149] In some instances, the latch manager 535 may be configured to or otherwise support components for transferring a fourth set of data from a second subset of the first set of latches to a second subset of the second set of latches during a third duration. In some instances, the transmitter 550 may be configured to or otherwise support components for transferring a fourth set of data from a second subset of the second set of latches during a fourth duration.

[0150] In some instances, the third duration may be directly consecutive with the second duration.

[0151] In some instances, the memory device may include an indicator indicating one of a first subset of planes or a second subset of planes, and the indicator manager 555 may be configured to or otherwise support components for determining that the indicator indicates the first subset of planes, wherein transferring the third set of data to the first subset of the second set of latches is at least partially based on determining that the indicator indicates the first subset of planes. In some instances, the memory device may include an indicator indicating one of a first subset of planes or a second subset of planes, and the indicator manager 555 may be configured to or otherwise support components for determining that the indicator indicates the second subset of planes, wherein transferring the fourth set of data to the second subset of the second set of latches is at least partially based on determining that the indicator indicates the second subset of planes.

[0152] In some instances, the receiver 525 may be configured to or otherwise support components for receiving a command to change planes. In some instances, the indicator manager 555 may be configured to or otherwise support components for setting the indicator to indicate the first subset of planes at least partially based on the indicator indicating the second subset of planes when receiving a command to change planes, wherein determining that the indicator indicates the first subset of planes is at least partially based on setting the indicator to indicate the first subset of planes. In some instances, the indicator manager 555 may be configured to or otherwise support components for setting the indicator to indicate the second subset of planes at least partially based on the indicator indicating the first subset of planes when receiving a command to change planes, wherein determining that the indicator indicates the second subset of planes is at least partially based on setting the indicator to indicate the second subset of planes.

[0153] In some instances, the indicator manager 555 may be configured to or otherwise support components for changing an indicator to indicate a second subset of planes after transmitting a first set of data to a first subset of a second set of latches. In some instances, the indicator manager 555 may be configured to or otherwise support components for changing an indicator to indicate a first subset of planes after transmitting a second set of data to a second subset of the second set of latches.

[0154] In some instances, the receiver 525 may be configured to or otherwise support components for receiving a first indication indicating a first subset of planes, wherein transmitting a third set of data to a first subset of the second set of latches is at least partially based on determining that the indicator indicates the first subset of planes. In some instances, the receiver 525 may be configured to or otherwise support components for receiving a second indication indicating a second subset of planes, wherein transmitting a fourth set of data to a second subset of the second set of latches is at least partially based on determining that the indicator indicates the second subset of planes.

[0155] In some instances, to support receiving the first indication, the receiver 525 may be configured to or otherwise support components for receiving a first command that triggers a first data transfer using the first subset of planes, wherein transmitting the first set of data to the first subset of the second set of latches is at least partially based on receiving the first command. In some instances, to support receiving the second indication, the receiver 525 may be configured to or otherwise support components for receiving a second command that triggers a second data transfer using the second subset of planes, wherein transmitting the second set of data to the second subset of the second set of latches is at least partially based on receiving the second command.

[0156] In some instances, to support transmitting a third set of data to a first subset of the second set of latches, the latch manager 535 may be configured to or otherwise support components for overwriting a first set of data in the first subset of the second set of latches with the third set of data.

[0157] In some instances, the first and second pages may correspond to pages of multi-level cells of a memory device.

[0158] In some instances, the first subset of planes and the second subset of planes may be disjoint subsets each including at least two planes.

[0159] Figure 6 FIG. 600 is a block diagram showing a memory system 620 that supports multi-plane cache transfer enhancements in accordance with examples disclosed herein. The memory system 620 may be a reference Figures 1 to 4Examples of aspects of the described memory system. Memory system 620 or its various components can be examples of components for performing various aspects of the multi-plane cache transfer enhancements described herein. For example, memory system 620 can include a transmitter 625, a receiver 630, or any combination thereof. Each of these components can communicate directly or indirectly with each other (e.g., via one or more buses).

[0160] Transmitter 625 can be configured to or otherwise support components for transferring write commands associated with multiple pages and multiple planes from a controller to a memory device. In some instances, transmitter 625 can be configured to or otherwise support components for transferring a first set of data associated with a first page of the multiple pages and a first subset of the multiple planes to the memory device within a first duration. In some instances, transmitter 625 can be configured to or otherwise support components for transferring a change plane command to the memory device. In some instances, transmitter 625 can be configured to or otherwise support components for transferring a second set of data associated with the first page and a second subset of the multiple planes to the memory device within a second duration. In some instances, transmitter 625 can be configured to or otherwise support components for transferring a command to write a second page of the multiple pages to the memory device. In some instances, transmitter 625 can be configured to or otherwise support components for transferring a third set of data associated with the second page and a first subset of the multiple planes to the memory device within a third duration, where the third duration is directly consecutive with the second duration.

[0161] In some instances, transmitter 625 can be configured to or otherwise support components for transferring a second change plane command to the memory device during the third duration. In some instances, transmitter 625 can be configured to or otherwise support components for transferring a fourth set of data associated with the second page to the memory device within a fourth duration, where the fourth duration is directly consecutive with the third duration.

[0162] In some instances, the first subset of planes and the second subset of planes can be disjoint subsets each including at least two planes.

[0163] In some instances, the transmitter 625 may be configured to or otherwise support components for transmitting memory read commands associated with multiple pages and multiple planes from the controller to the memory device. In some instances, the transmitter 625 may be configured to or otherwise support components for transmitting a command to send data associated with a first page of the multiple pages to the memory device. The receiver 630 may be configured to or otherwise support components for receiving a first set of data associated with the first page and a first subset of planes of the multiple planes from the memory device within a first duration. In some instances, the receiver 630 may be configured to or otherwise support components for receiving a second set of data associated with the first page and a second subset of planes of the multiple planes from the memory device within a second duration. In some instances, the transmitter 625 may be configured to or otherwise support components for transmitting a command to send data associated with a second page of the multiple pages to the memory device. In some instances, the receiver 630 may be configured to or otherwise support components for receiving a third set of data associated with the second page and a first subset of planes of the multiple planes from the memory device within a third duration, where the third duration is directly consecutive with the second duration.

[0164] In some instances, the transmitter 625 may be configured to or otherwise support components for transmitting a command to change planes to the memory device during the third duration. In some instances, the receiver 630 may be configured to or otherwise support components for receiving a fourth set of data associated with the second page and a second subset of planes of the multiple planes from the memory device within a fourth duration, where the fourth duration is directly consecutive with the third duration.

[0165] In some instances, the first subset of planes and the second subset of planes are disjoint subsets each including at least two planes.

[0166] Figure 7 A flowchart illustrating a method 700 for supporting multi-plane cache transfer enhancements according to the examples disclosed herein is shown. Operations of the method 700 may be implemented by the memory device or its components described herein. For example, the operations of the method 700 may be performed by the memory device referenced Figures 1 to 5 described. In some instances, the memory device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the wireless memory device may perform aspects of the described functions using dedicated hardware.

[0167] At 705, the method may include receiving a write command associated with multiple pages and multiple planes at the memory device. Operation 705 may be performed according to the examples disclosed herein. In some instances, aspects of operation 705 may be performed by the memory device referenced Figure 5performed by the described receiver 525.

[0168] At 710, the method may include loading a first set of data associated with a first page of a plurality of pages and a first subset of planes of a plurality of planes into a first subset of a first set of latches during a first duration. Operation 710 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 710 may be performed by the data loader 530 referenced Figure 5 in the description.

[0169] At 715, the method may include loading a second set of data associated with the first page and a second subset of planes of a plurality of planes into a second subset of the first set of latches during a second duration. Operation 715 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 715 may be performed by the data loader 530 referenced Figure 5 in the description.

[0170] At 720, the method may include transferring the first set of data from the first subset of the first set of latches to a first subset of a second set of latches during the second duration. Operation 720 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 720 may be performed by the latch manager 535 referenced Figure 5 in the description.

[0171] At 725, the method may include loading a third set of data associated with a second page of a plurality of pages and the first subset of planes into the first subset of the first set of latches during a third duration. Operation 725 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 725 may be performed by the data loader 530 referenced Figure 5 in the description.

[0172] At 730, the method may include transferring the second set of data from the second subset of the first set of latches to a second subset of the second set of latches during the third duration. Operation 730 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 730 may be performed by the latch manager 535 referenced Figure 5 in the description.

[0173] At 735, the method may include loading a fourth set of data associated with the second page and the second subset of planes into the second subset of the first set of latches during a fourth duration. Operation 735 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 735 may be performed by the latch manager 535 referenced Figure 5 in the description.

[0174] At 740, the method may include programming first, second, third, and fourth sets of data into memory cells of a memory device. Operation 740 may be performed according to the examples disclosed herein. In some examples, aspects of operation 740 may be performed by a programmer 540 described with reference to Figure 5 described.

[0175] In some examples, a device described herein may perform one or several methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0176] Aspect 1: A method, device, or non-transitory computer-readable medium including operations, features, circuitry, logic, components, or instructions or any combination thereof for: receiving, at a memory device, a write command associated with a plurality of pages and a plurality of planes; loading, during a first duration, a first set of data associated with a first page of the plurality of pages and a first subset of planes of the plurality of planes into a first subset of a first set of latches; loading, during a second duration, a second set of data associated with the first page and a second subset of planes of the plurality of planes into a second subset of the first set of latches; transferring, during the second duration, the first set of data from the first subset of the first set of latches to a first subset of a second set of latches; loading, during a third duration, a third set of data associated with a second page of the plurality of pages and the first subset of planes into the first subset of the first set of latches; transferring, during the third duration, the second set of data from the second subset of the first set of latches to a second subset of the second set of latches; loading, during a fourth duration, a fourth set of data associated with the second page and the second subset of planes into the second subset of the first set of latches; and programming the first, second, third, and fourth sets of data into memory cells of the memory device.

[0177] Aspect 2: The method, device, or non-transitory computer-readable medium according to aspect 1, wherein the third duration is directly consecutive with the second duration.

[0178] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 2, wherein the memory device includes an indicator indicating one of the first subset of planes or the second subset of planes, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuitry, logic, components, or instructions or any combination thereof for: determining that the indicator indicates the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches is at least partially based on determining that the indicator indicates the first subset of planes; and determining that the indicator indicates the second subset of planes, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches is at least partially based on determining that the indicator indicates the second subset of planes.

[0179] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to Aspect 3, wherein the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuitry, logic, components, or instructions or any combination thereof for: setting the indicator to indicate the first subset of planes at least partially based on receiving the write command, wherein determining that the indicator indicates the first subset of planes is at least partially based on setting the indicator to indicate the first subset of planes; receiving a second command to change planes; and when receiving the second command, setting the indicator to indicate the second subset of planes at least partially based on the indicator indicating the first subset of planes, wherein determining that the indicator indicates the second subset of planes is at least partially based on setting the indicator to indicate the second subset of planes.

[0180] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 3 to 4, further including operations, features, circuitry, logic, components, or instructions or any combination thereof for: changing the indicator to indicate the second subset of planes after loading the second set of data into the first subset of the first set of latches; and changing the indicator to indicate the first subset of planes after loading the fourth set of data into the second subset of the first set of latches.

[0181] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuitry, logic, components, or instructions or any combination thereof for: receiving a first indication together with the first and second sets of data, the first indication indicating the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches is at least partially based on receiving the first indication; and receiving a second indication together with the third and fourth sets of data, the second indication indicating the second subset of planes, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches is at least partially based on receiving the second indication.

[0182] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to Aspect 6, wherein receiving the first indication comprises receiving a first command that triggers a first data transfer using the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches is at least partially based on receiving the first command, and receiving the second indication comprises receiving a second command that triggers a second data transfer using the second subset of planes, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches is at least partially based on receiving the second command.

[0183] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuitry, logic, components, or instructions or any combination thereof for: transferring the third set of data from the first subset of the first set of latches to the first subset of a third set of latches during the fourth duration.

[0184] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to Aspect 8, further comprising operations, features, circuitry, logic, components, or instructions or any combination thereof for: after the fourth duration, transferring the fourth set of data from the second subset of the first set of latches to the second subset of the third set of latches, wherein programming the first, second, third, and fourth sets of data is at least partially based on transferring the fourth set of data to the second subset of the third set of latches.

[0185] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to aspect 9, wherein programming the first, second, third, and fourth sets of data into the memory cell includes operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: programming the first, second, third, and fourth sets of data using the first and second sets of data in the first and second subsets loaded in the second set of latches and the third and fourth sets of data in the first and second subsets loaded in the third set of latches.

[0186] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 8 to 10, further comprising operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: loading a fifth set of data associated with a third page and a first subset of planes of the plurality of pages into the first subset of the first set of latches during a fifth duration, wherein loading the fifth set of data is at least partially based on transferring the third set of data to the first subset of the third set of latches; transferring the fourth set of data from the second subset of the first set of latches to the second subset of the third set of latches during the fifth duration; loading a sixth set of data associated with the third page and a second subset of planes into the second subset of the first set of latches during a sixth duration; transferring the fifth set of data from the first subset of the first set of latches to the first subset of the fourth set of latches during the sixth duration; transferring the sixth set of data from the second subset of the first set of latches to the second subset of the fourth set of latches after the sixth duration; and programming the fifth and sixth sets of data into the memory cells of the memory device.

[0187] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the first and second pages correspond to pages of multi-level cells of the memory device.

[0188] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 12, wherein the first subset of planes and the second subset of planes are disjoint subsets each comprising at least two planes.

[0189] Figure 8A And 8B FIG. shows a flowchart illustrating method 800 for supporting multi-plane cache transfer enhancement according to the examples disclosed herein. The operations of method 800 may be implemented by the memory device or its components described herein. For example, the operations of method 800 may be implemented with reference to Figures 1 to 5The described memory device performs. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the wireless memory device may use dedicated hardware to perform aspects of the described functions.

[0190] At 805, the method may include receiving, at the memory device, a read memory command associated with a plurality of pages and a plurality of planes. Operation 805 may be performed in accordance with the examples disclosed herein. In some instances, aspects of operation 805 may be performed by the receiver 525 referenced Figure 5 in the description.

[0191] At 810, the method may include obtaining, from the memory of the memory device, a first set of data associated with a first page of the plurality of pages and a first subset of the planes of the plurality of planes and a second set of data associated with the first page and a second subset of the planes of the plurality of planes, where obtaining the first set of data includes loading the first set of data into a first subset of a first set of latches and loading the second set of data into a second subset of the first set of latches. Operation 810 may be performed in accordance with the examples disclosed herein. In some instances, aspects of operation 810 may be performed by the reader 545 referenced Figure 5 in the description.

[0192] At 815, the method may include receiving a command to transfer the first page. Operation 815 may be performed in accordance with the examples disclosed herein. In some instances, aspects of operation 815 may be performed by the receiver 525 referenced Figure 5 in the description.

[0193] At 820, the method may include transferring the first set of data from the first subset of the first set of latches to the first subset of a second set of latches and transferring the second set of data from the second subset of the first set of latches to the second subset of the second set of latches. Operation 820 may be performed in accordance with the examples disclosed herein. In some instances, aspects of operation 820 may be performed by the latch manager 535 referenced Figure 5 in the description.

[0194] At 825, the method may include transmitting, within a first duration and in response to receiving the command to transfer the first page, the first set of data from the first subset of the second set of latches. Operation 825 may be performed in accordance with the examples disclosed herein. In some instances, aspects of operation 825 may be performed by the transmitter 550 referenced Figure 5 in the description.

[0195] At 830, the method may include transmitting the second set of data from the second subset of the second set of latches within a second duration. Operation 830 may be performed in accordance with the examples disclosed herein. In some instances, aspects of operation 830 may be performed by the transmitter 550 referenced Figure 5 in the description.

[0196] At 835, the method may include obtaining, after transferring first and second sets of data from first and second subsets of a first set of latches to first and second subsets of a second set of latches, a third set of data associated with a second page and a first subset of planes and a fourth set of data associated with the second page and a second subset of planes from a memory of the memory device, wherein obtaining the third set of data includes loading the third set of data into the first subset of the first set of latches and the second subset of planes and loading the fourth set of data into the second subset of the first set of latches. Operation 835 may be performed according to the examples disclosed herein. In some examples, aspects of operation 835 may be performed by a reader 545 as described in Figure 5 reference.

[0197] At 840, the method may include transferring the third set of data from the first subset of the first set of latches to the first subset of the second set of latches during a second duration. Operation 840 may be performed according to the examples disclosed herein. In some examples, aspects of operation 840 may be performed by a latch manager 535 as described in Figure 5 reference.

[0198] At 845, the method may include receiving a command to transfer the second page. Operation 845 may be performed according to the examples disclosed herein. In some examples, aspects of operation 845 may be performed by a receiver 525 as described in Figure 5 reference.

[0199] At 850, the method may include transferring the third set of data from the first subset of the second set of latches during a third duration. Operation 850 may be performed according to the examples disclosed herein. In some examples, aspects of operation 850 may be performed by a transmitter 550 as described in Figure 5 reference.

[0200] At 855, the method may include transferring the fourth set of data from the second subset of the first set of latches to the second subset of the second set of latches during the third duration. Operation 855 may be performed according to the examples disclosed herein. In some examples, aspects of operation 855 may be performed by a latch manager 535 as described in Figure 5 reference.

[0201] At 860, the method may include transferring the fourth set of data from the second subset of the second set of latches during a fourth duration. Operation 860 may be performed according to the examples disclosed herein. In some examples, aspects of operation 860 may be performed by a transmitter 550 as described in Figure 5 reference.

[0202] In some instances, the devices described herein may perform one or several methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0203] Aspect 14: A method, device, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a read memory command associated with a plurality of pages and a plurality of planes at a memory device; obtaining from the memory of the memory device a first set of data associated with a first page of the plurality of pages and a first subset of planes of the plurality of planes and a second set of data associated with the first page and a second subset of planes of the plurality of planes, wherein obtaining the first set of data includes loading the first set of data into a first subset of a first set of latches and loading the second set of data into a second subset of the first set of latches; receiving a command to transfer the first page; transferring the first set of data from the first subset of the first set of latches to a first subset of a second set of latches and transferring the second set of data from the second subset of the first set of latches to a second subset of the second set of latches; transmitting the first set of data from the first subset of the second set of latches during a first duration and in response to receiving the command to transfer the first page; transmitting the second set of data from the second subset of the second set of latches during a second duration; after transferring the first and second sets of data from the first and second subsets of the first set of latches to the first and second subsets of the second set of latches, obtaining from the memory of the memory device a third set of data associated with a second page of the plurality of pages and the first subset of planes and a fourth set of data associated with the second page and the second subset of planes, wherein obtaining the third set of data includes loading the third set of data into the first subset of the first set of latches and the second subset of planes and loading the fourth set of data into the second subset of the first set of latches; transferring the third set of data from the first subset of the first set of latches to the first subset of the second set of latches during the second duration; receiving a command to transfer the second page; transmitting the third set of data from the first subset of the second set of latches during a third duration; transferring the fourth set of data from the second subset of the first set of latches to the second subset of the second set of latches during the third duration; and transmitting the fourth set of data from the second subset of the second set of latches during a fourth duration.

[0204] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to Aspect 14, wherein the third duration is directly consecutive with the second duration.

[0205] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 14 to 15, wherein the memory device includes an indicator indicating one of the first subset of planes or the second subset of planes, and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining that the indicator indicates the first subset of planes, wherein transmitting the third set of data to the first subset of the second set of latches is at least partially based on determining that the indicator indicates the first subset of planes; and determining that the indicator indicates the second subset of planes, wherein transmitting the fourth set of data to the second subset of the second set of latches is at least partially based on determining that the indicator indicates the second subset of planes.

[0206] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to Aspect 16, wherein the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a command to change planes; when receiving the command to change planes, setting the indicator to indicate the first subset of planes at least partially based on the indicator indicating the second subset of planes, wherein determining that the indicator indicates the first subset of planes is at least partially based on setting the indicator to indicate the first subset of planes; and when receiving the command to change planes, setting the indicator to indicate the second subset of planes at least partially based on the indicator indicating the first subset of planes, wherein determining that the indicator indicates the second subset of planes is at least partially based on setting the indicator to indicate the second subset of planes.

[0207] Aspect 18: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 16 to 17, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: changing the indicator to indicate the second subset of planes after transmitting the first set of data to the first subset of the second set of latches; and changing the indicator to indicate the first subset of planes after transmitting the second set of data to the second subset of the second set of latches.

[0208] Aspect 19: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 14 to 18, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a first indication indicative of the first subset of planes, wherein transmitting the third set of data to the first subset of the second set of latches is at least partially based on determining that an indicator indicates the first subset of planes; and receiving a second indication indicative of the second subset of planes, wherein transmitting the fourth set of data to the second subset of the second set of latches is at least partially based on determining that the indicator indicates the second subset of planes.

[0209] Aspect 20: The method, apparatus, or non-transitory computer-readable medium according to aspect 19, wherein receiving the first indication comprises receiving a first command that triggers a first data transfer using the first subset of planes, wherein transmitting the first set of data to the first subset of the second set of latches is at least partially based on receiving the first command, and receiving the second indication comprises receiving a second command that triggers a second data transfer using the second subset of planes, wherein transmitting the second set of data to the second subset of the second set of latches is at least partially based on receiving the second command.

[0210] Aspect 21: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 14 to 20, wherein transmitting the third set of data to the first subset of the second set of latches comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: overwriting the first set of data in the first subset of the second set of latches with the third set of data.

[0211] Aspect 22: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 14 to 21, wherein the first and second pages correspond to pages of multi-level cells of the memory device.

[0212] Aspect 23: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 14 to 22, wherein the first subset of planes and the second subset of planes are disjoint subsets each comprising at least two planes.

[0213] Figure 9 FIG. shows a flowchart illustrating method 900 for supporting multi-plane cache transfer enhancement according to examples disclosed herein. The operations of method 900 may be implemented by the memory system or its components described herein. For example, the operations of method 900 may be performed with reference to Figures 1 to 4and executed by the memory system described in 6. In some instances, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the wireless memory system may use dedicated hardware to perform aspects of the described functions.

[0214] At 905, the method may include transmitting a write command associated with a plurality of pages and a plurality of planes from the controller to the memory device. Operation 905 may be performed according to the examples disclosed herein. In some instances, aspects of operation 905 may be performed by the transmitter 625 referenced Figure 6 in the description.

[0215] At 910, the method may include transmitting a first set of data associated with a first page of the plurality of pages and a first subset of the plurality of planes to the memory device within a first duration. Operation 910 may be performed according to the examples disclosed herein. In some instances, aspects of operation 910 may be performed by the transmitter 625 referenced Figure 6 in the description.

[0216] At 915, the method may include transmitting a command to change planes to the memory device. Operation 915 may be performed according to the examples disclosed herein. In some instances, aspects of operation 915 may be performed by the transmitter 625 referenced Figure 6 in the description.

[0217] At 920, the method may include transmitting a second set of data associated with the first page and a second subset of the plurality of planes to the memory device within a second duration. Operation 920 may be performed according to the examples disclosed herein. In some instances, aspects of operation 920 may be performed by the transmitter 625 referenced Figure 6 in the description.

[0218] At 925, the method may include transmitting a command to write to a second page of the plurality of pages to the memory device. Operation 925 may be performed according to the examples disclosed herein. In some instances, aspects of operation 925 may be performed by the transmitter 625 referenced Figure 6 in the description.

[0219] At 930, the method may include transmitting a third set of data associated with the second page and a first subset of the plurality of planes to the memory device within a third duration, where the third duration is directly consecutive with the second duration. Operation 930 may be performed according to the examples disclosed herein. In some instances, aspects of operation 930 may be performed by the transmitter 625 referenced Figure 6 in the description.

[0220] In some examples, the devices described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, components, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0221] Aspect 24: A method, device, or non-transitory computer-readable medium that includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a write command associated with a plurality of pages and a plurality of planes from a controller to a memory device; transmitting a first set of data associated with a first page of the plurality of pages and a first subset of the plurality of planes to the memory device during a first duration; transmitting a change plane command to the memory device; transmitting a second set of data associated with the first page and a second subset of the plurality of planes to the memory device during a second duration; transmitting a command to write a second page of the plurality of pages to the memory device; and transmitting a third set of data associated with the second page and the first subset of the plurality of planes to the memory device during a third duration, where the third duration is directly consecutive with the second duration.

[0222] Aspect 25: The method, device, or non-transitory computer-readable medium of aspect 24, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a second change plane command to the memory device during the third duration; and transmitting a fourth set of data associated with the second page to the memory device during a fourth duration, where the fourth duration is directly consecutive with the third duration.

[0223] Aspect 26: The method, device, or non-transitory computer-readable medium of any of aspects 24 to 25, where the first subset of the plurality of planes and the second subset of the plurality of planes are disjoint subsets each including at least two planes.

[0224] Figure 10 FIG. 13 shows a flowchart illustrating method 1000 for supporting multi-plane cache transfer enhancements according to examples disclosed herein. The operations of method 1000 may be implemented by the memory system or its components described herein. For example, the operations of method 1000 may be performed by the memory system referenced Figures 1 to 4 and described in FIGS. 6. In some examples, the memory system may execute a set of instructions to control functional elements of a device to perform the described functions. Additionally or alternatively, the wireless memory system may perform aspects of the described functions using dedicated hardware.

[0225] At 1005, the method may include transmitting a memory read command associated with multiple pages and multiple planes from a controller to a memory device. Operation 1005 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 1005 may be performed by a transmitter 625 referenced Figure 6 described.

[0226] At 1010, the method may include transmitting a command to send data associated with a first page of the multiple pages to the memory device. Operation 1010 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 1010 may be performed by a transmitter 625 referenced Figure 6 described.

[0227] At 1015, the method may include receiving, from the memory device, a first set of data associated with the first page and a first subset of planes of the multiple planes during a first duration. Operation 1015 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 1015 may be performed by a receiver 630 referenced Figure 6 described.

[0228] At 1020, the method may include receiving, from the memory device, a second set of data associated with the first page and a second subset of planes of the multiple planes during a second duration. Operation 1020 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 1020 may be performed by a receiver 630 referenced Figure 6 described.

[0229] At 1025, the method may include transmitting a command to send data associated with a second page of the multiple pages to the memory device. Operation 1025 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 1025 may be performed by a transmitter 625 referenced Figure 6 described.

[0230] At 1030, the method may include receiving, from the memory device, a third set of data associated with the second page and a first subset of planes of the multiple planes during a third duration, where the third duration is directly consecutive with the second duration. Operation 1030 may be performed in accordance with the examples disclosed herein. In some examples, aspects of operation 1030 may be performed by a receiver 630 referenced Figure 6 described.

[0231] In some examples, the devices described herein may perform one or several methods, such as method 1000. The device may include features, circuitry, logic, components, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0232] Aspect 27: A method, apparatus, or non-transitory computer-readable medium that includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a memory read command associated with a plurality of pages and a plurality of planes from a controller to a memory device; transmitting a command to send data associated with a first page of the plurality of pages to the memory device; receiving, during a first duration, a first set of data associated with the first page and a first subset of the planes of the plurality of planes from the memory device; receiving, during a second duration, a second set of data associated with the first page and a second subset of the planes of the plurality of planes from the memory device; transmitting a command to send data associated with a second page of the plurality of pages to the memory device; and receiving, during a third duration, a third set of data associated with the second page and the first subset of the planes of the plurality of planes from the memory device, wherein the third duration is directly consecutive with the second duration.

[0233] Aspect 28: The method, apparatus, or non-transitory computer-readable medium of aspect 27, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a command to change planes to the memory device during the third duration; and receiving, during a fourth duration, a fourth set of data associated with the second page and the second subset of the planes of the plurality of planes from the memory device, wherein the fourth duration is directly consecutive with the third duration.

[0234] Aspect 29: The method, apparatus, or non-transitory computer-readable medium of any of aspects 27 to 28, wherein the first subset of planes and the second subset of planes are disjoint subsets each including at least two planes.

[0235] It should be noted that the described techniques include possible embodiments, and the operations and steps may be rearranged or otherwise modified and other embodiments are possible. Additionally, portions from two or more of the methods may be combined.

[0236] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0237] The terms "electronically communicate", "electrically contact", "connect", and "couple" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or in electrical contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in electrical contact or connected or coupled) with each other can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that can include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components can be interrupted over a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0238] The term "couple" (such as "electrically couple") can refer to a condition of transitioning from an open-circuit relationship between components (where signals cannot currently pass between the components through the conductive path) to a closed-circuit relationship between the components (where signals can pass between the components through the conductive path). If, for example, a component of a controller couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0239] The term "isolate" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, if a switch located between two components is open, the components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components through a conductive path that previously allowed signal flow.

[0240] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term "substantially") need not be absolute, but is close enough to achieve the advantage of the characteristic.

[0241] The terms "if", "when", "based on", or "at least in part based on" can be used interchangeably. In some instances, the terms can be interchangeable if the terms "if", "when", "based on", or "at least in part based on" are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0242] The term "responsive to" may refer to a condition or action occurring at least in part (if not entirely) as a result of a previous condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the previous condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0243] Additionally, the terms "directly responsive to" or "directly respond to" may refer to a condition or action occurring directly as a result of a previous condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of the previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of the previous condition or action occurring such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on", "at least in part based on", or "responsive to" some other step, action, event, or condition may additionally or alternatively (e.g., in an alternative instance) be performed "directly responsive to" or "directly respond to" this other condition or action.

[0244] The devices discussed herein (including memory arrays) may be formed on a semiconductor substrate such as silicon, germanium, silicon germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including (but not limited to) phosphorus, boron, or arsenic. Doping may be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0245] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “turned on” or “activated”. If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “turned off” or “deactivated”.

[0246] The descriptions presented herein describe example configurations in conjunction with the accompanying drawings and do not represent all examples that may be implemented or that are within the scope of the claims. The term “exemplary” as used herein means “serving as an example, instance, or illustration” and not “preferred” or “better than other examples”. “Detailed description” includes specific details for providing an understanding of the described technology. However, the technology may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0247] In the figures, similar components or features may have the same reference numerals. Additionally, various components of the same type may be distinguished by following the reference numeral with a hyphen and a second numeral that differentiates the similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0248] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0249] For example, the various illustrative blocks and components described in this disclosure in connection with the present disclosure may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0250] As used herein (including in the claims), the "or" in a list of items (e.g., a list of items that begins with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0251] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code instructions or data structures in the form of and that can be accessed by a general or special purpose computer or a general or special purpose processor.

[0252] Also, any connection is properly termed a computer-readable media. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave), then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0253] The description herein is provided to enable a person of ordinary skill in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a plurality of planes, comprising a first subset of planes and a second subset of planes; a plurality of latches, including a first group of latches and a second group of latches; and a controller coupled to the plurality of planes and the plurality of latches and configured to cause the memory device to: receiving, at the memory device, a write command associated with a plurality of pages and the plurality of planes; loading a first set of data associated with a first page of the plurality of pages and the first subset of planes into a first subset of the first set of latches for a first duration; loading a second set of data associated with the first page and the second subset of planes into a second subset of the first set of latches for a second duration; transferring the first set of data from the first subset of the first set of latches to a first subset of the second set of latches during the second duration; loading a third set of data associated with a second page of the plurality of pages and the first subset of planes into the first subset of the first set of latches for a third duration; transferring the second set of data from the second subset of the first set of latches to a second subset of the second set of latches during the third duration; loading a fourth set of data associated with the second page and the second subset of planes into the second subset of the first set of latches for a fourth duration; and The first, second, third and fourth sets of data are programmed to memory cells of the memory device.

2. The memory device of claim 1, wherein the third duration is directly consecutive to the second duration.

3. The memory device of claim 1 , further comprising: an indicator indicating one of the first subset of planes or the second subset of planes, wherein the controller is further configured to cause the memory device to: determining that the indicator indicates the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches is based at least in part on determining that the indicator indicates the first subset of planes; and The indicator is determined to indicate the second subset of planes, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches is based at least in part on determining the indicator indicates the second subset of planes.

4. The memory device of claim 3, wherein the controller is further configured to cause the memory device to: setting the indicator indicating the first subset of planes based at least in part on receiving the write command, wherein determining the indicator indicating the first subset of planes is based at least in part on setting the indicator indicating the first subset of planes; receiving a second command to change the plane; and When the second command is received, the second subset of indicator indication planes is set based at least in part on the first subset of indicator indication planes, wherein determining the second subset of indicator indication planes is based at least in part on setting the second subset of indicator indication planes.

5. The memory device of claim 3, wherein the controller is further configured to cause the memory device to: changing the indicator to indicate the second subset of planes after loading the second set of data into the first subset of the first set of latches; and The indicator is altered to indicate the first subset of planes after loading the fourth set of data into the second subset of the first set of latches.

6. The memory device of claim 1, wherein the controller is further configured to cause the memory device to: receiving a first indication along with the first and second sets of data, the first indication indicating the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches is based at least in part on receiving the first indication; and A second indication is received together with the third and fourth sets of data, the second indication indicating the second subset of the plane, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches is based at least in part on receiving the second indication.

7. The memory device of claim 6, wherein: To receive the first indication, the controller is configured to cause the memory device to receive a first command triggering a first data transfer using the first subset of planes, wherein loading the first set of data into the first subset of the first set of latches and loading the second set of data into the first subset of the first set of latches is based at least in part on receiving the first command; and In order to receive the second indication, the controller is further configured to cause the memory device to receive a second command triggering a second data transfer using the second subset of planes, wherein loading the third set of data into the second subset of the first set of latches and loading the fourth set of data into the second subset of the first set of latches is at least partially based on receiving the second command.

8. The memory device of claim 1 , wherein the plurality of latches further comprises a third group of latches, wherein the controller is further configured to cause the memory device to: The third set of data is transferred from the first subset of the first set of latches to a first subset of the third set of latches during the fourth duration.

9. The memory device of claim 8, wherein the controller is further configured to cause the memory device to: After the fourth duration, the fourth set of data is transferred from the second subset of the first set of latches to the second subset of the third set of latches, wherein programming the first, second, third, and fourth sets of data is based at least in part on transferring the fourth set of data to the second subset of the third set of latches.

10. The memory device of claim 9, wherein to program the first, second, third, and fourth sets of data to the memory cells, the controller is further configured to cause the memory device to: The first, second, third and fourth sets of data are programmed using the first and second sets of data loaded in the first and second subsets of the second set of latches and the third and fourth sets of data loaded in the first and second subsets of the third set of latches.

11. The memory device according to claim 8, wherein the controller is further configured to cause the memory device to: loading a fifth set of data associated with a third page of the plurality of pages and the first subset of planes into the first subset of the first set of latches for a fifth duration, wherein loading the fifth set of data is based at least in part on transferring the third set of data to the first subset of the third set of latches; transferring the fourth set of data from the second subset of the first set of latches to the second subset of the third set of latches during the fifth duration; loading a sixth set of data associated with the third page and the second subset of planes into the second subset of the first set of latches during a sixth duration; transferring the fifth set of data from the first subset of the first set of latches to the first subset of the fourth set of latches during the sixth duration; transferring the sixth set of data from the second subset of the first set of latches to the second subset of the fourth set of latches after the sixth duration; and The fifth and sixth sets of data are programmed to memory cells of the memory device.

12. The memory device of claim 1, wherein the first and second pages correspond to pages of multi-level cells of the memory device.

13. The memory device of claim 1, wherein the first subset of planes and the second subset of planes are disjoint subsets that each include at least two planes.

14. A memory device comprising: a plurality of planes, comprising a first subset of planes and a second subset of planes; a plurality of latches, including a first group of latches and a second group of latches; and a controller coupled to the plurality of planes and the plurality of latches and configured to cause the memory device to: receiving, at the memory device, a read memory command associated with a plurality of pages and the plurality of planes; obtaining, from a memory of the memory device, a first set of data associated with a first page of the plurality of pages and the first subset of planes and a second set of data associated with the first page and the second subset of planes, the obtaining the first set of data comprising loading the first set of data into a first subset of the first set of latches and loading the second set of data into a second subset of the first set of latches; receiving a command to transmit the first page; transferring the first set of data from the first subset of the first set of latches to a first subset of the second set of latches and transferring the second set of data from the second subset of the first set of latches to a second subset of the second set of latches; transferring the first set of data from the first subset of the second set of latches for a first duration and in response to receiving the command to transfer the first page; transmitting the second set of data from the second subset of the second set of latches for a second duration; obtaining, from the memory of the memory device, a third set of data associated with a second page of the plurality of pages and the first subset of planes and a fourth set of data associated with the second page and the second subset of planes after transferring the first and second sets of data from the first set of latches to the first and second subsets of the second set of latches, wherein the obtaining the third set of data includes loading the third set of data into the first subset of the first set of latches and the second subset of planes and loading the fourth set of data into the second subset of the first set of latches; transferring the third set of data from the first subset of the first set of latches to the first subset of the second set of latches during the second duration; receiving a command to transmit the second page; transmitting the third set of data from the first subset of the second set of latches for a third duration; transferring the fourth set of data from the second subset of the first set of latches to the second subset of the second set of latches during the third duration; and The fourth set of data is transmitted from the second subset of the second set of latches for a fourth duration.

15. The memory device of claim 14, wherein the third duration is directly consecutive to the second duration.

16. The memory device of claim 14, further comprising: an indicator indicating one of the first subset of planes or the second subset of planes, wherein the controller is further configured to cause the memory device to: determining that the indicator indicates the first subset of planes, wherein transferring the third set of data to the first subset of the second set of latches is based at least in part on determining that the indicator indicates the first subset of planes; and The indicator is determined to indicate the second subset of planes, wherein transferring the fourth set of data to the second subset of the second set of latches is based at least in part on determining the indicator to indicate the second subset of planes.

17. The memory device of claim 16, wherein the controller is further configured to cause the memory device to: receiving commands to change the plane; setting the first subset of indicators indicating planes based at least in part on the second subset of indicators indicating planes when the command to change planes is received, wherein determining the first subset of indicators indicating planes is based at least in part on setting the first subset of indicators indicating planes; and When the command to change the plane is received, the second subset of the indicator indication planes is set at least in part based on the first subset of the indicator indication planes, wherein determining the second subset of the indicator indication planes is based at least in part on setting the second subset of the indicator indication planes.

18. The memory device of claim 16, wherein the controller is further configured to cause the memory device to: changing the indicator to indicate the second subset of planes after transferring the first set of data to the first subset of the second set of latches; and The indicator is altered to indicate the first subset of planes after transferring the second set of data to the second subset of the second set of latches.

19. The memory device of claim 14, wherein the controller is further configured to cause the memory device to: receiving a first indication indicating the first subset of planes, wherein transferring the third set of data to the first subset of the second set of latches is based at least in part on determining that the indicator indicates the first subset of planes; and A second indication is received indicating the second subset of planes, wherein transferring the fourth set of data to the second subset of the second set of latches is based at least in part on determining that the indicator indicates the second subset of planes.

20. The memory device of claim 19, wherein: To receive the first indication, the controller is further configured to cause the memory device to receive a first command triggering a first data transfer using the first subset of planes, wherein transferring the first set of data to the first subset of the second set of latches is based at least in part on receiving the first command; and To receive the second indication, the controller is further configured to cause the memory device to receive a second command triggering a second data transfer using the second subset of planes, wherein transferring the second set of data to the second subset of the second set of latches is based at least in part on receiving the second command.

21. The memory device of claim 14, wherein to transfer the third set of data to the first subset of the second set of latches, the controller is further configured to cause the memory device to: The first set of data in the first subset of the second set of latches is overwritten with the third set of data.

22. The memory device of claim 14, wherein the first and second pages correspond to pages of multi-level cells of the memory device.

23. The memory device of claim 14, wherein the first subset of planes and the second subset of planes are disjoint subsets that each include at least two planes.

24. An apparatus comprising: a controller configured to couple with a memory device, wherein the controller is configured to cause the apparatus to: transmitting a write command associated with a plurality of pages and a plurality of planes to the memory device; transferring a first set of data associated with a first page of the plurality of pages and a first subset of the plurality of planes to the memory device for a first duration; transmitting a command to change the plane to the memory device; transferring a second set of data associated with the first page and a second subset of the plurality of planes to the memory device for a second duration; transmitting a command to write to a second page of the plurality of pages to the memory device; and A third set of data associated with the second page and the first subset of the plurality of planes is transferred to the memory device for a third duration, wherein the third duration is directly consecutive to the second duration.

25. The apparatus of claim 24, wherein the controller is further configured to cause the apparatus to: transmitting a second command to change the plane to the memory device during the third duration; and A fourth set of data associated with the second page is transferred to the memory device for a fourth duration, wherein the fourth duration is directly consecutive to the third duration.

26. The apparatus of claim 24, wherein the first subset of the plurality of planes and the second subset of the plurality of planes are disjoint subsets that each include at least two planes.

27. An apparatus comprising: a controller configured to couple with a memory device, wherein the controller is configured to cause the apparatus to: transmitting a memory read command associated with a plurality of pages and a plurality of planes to the memory device; transmitting a command to the memory device to send data associated with a first page of the plurality of pages; receiving, from the memory device, a first set of data associated with the first page and a first subset of planes of the plurality of planes for a first duration; receiving, from the memory device for a second duration, a second set of data associated with the first page and a second subset of planes of the plurality of planes; transmitting a command to the memory device to send data associated with a second page of the plurality of pages; and A third set of data associated with the second page and the first subset of planes of the plurality of planes is received from the memory device for a third duration, wherein the third duration is directly consecutive to the second duration.

28. The apparatus of claim 27, wherein the controller is further configured to cause the apparatus to: transmitting a command to change plane to the memory device during the third duration; and A fourth set of data associated with the second page and the second subset of planes of the plurality of planes is received from the memory device for a fourth duration, wherein the fourth duration is directly consecutive to the third duration.

29. The apparatus of claim 27, wherein the first subset of planes and the second subset of planes are disjoint subsets that each include at least two planes.

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