Area-Optimized DI Circuit Asynchronous Serial Register Bank, Chip and Electronic Device

Abstract

The present invention discloses an area-optimized asynchronous serial register bank of a DI circuit, a chip and an electronic device. The serial register bank includes a plurality of DI-latches, a Mux component, two Demux components and a Fork component; in front of each DI-latch storing Data, a DI-latch storing Null is connected, and the two DI-latches storing Data and Null respectively form a register unit. All register units are connected in series to form a register unit string; the front end of the register unit string is connected to a Mux component having the same width as the register, and at the rear end of the register unit string, there are two Demux components and a Fork component having the same width as the register; the register unit string forms a register unit loop through a rotation path. The area-optimized asynchronous serial register bank of the DI circuit of the present invention only requires two DI-latches for the register unit, and selective access can be achieved without large-scale Demux components and Mux components around the register unit, effectively reducing the area of the register bank design.

Description

Technical Field

[0001] The present invention belongs to the technical field of asynchronous circuits, and particularly relates to an area-optimized asynchronous serial register bank, a chip and an electronic device of a DI circuit. Background Art

[0002] With the increase of clock frequency and the reduction of chip size, the clock skew problem has become increasingly serious. Due to the advantages of low power consumption, low noise and low electromagnetic interference, asynchronous clockless circuits have gradually been applied in complex circuits. Especially in a system-on-chip (SoC), they can effectively reduce the crosstalk between analog and digital circuits, support the integration of multi-rate circuits, and contribute to component reuse.

[0003] In high-temperature application fields such as automotive, aerospace, oil exploration and power electronics, the reliability of clocks and circuits faces severe challenges, and these industries have higher requirements for the high-temperature stability of integrated circuits. As substitutes for silicon materials, the third-generation semiconductor materials (such as gallium nitride and silicon carbide) have higher thermal stability, current-carrying capacity and breakdown voltage, and perform excellently under high-temperature, high-voltage and high-frequency conditions. Therefore, they have broad application prospects in the fields of power electronics, automotive electronics, aerospace, etc. However, when designing circuits with third-generation semiconductor devices, the circuit delay cannot be effectively calculated. The delay-insensitive (DI) circuits in asynchronous circuits have innate advantages. They do not need to estimate the circuit delay and can work normally even when there are arbitrary delays in gates and wires. As early as 1994, delay-insensitive circuits were applied to the design of third-generation semiconductor NMOS digital circuits; by 2016, when implementing CMOS digital circuits with third-generation semiconductors, delay-insensitive circuit design was also adopted.

[0004] In asynchronous circuits, C-element (C unit) and DI-latch (dual-edge latch) are important elements of delay-insensitive circuits. The functional blocks of delay-insensitive circuits are used to implement combinational logic and are designed using dual-rail return-to-zero logic. The basic components of delay-insensitive circuit design include Join component, Fork component, Merge component, Mux component and Demux component. Among them, Join component and Fork component are the cores of parallel computing, while Merge component, Mux component and Demux component focus on data flow control. These components are usually used in combination in delay-insensitive circuit design.

[0005] Current delay-insensitive circuits adopt a parallel register bank design when designing register banks. When designing register cells in the existing parallel register bank design, it is necessary to maintain a data loop, and at least three DI latches are required to form a loop to avoid deadlocks. Therefore, the implementation of one register cell requires three DI-latches, one Demux component, and one Mux component, resulting in a relatively large area for the register cell. Since the read and write signals in the parallel register bank are independently input and appear alternately, it is necessary to equip each register cell with a Merge component. Moreover, when selectively accessing each register cell, a large-scale Demux component and Mux component need to be equipped around all register cells. The scale and area of the peripheral Demux component and Mux component increase with the number and bit width of the registers. When the number and bit width of the registers are relatively large, the size and area of the required Demux component and Mux component will become very large, leading to an increase in the overall area of the register bank. A register bank with a large number of transistors will incur huge costs when facing the design of third-generation semiconductor circuits. Summary of the Invention

[0006] Aiming at the problems existing in the above background technology, the purpose of the present invention is to provide an area-optimized DI circuit asynchronous serial register bank, chip, and electronic device.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions:

[0008] An area-optimized DI circuit asynchronous serial register bank includes multiple DI-latches, one Mux component, two Demux components, and one Fork component; a DI-latch storing Null is connected in front of each DI-latch storing Data, and the two DI-latches storing Data and Null respectively form a register cell, and all register cells are connected in series to form a register cell string; the front end of the register cell string is connected to one Mux component with the same width as the register, and there are two Demux components and one Fork component with the same width as the register at the back end of the register cell string. The Fork component is connected between the two Demux components, and the Demux component in front of the Fork component is connected to the back end of the register cell string; the Mux component is used to control data input or data rotation, the Demux component in front of the Fork component is used to control discarded data to enter the Sink or data rotation, the Demux component at the back end is used to control the correct register cell to be output during the rotation process, and the Fork component is used to generate data for the rotation path and the output path. The register cell string forms a register cell loop through the rotation path.

[0009] Furthermore, a DI-latch is added in front of the Fork component to avoid deadlocks during the rotation process.

[0010] The present invention further provides a chip, which includes an area-optimized asynchronous serial register bank of DI circuits, a controller, and an arithmetic unit.

[0011] The present invention further provides an electronic device, which includes the above-mentioned chip.

[0012] Compared with the disadvantages and deficiencies of the prior art, the present invention has the following beneficial effects:

[0013] 1. For the area-optimized asynchronous serial register bank of DI circuits proposed by the present invention, compared with the existing parallel register banks, only two DI-latches are required for the register cells, and selective access can be achieved without large-scale Demux components and Mux components around the register cells, effectively reducing the area of the register bank design.

[0014] 2. Compared with the existing parallel register bank design, the area of the serial register bank design of the present invention is reduced by 72% when implemented on an FPGA and by 70% under the UMC110 process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of the overall architecture of the area-optimized asynchronous serial register bank of DI circuits provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] An area-optimized asynchronous serial register bank of DI circuits, the overall architecture is as Figure 1As shown, it includes multiple DI-latches, a Mux component, two Demux components, and a Fork component. Among the two Demux components, the front-end one is denoted as the Demux1 component, and the back-end one is denoted as the Demux2 component. The DI-latch provides storage for variables and implements handshaking to support the Data flow. In addition to normal handshaking latches, many degenerate latches are often required: the latch with only the output channel is the Source that generates Data (with the same constant value), and the latch with only the input channel is the Sink that consumes Data. The Mux component and the Demux component are branch components with control functions, which select among several inputs or direct the input to one of several outputs. The Mux component is a one-of-many input path controller. When in use, it synchronizes the control channel and the corresponding input channel and sends the input data to the data output, while the other input channels are ignored. Similarly, the Demux component is a one-of-many output path controller. When in use, it synchronizes the control and data input channels and directs the input to the selected output channel. Figure 1 In the Mux component and the Demux component, the numbers 0 and 1 indicate that the component is a one-of-two input / output path controller. When the control signal is Data0, the 0th path is selected; when the control signal is Data1, the 1st path is selected. The Fork component unconditionally branches the input Data / Null into two Data / Null paths.

[0018] The area-optimized DI circuit asynchronous serial register bank with dual-rail input / output signals includes the target register number, read enable, write enable, write data Data_in, and output data Data_out. At the same time, each dual-rail signal has its corresponding request signal and response signal.

[0019] In the data path of the area-optimized DI circuit asynchronous serial register bank, there is no longer a loop composed of three DI-latches, a Mux component, and a Demux component to avoid deadlocks. Instead, all the DI-latches are connected in series. A DI-latch that stores Null is connected in front of each DI-latch that stores Data to maintain the Data-Null data flow. The two DI-latches that store Data and Null respectively are used as a register unit, and all the register units are connected in series to form a register unit string. Among them, V in the DI-latch represents that the data is initialized to Data, and E represents that the data is initialized to Null.

[0020] The front end of the register cell string is connected to a Mux component with the same width as the register. The back end of the register cell string is sequentially connected to a Demux1 component, a Fork component, and a Demux2 component, all with the same width as the register. The Mux component is used to control data input or data rotation. The Demux1 component is used to control the entry of discarded data into the Sink or data rotation. The Demux2 component is used to control the output of the correct register cell during the rotation process. The Fork component is used to generate data for the rotation path and the output path. The register cell string forms a register cell loop through the rotation path. Generally speaking, the serial register bank rotates through the Mux component and the Demux1 component. Data is written through the Mux component and output through the Demux2 component.

[0021] In addition, a DI-latch is added in front of the Fork component, that is, behind the Demux1 component, to avoid deadlocks during the rotation process.

[0022] For a general register bank of 16 32-bit (logical bits), only 32 32-bit (logical bits) DI-latches need to be serially connected. Only two 32-bit Demux components and one Mux component are required to cooperate with the rotation mechanism for selective access.

[0023] For example, when reading register No. 8, the registers in front of register No. 8 need to be rotated. During each rotation process, the Data in front of the Demux1 component reaches the Fork component through the Demux1 component. The DI-latch in front of the Fork component receives the Data and requests Null forward, thus prompting the forward flow of the DI-latch ring and making the input end of the Mux component access Null. The data entering the Demux2 component will enter the Sink, and the data entering the Mux component will enter the last DI-latch and request Null backward. At this time, the flow of Null will start. When the flow of Null is completed, it is regarded as one rotation.

[0024] One rotation will move the register ring backward once. In the initial state, for register No. 8, it needs to be rotated 7 times. At this time, the DI-latch storing the value of register No. 8 will be in front of the Demux1 component, that is, at the operable register position. At this time, only by changing the control signal of the Demux1 component to Data1 and the control signal of the Demux2 component to Data0, the value of register No. 8 can be output. When the corresponding Null is output, the register bank maintains the current state, that is, the operable register position stores register No. 8. The next time a register is read / written, it will start rotating from the current state until the next target register is found.

[0025] The process of writing to a register is similar to that of reading a register. When the target register reaches the operable register position, the control signal of the Mux component is set to Data0, and the new data is written into the DI-latch at the end. The control signal of the Demux1 component is set to Data0, and the old data will enter the Sink of the Demux1 component.

[0026] A general register bank of 16 32-bit (logical bits) is implemented under FPGA and UMC110 processes. The traditional parallel register bank based on DI latches requires 14,062 LUT resources to be implemented on FPGA, and the area is 217,045.293705 under the UMC110 process. While the serial register bank requires 3,937 LUT resources to be implemented on FPGA, and the area is 66,729.071360 under the UMC110 process. Compared with the parallel register bank, the area of the serial register bank is reduced by 72% when implemented on FPGA, and the area is reduced by 70% under the UMC110 process.

[0027] A chip composed of the area-optimized DI circuit asynchronous serial register bank described above, a controller, an arithmetic unit, and other devices, and an electronic device including the chip and other devices.

[0028] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An area-optimized DI circuit asynchronous serial register bank, characterized in that: It includes multiple DI-latches, a Mux component, two Demux components and a Fork component; each DI-latch storing Data is connected to a DI-latch storing Null, and the two DI-latches storing Data and Null respectively serve as a register unit, and all register units are connected in series to form a register unit string; the front end of the register unit string is connected to a Mux component with the same register width, and the back end of the register unit string is provided with two Demux components with the same register width and a Fork component, the Fork component is connected between the two Demux components, and the Demux component at the front end of the Fork component is connected to the back end of the register unit string; the Mux component is used to control data input or data rotation, the Demux component at the front end of the Fork component is used to control discarded data to enter the Sink or data rotation, the Demux component at the back end is used to control the correct register unit to be output during the rotation process, the Fork component is used to generate data of the rotation path and the output path, and the register unit string forms a register unit loop through the rotation path.

2. The area-optimized DI circuit asynchronous serial register bank according to claim 1, wherein: A DI-latch is added in front of the Fork component.

3. A chip, characterized in that: It comprises the area-optimized DI circuit asynchronous serial register group as claimed in claim 1 or 2, as well as a controller and an operator.

4. An electronic device, characterized in that: Comprising the chip as claimed in claim 3.

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