Time sequence analysis method and device

Abstract

The invention provides a time sequence analysis method which comprises the following steps: acquiring a first time sequence file which comprises a plurality of time sequence tables; according to the plurality of time sequence tables, loading a plurality of container control blocks in a memory, each of the plurality of container control blocks storing address information of to-be-stored data in a corresponding container in the first time sequence file; according to a first time sequence analysis task, a first container control block is determined from the multiple container control blocks, the first container control block corresponds to a first container, and the first container is used for storing data of a first time sequence table corresponding to the first time sequence analysis task; and loading the data of the first time sequence table to the first container according to the first container control block. According to the technical scheme, loading of unnecessary time sequence table data is avoided, the loading granularity is smaller and more flexible, and decoupling of different models in the time sequence table and the time sequence file is achieved.

Description

Technical Field

[0001] This application relates to the field of chip design, and more particularly, to a method and apparatus for timing analysis. Background Art

[0002] Integrated circuit static timing analysis (STA) is one of the key steps in integrated circuit design, which can verify the timing correctness of integrated circuit design and determine whether the integrated circuit design can operate at the required working frequency. The design of the chip can only be truly completed through static timing analysis. The static timing analysis process generally can be divided into three steps: decomposing the timing path, calculating the path delay, and checking whether the path meets the timing constraints.

[0003] The calculation of the timing path delay depends on the timing table data in the timing file. Different timing files divided according to process or function will include several sets of different model data. A single execution of the timing analysis task generally only requires a set of model data or the data of a certain module under a certain model. Therefore, during the STA process, it is necessary to perform partial or incremental loading of the data in the timing file to reduce the memory overhead. Summary of the Invention

[0004] This application provides a method and apparatus for timing analysis. The solution of this application does not require configuring any loading parameters and achieves decoupling from the data model. The electronic design automation (EDA) tool will only load the data of the timing tables required for the timing analysis process according to the call situation of the timing tables, and no redundant timing table data will be loaded into the memory. Furthermore, the unused timing tables will not be loaded, avoiding unnecessary memory overhead.

[0005] In a first aspect, a method for timing analysis is provided, including: obtaining a first timing file, where the first timing file includes multiple timing tables; loading multiple container control blocks in the memory according to the multiple timing tables, where each container control block in the multiple container control blocks corresponds to a container in the memory, and the container is used to store the data of at least one timing table in the multiple timing tables, and each container control block in the multiple container control blocks stores the address information of the data to be stored in the corresponding container in the first timing file; determining a first container control block from the multiple container control blocks according to a first timing analysis task, where the first container control block corresponds to a first container, and the first container is used to store the data of the first timing table corresponding to the first timing analysis task; and loading the data of the first timing table into the first container according to the first container control block to parse the first timing analysis task.

[0006] In the technical solution of this application, the first timing file may be a timing file obtained by an EDA tool in the STA process or a timing library file obtained by an EDA tool in the chip design process. In the memory model, the float data of the timing table is basically stored in a container, and each container corresponds to a container control block. The container control block is separated from the container in memory and is stored separately. For the data of the container, the memory size of the container control block is fixed and occupies very little memory.

[0007] Therefore, when this application loads the timing file, it can first only load multiple container control blocks without loading the data in the timing file into the container. Each container control block stores the address information of the data to be stored in the corresponding container in this first timing file. The EDA tool then only loads the data of the first timing table mentioned above into the memory according to the call situation of the timing table, thereby avoiding the loading of unnecessary timing table data.

[0008] In addition, the loading granularity is the timing table. Compared with loading the model or module of the standard timing file, the loading granularity is smaller and more flexible. At the same time, it does not involve the model or module in the standard timing file, enabling decoupling of the timing table and different models in the timing file during access.

[0009] Combined with the first aspect, in some implementation manners of the first aspect, loading the data of the first timing table into the first container according to the first container control block includes: obtaining the data of the first timing table from the first timing file according to the address information of the first timing table stored in the first container control block; loading the data of the first timing table into the first container.

[0010] Among them, the address information of the first timing table may be the starting address of the first timing table in the first timing file.

[0011] Combined with the first aspect, in some implementation manners of the first aspect, after loading the data of the first timing table into the first container, the method further includes: modifying the address information of the first timing table in the first timing file stored in the first container control block to the address information of the first timing table in the memory.

[0012] Combined with the first aspect, in some implementation manners of the first aspect, the method further includes: obtaining a second timing analysis task for timing analysis based on the first timing table; determining the data of the first timing table stored in the first container according to the address information of the first timing table in the memory to analyze the second timing analysis task.

[0013] In the technical solution of the present application, when calculating the timing analysis task, the called timing table data will basically be accessed repeatedly, but only the first access will the float data be read through the addressing of the timing file. This addressing process has an extra performance overhead, but this part of the overhead is not large. Therefore, the extra performance overhead of loading the timing table data during the first access is amortized to each access to the timing table data, and the impact on the entire process is minimal, and the performance is basically the same as directly loading all the data of the corresponding model into the memory and then reading it.

[0014] In combination with the first aspect, in some implementations of the first aspect, the first time sequence file is a persistent time sequence file.

[0015] It should be understood that the persistent timing file is used to store the data in the timing file for a long time, for example, storing the system events in the form of binary sequences to the disk. Correspondingly, the standard timing file is a formatted text file used to record system timestamps, storing events in the form of formatted text. The standard timing file can be saved as a persistent timing file after being loaded into the data model in the memory. The persistent timing file can be a binary file format customized by the EDA tool.

[0016] Since the persistent timing file is in binary file format, it is not necessary to parse the persistent timing file when loading data from the persistent timing file to the memory; and since the content of the standard timing file includes string statements, etc., it is necessary to parse the statement code in the standard timing file through a parser when loading data from the standard timing file to the memory, so the data loading efficiency is greatly improved when using the persistent timing file to load data.

[0017] In combination with the first aspect, in some implementations of the first aspect, determining a first container control block from the multiple container control blocks according to the first timing analysis task includes: obtaining the first timing table called by the application programming interface API; and determining, according to the first timing table, the first container control block corresponding to the first container in the memory for storing the first timing table.

[0018] Optionally, the user may call, access or select the first timing table required to parse the first timing analysis task through an application programming interface (API). For example, the user searches for a specific cell according to the timing analysis task, and obtains the first timing table according to the type of table under the specific cell.

[0019] Second aspect, a device for timing analysis is provided, including: an acquisition module, configured to: acquire a first timing file, where the first timing file includes a plurality of timing tables; a loading module, configured to: load a plurality of container control blocks in a memory according to the plurality of timing tables, where each container control block in the plurality of container control blocks corresponds to a container in the memory, and the container is used to store data of at least one timing table in the plurality of timing tables, and each container control block in the plurality of container control blocks stores address information of data to be stored in the corresponding container in the first timing file; a determination module, configured to: determine a first container control block from the plurality of container control blocks according to a first timing analysis task, where the first container control block corresponds to a first container, and the first container is used to store data of a first timing table corresponding to the first timing analysis task; the loading module is specifically configured to: load the data of the first timing table into the first container according to the first container control block, so as to analyze the first timing analysis task.

[0020] In combination with the second aspect, in a possible implementation manner of the second aspect, the loading module is specifically configured to: acquire the data of the first timing table from the first timing file according to the address information of the first timing table stored in the first container control block; load the data of the first timing table into the first container.

[0021] In combination with the second aspect, in a possible implementation manner of the second aspect, the device further includes a modification module. After the loading module loads the data of the first timing table into the first container, the modification module is configured to: modify the address information of the first timing table stored in the first container control block in the first timing file to the address information of the first timing table in the memory.

[0022] In combination with the second aspect, in a possible implementation manner of the second aspect, the acquisition module is further configured to: acquire a second timing analysis task for timing analysis based on the first timing table; the determination module is further configured to: determine the data of the first timing table stored in the first container according to the address information of the first timing table in the memory, so as to analyze the second timing analysis task.

[0023] In combination with the second aspect, in a possible implementation manner of the second aspect, the first timing file is a persistent timing file.

[0024] In combination with the second aspect, in a possible implementation manner of the second aspect, the acquisition module is specifically configured to: acquire the first timing table called by an application programming interface API; the determination module is specifically configured to: determine the first container control block corresponding to the first container for storing the first timing table in the memory according to the first timing table.

[0025] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the first aspect or any possible implementation manner of the first aspect.

[0026] In a fourth aspect, an embodiment of the present application provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to execute the first aspect or any possible implementation manner of the first aspect.

[0027] In a fifth aspect, an embodiment of the present application provides a computer device, which includes a processor for coupling with a memory to read and execute instructions and / or program code in the memory to execute the first aspect or any possible implementation manner of the first aspect.

[0028] In a sixth aspect, an embodiment of the present application provides a chip system, which includes logic circuits for coupling with an input / output interface to transmit data through the input / output interface to execute the first aspect or any possible implementation manner of the first aspect. Description of the Drawings

[0029] Figure 1 is a schematic flowchart of an integrated circuit static timing analysis input file and calculation provided by an embodiment of the present application.

[0030] Figure 2 is a schematic block diagram of a chip design process provided by an embodiment of the present application.

[0031] Figure 3 is a schematic flowchart of a timing calculation provided by an embodiment of the present application.

[0032] Figure 4 is a schematic diagram of loading a timing file provided by an embodiment of the present application.

[0033] Figure 5 is a schematic diagram of the relationship among a standard timing file, a memory, and a persistent timing file provided by an embodiment of the present application.

[0034] Figure 6 is a schematic block diagram of a timing analysis method provided by an embodiment of the present application.

[0035] Figure 7 is an access model of a container by an EDA tool provided by an embodiment of the present application.

[0036] Figure 8 is a schematic flowchart of loading a persistent timing file provided by an embodiment of the present application.

[0037] Figure 9 It is a schematic flowchart of a memory data model provided by an embodiment of the present application.

[0038] Figure 10 It is a schematic flowchart of loading timing table data provided by an embodiment of the present application.

[0039] Figure 11 It is a schematic diagram of loading according to a data model and recording on demand provided by an embodiment of the present application.

[0040] Figure 12 It is a schematic structural block diagram of a timing analysis device provided by an embodiment of the present application.

[0041] Figure 13 It is a schematic diagram of the hardware structure of a timing analysis device provided by an embodiment of the present application. Detailed implementation manners

[0042] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0043] Integrated circuit static timing analysis (STA) is one of the key technologies in integrated circuit design, which can verify the correctness of the design in terms of timing and determine whether the design can operate at the required working frequency. The design of the chip can only be truly completed through static timing analysis.

[0044] Figure 1 It shows a schematic flowchart of an integrated circuit static timing analysis input file and calculation provided by an embodiment of the present application. As Figure 1 shown, the files required for the STA process include a gate-level netlist, a time series file, and a timing constraints file. Among them, the gate-level netlist is used to describe the connection relationship between gates or circuit elements of the same level and is a text file that follows a relatively simple markup syntax; the time series file, or the timing library file, is used to describe the timing and power consumption information of physical units; the timing constraints file is used to specify the timing requirements and limitations in the integrated circuit design to ensure that the circuit operates correctly at a specific clock frequency.

[0045] The static timing analysis process generally can be divided into three steps: decomposing the timing path, calculating the path delay, and checking whether the path meets the timing constraints. Decomposing the timing path can be to decompose the circuit into timing paths, or to convert the integrated circuit into a set of timing paths. For example, the timing paths can be divided into input port to register, register to register, register to output port, input port to output port, etc. Calculating the path delay can be to calculate the wire delay, unit delay of combinational logic, etc. on each timing path. The delay of a timing path is the combination of the delays of all wires and the unit delay on this timing path. The delay is generally defined as the time between 50% of the input transition and 50% of the output transition.

[0046] Figure 1 The shown timing file, or the timing library file, contains various timing models and the timing data of each cell in the process library, such as input / output (IO) cells, power management cells, etc. The STA calculates the delay of the timing path mainly relying on the data in the timing library file. Figure 2 Fig. shows a schematic block diagram of a chip design process provided by an embodiment of the present application. As Figure 2 shown, the processes such as logic synthesis, physical synthesis, placement and routing in digital backend and physical layout design all need to use the timing data calculated by STA for optimization. Thus, it can be seen that timing calculation runs through the entire backend process.

[0047] At the present stage, timing calculation is mainly carried out by looking up tables. Figure 3 Fig. shows a schematic flowchart of a timing calculation provided by an embodiment of the present application. As Figure 3 shown, after constructing or decomposing the timing path, the electronic design automation (EDA) tool obtains the look-up table indexes such as load, transition time, etc., and then looks up the results of the timing table from the cells in the timing library according to the load, transition time, etc. After that, the obtained results of the timing table are input into the model for calculation, and finally the results such as the delay of the timing path are obtained.

[0048] It should be noted that this calculation process needs to read the content of the timing library file into the memory and construct a data model to complete. The calculation of the timing path delay depends on the data in the timing file. According to different processes or functions, there will be several sets of data of different models in the timing file. Under the same set of models, it is also divided into different parts such as delay, power consumption, noise, etc. However, a single execution of the timing analysis task generally only needs a set of model data or the data of a certain module under a certain model. Therefore, partial or incremental loading of the timing file is required to reduce the memory overhead.

[0049] At present, the method of reducing the memory overhead of the timing file can be: when reading in the timing file, only load specific timing table data under the timing file by setting parameters, and perform disk caching on the loaded but unused data. Figure 4 FIG. shows a schematic diagram of loading a timing file provided by an embodiment of the present application.

[0050] Figure 4 The timing file in [description] is a standardized timing file, that is, a formatted text file used to record system timestamps, and stores events in the form of formatted text. This standardized timing file perceives the service model, or rather, the data partitioning granularity is the model or the modules in the model. As Figure 4 shown, the standardized timing file includes N models, and each of the N models includes at least one module. At present, it is possible to load only part of the model data into memory by setting parameters. At the same time, data screening is performed on the models that have been loaded into the content, that is, the associated data is retained in memory, and the unassociated data is cached to disk. For example, as Figure 4 shown, the user loads only the data in model M into memory by setting parameters. Then, the data of model M is fully loaded into memory, and the data of other models not loaded in the standardized timing file is cached to disk. After that, the EDA tool can retrieve the association between the data of model M and files such as the gate-level netlist. The data of the associated module m 1 is retained in memory, and the data of the unassociated or loaded but unused module m 2 is cached to disk. Thus, by reducing the data loaded in memory, the memory occupancy of the timing file memory model can be reduced.

[0051] However, the above method has low flexibility for single-model loading. For example, when Figure 4 shown in the standardized timing file only includes one model or one module, the method of setting parameters is not applicable to this situation. In addition, there will be a process in which the data of the model or module is fully loaded into memory and then cached to disk, resulting in a relatively high peak memory occupancy when the data is fully loaded into memory. Since this method performs disk caching on the unused data, it will additionally occupy disk space.

[0052] To solve the above technical problems, the present application proposes a timing analysis method 600, in which the method 600 loads part of the data required for timing analysis into memory by persistently loading the timing file on demand.

[0053] For ease of understanding, the persistent timing files are introduced first. Persistent timing files are used to store the data in the timing files permanently. For example, system events are stored on the disk in the form of binary sequences. Figure 5 FIG. shows a schematic diagram of the relationship among the standard timing file, the memory, and the persistent timing file provided by an embodiment of the present application. As Figure 5 shown in (a) of FIG., after the standard timing file is loaded into the data model in the memory, it can be saved as a persistent timing file, and the persistent timing file can be a binary file format customized by an EDA tool. After that, the memory can directly load the data in the persistent timing file without loading the standard timing file. The reason is that: as Figure 5 shown in (b) of FIG., since the persistent timing file is in binary file format, it is not necessary to parse the persistent timing file when loading data from the persistent timing file into the memory; while since the content of the standard timing file includes string statements, etc., it is necessary to parse the statement code in the standard timing file through a parser when loading data from the standard timing file into the memory. Therefore, the data loading efficiency is greatly improved when using the persistent timing file to load data.

[0054] However, since the persistent file is not aware of the business model, it is impossible to limit the loaded model by setting parameters. Therefore, in order to obtain better file loading performance and avoid unnecessary memory overhead, the timing analysis method 600 proposed in the present application can meet the on-demand loading of the data in the persistent timing file. Figure 6 FIG. shows a schematic block diagram of the method 600. As Figure 6 shown, the method 600 includes steps 610 to 640.

[0055] Step 610: Obtain a first timing file, where the first timing file includes a plurality of timing tables.

[0056] Among them, the first timing file can be Figure 5 the persistent timing file shown in FIG., and the granularity of the persistent timing file is the timing table rather than the model or the module in the model of the standard timing file. Therefore, the granularity of dividing the data is smaller and more flexible. The first timing file can be Figure 1 the timing file obtained by the EDA tool in the STA process in FIG. or Figure 2 the timing file obtained by the EDA tool in the chip design process in FIG.

[0057] Step 620: According to the plurality of timing tables, load a plurality of container control blocks in the memory, where each container control block in the plurality of container control blocks stores the address information of the data to be stored in the corresponding container in the first timing file.

[0058] Among them, in the embodiments of the present application, each of the multiple container control blocks corresponds to a container in the memory. The container is used to store data of at least one of the multiple timing tables in step 610. Each of the multiple container control blocks stores address information of the data to be stored in the corresponding container in the first timing file.

[0059] For ease of understanding, the relationships among the timing table, the container control block, and the container are introduced below. At present, the characteristics of the timing file or the timing library file stored in the memory include the following points: (1) Timing calculation is mainly performed through the data in the timing table. The timing table mainly stores floating-point (float) data. In the memory model, the timing table in the timing file exists in the data structure of the container. If the entire timing file is loaded into the memory, the proportion of the float data in the timing table exceeds 50%. For example, the memory may also include data corresponding to data objects such as cells and pins of the timing file. (2) In the memory model, the float data of the timing table is basically stored in the container, and each container corresponds to a container control block to determine the data in the container. The container control block and the data in the container are separated in memory. For the data in the container, the memory size of the container control block is fixed and occupies very little memory.

[0060] Therefore, based on the relationship between the above container control block and the container, when the present application loads the persistent timing file, it can first only load multiple container control blocks without loading the data in the persistent timing file into the container. Each container control block stores address information of the data to be stored in the corresponding container in the first timing file. The following embodiments will introduce this part in detail and will not be elaborated here.

[0061] Step 630: Determine a first container control block from the multiple container control blocks according to the first timing analysis task.

[0062] Among them, the first container control block corresponds to a first container. The first container is used to store data of the first timing table corresponding to the first timing analysis task. The data of the first timing table is the data required for parsing the first timing analysis task, or the data required for loading the persistent timing file.

[0063] Optionally, in the embodiments of the present application, based on the corresponding relationship among the timing table, the container, and the container control block, the user can call, access, or select the first timing table required for parsing the first timing analysis task through an application programming interface (API). For example, the user searches for a specific cell according to the timing analysis task and obtains the first timing table according to the type of the table under the specific cell.

[0064] Furthermore, after determining the first timing table, the EDA tool determines the corresponding first container control block for the first timing table according to the above corresponding relationship, and loads the float data indicated by the address information stored in the first container control block into the first container corresponding to the first container control block.

[0065] It should be understood that the above first timing table may include multiple timing tables, the first container control block may include multiple container control blocks, and the first container may include multiple containers. The present application does not limit this.

[0066] Step 640: Load the data of the first timing table into the first container according to the first container control block.

[0067] It can be obtained from step 630 that the EDA tool can determine the first container control block from multiple container control blocks loaded from the memory through the first timing table. And, it can be obtained from step 620 that the first container control block stores the address information such as the starting address of the data of the first timing table in the first timing file. Furthermore, the EDA tool can obtain the data of the first timing table from the first timing file through the address information stored in the first container control block, and load the data of the first timing table into the first container in the memory to implement the process of parsing the timing analysis task.

[0068] Finally, based on the characteristics of the timing table stored in the memory, the present application, through the corresponding relationship between the timing table, the container control block, and the container, only loads the container control block in advance, and then only loads the data of the first timing table mentioned above into the memory according to the call situation of the timing table, thereby avoiding the loading of unnecessary timing table data. The loading granularity is the timing table, which is smaller and more flexible than the granularity of loading the standard timing file, which is the model or the module in the model. At the same time, it does not involve the model or module in the standard timing file, so that the decoupling of the timing table and different models in the timing file can be achieved during access.

[0069] Next, in conjunction with Figures 7 to 11 introduce the specific embodiments of method 600.

[0070] Figure 7 shows an access model of a container by an EDA tool provided by an embodiment of the present application. As Figure 7 shown, after loading the persistent timing file into the EDA tool, the EDA tool can provide an API, and the user can call, access, or select the required first timing table through the API. Furthermore, the EDA tool loads the first container in the memory through the first timing table selected by the user, and loads the data indicated by the address information in the first container control block into the first container.

[0071] Exemplarily,Figure 8 FIG. 1 shows a schematic flowchart of loading a persistent timing file provided by an embodiment of the present application. In an embodiment of the present application, after inputting the persistent timing file into the EDA tool, the EDA tool loads the persistent timing file into the memory.

[0072] As Figure 8 shown, after the EDA tool reads the persistent timing file, it reads and analyzes the data in the persistent timing file. When the EDA tool reads data other than the timing table, regardless of the data format of the data, it is fully loaded into the memory and a complete data object is created in the memory. The data objects other than the timing table in the persistent timing file can be cells (such as name and function), timing, or index, etc. When the EDA tool reads the data of the timing table, only an empty timing table object is created in the memory, and the float data offset of the read timing table is written into the container control block of the empty timing table object. Specifically, the process of offset writing can be: when the EDA tool reads the data of the timing table, it does not load the data of the timing table into the empty container in the memory, but creates an empty timing table object, and writes the address information of the float data of the timing table in the persistent timing file, such as the starting address, into the container control block corresponding to the empty container.

[0073] Finally, when the EDA tool finishes reading, the data model constructed in the memory includes multiple empty timing table classes and complete other data classes. And, the address information of the data to be stored in the corresponding container is written into the container control block in each empty timing table object. For example, this address information can be used to indicate the starting address of the data to be stored in the corresponding container in the persistent timing file. It should be noted that in an embodiment of the present application, the empty timing table object is not completely empty in content, but only does not include the float data of the timing table. The empty timing table object can also include data objects such as indexes.

[0074] Figure 9 FIG. 2 shows a schematic diagram of a memory data model provided by an embodiment of the present application. As mentioned above, when the EDA tool reads data other than the timing table, regardless of the data format of the data, it is fully loaded into the memory and a complete data object is created in the memory. As Figure 9 shown, the EDA tool can create data objects such as library files, cells, pins, timing, timing tables, indexes, variable names, etc. in the memory. The nesting relationship of these data objects is as Figure 9As shown. For another example, the data object regarding the index under the time sequence table (table) can be used to store the coordinate data of the time sequence table, and the data object regarding the parameter name (variable) under the index (index) can be used to store the coordinate parameter name of the time sequence table. The above data objects are all completely created, while the data object involving float data does not include float data, but stores the address information of the float data in the persistent time sequence file.

[0075] In the embodiments of the present application, the float data in the time sequence table, such as the table data of the time sequence table or the data of the coordinate variable, will not be loaded into the memory, but the address information of the data in the persistent time sequence file, such as the starting address, is written in the container control block. As Figure 9 shown, Figure 9 the address information of the table data of the time sequence table in the persistent time sequence file and the address information of the coordinate data of the time sequence table in the persistent time sequence file are respectively written into the two control blocks in. Furthermore, when the EDA tool loads the data of the time sequence table into the memory, two containers can be created in the memory, and according to the Figure 9 corresponding relationship between the control block and the container shown, the float data indicated by the address information in the control block is loaded into the container.

[0076] Exemplarily, Figure 10 shows a schematic flowchart of loading time sequence table data provided by an embodiment of the present application. In the embodiments of the present application, the EDA tool needs to load the time sequence table data into the container in the memory for parsing the time sequence analysis task.

[0077] As Figure 10 shown, when the EDA tool accesses the time sequence table data, it will obtain the container control block corresponding to the time sequence table data. If the EDA tool has never accessed the data in the time sequence table, the address information stored in the container control block is the address information of the time sequence table in the persistent time sequence file, and the EDA tool will jump to the position indicated by the address information from the persistent time sequence file and load the time sequence table data to be obtained into the memory.

[0078] As Figure 10 shown, in some other embodiments of the present application, after the EDA tool has accessed the time sequence table data, the address saved in the container control block can be modified to the address information of the data of the time sequence table in the memory, or the address information of the container in the memory. In this way, if the EDA tool needs to process the second time sequence analysis task and the second time sequence analysis task needs to use the data of the first time sequence table that has been loaded into the memory, the EDA tool can directly find the data of the first time sequence table by addressing in the memory according to the address information stored in the container control block, and thus there is no need to repeatedly load the data from the persistent time sequence file.

[0079] When the timing analysis task is actually calculated, the called timing table data will basically be accessed repeatedly, but only the first access will read the float data through the addressing of the timing file. This addressing process has an additional performance overhead, but this part of the overhead is not large. Therefore, after the additional performance overhead of loading the timing table data during the first access is amortized to each access to the timing table data, the impact on the entire process is minimal, and the performance is basically the same as directly loading all the data of the corresponding model into the memory and then reading it.

[0080] Figure 11 FIG. 1 shows a schematic diagram of loading and recording according to a data model provided by an embodiment of the present application. Figure 11 As shown in (a), the timing tables 1-1, 1-2 and 2-1 are divided according to the granularity of the model in the standard timing file. Timing tables 1-1 and 1-2 belong to model 1, and timing table 2-1 belongs to model 2. Assuming that timing table 1-1 in model 1 is the data required for timing analysis or to be accessed, if loaded according to the data model, the entire data of model 1 is loaded into the memory, that is, all the data of timing tables 1-1 and 1-2 are loaded into the container in the memory. Among them, timing table 1-2 also occupies the same space in the memory as timing table 1-1, but it is not accessed, that is, this part of the memory is allocated but has no actual use.

[0081] like Figure 11 As shown in (b) in the figure, in the case of on-demand loading, the data is divided into time series tables in the persistent time series file. Assuming that the time series table 1-1 in model 1 is the data required for time series analysis or to be accessed, it is loaded first. Figure 11 All container control blocks shown in (b) in the figure. After the API call of the EDA tool accesses the interface of timing table 1-1, the EDA tool reads the address information stored in container control blocks 1-1-1, 1-1-2 and 1-1-3, reads the float data in timing table 1-1 from the persistent timing file and loads it into the memory, or in other words, loads it into the container in the memory. At this time, only timing table 1-1 is fully loaded in the memory. Since timing table 1-2 and timing table 2-1 have not been called, they still maintain the state of only loading the container control block. The memory size of the container control block can be ignored. Figure 11 In the case shown in (b), compared with Figure 11 The situation shown in (a) saves the memory overhead of the timing table 1-2.

[0082] It is worth noting that Figure 11 The schematic diagrams shown are examples only. Figure 11Each timing table in [the present application] corresponds to three container control blocks, and the three container control blocks correspond to three containers, that is, these three containers are used to store the data of the corresponding timing table. For example, in some other embodiments of the present application, each timing table may correspond to other numbers of container control blocks, such as 1 or 2. For another example, Figure 11 The three containers corresponding to each timing table shown in [Figure] can respectively store different data in the timing table. For example, one is used to store the first-dimensional coordinates in the timing table, one is used to store the second-dimensional coordinates in the timing table, and the other is used to store the values corresponding to each coordinate in the timing table. The present application does not limit the number and actual functions of the container control blocks and containers.

[0083] In the technical solution of the present application, compared with the method of loading by model granularity, the on-demand loading solution in the present application does not require configuring any loading parameters, achieving decoupling from the data model. The EDA tool will only load the data of the required timing table according to the call situation of the timing table, and no redundant timing table data is loaded into the memory. The memory occupation of the multi-loaded container control blocks is extremely small compared to the float data of the timing table and can be ignored.

[0084] The following combines Figure 12 and Figure 13 to describe the device of the embodiments of the present application. It should be understood that the device described below can execute the methods of the foregoing embodiments of the present application. To avoid unnecessary repetition, the following description of the device of the embodiments of the present application appropriately omits the repeated description.

[0085] Figure 12 is a schematic structural block diagram of a timing analysis device provided according to an embodiment of the present application. As Figure 12 shown, the timing analysis device 1200 includes an acquisition module 1201, a loading module 1202, and a determination module 1203.

[0086] An acquisition module 1201, configured to: acquire a first timing file, where the first timing file includes a plurality of timing tables; a loading module 1202, configured to: according to the plurality of timing tables, load a plurality of container control blocks in a memory, where each container control block in the plurality of container control blocks corresponds to a container in the memory, and the container is used to store data of at least one timing table in the plurality of timing tables, and each container control block in the plurality of container control blocks stores address information of data to be stored in the corresponding container in the first timing file; a determination module 1203, configured to: according to a first timing analysis task, determine a first container control block from the plurality of container control blocks, where the first container control block corresponds to a first container, and the first container is used to store data of a first timing table corresponding to the first timing analysis task; the loading module 1202, configured to: according to the first container control block, load the data of the first timing table into the first container to parse the first timing analysis task.

[0087] The device provided in the above embodiment and the method embodiment belong to the same concept. For the specific implementation process, refer to the method embodiment in the above text, which will not be elaborated here.

[0088] In the embodiments of the present application, the modules of each example described can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0089] For example, during the implementation process, the acquisition module 1201, the loading module 1202, and the determination module 1203 can be completed through instructions or program codes in software form, for example, executed by a combination of hardware and software modules in a processor. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to implement the acquisition module 1201, the loading module 1202, and the determination module 1203.

[0090] It should be noted that: when the device provided in the above embodiment executes the above method, only the division of the above function modules is used for illustration. In actual applications, the above functions can be allocated to different function modules according to needs, that is, the internal structure of the device is divided into different function modules to complete all or part of the functions described above. For example, in the device 1200, the acquisition module 1201 can be used to execute any step in the above method, and the loading module 1202 can be used to execute any step in the above method. The steps to be implemented by each unit can be specified according to needs, and all functions of the above device can be implemented by each unit respectively implementing different steps in the above method.

[0091] Figure 13 It is a schematic diagram of the hardware structure of a timing analysis device provided by an embodiment of the present application. Figure 13 The timing analysis device 1300 shown (this device 1300 can specifically be a computer device) includes a memory 1301, a processor 1302, a communication interface 1303, and a bus 1304. Among them, the memory 1301, the processor 1302, and the communication interface 1303 are communicatively connected to each other through the bus 1304.

[0092] The memory 1301 can be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1301 can store a program. When the program stored in the memory 1301 is executed by the processor 1302, the processor 1302 is used to execute each step of the method of the embodiment of the present application. For example, the processor 1302 can execute the method 600 described above.

[0093] The processor 1302 can be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits, and is used to execute relevant programs to implement the method of the method embodiment of the present application.

[0094] The processor 1302 can also be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the method of the present application can be completed by the integrated logic circuit in the hardware of the processor 1302 or instructions in software form.

[0095] The above-mentioned processor 1302 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory 1301, and the processor 1302 reads the information in the memory 1301 and combines it with its hardware to complete Figure 12 the functions that the modules included in the device shown need to execute, or execute the method 600 of the method embodiments of the present application.

[0096] The communication interface 1303 uses a transceiver device such as, but not limited to, a transceiver to implement the communication between the device 1300 and other devices or communication networks.

[0097] The bus 1304 may include a path for transmitting information between various components of the device 1300 (for example, the memory 1301, the processor 1302, and the communication interface 1303).

[0098] The embodiments of the present application also provide a computer device, which includes a processor for coupling with a memory, reading, and executing instructions and / or program codes in the memory to execute the method described in any one of the above embodiments.

[0099] The embodiments of the present application also provide a chip system, which includes a logic circuit for coupling with an input / output interface and transmitting data through the input / output interface to execute the method described in any one of the above embodiments.

[0100] It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method embodiments may be completed by the integrated logic circuit in the hardware of the processor or the instructions or program codes in software form. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0101] It can be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0102] The present application also provides a computer program product, which includes: computer program code, and when the computer program code runs on a computer, it causes the computer to execute the method of any one of the above embodiments.

[0103] The present application also provides a computer-readable medium storing program code which, when run on a computer, causes the computer to execute the method of any one of the above embodiments.

[0104] Those of ordinary skill in the art will appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0105] Those skilled in the art can clearly understand that for the sake of convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0106] In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings, direct couplings, or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0107] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions or program codes for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0108] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A method for timing analysis, characterized in that, comprising: Obtaining a first timing file, the first timing file including a plurality of timing tables; According to the plurality of timing tables, loading a plurality of container control blocks in memory, each container control block in the plurality of container control blocks corresponding to a container in the memory, the container being used to store data of at least one timing table in the plurality of timing tables, and each container control block in the plurality of container control blocks storing address information of the data to be stored in the corresponding container in the first timing file; According to a first timing analysis task, determining a first container control block from the plurality of container control blocks, the first container control block corresponding to a first container, the first container being used to store data of a first timing table corresponding to the first timing analysis task; According to the first container control block, loading the data of the first timing table into the first container to parse the first timing analysis task.

2. The method according to claim 1, characterized in that, The step of loading the data of the first timing table into the first container according to the first container control block includes: Obtaining the data of the first timing table from the first timing file according to the address information of the first timing table stored in the first container control block; Loading the data of the first timing table into the first container.

3. The method according to claim 2, characterized in that, After loading the data of the first timing table into the first container, the method further includes: Modifying the address information of the first timing table stored in the first container control block in the first timing file to the address information of the first timing table in the memory.

4. The method according to claim 3, characterized in that, The method further includes: Obtaining a second timing analysis task for timing analysis based on the first timing table; According to the address information of the first timing table in the memory, determining the data of the first timing table stored in the first container to parse the second timing analysis task.

5. The method according to any one of claims 1 to 4, characterized in that, The first timing file is a persistent timing file.

6. The method according to any one of claims 1 to 5, characterized in that, The step of determining a first container control block from the plurality of container control blocks according to a first timing analysis task includes: Obtaining the first timing table called by an application programming interface API; According to the first timing table, determining the first container control block corresponding to the first container for storing the first timing table in the memory.

7. A device for timing analysis, characterized in that, comprising: An obtaining module, configured to: obtain a first timing file, the first timing file including a plurality of timing tables; A loading module, configured to: load a plurality of container control blocks in a memory according to the plurality of timing tables, each container control block in the plurality of container control blocks corresponding to a container in the memory, the container being used to store data of at least one timing table in the plurality of timing tables, and each container control block in the plurality of container control blocks storing address information of data to be stored in the corresponding container in a first timing file; A determining module, configured to: determine a first container control block from the plurality of container control blocks according to a first timing analysis task, the first container control block corresponding to a first container, the first container being used to store data of a first timing table corresponding to the first timing analysis task; The loading module is specifically configured to: load the data of the first timing table into the first container according to the first container control block, so as to parse the first timing analysis task.

8. The apparatus according to claim 7, wherein, the loading module is specifically configured to: obtain the data of the first timing table from the first timing file according to the address information of the first timing table stored in the first container control block; load the data of the first timing table into the first container.

9. The apparatus according to claim 8, wherein, the apparatus further includes a modification module, after the loading module loads the data of the first timing table into the first container, the modification module is configured to: modify the address information of the first timing table in the first timing file stored in the first container control block to the address information of the first timing table in the memory.

10. The apparatus according to claim 9, wherein, the obtaining module is further configured to: obtain a second timing analysis task for timing analysis based on the first timing table; the determining module is further configured to: determine the data of the first timing table stored in the first container according to the address information of the first timing table in the memory, so as to parse the second timing analysis task.

11. The apparatus according to any one of claims 7 to 10, wherein, the first timing file is a persistent timing file.

12. The apparatus according to any one of claims 7 to 11, wherein, the obtaining module is specifically configured to: obtain the first timing table called by an application programming interface API; the determining module is specifically configured to: determine the first container control block corresponding to the first container for storing the first timing table in the memory according to the first timing table.

13. A computer-readable medium, wherein, the computer-readable medium stores program code, and when the computer program code runs on a computer, the computer is caused to execute the method according to any one of claims 1 to 6.

14. A computer program product, wherein, the computer program product includes computer program code, and when the computer program code runs on a computer, the computer is caused to execute the method according to any one of claims 1 to 6.

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