An inference calculation circuit system applicable to Mamba block

Abstract

The present invention belongs to the technical field related to circuit design, and discloses an inference calculation circuit system applicable to a Mamba block. Input F generates F1 through a normalization circuit. F1 generates F2 and F3 through projection by a memristor array. F2 is activated to generate F4. F3 is convolved by a memristor array and then activated to generate Xt. F1 generates S through projection by a memristor array. S undergoes an exponential operation through a memristor array to generate an M*N-dimensional matrix A; Xt generates B and C through projection by a memristor array; Xt performs element-wise multiplication through a memristor array to generate D; in the hidden state calculation circuit array with dimensions N*M, the hidden state calculation circuit in the nth row and mth column obtains Xt m , A m,n , B n , S m to perform hidden state calculation to obtain Ht n,m . A multiply-accumulate circuit performs a multiply-accumulate operation on Ht, B, C, and D to obtain Yt; F4 and Yt pass through a multiplication circuit and then through projection by a memristor array to obtain F5. F5 and F are superimposed through a summation circuit to obtain the output. Implementing inference calculation through a circuit can reduce the operation time and save power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field related to circuit design, and more specifically, relates to an inference calculation circuit system applicable to Mamba block. Background Art

[0002] The Mamba model is a new type of linear time series model that combines the advantages of CNN and transformer. It can capture global information while maintaining linear complexity. And through a parameterized selection mechanism, the Mamba model can selectively choose or ignore specific data according to the characteristics of the input data. Therefore, it does not require a huge parameter storage matrix. When dealing with many problems, its performance is often better than that of the transformer model and is the first choice for the new generation of large language model architectures.

[0003] The basis of the Mamba model is the Mamba block. A large Mamba model consists of many Mamba blocks. The core of the Mamba Block lies in its Selective State Spaces. After performing linear projection and convolution operations, relevant information in long sequences is efficiently captured through the selective state space, with linear time complexity. This makes it perform well when dealing with very long sequences. And because it relaxes the strict state transitions of traditional state space models, it is more adaptable and flexible.

[0004] Due to the complex control and data transfer of the Mamba block and the complex calculation process of the internal selection space state of the Mamba block, there has been no circuit implementation. Currently, model inference calculations are all performed through GPUs. However, when using GPUs for inference, problems such as the separation of memory and computing in the von Neumann architecture are often faced, and the transfer of data from storage to the computing unit often consumes a large amount of time and power.

[0005] Therefore, it is necessary to design a circuit system for Mamba block inference calculation to reduce the operation time and save power. Summary of the Invention

[0006] In view of the above deficiencies or improvement requirements of the prior art, the present invention provides an inference calculation circuit system applicable to Mamba block, aiming to implement the inference calculation of Mamba block through a circuit, reduce the operation time, and save power.

[0007] To achieve the above object, the present invention provides an inference calculation circuit system applicable to Mamba block, which includes;

[0008] The first circuit structure includes a normalization circuit, a first to second memristor array, and an activation circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1. The vector F1 is projected twice by the first memristor array to generate an M-dimensional vector F2 and an M-dimensional vector F3. The vector F2 is activated by the activation circuit to generate an M-dimensional vector F4. The vector F3 is convolved by the second memristor array and then activated by the activation circuit to generate an M-dimensional vector Xt, where t is the time index.

[0009] The second circuit structure includes a third to sixth memristor array. The vector F1 is projected by the third memristor array to generate an M-dimensional vector S. The vector S is element-wise multiplied with each column of the M * N-dimensional fifth memristor array to generate an M * N-dimensional matrix, and the e-exponential calculation circuit performs e-exponential operations on the elements of the matrix to generate an M * N-dimensional matrix A. The vector Xt is projected twice by the fourth memristor array to generate an N-dimensional vector B and an N-dimensional vector C. The vector Xt is element-wise multiplied by the sixth memristor array to generate an M-dimensional vector D.

[0010] The selective state space calculation circuit structure includes an N * M-dimensional hidden state calculation circuit array and M multiply-accumulate circuits. The hidden state calculation circuit in the nth row and mth column obtains the mth element Xt in the vector Xt m and the element A in the mth row and nth column of the matrix A m,n and the nth element B in the vector B n and the mth element S in the vector S m to perform hidden state calculation, obtaining the state element Ht in the nth row and mth column. n,m The state elements obtained by the hidden state calculation circuit array form an N * M-dimensional state matrix Ht. The M columns in the matrix Ht are respectively input into M multiply-accumulate circuits to perform multiply-accumulate operations with the vectors C and D, obtaining an M-dimensional vector Yt.

[0011] The result fusion circuit structure includes a multiplication circuit, a seventh memristor array, and a summation circuit. The vectors F4 and Yt are element-wise multiplied by the multiplication circuit and then projected by the seventh memristor array to obtain a K-dimensional vector F5. The vector F5 and the vector F are superimposed by the summation circuit to obtain a K-dimensional output vector.

[0012] Optionally, each hidden state calculation circuit includes switches S1 to S2, capacitors C1 to C2, operational amplifiers U1 to U4, a first-branch multiplier, a second-branch multiplier, and multiple resistors.

[0013] In the hidden state calculation circuit in the nth row and mth column:

[0014] The positive input terminal of operational amplifier U1 is grounded through capacitor C1 and connected to the output terminal of operational amplifier U4 through switch S1, and the negative input terminal is connected to its output terminal;

[0015] The first-branch multiplier respectively obtains element A m,n and performs a multiplication operation with the output result of operational amplifier U1, and the multiplication result is connected to the negative input terminal of operational amplifier U2 through a resistor;

[0016] The second-branch multiplier respectively obtains element S m , element Xt m , element B n and performs a multiplication operation, and the multiplication result is connected to the negative input terminal of operational amplifier U2 through a resistor;

[0017] The positive input terminal of operational amplifier U2 is grounded, the negative input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the negative input terminal of operational amplifier U3 through a resistor;

[0018] The positive input terminal of operational amplifier U3 is grounded, the negative input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the positive input terminal of operational amplifier U4 through switch S2;

[0019] The positive input terminal of operational amplifier U4 is grounded through capacitor C2, the negative input terminal is connected to its output terminal, and its output terminal outputs state element Ht n,m ;

[0020] Among them, switch S1 is controlled by clock signal CL0, and switch S2 is controlled by clock signal CL1. In the first transmission cycle, switch S2 is turned on and switch S1 is turned off, and the hidden state calculation circuit completes the state calculation at the current moment, and operational amplifier U4 outputs the state element. In subsequent transmission cycles, the states of switch S1 and switch S2 are opposite. In the early stage of the transmission cycle, switch S1 is turned on and switch S2 is turned off, so that the state element H(t - 1) n,m output by U4 at the previous moment (t - 1) is stored in capacitor C1, then switch S1 is turned off and switch S2 is turned on, so that the hidden state calculation circuit completes the state calculation at the current moment t, and operational amplifier U4 outputs state element Ht n,m .

[0021] Optionally, the second-branch multiplier includes multiplier G2 and multiplier G3. Multiplier G2 obtains element S m and element Xt m and performs a multiplication operation. Multiplier G3 obtains element B n and the multiplication result of multiplier G2 and performs a multiplication operation, and outputs the multiplication result of the second-branch multiplier.

[0022] Optionally, the K-dimensional input vector F is normalized by the normalization circuit to generate vector F1, where vector F consists of K voltage signals VI1 ~V IK Composed of;

[0023] The normalization circuit is a root mean square normalization circuit. The root mean square normalization circuit includes a root mean square circuit and K normalization branches. The K normalization branches perform normalization processing in one-to-one correspondence with K voltage signals. Each normalization branch includes an operational amplifier, a multiplier, and a resistor;

[0024] In the k-th normalization branch:

[0025] The inverting input terminal of operational amplifier U7 obtains the voltage signal V through a resistor Ik , its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U8 through a resistor;

[0026] The multiplier G4 respectively obtains the output result V of the root mean square circuit RMS and the output result of operational amplifier U7 and performs a multiplication operation. The multiplication result is connected to the inverting input terminal of operational amplifier U7 through a resistor;

[0027] The inverting input terminal of operational amplifier U8 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded;

[0028] The multiplier G4 respectively obtains the voltage parameter g i and the output result of operational amplifier U8 and performs a multiplication operation, and outputs the normalized result V of the voltage signal V Ik , where g Ok is a trained parameter. i

[0029] Optionally, the root mean square circuit includes K receiving branches, a multiplier G6, operational amplifiers U5 and U6, where

[0030] The K receiving branches respectively receive K voltage signals V I1 ~V IK , and in each receiving branch, the received voltage signal is squared by a multiplier and then connected to the inverting input terminal of operational amplifier U5 through a resistor;

[0031] The non-inverting input terminal of operational amplifier U5 is grounded, its inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of operational amplifier U6 through a resistor;

[0032] The non-inverting input terminal of operational amplifier U6 is grounded, the signal at the output terminal is squared by multiplier G6 and then connected to the inverting input terminal of operational amplifier U6 through a resistor, and the output terminal of operational amplifier U6 outputs the output result V of the root mean square circuit RMS .

[0033] ​Optionally, the exponential calculation circuit includes operational amplifiers U9 to U11, multiplier G7, and resistors;

[0034] Multiplier G7 accesses the external voltage signal V to be exponentially calculated j and after performing a squaring operation, it is grounded through two resistors;

[0035] The inverting input terminal of operational amplifier U9 is connected to three branches. The first branch accesses the voltage signal V through a resistor j , the second branch is connected to the other end of the grounding resistor through a resistor, and the third branch is connected to the output terminal of operational amplifier U9 through a resistor. The non-inverting input terminal of operational amplifier U9 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U10 through a resistor;

[0036] The inverting input terminal of operational amplifier U10 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U11 through a resistor;

[0037] The inverting input terminal of operational amplifier U11 accesses the external 1V voltage source through a resistor and is connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U12 through a resistor;

[0038] The inverting input terminal of operational amplifier U12 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the result V of the exponential calculation for the voltage signal V j ej .

[0039] Optionally, the activation circuit is a Silu activation circuit. The Silu activation circuit includes an exponential calculation circuit, operational amplifiers U13 to U16, multipliers G8 to G9, and resistors; among them,

[0040] The exponential calculation circuit is used to obtain the voltage V to be activated i and after performing an exponential calculation, it is connected to the inverting input terminal of operational amplifier U13 through a resistor;

[0041] The inverting input terminal of operational amplifier U13 accesses the external 1V voltage source through a resistor and is connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U14 through a resistor;

[0042] The inverting input terminal of operational amplifier U14 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded;

[0043] Multiplier G8 respectively obtains the voltage V i and the output result of the exponential calculation circuit and performs a multiplication operation, and then is connected to the inverting input terminal of operational amplifier U15 through a resistor;

[0044] The multiplier G9 separately obtains the output results of the operational amplifier U14 and the operational amplifier U15, performs a multiplication operation, and then connects to the inverting input terminal of U15 through a resistor;

[0045] The non-inverting input terminal of the operational amplifier U15 is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U16 through a resistor;

[0046] The inverting input terminal of the operational amplifier U16 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the activation result V i of V o .

[0047] Optionally, the m-th multiply-accumulate circuit is used to obtain the m-th column in the matrix Ht, the vector C, and the m-th element D in the vector D m and perform calculations; each multiply-accumulate circuit includes N multiplication branches, operational amplifiers U17 to U20, and resistors;

[0048] In the m-th multiply-accumulate circuit:

[0049] The n-th multiplication branch obtains the element Ht in the matrix Ht n,m and the m-th element C in the vector C m performs a multiplication operation and then connects to the inverting input terminal of the operational amplifier U17 through a resistor;

[0050] The inverting input terminal of the operational amplifier U17 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U18 through a resistor;

[0051] The inverting input terminal of the operational amplifier U18 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U19 through a resistor;

[0052] The inverting input terminal of the operational amplifier U19 is connected to the element D in the vector D through a resistor m and is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U20 through a resistor;

[0053] The inverting input terminal of the operational amplifier U20 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the m-th element Yt in the vector Yt m .

[0054] Optionally, the summing circuit is used to superimpose the elements at the same positions in the vectors F5 and F;

[0055] The summing circuit includes operational amplifiers U21 to U22 and resistors, where:

[0056] The inverting input terminal of operational amplifier U21 is connected to the voltage signal V of one of the elements of vector F5 through a resistor F5 and is connected to the voltage signal V of the element at the corresponding position of vector F through a resistor F and is also connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U22 through a resistor;

[0057] The inverting input terminal of operational amplifier U22 is connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal outputs the superposition result.

[0058] Optionally, the memristor array is a 1T1M memristor array.

[0059] Generally speaking, compared with the prior art by the above technical solution conceived by the present invention, the present invention mainly has the following beneficial effects.

[0060] 1. The inference calculation circuit system proposed by the present invention uses a memristor array to store weight parameters and can simultaneously complete the calculation of input and weight parameters, realizing in-memory computing. Its power consumption is greatly reduced compared with the traditional von Neumann architecture with separate memory and computing.

[0061] 2. The inference calculation circuit system proposed by the present invention designs a selective state space calculation circuit structure by analyzing the selective state space calculation, and combines an N*M-dimensional hidden state calculation circuit array and M multiply-accumulate circuits to realize the selective state space calculation. The inference of the Mamba block is realized through the circuit, and the circuit uses analog signals for calculation, avoiding the consumption of redundant digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). At the same time, compared with the large amount of storage and computing resources required by a high-precision digital signal calculation system, the resource overhead is further reduced.

[0062] 3. The circuit system realizes the full acceleration of the Mamba block inference calculation by correctly integrating all the above-mentioned circuit modules, reduces redundant data calculations, and the calculation efficiency is significantly improved compared with a general GPU. At the same time, through correct integration and control, it can independently and correctly generate an output vector, so this module can be further used as a basic unit for large-scale integration in complex large model generation tasks.

[0063] 4. Further, in the hidden state calculation circuit provided by the embodiment, U1 and U4 are used as source followers to stably hold the voltage stored in the capacitor, and U2 and U3 together form an adder. Through this circuit design, the addition of A⊙H(t-1) and S⊙B⊙Xt can be quickly and accurately realized.

[0064] 5. Further, in the root mean square normalization circuit provided by the embodiment, the operational amplifier U5 is used to aggregate the currents of all the branches after square operation, and U6 and G6 together implement the square root operation to obtain the result V of calculating the root mean square of the input. RMS , U7 and G4 are used to implement the division operation between V Ik and V RMS , but the operation result is the opposite number, and the operational amplifier U8 is required to reverse it to obtain the correct division result. Finally, it is multiplied by G5 and gi to quickly and accurately obtain the root mean square normalization result.

[0065] 6. Further, in the e-exponent calculation circuit provided by the embodiment, after G7 performs the square operation, it is divided by two resistors R to achieve 1 / 2 V j 2 , and U9 and U10 form an adder to perform the addition of V j and 1 / 2 V j 2 , and U11 and U12 also form an adder to implement 1 + V j + 1 / 2V j 2 , thus implementing the calculation of the e-exponent through Taylor expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 is a schematic structural diagram of the Mamba block.

[0067] Figure 2 is a schematic structural diagram of the inference calculation circuit system applicable to the Mamba block in an embodiment of the present invention.

[0068] Figure 3 is a schematic structural diagram of the memristor array in an embodiment of the present invention.

[0069] Figure 4 is a schematic structural diagram of the hidden state calculation circuit in an embodiment of the present invention.

[0070] Figure 5 is a timing diagram of each clock signal in an embodiment of the present invention.

[0071] Figure 6 is a schematic structural diagram of the root mean square normalization circuit in an embodiment of the present invention.

[0072] Figure 7 is a schematic structural diagram of the e-exponent calculation circuit in an embodiment of the present invention.

[0073] Figure 8 is a schematic structural diagram of the Silu activation circuit in an embodiment of the present invention.

[0074] Figure 9 It is a schematic structural diagram of a multiply-accumulate circuit in an embodiment of the present invention.

[0075] Figure 10 It is a schematic structural diagram of a summation circuit in an embodiment of the present invention. Specific embodiments

[0076] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0077] For the convenience of understanding, the working process of the Mamba block is introduced first, as Figure 1 shown in the schematic structural diagram of the Mamba block. The input vector is first projected and dimensionally elevated to obtain two vectors after projection and dimensional elevation. One of the projected vectors is successively subjected to one-dimensional convolution and Silu activation, and then enters the spatial state calculation part. After completing the spatial state calculation, it performs element-wise multiplication with the other vector after projection and Silu activation. The obtained result is dimensionally reduced through projection to make its dimension the same as that of the input vector. The vector after projection and dimensional reduction and the input vector are subjected to residual summation, and finally the operation of the Mamba block is completed to generate an output vector.

[0078] The Mamba block is a trainable module. In the present invention, it is aimed at the already trained Mamba block and how to implement it through a circuit when it is put into application. Therefore, the trainable parameters in this module are all determined in advance through training, that is, the parameters stored in all memristor arrays in the present invention are determined in advance.

[0079] As Figure 2 shown in the schematic structural diagram of an inference calculation circuit system suitable for the Mamba block in an embodiment of the present invention. This circuit system can be divided into four parts, namely the first circuit structure, the second circuit structure, the selective state space calculation circuit structure and the result fusion circuit structure. Among them, the first circuit structure realizes the Figure 1 operations of normalization, projection and activation in the early stage, the second circuit structure and the selective state space calculation circuit structure realize the Figure 1 operations of selective state space calculation in, and the result fusion circuit structure realizes the Figure 1Operations for data fusion in the middle and late stages. It should be noted that in the circuit, all signals are analog signals, and the elements in the vectors and matrices described in the solution are all analog signals. The following is a detailed description of each circuit structure.

[0080] The first circuit structure includes a normalization circuit, the first to second memristor arrays, and an activation circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate the vector F1. The vector F1 is projected twice by the first memristor array to generate the M-dimensional vector F2 and the M-dimensional vector F3. The vector F2 is activated by the activation circuit to generate the M-dimensional vector F4. The vector F3 is convolved by the second memristor array and then activated by the activation circuit to generate the M-dimensional vector Xt, where t is the time index.

[0081] Specifically, each signal in the K-dimensional input vector F respectively passes through a transistor controlled by a step signal and enters the normalization circuit. After normalization, the K-dimensional vector F1 is obtained. The K-dimensional vector F1 is input into the memristor array 1 for projection. Through projection, the signal can be dimensionally enhanced to obtain the M-dimensional vector F2 and the M-dimensional vector F3. Among them, the M-dimensional vector F3 enters the memristor array 2 for convolution operation and then undergoes an activation operation to obtain the M-dimensional vector Xt. The M-dimensional vector F2 directly undergoes an activation operation to obtain the M-dimensional vector F4.

[0082] The second circuit structure includes the third to sixth memristor arrays. The vector F1 is projected by the third memristor array to generate the M-dimensional vector S. The vector S is element-wise multiplied with each column of the fifth memristor array of M * N dimensions to generate an M * N-dimensional matrix, and the e-exponential calculation circuit performs e-exponential operations on the elements of the matrix to generate an M * N-dimensional matrix A; the vector Xt is projected twice by the fourth memristor array to generate the N-dimensional vector B and the N-dimensional vector C; the vector Xt is element-wise multiplied by the sixth memristor array to generate the M-dimensional vector D.

[0083] The function of the second circuit structure is to generate the intermediate parameters B, C, and D required for selective state space calculation.

[0084] Specifically, the K-dimensional vector F1 is projected by the memristor array 3 to generate an M-dimensional vector S. The vector S is element-wise multiplied with each column of the M * N-dimensional memristor array 5 to generate an M * N-dimensional matrix, and the e-exponentiation circuit performs e-exponentiation on each element of the matrix to generate an M * N-dimensional matrix A. Assuming that the weight parameter stored in the memristor array 5 is σ5, then the matrix A = exp(S' ⊙ σ5), where S' represents the matrix obtained by replicating the vector S N times. The vector Xt is projected twice by the memristor array 4 to generate an N-dimensional vector B and an N-dimensional vector C. The vector Xt is element-wise multiplied with the memristor array 6 to generate an M-dimensional vector D. Assuming that the weight parameter stored in the memristor array 6 is σ6, then D = σ6 ⊙ Xt, where ⊙ represents element-wise multiplication. Among them, element-wise multiplication between vectors means that the elements in the same position of the two vectors are weighted.

[0085] The selective state space calculation circuit structure includes an N * M-dimensional hidden state calculation circuit array and M multiplication and addition circuits. The hidden state calculation circuit in the nth row and mth column obtains the mth element Xt in the vector Xt m 、the element A in the mth row and nth column of the matrix A m,n 、the nth element B in the vector B n 、the mth element S in the vector S m to perform hidden state calculation and obtain the state element Ht in the nth row and mth column. n,m The state elements obtained by the hidden state calculation circuit array form an N * M-dimensional state matrix Ht. The M columns in the matrix Ht correspond one-to-one to the input M multiplication and addition circuits to perform multiplication and addition operations with the vector C and the vector D to obtain an M-dimensional vector Yt.

[0086] The selective state space calculation belongs to the most core structure of the Mamba block, and this operation involves complex calculations of multiple parameters. In the Mamba block, the formula for the selective state space calculation is as follows:

[0087] Yt = C * Ht + D;

[0088] Ht = A ⊙ H(t - 1) + S ⊙ B ⊙ Xt.

[0089] In the present invention, by analyzing this calculation process and combining an N * M-dimensional hidden state calculation circuit array and M multiplication and addition circuits, the selective state space calculation is realized.

[0090] Among them, the hidden state calculation circuit array realizes the calculation of Ht = A ⊙ H(t - 1) + S ⊙ B ⊙ Xt.

[0091] Specifically, the hidden state calculation circuit in the nth row and mth column obtains the mth element Xt in the vector Xt m 、the element A in the mth row and nth column of the matrix Am,n 、 The nth element B in vector B n 、 The mth element S in vector S m Perform hidden state calculation to obtain the state element Ht at the nth row and mth column n,m 。 For example, the hidden state calculation circuit 1_1 obtains Xt1, A 1,1 、 B1, S1 to perform hidden state calculation to obtain Ht 1,1 , the hidden state calculation circuit 1_M obtains Xt M 、 A M,1 、 B1, S M Perform hidden state calculation to obtain Ht 1,M , the hidden state calculation circuit N_1 obtains Xt1, A 1,N 、 B N 、 S1 to perform hidden state calculation to obtain Ht N,1 , the hidden state calculation circuit N_M obtains Xt M 、 A M,N 、 B N 、 S M Perform hidden state calculation to obtain Ht N,M 。 The state elements obtained by the hidden state calculation circuit array form an N * M - dimensional state matrix Ht

[0092] M multiplication - addition circuits implement the calculation of Yt = C * Ht+D

[0093] Specifically, the M columns in the matrix Ht respectively correspond to inputting M multiplication - addition circuits to perform multiplication - addition operations with vector C and vector D to obtain the M - dimensional vector Yt

[0094] The result fusion circuit structure includes a multiplication circuit, a seventh memristor array, and a summation circuit. Vector F4 and vector Yt pass through the multiplication circuit for element - by - element multiplication and then pass through the seventh memristor array for projection to obtain a K - dimensional vector F5. After vector F5 and vector F are superimposed through the summation circuit, a K - dimensional output vector is obtained

[0095] Among them, the purpose of the memristor array 7 is to restore the dimension to the dimension of the output vector

[0096] Such as Figure 3 shown is the structural schematic diagram of the memristor array in an embodiment of the present invention. The memristor array includes a plurality of 1T1M memristor units in an array form. The memristor in the 1T1M unit is used to store fixed weights. After the array receives an input signal, it outputs an analog voltage signal through matrix multiplication addition or element - by - element multiplication. Specifically, the word line WL is used to control the on - off of the memristors corresponding to the corresponding rows. When the circuit starts to work, all WLs are at high level, the transistors are turned on, and the memristors start to calculate. Because the conductance of each memristor unit M ij is Gij , namely G ij = 1 / R ij , the input voltage signals X1~X of the memristor array i , after entering the memristor array, the input voltage signal is multiplied by the voltage and conductance of different memristor units to obtain current. In the array, the currents are added on one output, and I sum1 ~I sumj are the sum of the corresponding currents of the output V1~V j part. After passing through the resistor R s and the operational amplifier for current-to-voltage conversion, the current I sum1 ~I sumj is converted into the corresponding output voltages V1~V j .

[0097] Such as Figure 4 shown is the structural schematic diagram of the hidden state calculation circuit in an embodiment of the present invention. Each hidden state calculation circuit includes switches S1~S2, capacitors C1~C2, operational amplifiers U1~U4, a first-branch multiplier, a second-branch multiplier, and multiple resistors.

[0098] Taking the hidden state calculation circuit in the nth row and mth column as an example for illustration.

[0099] The non-inverting input terminal of operational amplifier U1 is grounded through capacitor C1 and connected to the output terminal of operational amplifier U4 through switch S1, and its inverting input terminal is connected to its output terminal;

[0100] The first-branch multiplier respectively obtains element A m,n and performs a multiplication operation on the output result of operational amplifier U1. The multiplication result is connected to the inverting input terminal of operational amplifier U2 through a resistor;

[0101] The second-branch multiplier respectively obtains element S m , element Xt m , element B n and performs a multiplication operation. The multiplication result is connected to the inverting input terminal of operational amplifier U2 through a resistor;

[0102] The non-inverting input terminal of operational amplifier U2 is grounded, and its inverting input terminal is connected to its output terminal through a resistor. Its output terminal is connected to the inverting input terminal of operational amplifier U3 through a resistor;

[0103] The non-inverting input terminal of operational amplifier U3 is grounded, and its inverting input terminal is connected to its output terminal through a resistor. Its output terminal is connected to the non-inverting input terminal of operational amplifier U4 through switch S2;

[0104] The non-inverting input terminal of operational amplifier U4 is grounded through capacitor C2, and its inverting input terminal is connected to its output terminal. Its output terminal outputs the state element Ht n,m .

[0105] Further, the second branch multiplier includes multiplier G2 and multiplier G3. Multiplier G2 obtains element S m and element Xt m to perform a multiplication operation. Multiplier G3 obtains element B n and the multiplication result of multiplier G2 and performs a multiplication operation to output the multiplication result of the second branch multiplier.

[0106] Among them, switch S1 is controlled by clock signal CL0, and switch S2 is controlled by clock signal CL1. As Figure 5 shown is the timing diagram of each clock signal in an embodiment of the present invention.

[0107] In the first transfer cycle, switch S2 is turned on and switch S1 is turned off. The hidden state calculation circuit completes the state calculation at the current moment, and operational amplifier U4 outputs the state element. In subsequent transfer cycles, the states of switch S1 and switch S2 are opposite. In the early stage of the transfer cycle, switch S1 is turned on and switch S2 is turned off, so that the state element H(t - 1) n,m output by U4 at the previous moment (t - 1) is stored in capacitor C1. Then, switch S1 is turned off and switch S2 is turned on, so that the hidden state calculation circuit completes the state calculation at the current moment t, and operational amplifier U4 outputs the state element Ht n,m .

[0108] When the circuit is powered on, there will be signal fluctuations for a period of time. When the circuit is stable, the step signal becomes high level to turn on, and at the same time the circuit starts to work. The initial voltages of capacitor C1 and capacitor C2 are both 0. Capacitor C1 stores H(t - 1), and capacitor C2 stores Ht. In the first cycle, CL0 is at a low level, that is, switch S1 is disconnected and not closed. In the first half cycle, CL1 is at a low level, and the circuit calculation before switch S2 is performed to calculate Ht = A⊙H(t - 1)+ S⊙B⊙Xt to calculate Ht n,m as an example. As Figure 3 shown, when CL1 is at a high level, switch S2 is closed, and the circuit charges capacitor C2, that is, a new H is obtained t , which is stored and held. When the next cycle starts, CL0 is at a high level, CL1 is at a low level, switch S1 is closed, and S2 is disconnected. Capacitor C2 charges and discharges capacitor C1 through R c to realize the conversion of the hidden state H t as H t-1 . At the same time, the circuit performs the operation of A⊙H(t - 1)+S⊙B⊙Xt. When CL0 is at a low level and CL1 is at a high level, switch S1 is disconnected and switch S2 is closed to charge and discharge capacitor C2, realizing the calculation of Ht at the new moment, thereby realizing the storage, holding and conversion of Ht, and continuously calculating new outputs by analogy.

[0109] The hidden state calculation circuit provided in this embodiment uses U1 and U4 as source followers to stably hold the voltage stored in the capacitor. U2 and U3 together form an adder. Through this circuit design, the addition of A⊙H(t-1) and S⊙B⊙Xt can be quickly and accurately achieved.

[0110] In one embodiment, the normalization circuit is a root mean square normalization circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate the vector F1. Among them, the vector F is composed of K voltage signals V I1 ~ V IK .

[0111] The formula for root mean square normalization is:

[0112] V ok =g i ×V Ik / V RMS ;

[0113] ;

[0114] In the formula, R / R f =1 / K, where K is the dimension of the input vector, and g i is a trained parameter given by voltage. V ok is the voltage signal after normalization of V Ik , and V RMS is the root mean square result.

[0115] As Figure 6 shown is the structural schematic diagram of the root mean square normalization circuit in an embodiment of the present invention.

[0116] The root mean square normalization circuit includes a root mean square circuit and K normalization branches. The K normalization branches perform normalization processing in one-to-one correspondence with K voltage signals. Each normalization branch includes an operational amplifier, a multiplier, and a resistor.

[0117] In the kth normalization branch:

[0118] The inverting input terminal of the operational amplifier U7 obtains the voltage signal V Ik through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U8 through a resistor;

[0119] The multiplier G4 respectively obtains the output result V RMS of the root mean square circuit and the output result of the operational amplifier U7 and performs a multiplication operation. The multiplication result is connected to the inverting input terminal of the operational amplifier U7 through a resistor;

[0120] The inverting input terminal of the operational amplifier U8 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded;

[0121] The multiplier G4 respectively obtains the voltage parameter g i and the output result of the operational amplifier U8 and performs a multiplication operation to output the voltage signal V Ik 's normalization result V Ok .

[0122] In one embodiment, the root mean square circuit includes K receiving branches, a multiplier G6, operational amplifiers U5 and U6. Among them,

[0123] the K receiving branches respectively receive K voltage signals V I1 ~V IK . In each receiving branch, after the received voltage signal is squared by the multiplier, it is then connected to the inverting input terminal of the operational amplifier U5 through a resistor;

[0124] the non-inverting input terminal of the operational amplifier U5 is grounded, its inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of the operational amplifier U6 through a resistor;

[0125] the non-inverting input terminal of the operational amplifier U6 is grounded, the signal at the output terminal is squared by the multiplier G6 and then connected to the inverting input terminal of the operational amplifier U6 through a resistor, and the output terminal of the operational amplifier U6 outputs the output result V RMS of the root mean square circuit.

[0126] In the root mean square normalization circuit provided by this embodiment, the operational amplifier U5 is used to aggregate the currents of all the squared branches, and U6 and G6 together implement the square root operation to obtain the result V of the root mean square calculation of the input RMS , U7 and G4 are used to implement the division operation of V Ik and V RMS , but the operation result is the opposite number, and the operational amplifier U8 is needed to reverse it to obtain the correct division result. Finally, it is multiplied by G5 and gi to obtain the root mean square normalization result.

[0127] In one embodiment, the e exponential calculation circuit calculates the e exponential in the way of Taylor expansion, and the calculation formula is:

[0128] V ek = 1 + V j + 1 / 2V j 2 ;

[0129] In the formula, V j is the voltage signal to be calculated for the e exponential, and V ek is the e exponential calculation result of V j .

[0130] As Figure 7 shown is the structural schematic diagram of the e exponential calculation circuit in an embodiment of the present invention.

[0131] The e - exponential calculation circuit includes operational amplifiers U9 to U11, multiplier G7 and resistors;

[0132] The multiplier G7 accesses the external voltage signal V to be subjected to e - exponential calculation j and after performing a squaring operation, it is grounded through two resistors;

[0133] The inverting input terminal of operational amplifier U9 is connected to three branches. The first branch accesses the voltage signal V through a resistor j , the second branch is connected to the other end of the grounding resistor through a resistor, the third branch is connected to the output terminal of operational amplifier U9 through a resistor. The non - inverting input terminal of operational amplifier U9 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U10 through a resistor;

[0134] The inverting input terminal of operational amplifier U10 is connected to its output terminal through a resistor, its non - inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U11 through a resistor;

[0135] The inverting input terminal of operational amplifier U11 accesses an external 1V voltage source through a resistor and is connected to its output terminal through a resistor. Its non - inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U12 through a resistor;

[0136] The inverting input terminal of operational amplifier U12 is connected to its output terminal through a resistor, its non - inverting input terminal is grounded, and its output terminal outputs the result V of the e - exponential calculation for the voltage signal V j ej .

[0137] In the e - exponential calculation circuit provided in this embodiment, after G7 performs a squaring operation, it is divided by two resistors R to achieve 1 / 2 V j 2 , U9 and U10 form an adder for adding V j and 1 / 2 V j 2 , U11 and U12 also form an adder to achieve 1 + V j + 1 / 2V j 2 , realizing the calculation of the e - exponential through Taylor expansion.

[0138] In one embodiment, the activation circuit is a Silu activation circuit, and the calculation formula for Silu activation is:

[0139] ;

[0140] where V i is the voltage signal to be activated, and V o is V i ​Activation result

[0141] As Figure 8 shown is a schematic structural diagram of the Silu activation circuit in an embodiment of the present invention

[0142] The Silu activation circuit includes an exponential calculation circuit, operational amplifiers U13 to U16, multipliers G8 to G9, and resistors; where:

[0143] The exponential calculation circuit is used to obtain the voltage V to be activated i and after performing exponential calculation, it is connected to the inverting input terminal of operational amplifier U13 through a resistor

[0144] The inverting input terminal of operational amplifier U13 is connected to an external 1V voltage source through a resistor and to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U14 through a resistor

[0145] The inverting input terminal of operational amplifier U14 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded

[0146] Multiplier G8 respectively obtains the voltage V i and the output result of the exponential calculation circuit and performs a multiplication operation, and then is connected to the inverting input terminal of operational amplifier U15 through a resistor

[0147] Multiplier G9 respectively obtains the output result of operational amplifier U14 and the output result of operational amplifier U15 and performs a multiplication operation, and then is connected to the inverting input terminal of U15 through a resistor

[0148] The non-inverting input terminal of operational amplifier U15 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U16 through a resistor

[0149] The inverting input terminal of operational amplifier U16 is connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal outputs the activation result V i of V o

[0150] In the Silu activation circuit provided in this embodiment, U13 and U14 together form an adder to complete the addition of the result of the exponential calculation circuit and the 1V voltage. U15 and G9 complete the division operation, but the result is the opposite of the correct value. Therefore, the final U16 is required to perform inversion to obtain the correct Silu activation result

[0151] Specifically, the multiplication and addition formula executed by the mth multiplication and addition circuit is:

[0152]

[0153] As Figure 9 ​​The figure shows a schematic structural diagram of a multiply-accumulate circuit in an embodiment of the present invention. Each multiply-accumulate circuit includes N multiplication branches, operational amplifiers U17 to U20, and resistors.

[0154] In the m-th multiply-accumulate circuit:

[0155] The n-th multiplication branch obtains the element Ht in the matrix Ht n,m and the m-th element C in the vector C m After performing a multiplication operation, it is connected to the inverting input terminal of the operational amplifier U17 through a resistor;

[0156] The inverting input terminal of the operational amplifier U17 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U18 through a resistor;

[0157] The inverting input terminal of the operational amplifier U18 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U19 through a resistor;

[0158] The inverting input terminal of the operational amplifier U19 accesses the element D in the vector D through a resistor m and is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U20 through a resistor;

[0159] The inverting input terminal of the operational amplifier U20 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the m-th element Yt in the vector Yt m .

[0160] In the multiply-accumulate circuit provided in this embodiment, U17 and U18 are used to add all the multiplication calculation results, and U19 and U20 also jointly form an adder, which is added to Dm to obtain the final multiply-accumulate result.

[0161] As Figure 10 shown is a schematic structural diagram of a summing circuit in an embodiment of the present invention.

[0162] The summing circuit includes operational amplifiers U21 to U22 and resistors, where:

[0163] The inverting input terminal of the operational amplifier U21 accesses the voltage signal V of one of the elements in the vector F5 through a resistor F5 and accesses the voltage signal V of the element at the corresponding position in the vector F through a resistor F and is also connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U22 through a resistor;

[0164] The inverting input terminal of the operational amplifier U22 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the superimposed result.

[0165] In the summation circuit provided in this embodiment, U21 and U22 together form an adder to implement the addition of the voltages of V F and V F5 .

[0166] The above circuit system applicable to Mamba block inference calculation includes multiple memristor arrays, an in-memory computing hidden state calculation circuit, a normalization circuit, a Silu activation circuit, a multiply-accumulate circuit, and a summation circuit. Among them, the memristor array is responsible for matrix multiply-accumulate calculation and element multiplication operation, the in-memory computing hidden state calculation circuit is used to calculate, store, and transfer the hidden state of the Mamba block, and various functional circuits implement various types of analog signal calculations, including root mean square calculation, Silu activation calculation, multiplication and addition operations, and summation operations. All circuit modules are integrated in sequence to complete the inference calculation of the Mamba block from the input vector to the output vector.

[0167] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification. It should be noted that the "in one embodiment", "for example", "again, for example", etc. of the present invention are intended to illustrate the present invention, rather than to limit the present invention.

[0168] The above-described embodiments only represent several implementation manners of the present invention, and the description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. An inference calculation circuit system applicable to a Mamba block, characterized in that, including; The first circuit structure includes a normalization circuit, a first to a second memristor array, and an activation circuit. The K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1. The vector F1 is projected twice by the first memristor array to generate an M-dimensional vector F2 and an M-dimensional vector F3. The vector F2 is activated by the activation circuit to generate an M-dimensional vector F4. The vector F3 is convolved by the second memristor array and then activated by the activation circuit to generate an M-dimensional vector Xt, where t is the time index; The second circuit structure includes a third to a sixth memristor array. The vector F1 is projected by the third memristor array to generate an M-dimensional vector S. The vector S is element-wise multiplied with each column of the M * N-dimensional fifth memristor array to generate an M * N-dimensional matrix, and the e exponential calculation circuit performs e exponential operations on the elements of the matrix to generate an M * N-dimensional matrix A. The vector Xt is projected twice by the fourth memristor array to generate an N-dimensional vector B and an N-dimensional vector C. The vector Xt is element-wise multiplied by the sixth memristor array to generate an M-dimensional vector D; Selective state space calculation circuit structure, including an N * M - dimensional hidden state calculation circuit array and M multiply - add circuits. The hidden state calculation circuit in the n - th row and m - th column obtains the m - th element Xt of the vector Xt m , the element A in the m - th row and n - th column of the matrix A m,n , the n - th element B of the vector B n , the m - th element S of the vector S m to perform hidden state calculation and obtain the state element Ht in the n - th row and m - th column n,m . The state elements obtained by the hidden state calculation circuit array form an N * M - dimensional state matrix Ht. The M columns in the matrix Ht correspond one - to - one to the input of M multiply - add circuits to perform multiply - add operations with the vectors C and D to obtain an M - dimensional vector Yt; The result fusion circuit structure includes a multiplication circuit, a seventh memristor array, and a summation circuit. The vector F4 and the vector Yt are element-wise multiplied by the multiplication circuit and then projected by the seventh memristor array to obtain a K-dimensional vector F5. The vector F5 and the vector F are superimposed by the summation circuit to obtain a K-dimensional output vector.

2. The inference calculation circuit system according to claim 1, wherein Each hidden state calculation circuit includes switches S1~S2, capacitors C1~C2, operational amplifiers U1~U4, a first branch multiplier, a second branch multiplier, and multiple resistors; In the hidden state calculation circuit at the nth row and the mth column: The non-inverting input terminal of the operational amplifier U1 is grounded through the capacitor C1 and connected to the output terminal of the operational amplifier U4 through the switch S1, and the inverting input terminal is connected to its output terminal; The first branch multiplier separately obtains element A m,n and performs a multiplication operation on the output result of operational amplifier U1. The multiplication result is connected to the inverting input terminal of operational amplifier U2 through a resistor; The second-branch multiplier separately obtains elements S m , element Xt m , element B n to perform a multiplication operation, and the multiplication result is connected to the inverting input terminal of operational amplifier U2 through a resistor; The non-inverting input terminal of the operational amplifier U2 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of the operational amplifier U3 through a resistor; The non-inverting input terminal of the operational amplifier U3 is grounded, the inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the non-inverting input terminal of the operational amplifier U4 through the switch S2; The non-inverting input terminal of the operational amplifier U4 is grounded through the capacitor C2, the inverting input terminal is connected to its output terminal, and the output terminal outputs the state element Ht n,m ; Among them, switch S1 is controlled by clock signal CL0, and switch S2 is controlled by clock signal CL1. In the first transfer cycle, switch S2 is turned on and switch S1 is turned off. The hidden state calculation circuit completes the state calculation at the current moment, and operational amplifier U4 outputs the state element. In subsequent transfer cycles, the states of switch S1 and switch S2 are opposite. In the early stage of the transfer cycle, switch S1 is turned on and switch S2 is turned off, so that the state element H(t - 1) output by U4 at the previous moment (t - 1) n,m is stored in capacitor C1. Then, switch S1 is turned off and switch S2 is turned on, enabling the hidden state calculation circuit to complete the state calculation at the current moment t, and operational amplifier U4 outputs the state element Ht n,m .

3. The inference calculation circuit system according to claim 2, characterized in that, The second branch multiplier includes multiplier G2 and multiplier G3. Multiplier G2 obtains element S m and element Xt m to perform a multiplication operation. Multiplier G3 obtains element B n and the multiplication result of multiplier G2 and performs a multiplication operation to output the multiplication result of the second branch multiplier.

4. The inference calculation circuit system according to claim 1, wherein The K-dimensional input vector F is normalized by the normalization circuit to generate a vector F1, where the vector F is composed of K voltage signals V I1 ~ V IK ; The normalization circuit is a root mean square normalization circuit. The root mean square normalization circuit includes a root mean square circuit and K normalization branches. The K normalization branches perform normalization processing in one-to-one correspondence with K voltage signals. Each normalization branch includes an operational amplifier, a multiplier, and a resistor; In the kth normalization branch: The inverting input terminal of operational amplifier U7 obtains the voltage signal V through a resistor Ik , its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U8 through a resistor; The multiplier G4 respectively obtains the output result V of the root mean square circuit RMS and the output result of the operational amplifier U7, and performs a multiplication operation. The multiplication result is connected to the inverting input terminal of the operational amplifier U7 through a resistor; The inverting input terminal of the operational amplifier U8 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; The multiplier G5 respectively obtains the voltage parameter g i and the output result of the operational amplifier U8, and performs a multiplication operation to output the normalized result V Ik of the voltage signal V Ok , where g i is the trained parameter.

5. The inference calculation circuit system according to claim 4, characterized in that, The root mean square circuit includes K receiving branches, a multiplier G6, operational amplifiers U5 and U6, where K receiving branches respectively receive K voltage signals V I1 ~ V IK , in each receiving branch, after the received voltage signal is squared by a multiplier, it is then connected to the inverting input terminal of the operational amplifier U5 through a resistor; The non-inverting input terminal of the operational amplifier U5 is grounded, its inverting input terminal is connected to its output terminal through a resistor, and its output terminal is connected to the inverting input terminal of the operational amplifier U6 through a resistor; The non-inverting input terminal of operational amplifier U6 is grounded. The signal at the output terminal is squared by multiplier G6 and then connected to the inverting input terminal of operational amplifier U6 through a resistor. The output terminal of operational amplifier U6 outputs the output result V of the RMS circuit RMS .

6. The inference calculation circuit system according to claim 1, wherein The e exponential calculation circuit includes operational amplifiers U9~U11, a multiplier G7, and a resistor; The multiplier G7 is connected to the external voltage signal V to be subjected to e exponential calculation j After performing a squaring operation, it is grounded through two resistors; The inverting input terminal of the operational amplifier U9 is connected to three branches. The first branch accesses the voltage signal V through a resistor j , the second branch is connected to the other end of the grounding resistor through a resistor, the third branch is connected to the output terminal of the operational amplifier U9 through a resistor, the non-inverting input terminal of the operational amplifier U9 is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U10 through a resistor; The inverting input terminal of the operational amplifier U10 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of the operational amplifier U11 through a resistor; The inverting input terminal of operational amplifier U11 is connected to an external 1V voltage source through a resistor and is also connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U12 through a resistor; The inverting input terminal of the operational amplifier U12 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the voltage signal V j The result V of performing the exponential calculation ej .

7. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that The activation circuit is a Silu activation circuit. The Silu activation circuit includes an exponential calculation circuit, operational amplifiers U13 to U16, multipliers G8 to G9, and resistors. Among them, The e - exponential calculation circuit is used to obtain the voltage V to be activated i and after performing e - exponential calculation, it is connected to the inverting input terminal of the operational amplifier U13 through a resistor; The inverting input terminal of operational amplifier U13 is connected to an external 1V voltage source through a resistor and is also connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U14 through a resistor; The inverting input terminal of operational amplifier U14 is connected to its output terminal through a resistor, and its non-inverting input terminal is grounded; The multiplier G8 respectively obtains the voltage V i and the output result of the e exponential calculation circuit, performs a multiplication operation, and then is connected to the inverting input terminal of the operational amplifier U15 through a resistor; Multiplier G9 respectively obtains the output results of operational amplifier U14 and operational amplifier U15, performs a multiplication operation, and then is connected to the inverting input terminal of U15 through a resistor; The non-inverting input terminal of operational amplifier U15 is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U16 through a resistor; The inverting input terminal of the operational amplifier U16 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the voltage V i The activation result V o .

8. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that The m-th multiply-accumulate circuit is used to obtain the m-th column in the matrix Ht, the vector C, and the m-th element D in the vector D m and perform calculations; each multiply-accumulate circuit includes N multiplying branches, operational amplifiers U17 to U20, and resistors In the m-th multiply-accumulate circuit: The nth multiplication branch obtains the element Ht in the matrix Ht n,m and the nth element C in the vector C n After performing multiplication, it is connected to the inverting input terminal of the operational amplifier U17 through a resistor; The inverting input terminal of operational amplifier U17 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U18 through a resistor; The inverting input terminal of operational amplifier U18 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U19 through a resistor; The inverting input terminal of operational amplifier U19 is connected to the element D in vector D through a resistor m and is connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U20 through a resistor; The inverting input terminal of the operational amplifier U20 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the m-th element Yt in the vector Yt m .

9. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that The summing circuit is used to superimpose the elements at the same positions in vector F5 and vector F; The summing circuit includes operational amplifiers U21 to U22 and resistors, where: The inverting input terminal of operational amplifier U21 is connected to the voltage signal V of one of the elements of vector F5 through a resistor F5 and is connected to the voltage signal V of the element at the corresponding position of vector F through a resistor F and is also connected to its output terminal through a resistor. Its non-inverting input terminal is grounded, and its output terminal is connected to the inverting input terminal of operational amplifier U22 through a resistor; The inverting input terminal of operational amplifier U22 is connected to its output terminal through a resistor, its non-inverting input terminal is grounded, and its output terminal outputs the superimposed result.

10. The inference calculation circuit system according to any one of claims 1 to 6, characterized in that, The memristor array is a 1T1M memristor array.

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