Gate driving circuit, fabrication method and display panel

Abstract

This application belongs to the field of display driving technology, specifically relating to a gate driving circuit, a fabrication method, and a display panel. The gate driving circuit includes N cascaded GOA circuit units; a reset signal line disposed on any side near the GOA circuit unit, electrically connected to the gate of a reset transistor, and located on the same metal layer as the gate of the reset transistor; a cathode signal line disposed on the same side as the reset signal line and away from the GOA circuit unit; the cathode signal line electrically connected to the drain or source of the reset transistor, and located on the same metal layer as the source or drain of the reset transistor; and multiple clock signal lines disposed between the reset signal line and the cathode signal line, electrically connected to the clock signal line of the GOA circuit unit. This application eliminates the presence of ITO vias on the low-level signal lines, avoiding electrochemical corrosion of the ITO layer in high-temperature and high-humidity environments, thus improving the stability of the gate driving circuit.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit, a fabrication method, and a display panel. Background Technology

[0002] With the development of TFT-LCD display technology, narrow bezel displays have become the main trend in the development of high-quality displays due to their advantages such as simplicity, aesthetics, and large viewable area for the same size. In particular, the requirements for narrow bezels are becoming increasingly stringent for small-sized displays, and the application of GOA (Gate On Array) technology is becoming more frequent. GOA technology utilizes the array process of the liquid crystal display panel to fabricate the gate driving circuit on the array substrate, realizing a driving method of scanning the gate line by line. This eliminates the need for a separate gate driving integrated circuit, which not only reduces the material and manufacturing costs of display devices, but also reduces the bezel design of the panel, making it more in line with the development trend of display panels.

[0003] However, since GOA technology is a combination design of TFT (Thin Film Transistor) devices, in high temperature and high humidity environments, the ITO (Indium Tin Oxide) vias on the signal lines of the GOA circuit unit are subject to chemical corrosion, which has a direct impact on the stable output of the GOA circuit unit. Therefore, how to improve the stability of GOA circuit driving has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit, a fabrication method, and a display panel, which solves the problem of electrochemical corrosion of ITO vias in the GOA circuit unit under high temperature and high humidity environments, and improves the stability of the gate driving circuit.

[0005] In a first aspect, this application provides a gate driving circuit, comprising: N cascaded GOA circuit units, each GOA circuit unit including at least a reset transistor; a reset signal line disposed on any side near the GOA circuit unit, the reset signal line being electrically connected to the gate of the reset transistor and located on the same metal layer as the gate of the reset transistor; the reset signal line being used to provide a reset signal to the reset transistor; a cathode signal line disposed on the same side as the reset signal line and away from the GOA circuit unit; the cathode signal line being electrically connected to the drain or source of the reset transistor and located on the same metal layer as the source or drain of the reset transistor; the cathode signal line being used to provide a low voltage signal to the reset transistor; and a plurality of clock signal lines disposed between the reset signal line and the cathode signal line and electrically connected to the clock signal line of the GOA circuit unit; the clock signal lines providing a clock signal to the GOA circuit unit, causing the GOA circuit unit to output a corresponding gate driving signal.

[0006] Optionally, the nth-stage GOA circuit unit includes a control voltage terminal, a stage transmission output terminal, and a drive output terminal. The nth-stage GOA circuit unit further includes: a storage capacitor, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is connected to the drive output terminal; a pre-charge module, the control terminal of which is connected to the stage transmission output terminal of the nith-stage GOA circuit unit, the first terminal of which is connected to the drive output terminal of the nith-stage GOA circuit unit, and the second terminal of which is connected to the control voltage terminal, used to pre-charge the voltage on the control voltage terminal using the gate drive signal output by the nith-stage GOA circuit unit; and an output module, the control terminal of which is connected to the output terminal of the pre-charge module, the first terminal of which is connected to a clock signal line, and the second terminal of which is connected to the second terminal of the storage capacitor, used to output a gate drive signal under the action of the first target voltage on the control voltage terminal and the clock signal output by the clock signal line; and a stage transmission module. The module comprises a control terminal of the cascading transmission module connected to the control voltage terminal of the nth-level GOA circuit unit, a first terminal of the cascading transmission module connected to the clock signal line, and a second terminal of the cascading transmission module connected to the pre-charge module of the (n+i)th-level GOA circuit unit. It outputs a cascading transmission signal under the influence of the first target voltage at the control voltage terminal and the clock signal output from the clock signal line. A pull-down module has its control terminal connected to the drive output terminal of the (n+j)th-level GOA circuit unit, its first output terminal connected to the control voltage terminal of the nth-level GOA circuit unit, and its second output terminal connected to the drive output terminal of the nth-level GOA circuit unit. It discharges the voltage at the control voltage terminal and the drive output terminal to the second target voltage. A reset module has its control terminal connected to the reset signal line, and its output terminal connected to the control voltage terminal of the nth-level GOA circuit unit. It resets the voltage at the control voltage terminal under the influence of the reset signal.

[0007] Optionally, the nth-level GOA circuit unit further includes: a first pull-down control module, the control terminal of which is connected to a first pull-down signal line, and the output terminal of which is connected to the control voltage terminal, the stage transmission output terminal, and the drive output terminal of the nth-level GOA circuit unit, respectively, for maintaining the second target voltage on the control voltage terminal, the stage transmission output terminal, and the drive output terminal; and a second pull-down control module, the control terminal of which is connected to a second pull-down signal line, and the output terminal of which is connected to the control voltage terminal, the stage transmission output terminal, and the drive output terminal of the nth-level GOA circuit unit, respectively, for maintaining the second target voltage on the control voltage terminal, the stage transmission output terminal, and the drive output terminal.

[0008] Optionally, the precharge module includes: a first transistor, the gate of the first transistor being connected to the stage output terminal of the ni-th stage GOA circuit unit, the first terminal of the first transistor being connected to the drive output terminal of the ni-th stage GOA circuit unit, and the second terminal of the first transistor being connected to the control voltage terminal.

[0009] Optionally, the output module includes: a second transistor, the gate of the second transistor being connected to the control voltage terminal, the first terminal of the second transistor being connected to the clock signal line, and the second terminal of the second transistor serving as a drive output terminal.

[0010] Optionally, the stage transmission module includes: a third transistor, the gate of which is connected to the control voltage terminal, the first terminal of which is connected to the clock signal line, and the second terminal of which serves as the stage transmission output terminal; the reset module includes: a fourth transistor, the gate of which is connected to the reset signal line, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is connected to the cathode signal line; wherein, the fourth transistor serves as the reset transistor.

[0011] Optionally, the pull-down module includes: a fifth transistor, the gate of which is connected to the drive output terminal of the (n+j)th level GOA circuit unit, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is connected to the cathode signal line; and a sixth transistor, the gate of which is connected to the gate of the fifth transistor, the first terminal of which is connected to the drive output terminal, and the second terminal of which is connected to the cathode signal line.

[0012] Optionally, the first pull-down control module and the second pull-down control module include: a seventh transistor, the gate of which is connected to the control voltage terminal and the second terminal of which is connected to the cathode signal line; an eighth transistor, the gate of which is connected to the gate of the seventh transistor and the second terminal of which is connected to the cathode signal line; a ninth transistor, the gate of which is connected to the first pull-down signal line or the second pull-down signal line, the first terminal of which is connected to the gate ... The tenth transistor is connected to the first terminal of the eighth transistor; the eleventh transistor has its gate connected to the second terminal of the tenth transistor, its first terminal connected to the control voltage terminal, and its second terminal connected to the cathode signal line; the twelfth transistor has its gate connected to the gate of the eleventh transistor, its first terminal connected to the drive output terminal, and its second terminal connected to the cathode signal line; the thirteenth transistor has its gate connected to the gate of the twelfth transistor, its first terminal connected to the stage transmission output terminal, and its second terminal connected to the cathode signal line.

[0013] Secondly, this application provides a method for fabricating a gate driving circuit, the method comprising: fabricating a first metal layer on an array substrate, the first metal layer including a gate of a reset transistor and a reset signal line; coating a silicon nitride compound on the first metal layer to form a gate insulating layer; sequentially fabricating an amorphous silicon layer and an N-type conductive layer on the gate insulating layer; fabricating a second metal layer on the N-type conductive layer, the second metal layer including a source, a drain, and a cathode signal line of a reset transistor; coating a silicon nitride layer on the second metal layer to form a source-drain protection layer; forming a via between the first metal layer and the second metal layer; and depositing a metal oxide layer on the source-drain protection layer to form an ITO layer, thereby fabricating the gate driving circuit.

[0014] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes the gate driving circuit, wherein the drive output terminal of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] This application sets the reset signal line and the gate of the reset transistor in the GOA circuit unit on the same metal layer, and sets the cathode signal line, the source and drain of the reset transistor on another identical metal layer. This eliminates the presence of ITO vias on the low-level signal line, avoids electrochemical corrosion of the ITO layer in high-temperature and high-humidity environments, and improves the stability of the gate drive circuit. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0019] Figure 2 The diagram shown is a cross-sectional view of a circuit board provided in an embodiment of this application.

[0020] Figure 3 The diagram shown is a schematic diagram of an ITO via connection provided in an embodiment of this application.

[0021] Figure 4 The diagram shown is a schematic representation of the manufacturing process of a circuit board according to an embodiment of this application.

[0022] Figure 5 The diagram shown is a structural schematic of a GOA circuit unit provided in an embodiment of this application.

[0023] Figure 6 The diagram shown is a circuit diagram of a GOA circuit unit provided in an embodiment of this application.

[0024] Figure 7 The diagram shown is a design schematic of a GOA circuit unit provided in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 10. Gate drive circuit;

[0027] 100. GOA circuit unit; 110. Precharge module; 120. Output module; 130. Cascade module; 140. Pull-down module; 150. Reset module; 160. First pull-down control module; 170. Second pull-down control module;

[0028] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; C1, storage capacitor;

[0029] Qn, control voltage terminal; Cn, stage output terminal; Gn, drive output terminal; CKn, clock signal line; LC1, first pull-down signal line; LC2, second pull-down signal line; STV, reset signal line; VSS, cathode signal line.

[0030] 20. Array substrate; 21. First metal layer; 22. Gate insulating layer; 23. Amorphous silicon layer; 24. N-type conductive layer; 25. Second metal layer; 26. Source and drain protection layer; 27. ITO layer. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0034] The inventors of this application have discovered that, because GOA technology is a combined design of TFT devices, it is manufactured along with the array substrate process. Furthermore, the GOA driving circuit structure is complex. On the one hand, it is affected by the array substrate manufacturing process, resulting in defects; on the other hand, it is affected by the inherent instability of the TFT devices themselves and external environmental conditions. This frequently leads to display abnormalities in TFT-LCD displays due to GOA driving issues during use. Recent feedback from major panel manufacturers regarding GOA driving display abnormalities indicates that, in high-temperature and high-humidity environments, the corrosion of ITO vias on the GOA signal lines directly impacts the stable output of the GOA circuit.

[0035] The ITO corrosion mechanism is as follows: During long-term operation under high temperature and humidity conditions, moisture continuously penetrates the cell through the sealant or polyimide (PI) film layer, enhancing the conductivity of the PI and LC (liquid crystal) in the surrounding area, forming a pathway. This leads to electrochemical corrosion of the ITO at the cathode (low potential). However, the signal lines in the GOA are located on the periphery of the display area, close to the edge of the TFT glass; therefore, the vias on the signal lines in the GOA have the highest risk of ITO corrosion.

[0036] To address the issue of ITO corrosion of vias on GOA signal lines in high-temperature and high-humidity environments, this application provides a gate drive circuit, specifically including the following embodiments:

[0037] Figure 1 The diagram shown is a schematic representation of a gate driving circuit according to an embodiment of this application; as follows: Figure 1 As shown, the gate drive circuit includes: N cascaded GOA circuit units 100, each GOA circuit unit 100 including at least a reset transistor T0; wherein, the reset transistor T0 is used to reset the control voltage terminal in the GOA circuit unit to prevent the residual voltage of the previous frame from affecting the display of the current frame; the reset transistor includes a gate (i.e., gate), a drain, and a source.

[0038] In this embodiment, the gate drive circuit 10 further includes a reset signal line STV, which is disposed on any side near the GOA circuit unit 100. The reset signal line STV is electrically connected to the gate of the reset transistor T0 and is located on the same metal layer as the gate of the reset transistor T0. The reset signal line STV is used to provide a reset signal to the reset transistor T0. Specifically, the reset signal on the reset signal line STV controls the reset transistor T0 to turn on, so the reset signal line STV needs to be electrically connected to the gate of the reset transistor T0. In addition, by setting the reset signal line STV and the gate of the reset transistor T0 to the same metal layer, the reset signal line STV and the gate of the reset transistor T0 are directly connected, without the need for via conduction connection, thus avoiding the problem of ITO corrosion on the via.

[0039] In this embodiment, the gate drive circuit 10 further includes a cathode signal line VSS, which is located on the same side as the reset signal line STV and is disposed away from the GOA circuit unit 100. The cathode signal line VSS is electrically connected to the drain or source of the reset transistor T0 and is located on the same metal layer as the drain or source of the reset transistor T0. The cathode signal line VSS is used to provide a low voltage signal to the GOA circuit unit 100. Specifically, the cathode signal line VSS is equivalent to a low-level signal line, which pulls down the voltage on the control voltage terminal in the GOA circuit unit 100 (i.e., resets) through the conducting reset transistor T0. Therefore, the cathode signal line VSS needs to be electrically connected to the drain or source of the reset transistor T0. In addition, by setting the cathode signal line VSS and the source or drain of the reset transistor T0 on the same metal layer, the cathode signal line VSS is directly connected to the source or drain of the reset transistor T0, without the need for via conduction connection, thus avoiding the problem of ITO corrosion on the via.

[0040] In this embodiment, the gate drive circuit 10 further includes a plurality of clock signal lines disposed between the reset signal line STV and the cathode signal line VSS, and electrically connected to the clock signal line of the GOA circuit unit 100; the clock signal lines provide clock signals to the GOA circuit unit 100, so that the GOA circuit unit 100 outputs corresponding gate drive signals.

[0041] Figure 1 Taking the 4CK drive architecture as an example, CK1, CK2, CK3 and CK4 represent the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line, LC1 and LC2 represent the first pull-down signal line and the second pull-down signal line, STV represents the reset signal line and VSS represents the cathode signal line. Figure 1 In the gate drive circuit 10 of this application, both the clock signal line and the pull-down signal line transmit high potentials. In high-temperature and high-humidity environments, the ITO on the vias will not corrode. Therefore, the clock signal line and other transistors in the GOA circuit unit 100 can be connected through ITO vias, or they can be placed in the same metal layer as the source or drain of the transistors. This can be flexibly configured according to the actual circuit layout design. However, although the reset signal line STV is high when resetting the circuit, it is at a low potential at other times. Therefore, the reset signal line STV and the cathode signal line VSS are both low-potential signal lines, and the ITO vias on their lines will corrode in high-temperature and high-humidity environments. Here, in this embodiment, the reset signal line STV and the cathode signal line VSS are laid out by directly connecting them to the corresponding terminals of the reset transistor, avoiding the risk of corrosion of the ITO vias on the lines, which can further improve the stability of the output of the gate drive circuit 10.

[0042] Figure 2The diagram shown is a cross-sectional view of a circuit board provided in an embodiment of this application. The circuit board is fabricated from the gate drive circuit of this embodiment. Only a portion of the gate drive circuit board is shown in cross-section, including multiple transistors, reset signal lines, cathode signal lines, and multiple clock signal lines. Figure 2 In the diagram, 20 represents the array substrate; 21 represents the first metal layer; 22 represents the gate insulating layer; 23 represents the amorphous silicon layer; 24 represents the N-type conductive layer; 25 represents the second metal layer; 26 represents the source / drain protection layer; and 27 represents the ITO layer. Figure 2 The left side is a cross-sectional view of the transistor. The first metal layer 21 is the metal layer containing the gate, and the second metal layer 25 is the metal layer containing the source and drain. Figure 2 The first metal layer 21 on the right side can be understood as the reset signal line, so that the gate of the reset transistor is directly connected to the reset signal line without needing to be connected through an ITO via. In addition, the cathode signal line and the drain and source of the transistor are all located on the second metal layer 25, so that the drain or source of the reset transistor can be directly connected to the cathode signal line without needing to be connected through an ITO via.

[0043] Figure 3 The diagram shown is a schematic representation of an ITO via connection provided in an embodiment of this application; Figure 3 When a certain position of the first metal layer 21 and the second metal layer 25 needs to be turned on, an opening is made in the gate insulating layer 22 and the source-drain protection layer 26 and they are connected through the ITO layer 27.

[0044] Figure 4 The diagram shown is a schematic representation of the manufacturing process of a circuit board according to an embodiment of this application; as follows: Figure 4 As shown, the specific process flow includes:

[0045] (1) A patterned first metal layer 21 is fabricated on the array substrate. The first metal layer 21 includes the gate of the transistor, the reset signal line and the common electrode, etc.

[0046] (2) A silicon nitrogen compound is coated on the first metal layer 21 to form a gate insulating layer 22.

[0047] (3) An amorphous silicon layer 23 and an N-type conductive layer are sequentially fabricated on the gate insulating layer. This forms a carrier transport channel in the transistor.

[0048] (4) A second metal layer 25 is prepared on the N-type conductive layer 24, wherein the second metal layer 25 includes the source, drain and cathode signal lines of the transistor.

[0049] (5) Silicon nitride is coated on the second metal layer 25 to form a source-drain protection layer 26 to prevent the second metal layer 25 from being oxidized.

[0050] (6) A via is formed between the first metal layer 21 and the second metal layer 25.

[0051] (7) Deposit metal oxide on the source and drain protection layer 26 to form an ITO layer 27, thereby obtaining the corresponding gate drive circuit.

[0052] Therefore, this application sets the reset signal line and the gate of the reset transistor in the GOA circuit unit on the same metal layer, and sets the cathode signal line, the source and drain of the reset transistor on another metal layer. This ensures that there are no ITO vias on the low-level signal line, avoids electrochemical corrosion of the ITO layer in high-temperature and high-humidity environments, and improves the stability of the gate drive circuit.

[0053] Figure 5 The diagram shown is a structural schematic of a GOA circuit unit provided in an embodiment of this application; as shown Figure 5 As shown, the nth-stage GOA circuit unit 100 includes a control voltage terminal Qn, a stage output terminal Fn, and a drive output terminal Gn; wherein, Figure 2 In this diagram, Qn represents the control voltage terminal Qn of the nth-stage GOA circuit unit 100, Fn represents the stage transmission output terminal Fn of the nth-stage GOA circuit unit 100, Gn represents the drive output terminal Gn of the nth-stage GOA circuit unit 100, CKn represents the clock signal line of the nth-stage GOA circuit unit 100, Fn-i represents the stage transmission output terminal of the nith-stage GOA circuit unit 100, Gn-i represents the drive output terminal of the nith-stage GOA circuit unit 100, and Gn+i represents the drive output terminal of the (n+i)th-stage GOA circuit unit 100.

[0054] In this embodiment, the nth-stage GOA circuit unit 100 further includes: a storage capacitor C1, a pre-charge module 110, an output module 120, and a stage transmission module 130. The first terminal of the storage capacitor C1 is connected to the control voltage terminal Qn, and the second terminal of the storage capacitor C1 is connected to the drive output terminal Gn. The control terminal of the pre-charge module 110 is connected to the stage transmission output terminal of the nith-stage GOA circuit unit 100. The first terminal of the pre-charge module 110 is connected to the drive output terminal of the nith-stage GOA circuit unit 100, and the second terminal of the pre-charge module 110 is connected to the control voltage terminal Qn. It is used to pre-charge the voltage on the control voltage terminal Qn through the gate drive signal output by the nith-stage GOA circuit unit 100. The control terminal of the output module 120 is connected to the pre-charge module. The output terminal of 110 is connected, the first terminal of the output module 120 is connected to the clock signal line CKn, and the second terminal of the output module 120 is connected to the second terminal of the storage capacitor C1. It is used to output the gate drive signal under the action of the first target voltage on the control voltage terminal Qn and the clock signal output by the clock signal line CKn. The control terminal of the stage transmission module 130 is connected to the control voltage terminal Qn of the nth stage GOA circuit unit 100, the first terminal of the stage transmission module 130 is connected to the clock signal line CKn, and the second terminal of the stage transmission module 130 is connected to the precharge module 110 of the (n+i)th stage GOA circuit unit 100. It is used to output the stage transmission signal under the action of the first target voltage on the control voltage terminal Qn and the clock signal output by the clock signal line CKn.

[0055] It should be noted that the variable i in this embodiment can take any value from 1, 2, 3, 4, 5, etc. This application takes i=2 as an example; the output of the voltage control drive signal and the stage transmission signal on the control voltage terminal Qn in this embodiment belongs to an important node (commonly known as the Q point) in the GOA circuit unit 100. The drive signal output by the drive output terminal Gn of the (n-2)th stage GOA circuit unit 100 precharges the control voltage terminal Qn of the nth stage GOA circuit unit 100 and stores it in the storage capacitor C1. Before the clock signal of the nth stage GOA circuit unit 100 arrives, the control voltage terminal Qn is made to be at the first target voltage in advance; optionally, the first target voltage is high level, which can control the conduction of the output module 120 and the stage transmission module 130, and output the gate drive signal and the stage transmission signal at the same time.

[0056] In this embodiment, the nth-level GOA circuit unit 100 further includes a pull-down module 140. The control terminal of the pull-down module 140 is connected to the drive output terminal of the (n+j)th-level GOA circuit unit. The first output terminal of the pull-down module 140 is connected to the control voltage terminal Qn of the nth-level GOA circuit unit. The second output terminal of the pull-down module 140 is connected to the drive output terminal Gn of the nth-level GOA circuit unit. The connection terminal of the pull-down module 140 is connected to the cathode signal line and is used to discharge the voltage on the control voltage terminal and the drive output terminal to the second target voltage.

[0057] It should be noted that the voltage attributes of the first target voltage and the second target voltage in this embodiment are opposite, that is, the first target voltage is high level and the second target voltage is low level; wherein, the first target voltage can control the output module 120 to output a drive signal, while the second target voltage causes the output module 120 to stop outputting a drive signal; therefore, the function of the pull-down module 140 is to pull down the potential on the control voltage terminal and the drive output terminal to the second target voltage through the drive signal output by the next j-stage GOA circuit unit after the current stage drive signal output is completed, so as to ensure that the current stage output module 120 and the cascade module 130 are completely turned off.

[0058] In this embodiment, the nth-level GOA circuit unit 100 further includes a reset module 150. The control terminal of the reset module 150 is connected to the reset signal line STV, and the output terminal of the reset module 150 is connected to the control voltage terminal of the nth-level GOA circuit unit. This is used to reset the voltage on the control voltage terminal under the action of the reset signal. Specifically, the reset signal line in this embodiment can be the port that outputs the frame start signal. That is, the control terminal of the reset module 150 of each GOA circuit unit 110 is connected to the same reset signal line STV. Before charging the new frame of data, the voltage on all control voltage terminals Qn is reset to a low level through the frame start signal to prevent residual charge from the previous frame from affecting the charging of the next frame of data.

[0059] In one embodiment, the nth-level GOA circuit unit 100 further includes: a first pull-down control module and a second pull-down control module. The control terminal of the first pull-down control module is connected to a first pull-down signal line, and the output terminal of the first pull-down control module is connected to the control voltage terminal, the stage transmission output terminal, and the drive output terminal of the nth-level GOA circuit unit, respectively, for maintaining the second target voltage on the control voltage terminal, the stage transmission output terminal, and the drive output terminal. The control terminal of the second pull-down control module is connected to a second pull-down signal line, and the output terminal of the second pull-down control module is connected to the control voltage terminal, the stage transmission output terminal, and the drive output terminal of the nth-level GOA circuit unit, respectively, for maintaining the second target voltage on the control voltage terminal, the stage transmission output terminal, and the drive output terminal.

[0060] It should be noted that since the pull-down module 140 of this stage is controlled by the stage transmission signal of the next j stage, when the next j stage does not output the stage transmission signal, it is impossible to maintain the low potential of the control voltage terminal through the pull-down module 140. Therefore, in this embodiment, the control voltage terminal is always kept at a low potential, i.e., the second target voltage, through the first pull-down control module or the second pull-down control module. In addition, the first pull-down control module and the second pull-down control module in this embodiment are redundant designs. In order to prevent transistor aging, the two pull-down control modules are alternately turned on between different frames. That is to say, in the current frame, the first pull-down control module is controlled to be in the working state by the first pull-down signal, and in the next frame, the second pull-down control module is controlled to be in the working state by the second pull-down signal.

[0061] Figure 6 The diagram shown is a circuit schematic of a GOA circuit unit provided in an embodiment of this application; as follows: Figure 6 As shown, the pre-charge module 110 includes: a first transistor T1, the gate of which is connected to the stage transmission output terminal of the ni-th stage GOA circuit unit 100, the first terminal of which is connected to the drive output terminal of the ni-th stage GOA circuit unit 100, and the second terminal of which is connected to the control voltage terminal Qn. Specifically, the first transistor T1 is an N-type MOS transistor, which is turned on when a high level is input to the control terminal; wherein, the first terminal of the first transistor T1 can be the source, and the second terminal of the first transistor T1 can be the drain; in addition, the first terminal of the first transistor T1 can also be the drain, and the second terminal of the first transistor T1 can also be the source; this application does not make specific limitations, and the same applies to other transistors below, which will not be described in detail later. When the stage transmission output terminal of the ni-th stage GOA circuit unit 100 outputs a high level, the first transistor T1 is turned on, and the gate drive signal output by the drive output terminal of the ni-th stage GOA circuit unit 100 charges the storage capacitor C1 connected to the control voltage terminal Qn.

[0062] In one embodiment, such as Figure 6 As shown, the output module 120 includes a second transistor T2, the gate of which is connected to the second terminal of the first transistor T1, the first terminal of which is connected to the clock signal line CKn, and the second terminal of which serves as the drive output terminal Gn. Specifically, in this embodiment, the second transistor T2 is an N-type MOS transistor; when the control voltage terminal Qn is high, the second transistor T2 is turned on, and the clock signal is output as a drive signal to the scan line in the panel through the drive output terminal Gn.

[0063] In one embodiment, such as Figure 6As shown, the stage transmission module 130 includes: a third transistor T3, the gate of which is connected to the control voltage terminal Qn, the first terminal of which is connected to the clock signal line CKn, and the second terminal of which serves as the stage transmission output terminal Fn. Specifically, in this embodiment, the third transistor T3 is an N-type MOS transistor; when the control voltage terminal Qn is high, the third transistor T3 is turned on, and the clock signal is output to other stages as a stage transmission signal through the stage transmission output terminal Fn.

[0064] In one embodiment, such as Figure 6 As shown, the pull-down module 140 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is connected to the stage output terminal of the (n+j)th stage GOA circuit unit 110. The first terminal of the fifth transistor T5 is connected to the control voltage terminal Qn of the nth stage GOA circuit unit 110, and the second terminal of the fifth transistor T5 is connected to the cathode signal line VSS. The gate of the sixth transistor T6 is connected to the gate of the fifth transistor T5. The first terminal of the sixth transistor T6 is connected to the drive output terminal Gn of the nth stage GOA circuit unit 110, and the second terminal of the sixth transistor T6 is connected to the cathode signal line VSS.

[0065] It should be noted that in this embodiment, the fifth transistor T5 and the sixth transistor T6 are both N-type MOS transistors; when the stage transmission output terminal of the (n+j)th stage GOA circuit unit 110 outputs a high level, both the fifth transistor T5 and the sixth transistor T6 are turned on, pulling down the voltage of the control voltage terminal Qn and the drive output terminal Gn to the second target voltage, respectively.

[0066] In one embodiment, such as Figure 6 As shown, the reset module 150 includes a fourth transistor T4, the gate of which is connected to the reset signal line STV, the first terminal of which is connected to the control voltage terminal Qn of the nth stage GOA circuit unit 110, and the second terminal of which is connected to the cathode signal line VSS. Specifically, in this embodiment, the fourth transistor T4 is an N-type MOS transistor, and the cathode signal line VSS outputs a second target voltage. When the reset signal output by the reset signal line STV is high, the fourth transistor T4 is turned on, thereby resetting the voltage on the control voltage terminal Qn to the second target voltage. In addition, in this embodiment, the fourth transistor T4 is used as the reset transistor in the GOA circuit unit.

[0067] In one embodiment, such as Figure 6As shown, the first pull-down control module 160 and the second pull-down control module 170 include: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The gate of the seventh transistor T7 is connected to the control voltage terminal, and the second terminal of the seventh transistor T7 is connected to the cathode signal line. The gate of the eighth transistor T8 is connected to the gate of the seventh transistor T7, and the second terminal of the eighth transistor T8 is connected to the cathode signal line. The gate of the ninth transistor T9 is connected to either the first pull-down signal line or the second pull-down signal line. The first terminal of the ninth transistor T9 is connected to its gate, and the second terminal of the ninth transistor T9 is connected to the first terminal of the seventh transistor T7. The gate of the tenth transistor T10 is connected to the second terminal of the ninth transistor T9. The tenth transistor T10 has its first terminal connected to the first terminal of the ninth transistor T9, and its second terminal connected to the first terminal of the eighth transistor T8. The eleventh transistor T11 has its gate connected to the second terminal of the tenth transistor T10, its first terminal connected to the control voltage terminal, and its second terminal connected to the cathode signal line. The twelfth transistor T12 has its gate connected to the gate of the eleventh transistor T11, its first terminal connected to the drive output terminal, and its second terminal connected to the cathode signal line. The thirteenth transistor T13 has its gate connected to the gate of the twelfth transistor T12, its first terminal connected to the stage transmission output terminal, and its second terminal connected to the cathode signal line.

[0068] It should be noted that in this embodiment, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all N-type MOSFETs. Since the circuit designs of the first pull-down control module 160 and the second pull-down control module 170 are completely identical, their working principles are also the same. In this explanation, the first pull-down control module 160 will be used as an example to illustrate its working principle:

[0069] (1) When the control voltage terminal Qn is high, both the seventh transistor T7 and the eighth transistor T8 are turned on, thus turning on the control voltage terminal Qn. Figure 6 The voltage at node Pn is pulled low, which turns off the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13. Even if the first pull-down signal line LC1 continues to output a high level, it cannot pull down the voltage at the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn. Therefore, by controlling the seventh transistor T7 and the eighth transistor T8 through the control voltage terminal Qn, the high level at the control voltage terminal Qn can be maintained.

[0070] (2) When the control voltage terminal Qn is low (that is, when the current stage completes the output of the drive signal), the seventh transistor T7 and the eighth transistor T8 are turned off, and the voltage on node Pn is controlled by the ninth transistor T9 and the tenth transistor T10. The first pull-down signal line LC1 continuously outputs a high level in the current frame to turn on the ninth transistor T9 and the tenth transistor T10, pull the voltage on node Pn to a high level, and turn on the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13. Therefore, the voltage on the stage transmission output terminal Fn is continuously pulled down by the thirteenth transistor T13, the voltage on the control voltage terminal Qn is continuously pulled down by the eleventh transistor T11, and the voltage on the drive output terminal Gn is continuously pulled down by the twelfth transistor T12, thereby maintaining the voltage on the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn as the second target voltage.

[0071] It should also be noted that Figure 6 The physical design diagram corresponding to the GOA circuit unit shown is as follows: Figure 7 As shown; in addition, Figure 7 Only one GOA circuit unit is shown, along with the design relationship between the reset signal and the cathode signal line. The layout design of other GOA circuit units is almost the same, so it will not be described again here.

[0072] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes the gate driving circuit in the above embodiment, wherein the drive output terminal of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0073] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0074] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0075] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: N cascaded GOA circuit units, wherein each GOA circuit unit includes at least a reset transistor; A reset signal line is disposed on any side near the GOA circuit unit. The reset signal line is electrically connected to the gate of the reset transistor and is located on the first metal layer with the gate of the reset transistor. The reset signal line is used to provide a reset signal to the reset transistor. The cathode signal line is located on the same side as the reset signal line and is disposed away from the GOA circuit unit; the cathode signal line is electrically connected to the drain or source of the reset transistor and is located on the second metal layer with the source or drain of the reset transistor; the cathode signal line is used to provide a low voltage signal to the reset transistor; Multiple clock signal lines are disposed between the reset signal line and the cathode signal line and are electrically connected to the clock signal line of the GOA circuit unit; the clock signal lines provide clock signals to the GOA circuit unit, causing the GOA circuit unit to output corresponding gate drive signals.

2. The gate driving circuit according to claim 1, characterized in that, The nth-level GOA circuit unit includes a control voltage terminal, a stage transmission output terminal, and a drive output terminal. The nth-level GOA circuit unit also includes: A storage capacitor, wherein a first terminal of the storage capacitor is connected to the control voltage terminal, and a second terminal of the storage capacitor is connected to the drive output terminal; A pre-charge module, wherein the control terminal of the pre-charge module is connected to the stage output terminal of the ni-th stage GOA circuit unit, the first terminal of the pre-charge module is connected to the drive output terminal of the ni-th stage GOA circuit unit, and the second terminal of the pre-charge module is connected to the control voltage terminal, and is used to pre-charge the voltage on the control voltage terminal by the gate drive signal output by the ni-th stage GOA circuit unit. An output module, wherein the control terminal of the output module is connected to the output terminal of the precharge module, the first terminal of the output module is connected to the clock signal line, and the second terminal of the output module is connected to the second terminal of the storage capacitor, and is used to output a gate drive signal under the action of the first target voltage on the control voltage terminal and the clock signal output by the clock signal line; The stage transmission module has its control terminal connected to the control voltage terminal of the nth stage GOA circuit unit, its first terminal connected to the clock signal line, and its second terminal connected to the pre-charge module of the (n+i)th stage GOA circuit unit. It is used to output a stage transmission signal under the action of the first target voltage on the control voltage terminal and the clock signal output by the clock signal line. A pull-down module, wherein the control terminal of the pull-down module is connected to the drive output terminal of the (n+j)th level GOA circuit unit, the first output terminal of the pull-down module is connected to the control voltage terminal of the nth level GOA circuit unit, and the second output terminal of the pull-down module is connected to the drive output terminal of the nth level GOA circuit unit, for discharging the voltage on the control voltage terminal and the drive output terminal to the second target voltage; A reset module, wherein the control terminal of the reset module is connected to the reset signal line, and the output terminal of the reset module is connected to the control voltage terminal of the nth stage GOA circuit unit, for resetting the voltage on the control voltage terminal under the action of the reset signal.

3. The gate driving circuit according to claim 2, characterized in that, The nth-level GOA circuit unit also includes: The first pull-down control module has its control terminal connected to the first pull-down signal line, and its output terminal connected to the control voltage terminal, stage transmission output terminal, and drive output terminal of the nth stage GOA circuit unit, respectively, for maintaining the second target voltage on the control voltage terminal, stage transmission output terminal, and drive output terminal. The second pull-down control module has its control terminal connected to the second pull-down signal line, and its output terminal connected to the control voltage terminal, stage transmission output terminal, and drive output terminal of the nth stage GOA circuit unit, respectively, for maintaining the second target voltage on the control voltage terminal, stage transmission output terminal, and drive output terminal.

4. The gate driving circuit according to claim 2, characterized in that, The pre-charge module includes: The first transistor has its gate connected to the stage output terminal of the ni-th stage GOA circuit unit, its first terminal connected to the drive output terminal of the ni-th stage GOA circuit unit, and its second terminal connected to the control voltage terminal.

5. The gate driving circuit according to claim 2, characterized in that, The output module includes: The second transistor has its gate connected to the control voltage terminal, its first terminal connected to the clock signal line, and its second terminal serving as the drive output terminal.

6. The gate driving circuit according to claim 2, characterized in that, The stage transmission module includes: a third transistor, the gate of which is connected to the control voltage terminal, the first terminal of which is connected to the clock signal line, and the second terminal of which serves as the stage transmission output terminal; The reset module includes: a fourth transistor, the gate of which is connected to a reset signal line, a first terminal of which is connected to a control voltage terminal, and a second terminal of which is connected to a cathode signal line; wherein, the fourth transistor is used as the reset transistor.

7. The gate driving circuit according to claim 2, characterized in that, The drop-down module includes: The fifth transistor has its gate connected to the drive output terminal of the (n+j)th stage GOA circuit unit, its first terminal connected to the control voltage terminal, and its second terminal connected to the cathode signal line. The sixth transistor has its gate connected to the gate of the fifth transistor, its first terminal connected to the drive output terminal, and its second terminal connected to the cathode signal line.

8. The gate driving circuit according to claim 3, characterized in that, The first drop-down control module and the second drop-down control module include: The seventh transistor has its gate connected to the control voltage terminal and its second terminal connected to the cathode signal line. The eighth transistor has its gate connected to the gate of the seventh transistor, and its second terminal is connected to the cathode signal line. The ninth transistor has its gate connected to either a first pull-down signal line or a second pull-down signal line, its first terminal connected to its gate, and its second terminal connected to the first terminal of the seventh transistor. The tenth transistor has its gate connected to the second terminal of the ninth transistor, its first terminal connected to the first terminal of the ninth transistor, and its second terminal connected to the first terminal of the eighth transistor. The eleventh transistor has its gate connected to the second terminal of the tenth transistor, its first terminal connected to the control voltage terminal, and its second terminal connected to the cathode signal line. The twelfth transistor has its gate connected to the gate of the eleventh transistor, its first terminal connected to the drive output terminal, and its second terminal connected to the cathode signal line. The thirteenth transistor has its gate connected to the gate of the twelfth transistor, its first terminal connected to the stage output terminal, and its second terminal connected to the cathode signal line.

9. A method for fabricating a gate driving circuit based on any one of claims 1-8, characterized in that, The method for fabricating the gate drive circuit includes: A first metal layer is fabricated on an array substrate, the first metal layer including the gate of a reset transistor and a reset signal line; A silicon nitrogen compound is coated on the first metal layer to form a gate insulating layer; An amorphous silicon layer and an N-type conductive layer are sequentially fabricated on the gate insulating layer; A second metal layer is fabricated on the N-type conductive layer, the second metal layer including the source, drain and cathode signal lines of the reset transistor; Silicon nitride is coated on the second metal layer to form a source / drain protection layer; A via is formed between the first metal layer and the second metal layer; A metal oxide layer is deposited on the source and drain protection layer to form an ITO layer, thereby preparing the gate drive circuit.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1 to 8, wherein the driving output terminal of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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