Memory system
By introducing configuration tables and memory controller designs into the memory system and selecting appropriate configuration information according to different startup stages, the problem that existing memory systems cannot adjust parameters during startup is solved, and more efficient startup process and resource management are achieved.
Patent Information
- Application Number
- CN202411126780.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-29
- Filing Date
- 2024-08-16
- Publication Date
- 2025-05-30
AI Technical Summary
Existing memory systems cannot adjust parameters appropriately according to different startup stages at startup, resulting in inefficiency and waste of resources.
A memory system is designed that includes nonvolatile memory and memory controllers to control the operation of the memory by selecting appropriate configuration information at different startup stages by the configuration table.
It realizes that the parameters are adjusted as needed at different startup stages, thereby improving the system startup efficiency and reducing current consumption and startup time.
Smart Images
Figure CN120072001A_ABST
Abstract
Description
[0001] [Related Application]
[0002] This application claims priority based on Japanese Patent Application No. 2023-201532 (filing date: November 29, 2023). This application incorporates all the contents of the base application by reference thereto. Technical Field
[0003] Embodiments of the present invention relate to a memory system. Background Art
[0004] An information processing system including a memory system and a host connected to the memory system is known. The memory system includes a NAND (Not AND) memory as a semiconductor storage device and a memory controller that controls the semiconductor storage device. In addition, the information processing system starts the BIOS (Basic Input / Output System), starts the boot loader, and then starts the OS (Operating System). Summary of the Invention
[0005] Provided is a memory system that operates with parameters suitable for startup at startup.
[0006] To achieve the above problems, a memory system according to an embodiment includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a plurality of profile information. Each of the plurality of profile information includes parameters. When the host starts a startup sequence, the memory controller controls the non-volatile memory according to a first profile information among the plurality of profile information during a first period of the startup sequence. The first profile information includes parameters to be referred to when controlling the non-volatile memory during the first period. Brief Description of the Drawings
[0007] Figure 1 It is a block diagram showing a configuration example of an information processing system including the memory system according to the embodiment.
[0008] Figure 2 It is a diagram showing an example of a configuration table used in the memory system according to the embodiment.
[0009] Figure 3 It is a block diagram for explaining the configuration when applying the configuration information of application configuration number 0, configuration number 1, and configuration number N of the information processing system including the memory system according to the embodiment.
[0010] Figure 4It is a diagram showing the processing sequence during the configuration table setting process of an information processing system including a memory system according to an embodiment.
[0011] Figure 5 It is a diagram showing the processing sequence during the boot processing A of an information processing system including a memory system according to an embodiment.
[0012] Figure 6 It is a diagram showing the processing sequence during the boot processing B of an information processing system including a memory system according to an embodiment.
[0013] Figure 7 It is a diagram showing the processing sequence during the post-boot processing of an information processing system including a memory system according to an embodiment. Detailed Embodiments
[0014] Figure 1 It is a block diagram showing a configuration example of an information processing system 1 including a memory system according to an embodiment of the present invention. The information processing system 1 includes a host element 2 (hereinafter referred to as the host 2) and a memory system 3.
[0015] The host 2 is an information processing device external to the memory system 3. The host 2 can be a personal computer, a server, a mobile phone, a camera device, or can also be a mobile terminal such as a tablet or a smart phone, or can also be an in-vehicle terminal such as a car navigation system.
[0016] The memory system 3 is, for example, a storage element configured to read data from a non-volatile memory. The memory system can be implemented as an SSD (Solid State Drive), for example. Alternatively, the memory system can also be implemented as a hard disk drive (HDD) or a memory card. Here, an example where the memory system 3 is connected to the host 2 via a cable or a network is described, but the memory system 3 can also be built in the host 2.
[0017] The memory system 3 includes a memory controller 4 and a NAND memory 5. The NAND memory 5 is an example of a semiconductor storage device. The semiconductor storage device is an example of a non-volatile memory that stores data non-volatilely. The NAND memory 5 is, for example, a NAND type flash memory. The NAND type flash memory includes a plurality of blocks. Each of the plurality of blocks includes a plurality of memory cells. A block is an erasure unit of data. A block includes a plurality of pages. A page is a unit for reading and writing data.
[0018] The memory controller 4 can also be implemented by a circuit such as a system-on-a-chip (SoC). The memory controller 4 is electrically connected to the NAND memory 5 via a NAND interface (I / F) 13.
[0019] The memory CPU 12 is a processor configured to control a host interface (I / F) 11 and a NAND I / F 13. The memory CPU 12 loads a control program from the NAND memory 5 or a ROM (Read Only Memory) not shown into a DRAM (Dynamic Random Access Memory) not shown, and then performs various processes by executing the control program. In addition, the control program may also be loaded onto an SRAM (Static Random Access Memory) not shown within the memory controller 4. The memory CPU 12 can execute command processing and the like for processing various commands from the host 2. The operation of the memory CPU 12 is controlled by the control program executed by the memory CPU 12. In addition, it may also be executed by dedicated hardware within the controller 4.
[0020] The NAND I / F 13 is, for example, based on a Toggle NAND flash interface or an Open NAND Flash Interface (ONFI). The NAND I / F 13 is respectively connected to a plurality of NAND memory chips within the NAND memory 5 via a plurality of channels (Ch).
[0021] The host I / F 11 is a host interface circuit configured to communicate with the host 2. The host I / F 11 can use, for example, a SATA interface (Serial ATA), a SAS interface (Serial Attached SCSI), PCI Express (PCIe) (registered trademark), Ethernet (registered trademark), etc.
[0022] The host I / F 11 receives various commands from the host 2. In the SATA interface, ATA commands defined by the ATA standard are used. In the SAS interface, SCSI commands defined by the SCSI standard are used. In PCIe (registered trademark) and Ethernet (registered trademark), NVMe commands defined by the NVM Express (NVMe) (registered trademark) standard are used.
[0023] The NAND memory 5 includes a stored boot area 20 and a user area 21. The boot area 20 includes a boot loader 22.
[0024] In the user area 21, for example, the OS 23 and user data are saved.
[0025] The OS 23 is a program for providing basic functions of the host 2. Thus, an interface that abstracts various hardware can be provided to application programs, or when multiple application programs are utilized simultaneously, resources can be managed to perform processing efficiently and independently.
[0026] The boot loader 22 is a program that is read out to the host RAM 32 through the BIOS 33 and loads specific programs such as the OS 23.
[0027] The host 2 includes a host CPU 30, a host ROM 31, and a host RAM 32. The host ROM 31 and the host RAM 32 may also be inside the host CPU 30.
[0028] The host CPU 30 is a processor provided to control the overall operation of the host 2, and starts the BIOS 33, the boot loader 22, and the OS 23.
[0029] The host ROM 31 has data required for program startup, etc. The host ROM 31 stores the BIOS 33. The BIOS 33 may also be a program recorded when manufactured as part of EFI (Extensible Firmware Interface) / UEFI (Unified Extensible Firmware Interface). The BIOS 33 is read out to the host RAM 32 through the host CPU 30 as needed and started by the host CPU.
[0030] The host RAM 32 temporarily stores programs and data and functions as a working memory for the host CPU 30.
[0031] The memory system 3 is configured to hold the configuration table 24 in the boot area 20 within the NAND memory 5.
[0032] The configuration table 24 has a plurality of configuration information. The plurality of configuration information are respectively information for setting parameters for items related to the processing of the memory system 3. There are a plurality of items related to the processing of the memory system 3, and one parameter is set for each item.
[0033] The configuration table 24 includes a plurality of configuration numbers. The plurality of configuration numbers respectively correspond to the configuration information. The memory controller 4 makes the configuration information correspond to the configuration numbers and stores them in the configuration table 24.
[0034] Figure 2 It is a diagram showing an example of the configuration table 24 held by the memory system 3.
[0035] The plurality of configuration information included in the configuration table 24 each have parameters for setting items related to the processing of the memory system 3. In Figure 2 It is exemplified that the items related to the processing of the memory system 3 are the access area, the access type, and the speed of the host I / F 11. In Figure 2For example, the configuration information of configuration number 0 indicates that the parameter of the item of access area is "boot area only", the parameter of the item of access type is "read only", and the parameter of the item of host I / F 11 is "minimum speed". Other items that may be included in the items related to the processing of the memory system 3 include the operating clock of the circuit in the memory system 3, the circuit selected at startup, the number of CPU cores used by the memory controller 4, and the like.
[0036] In the information processing system 1, the process from when the power of the information processing system 1 is turned on to when the application program etc. can be executed is called a boot sequence. The boot sequence can be mainly classified into three processes. The three processes are a boot process A, a boot process B, and a post-boot process, and are executed in the order of the boot process A, the boot process B, and the post-boot process. The period during which the boot process A is executed is called a boot phase A. The period during which the boot process B is executed is called a boot phase B. The period during which the post-boot process is executed is called a post-boot phase. Here, the boot phase A is also referred to as the first period. The boot phase B is also referred to as the second period. The post-boot phase is also referred to as the third period.
[0037] In boot process A, the host CPU 30 starts the BIOS 33, and then the host CPU 30 initializes the memory system 3. Here, the so-called initialization of the memory system 3 means that the host CPU 30 sends a reset signal to the memory controller 4. In the boot sequence of the information processing system 1, when the memory controller 4 receives the reset signal, it erases the parameters set for each item related to the processing of the memory system 3. Then, the memory controller 4 selects the configuration number corresponding to the boot process A. The memory controller 4 sets the configuration information of the selected configuration number for each item related to the processing of the memory system 3. Here, the so-called setting of the configuration information of the configuration number means setting a plurality of parameters corresponding to the selected configuration information for each item related to the processing of the memory system 3. Then, the host CPU 30 reads out the boot loader 22 and moves to the boot process B.
[0038] In the boot process B, the host CPU 30 starts the boot loader 22 and then initializes the memory system 3. Then, the memory controller 4 selects the configuration number corresponding to the boot process B. The memory controller 4 sets the configuration information of the selected configuration number to each item related to the process of the memory system 3. Then, the host CPU 30 reads the OS 23 and moves to the post-boot process.
[0039] In the post-boot process, after the host CPU 30 starts the OS 23, it initializes the memory system 3. The memory controller 4 selects a configuration number corresponding to the post-boot process. The memory controller 4 sets the configuration information of the selected configuration number for each item related to the processing of the memory system 3. Then, the post-boot process ends. Parameters required to execute the application program are set in the post-boot process.
[0040] Figure 3 It is a block diagram showing the configuration when the information processing system including the memory system 3 executes according to the configuration information of each configuration number. Specifically, it shows the block diagram of the memory system 3 when the memory system 3 executes according to the configuration information corresponding to the three configuration numbers 0, configuration number 1, and configuration number N exemplified in Figure 2 The user area 21 has N areas of user area 21-1 to user area 21-N. In Figure 3 It shows the case where the OS 23 is included in the user area 21-1.
[0041] When the memory system 3 executes according to the configuration information of configuration number 0, the memory controller 4 can access only the boot area 20 of the memory system 3. When the memory system 3 executes according to the configuration information of configuration number 1, the memory controller 4 can access the boot area 20 and the user area 21-1 of the memory system 3. When the memory system 3 executes according to the configuration information of configuration number N, the memory controller 4 can access the boot area 20 and all user areas 21 of the memory system 3.
[0042] In the boot process A, the host 2 requests the memory system 3 to read the boot loader 22 in the boot area 20. That is, in the boot process A, the memory controller 4 only needs to be able to access the boot area 20. Therefore, in the boot stage A, the memory system 3 only needs to execute according to the configuration information of configuration number 0.
[0043] In the boot process B, the host 2 requests the memory system 3 to read the OS 23 in the user area 21. That is, in the boot process B, the memory controller 4 only needs to be able to access the user area 21-1. Therefore, in the boot stage B, the memory system 3 only needs to execute according to the configuration information of configuration number 1.
[0044] When the post-boot process ends and the information processing system 1 executes the application program, the host 2 may request to read and write to any area in the user area 21. Therefore, in the post-boot stage, the memory system 3 only needs to execute according to the configuration information of configuration number N.
[0045] An information processing system including a memory system without a configuration table 24 sets fixed parameters for items related to the processing of the memory system and runs. Here, the fixed parameters refer to the parameters set for items related to the processing of the memory system in the post-boot phase of the memory system 3. Therefore, even immediately after the BIOS is started, the memory controller of the information processing system including the memory system without a configuration table can access any area within the user area. The information processing system including the memory system without a configuration table can request reading and writing to any area within the user area. In addition, the memory system without a configuration table can communicate with the host at the highest speed. That is, it is considered that the information processing system including the memory system without a configuration table operates with performance beyond necessity, resulting in excessive power consumption and an increase in startup time.
[0046] According to the first embodiment, at the startup sequence of the memory system 3, by having the memory system 3 hold the configuration table 24, it can operate with performance suitable for each process of the startup sequence. Therefore, compared with the information processing system without a configuration table, it is possible to expect the effects of reducing the consumption current and shortening the startup time of the memory system 3.
[0047] Figure 4 FIG. is an example of a process of setting configuration information in the configuration table 24 of the information processing system 1 including the memory system 3. In Figure 4 it is described that when the supplier of the information processing system 1 that purchased the memory system 3 first starts the information processing system 1, the process of setting the configuration information required for each process of the startup sequence in the configuration table 24. In addition, the Figure 4 series of processes is called the configuration table setting process.
[0048] The configuration table setting process is not limited to being performed at the first startup of the information processing system 1.
[0049] The memory system 3 has a flag in the NAND memory 5. This flag designates the configuration number selected by the memory system 3. In addition, the configuration table 24 has configuration information corresponding to the configuration number S. At the time when the supplier of the information processing system 1 that has purchased the memory system 3 purchases the memory system 3, the memory system 3 has a flag designating the configuration number S. Therefore, at the first startup of the information processing system 1, the memory system 3 executes according to the configuration information of the configuration number S.
[0050] Hereinafter, the Figure 4 flowchart will be described.
[0051] When the power of the information processing system 1 is turned on, the host CPU 30 reads the BIOS 33 from the host ROM 31 (step S401). The host CPU 30 starts the BIOS 33 (step S402).
[0052] The host CPU 30 sends an initialization command to the memory controller 4. (Step S403). When receiving the initialization command, the memory controller 4 initializes the memory system 3 (step S404). The memory controller 4 confirms the configuration number specified by the flag. The memory controller 4 sets the configuration information of the specified configuration number (in this case, the configuration number S) for each item related to the processing of the memory system 3 (step S405). When the setting of the configuration information is completed, the memory controller 4 sends a configuration information setting completion command to the host 2 (step S406).
[0053] The host CPU 30 sends a configuration table setting command to the memory controller 4 (step S407). The configuration information of at least three configuration numbers K, configuration number M, and configuration number N is included in this command. The configuration number of the configuration information executed in the boot process A is set to K, the configuration number of the configuration information executed in the boot process B is set to M, and the configuration number of the configuration information executed in the post-boot process is set to N. S, K, M, and N are distinct natural numbers.
[0054] The memory controller 4 sets at least three pieces of configuration information in the configuration table 24 of the memory system 3 (step S408). When the setting is completed, the memory controller 4 sends a configuration table setting completion command to the host 2 (step S409).
[0055] The host 2 sends a command to determine that the configuration number specified by the flag is K to the memory controller 4 (step S410). The memory controller 4 changes the configuration number specified by the flag to K (step S411). The memory controller 4 sends a configuration number setting completion command to the host 2 (step S412), ending the configuration table setting process of the information processing system 1.
[0056] The transition of the configuration number specified by the flag in the configuration table setting process of the information processing system 1 is described. At the start of the configuration table setting process, the configuration number specified by the flag is S. Through the process of changing the configuration number specified by the flag to K (step S411), the configuration number specified by the flag is changed from S to K.
[0057] The transition of the configuration numbers of the configuration information referred to by the memory system 3 in the configuration table setting process of the information processing system 1 is described. The memory controller 4 sets the configuration information of the configuration number S for each item related to the processing of the memory system 3 (step S405). In the subsequent processing of the memory system 3, it is executed according to the configuration information of the configuration number S.
[0058] When the configuration table setting process of the information processing system 1 ends and then the information processing system 1 is started, the memory system 3 starts the startup sequence from the boot process A. When the boot process A starts, the configuration number specified by the flag is K. Therefore, the memory system 3 executes according to the configuration information of the configuration number K in the boot process A.
[0059] In Figure 4 It shows the processing when the supplier of the information processing system 1 that purchased the memory system 3 sets the configuration information of the configuration numbers K, M, and N in the configuration table 24 and sets the configuration number specified by the flag to K. On the other hand, before the supplier of the information processing system 1 purchases the memory system 3, the configuration table 24 can also have the configuration information of the configuration numbers K, M, and N. In this case, at the time when the supplier of the information processing system 1 purchases the memory system 3, the memory system 3 can also be configured to have a flag specifying the configuration number K. When the configuration table 24 has the configuration information of the configuration numbers K, M, and N and the memory system 3 holds a flag specifying the configuration number K, the information processing system 1 may not perform the configuration table setting process.
[0060] Figure 5 It is a diagram showing an example of the boot process A of the information processing system 1. It is assumed that the configuration table 24 has the configuration information of the configuration numbers K, M, and N and the memory system 3 holds a flag specifying the configuration number K. When the power of the information processing system 1 is turned on, the boot process A of the information processing system 1 starts. In Figure 5 It shows an example of the boot process A. When the boot process A is completed, the following Figure 6 boot process B and the following Figure 7 post-boot process are continued to complete the startup sequence.
[0061] Next, the Figure 5 flowchart is explained.
[0062] When the power of the information processing system 1 is turned on, the host CPU 30 reads the BIOS 33 from the host ROM 31 (step S501). The host CPU 30 starts the BIOS 33 (step S502).
[0063] The host CPU 30 sends an initialization command to the memory controller 4. (Step S503). When receiving the initialization command, the memory controller 4 initializes the memory system 3 (Step S504). The memory controller 4 confirms the configuration number specified by the flag. The memory controller 4 sets the configuration information of the specified configuration number (in this case, configuration number K) for each item related to the processing of the memory system 3 (Step S505). When the setting of the configuration information is completed, the memory controller 4 sends a configuration information setting completion command to the host 2 (Step S506).
[0064] The host 2 sends a command determining the configuration number specified by the flag as M to the memory controller 4 (Step S507). The memory controller 4 changes the configuration number specified by the flag to M (Step S508). Then, the memory controller 4 sends a configuration number setting completion command to the host 2 (Step S509).
[0065] The host CPU 30 sends a command requesting to read the boot loader 22 to the memory controller 4 (Step S510). The memory controller 4 receives the command and reads out the boot loader 22 (Step S511). The memory controller 4 sends the read boot loader 22 to the host 2 (Step S512), and the host 2 receives the boot loader 22, and the boot process A ends.
[0066] Describe the transition of the configuration number specified by the flag in the boot process A of the information processing system 1. When the boot process A starts, the configuration number specified by the flag is K. By changing the configuration number specified by the flag to M (Step S508), the configuration number specified by the flag is changed from K to M.
[0067] Describe the transition of the configuration number of the configuration information referred to by the memory system 3 in the boot process A of the information processing system 1. It is initialized by performing the initialization process of the memory system 3 (Step S504). The memory controller 4 sets the configuration information of configuration number K for each item related to the processing of the memory system 3 (Step S505). In the subsequent processing of the memory system 3, it is executed according to the configuration information of configuration number K.
[0068] When the boot process A ends, the information processing system 1 starts the boot process B. When the boot process B starts, the configuration number specified by the flag is M. Therefore, the memory system 3 is executed according to the configuration information of configuration number M in the boot process B.
[0069] In addition, regarding the step (S510) in which the host CPU 30 sends a command to the memory controller 4 to request reading of the boot loader 22, it can be performed at any time as long as it is after the step (S506) in which the memory controller 4 sets the configuration information setting completion command for the host 2 and during the boot process A.
[0070] Figure 6 FIG. is an example showing the boot process B of the information processing system 1. Following Figure 5 the boot process A of Figure 6 is the boot process B.
[0071] Next, the Figure 6 flowchart will be described.
[0072] The host CPU 30 starts the boot loader 22 (step S601).
[0073] The host CPU 30 sends an initialization command to the memory controller 4 (step S602). When the memory controller 4 receives the initialization command, it initializes the memory system 3 (step S603). The memory controller 4 confirms the configuration number specified by the flag. The memory controller 4 sets the configuration information of the specified configuration number (in this case, the configuration number M) for each item related to the processing of the memory system 3 (step S604). When the setting of the configuration information is completed, the memory controller 4 sends a configuration information setting completion command to the host 2 (step S605).
[0074] The host 2 sends a command to determine the configuration number specified by the flag as N to the memory controller 4 (step S606). The memory controller 4 changes the configuration number specified by the flag to N (step S607). Then, the memory controller 4 sends a configuration number setting completion command to the host 2 (step S608).
[0075] The host CPU 30 sends a command to request reading of the OS 23 to the memory controller 4 (step S609). The memory controller 4 receives the command and reads out the OS 23 (step S610). The memory controller 4 sends the OS 23 to the host 2 (step S611), and the host 2 receives the OS 23, and the boot process B ends.
[0076] The transition of the configuration number specified by the flag in the boot process B of the information processing system 1 will be described. At the start of the boot process B, the configuration number specified by the flag is M. By the process of changing the configuration number specified by the flag to N (step S607), the configuration number specified by the flag is changed from M to N.
[0077] The transition of the configuration numbers of the configuration information referred to by the memory system 3 in the boot process B of the information processing system 1 will be described. At the start of the boot process B, the memory system 3 executes according to the configuration information with the configuration number K. It is initialized by performing the initialization process of the memory system 3 (step S603). The memory controller 4 sets the configuration information with the configuration number M for each item related to the processing of the memory system 3 (step S605). In the subsequent processing of the memory system 3, it executes according to the configuration information with the configuration number M.
[0078] At the end of the boot process B, the information processing system 1 starts the post-boot process. At the start of the post-boot process, the configuration number specified by the flag is N. Therefore, the memory system 3 executes according to the configuration information with the configuration number N in the post-boot process.
[0079] In addition, regarding the step (S609) in which the host CPU 30 sends a command to request reading of the OS 23 to the memory controller 4, it can be performed at any time as long as it is after the step (S605) in which the memory controller 4 sets the configuration information completion command for the host 2 and during the boot process B.
[0080] Figure 7 It is a diagram showing an example of the post-boot process of the information processing system 1. Following Figure 6 the boot process B Figure 7 the post-boot process is carried out.
[0081] Next, Figure 7 the flowchart will be explained.
[0082] The host CPU 30 starts the OS 23 (S701).
[0083] The host CPU 30 sends an initialization command to the memory controller 4 (S702). When the memory controller 4 receives the initialization command, it initializes the memory system 3 (S703). The memory controller 4 confirms the configuration number specified by the flag. The memory controller 4 sets the configuration information with the specified configuration number (in this case, the configuration number N) for each item related to the processing of the memory system 3 (step S704). When the setting of the configuration information is completed, the memory controller 4 sends a configuration information setting completion command to the host 2 (step S705).
[0084] The host 2 sends a command to determine the configuration number specified by the flag as K to the memory controller 4 (step S706). The memory controller 4 changes the configuration number specified by the flag to K (step S707). Then, the memory controller 4 sends a configuration number setting completion command to the host 2 (step S708), and ends the post-boot process.
[0085] Describe the transition of the configuration number specified by the flag in the post-boot process of the information processing system 1. At the start of the post-boot process, the configuration number specified by the flag is N. The configuration number specified by the flag is changed from N to K by the step of changing the configuration number specified by the flag to K (step S707).
[0086] Describe the transition of the configuration number of the configuration information referred to by the memory system 3 in the post-boot process of the information processing system 1. At the start of the post-boot process, the memory system 3 executes according to the configuration information of the configuration number M. It is initialized by performing the process of initializing the memory system 3 (step S703). The memory controller 4 sets the configuration information of the configuration number N for each item related to the process of the memory system 3 (step S705). In the subsequent process of the memory system 3, it executes according to the configuration information of the configuration number N.
[0087] At the end of the post-boot process, then, for example, the information processing system 1 executes an arbitrary application program. At this time, the memory system 3 executes according to the configuration information of the configuration number N.
[0088] When the power of the information processing system 1 is turned off and then turned on, the memory system 3 starts the startup sequence from the boot process A. At the start of the boot process A, the configuration number specified by the flag is K. Therefore, the memory system 3 executes according to the configuration information of the configuration number K in the boot process A.
[0089] In an information processing system including a memory system that does not have the configuration table 24, during the operation of the memory system, for example, when changing the parameters set for items related to hardware such as the operation clock, it is necessary to temporarily stop the operating memory system. Therefore, the operation of the memory system may become unstable. Furthermore, a circuit for temporarily stopping and restarting the operation of the memory system is required, increasing the circuit scale.
[0090] According to the present embodiment, the memory system 3 sets parameters for each item related to the process of the memory system 3 at the timing of initializing the memory system 3, changing the parameters. Therefore, the memory system 3 can stably change even for items related to the setting of hardware.
[0091] In addition, of course, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention, and are also included in the scope equivalent to the invention described in the claims.
[0092] [Reference Signs]
[0093] 1: Information processing system
[0094] 2: Host
[0095] 3: SSD
[0096] 4: Memory controller
[0097] 5: NAND memory
[0098] 10: Bus
[0099] 11: Host I / F
[0100] 12: Memory CPU
[0101] 13: NAND I / F
[0102] 20: Boot area
[0103] 21: User area
[0104] 22: Boot loader
[0105] 23: OS
[0106] 24: Configuration table
[0107] 30: Host CPU
[0108] 31: Host ROM
[0109] 32: Host RAM
[0110] 33: BIOS.
Claims
1. A memory system capable of being connected to a host and having: Non-volatile memory; and A memory controller, controlling the non-volatile memory; The non-volatile memory stores a plurality of configuration information. The first configuration information in the configuration information includes a first parameter, The memory controller, during the first period of the boot sequence, The nonvolatile memory is controlled according to the first parameter.
2. The memory system according to claim 1, wherein The memory controller controls the nonvolatile memory in a second period after the first period according to a second parameter included in second configuration information different from the first configuration information among the plurality of configuration information.
3. The memory system of claim 2, wherein The second configuration information is stored before the second period based on information received by the memory controller from the host.
4. The memory system of claim 2, wherein The memory controller receives a second command from the host during the second period, When the second command is received, the memory system is initialized, and then the nonvolatile memory is controlled according to the second configuration information.
5. The memory system of claim 2, wherein The memory controller sets a flag in the nonvolatile memory during the first period, the flag designating the second configuration information used during the second period, During the second period, the flag is confirmed and the nonvolatile memory is controlled according to the second configuration information.
6. The memory system of claim 2, wherein During the first period, the memory controller can access a first area of the nonvolatile memory storing a boot loader and the plurality of configuration information, but cannot access a second area of the nonvolatile memory storing an operating system. During the second period, the memory controller can access both the first area of the nonvolatile memory and the second area of the nonvolatile memory.
7. The memory system of claim 2, wherein The first configuration information is information indicating that the interface to the host is operated at a first speed during the first period. The second configuration information is information indicating that, during the second period, the interface to the host is operated at a second speed that is faster than the first speed.
8. The memory system of claim 1, wherein The memory controller receives a first command from the host during the first period, When the first command is received, the memory system is initialized, and then the nonvolatile memory is controlled according to the first configuration information.
9. A memory system capable of being connected to a host and comprising: Non-volatile memory; and A memory controller, controlling the non-volatile memory; The non-volatile memory stores: Flag, specifying the configuration number of No. 1 or No. 2; The first configuration information includes parameters for the memory controller to refer to during the first period of the boot sequence and is assigned the first number; as well as second configuration information including parameters for reference by the memory controller in a second period in the activation sequence after the first period and assigned the second number; The memory controller performs the following actions during the first period: initializing the memory system if a first command is received from the host; referring to the flag specifying the first number; setting parameters related to processing of the memory system according to the first configuration information; And changing the configuration number from the first number to the second number.
10. The memory system of claim 9, wherein The nonvolatile memory further includes third configuration information, the third configuration information including parameters for reference by the memory controller in a third period different from the second period in the boot sequence, and the third configuration information is assigned a third number. The flag is a flag that specifies the first number, the second number, or the third number, The second period starts following the first period. When receiving a second command from the host during the second period, the memory controller initializes the memory system, checks the flag, controls the nonvolatile memory according to the second configuration information, and changes the flag to the third number.
11. The memory system of claim 9, wherein The third period starts following the second period. When receiving a third command from the host during the third period, the memory controller initializes the memory system, checks the flag, controls the nonvolatile memory according to the third configuration information, and changes the flag to the first number.
12. A memory system capable of being connected to a host and comprising: Non-volatile memory; and A memory controller, controlling the non-volatile memory; The non-volatile memory stores a plurality of configuration information for a boot sequence of the memory system, The memory controller When a first command is received from the host, a first process is performed according to the first configuration information among the plurality of configuration information. When a second command is received from the host, a second process is performed according to second configuration information different from the first configuration information among the plurality of configuration information. When a third command is received from the host, a third process is performed according to third configuration information different from the first and second configuration information among the plurality of configuration information, After the first, second and third processes, the startup sequence is terminated.
13. The memory system of claim 12, wherein The memory controller receiving the second command after the first command, The third command is received after the second command.
14. The memory system of claim 12, wherein The host At startup, the startup sequence is executed. During a first period of the execution of the boot sequence, the first command is sent to the memory system, In the second period following the first period, the second command is sent to the memory system, In the third period following the second period, the third command is sent to the memory system.