Semiconductor packaging substrate and preparation method thereof

Abstract

The invention discloses a semiconductor packaging substrate and a preparation method thereof, and relates to the technical field of semiconductor devices.The packaging substrate comprises a first substrate layer, a second substrate layer and a base, a first matching through groove is formed in the middle of the first substrate layer, and the base is embedded in the first matching through groove; an opening frame hollowed-out through groove is formed in the middle of the second substrate layer, the second substrate layer is correspondingly overlapped on the first substrate layer, and the second substrate layer is matched with the first substrate layer based on the opening frame hollowed-out through groove to form a notch structure; a die bonding area for accommodating a chip is arranged in the notch structure, and the base and a part of the circuit structure of the first substrate layer are located in the notch structure. The substrate is embedded in the first matching through groove of the first substrate layer, and the circuit arrangement of the substrate, the first substrate layer and the second substrate layer replaces the bonding wire connection, so that the packaging process is optimized, the parasitic effect is reduced, the switching loss and the conduction loss are reduced, and the working stability of the high-power chip device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a semiconductor packaging substrate and a preparation method thereof. Background Art

[0002] At present, semiconductor devices mainly package and encapsulate power chips by wire bonding. Since the parasitic inductance of the wire bonding connection method is relatively high, it is difficult to meet the requirements of fast switching and low loss of high-power chips. Moreover, the traditional wire bonding method cannot meet the electrical transmission requirements of high-power chip devices, resulting in reduced working efficiency and insufficient working stability of high-power chip devices. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art. The present invention provides a semiconductor packaging substrate and a preparation method thereof. By embedding a base in the first fitting through groove of the first substrate layer, and replacing the wire bonding connection with the circuit layout of the base, the first substrate layer and the second substrate layer, the packaging process is optimized, and at the same time, the parasitic effect is reduced, the switching loss and conduction loss are reduced, and the working stability of high-power chip devices is improved.

[0004] The present invention provides a semiconductor packaging substrate, which includes: a first substrate layer, a second substrate layer and a base. A first fitting through groove is provided in the middle of the first substrate layer, and the base is fitted in the first fitting through groove; A frame hollow through groove is provided in the middle of the second substrate layer. The second substrate layer is correspondingly stacked on the first substrate layer, and the second substrate layer and the first substrate layer cooperate to form a notch structure based on the frame hollow through groove; A die bonding area for accommodating a chip is provided in the notch structure. Part of the circuit structures of the base and the first substrate layer are located in the notch structure.

[0005] Further, the first substrate layer is a printed circuit board.

[0006] Further, a plurality of top connection pads are provided on the top of the first substrate layer, and a plurality of bottom connection pads are provided on the bottom of the second substrate layer; The plurality of top connection pads of the first substrate layer are connected to the plurality of bottom connection pads of the second substrate layer in one-to-one correspondence, and the top connection pads of the first substrate layer and the bottom connection pads of the second substrate layer are bonded and fixed based on an adhesive material.

[0007] Further, a gap is formed at the non-connected position of the first substrate layer and the second substrate layer. The thickness of the gap is h, and the value range of h is: h≥100μm.

[0008] Further, the slot size of the port frame hollow through - slot of the second substrate layer is larger than the slot size of the first mating through - slot of the first substrate layer; The top surface of the base and the top surface of a part of the first substrate layer are exposed in the port frame hollow through - slot of the second substrate layer.

[0009] Further, the semiconductor packaging substrate is provided with a plurality of through - holes, and a plurality of conductive channels are formed based on copper plug holes in the plurality of through - holes, or a plurality of conductive channels are formed based on a conductive layer covering in the plurality of through - holes.

[0010] Further, the plurality of through - holes include a plurality of first sub - through - holes provided in the first substrate layer and a plurality of second sub - through - holes provided in the second substrate layer; The plurality of first sub - through - holes are electrically connected to the plurality of second sub - through - holes correspondingly, and / or the plurality of first sub - through - holes are electrically connected to the plurality of second sub - through - holes based on a layout circuit.

[0011] The present invention also provides a preparation method of a semiconductor packaging substrate. The preparation method is used to prepare the semiconductor packaging substrate, and the preparation method includes: Performing grooving processing on a substrate raw material through a grooving process to form a first substrate layer plate and a second substrate layer plate with a hollow frame; Processing through - holes in the first substrate layer based on a laser drilling process, and depositing a metal material in the through - holes to form an electrical channel; A wiring structure is arranged on the base, and the base with the wiring structure is embedded in the hollow frame of the first substrate layer plate; Forming a plurality of solder pads in the first substrate layer and the base through a dry film process; Stacking and integrating the first substrate layer plate and the second substrate layer plate to form a packaging substrate with a notch structure.

[0012] Further, both the first substrate layer and the second substrate layer are panel structures; Printing a conductive medium at the upper and lower conductive connection positions corresponding to the first substrate layer on the second substrate layer; The first substrate layer stacks the substrates by identifying the positions of the top solder pads of the second substrate layer. The present invention provides a semiconductor packaging substrate and a preparation method thereof. By providing a first substrate layer with a first mating through - slot and embedding a base in the first mating through - slot of the first substrate layer, replacing wire bonding with the circuit arrangement of the base, the first substrate layer and the second substrate layer, the packaging process is optimized, and at the same time, the parasitic effect is reduced, the switching loss and the conduction loss are reduced, and the working stability of high - power chip devices is improved. Description of the Drawings

[0013] Figure 1It is a top view of the structure of a semiconductor packaging substrate in an embodiment of the present invention; Figure 2 It is a cross-sectional view of the structure of the via position of a semiconductor packaging substrate in an embodiment of the present invention; Figure 3 It is a flowchart of the manufacturing method of a semiconductor packaging substrate in an embodiment of the present invention; Figure 4 It is a schematic structural diagram of a base in an embodiment of the present invention; Figure 5 It is a schematic diagram of the fitting state of the base and the first substrate layer board in an embodiment of the present invention; Figure 6 It is a schematic diagram of the processing state of the electrical channel of the first substrate layer in an embodiment of the present invention; Figure 7 It is a schematic diagram of the state of processing pads based on a dry film process in an embodiment of the present invention; Figure 8 It is a schematic structural diagram of the pads of the first substrate in an embodiment of the present invention; Figure 9 It is a schematic diagram of the second substrate panel structure in an embodiment of the present invention; Figure 10 It is a schematic diagram of the panel structure of the fitting state of the base and the first substrate layer board in an embodiment of the present invention; Figure 11 It is a schematic diagram of the cooperation state of the first substrate layer board and the second substrate layer board in an embodiment of the present invention; Figure 12 It is a cross-sectional view of the via position of the panel structure state of the first substrate layer and the second substrate layer in an embodiment of the present invention. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0015] Embodiment 1: Figure 1 It shows a top view of the structure of a semiconductor packaging substrate in an embodiment of the present invention; Figure 2 It shows a cross-sectional view of the structure of the via position of a semiconductor packaging substrate in an embodiment of the present invention. The packaging substrate includes: a first substrate layer 2, a second substrate layer 3, and a base 1. A first fitting through groove is provided in the middle of the first substrate layer 2, and the base 1 is fitted in the first fitting through groove.

[0016] A mouth frame hollow through slot is provided in the middle of the second substrate layer 3. The second substrate layer 3 is correspondingly laminated on the first substrate layer 2, and the second substrate layer 3 and the first substrate layer 2 cooperate to form a notch structure based on the mouth frame hollow through slot.

[0017] Specifically, a plurality of top connection pads are provided on the top surface of the first substrate layer 2, and a plurality of bottom connection pads are provided on the bottom surface of the second substrate layer 3. The top connection pads of the first substrate layer 2 and the bottom connection pads of the second substrate layer 3 are connected in one-to-one correspondence. Moreover, the first substrate layer 2 and the second substrate layer 3 are adhesively fixed based on an adhesive material 6. The adhesive material 6 is correspondingly provided between the top connection pads of the first substrate layer 2 and the bottom connection pads of the second substrate layer 3. By adhesively fixing the first substrate layer 2 and the second substrate layer 3 based on the adhesive material 6 and supporting the top connection pads of the first substrate layer 2 and the bottom connection pads of the second substrate layer 3 through the adhesive material 6, the smoothness of the structural connection between the first substrate layer 2 and the second substrate layer 3 can be ensured.

[0018] Furthermore, the distance between the first substrate layer 2 and the second substrate layer 3 is h, and the value range of h is: h≥100μm. That is, based on the corresponding connection between the top connection pads of the first substrate layer 2 and the bottom connection pads of the second substrate layer 3 and in combination with the set thickness of the adhesive material 6, a gap of at least 100μm is formed at the non-contact position between the first substrate layer 2 and the second substrate layer 3, so as to meet the convenience of the encapsulation colloid flowing between the first substrate layer 2 and the second substrate layer 3 during subsequent device encapsulation, and improve the convenience and reliability of the encapsulation operation.

[0019] Furthermore, the adhesive material 6 can be solder paste, which has good adhesive performance and improves the connection stability between the first substrate layer 2 and the second substrate layer 3; the adhesive material 6 can also be silver paste, which has good electrical conductivity and can meet the electrical connection requirements between the first substrate layer 2 and the second substrate layer 3.

[0020] A die bonding area for accommodating a chip is provided in the notch structure. Part of the circuit structure of the base 1 and the first substrate layer 2 is located in the notch structure. The top surface circuit of the base 1 can be electrically connected to the circuit structure of the first substrate layer 2 based on pads, and die bonding pads for the chip are formed to meet the die bonding and chip interconnection requirements of the chip in the packaging substrate.

[0021] Further, there is a clearance fit between the base 1 and the first mating through groove of the first substrate layer 2, enabling quick snap-fit between the base 1 and the first substrate layer 2 and improving the convenience of fitting and matching between the base 1 and the first substrate layer 2.

[0022] Specifically, in the design and application of high-power chips, by integrating the structure of the base 1 into the first substrate layer 2, the single-point or multi-point connection methods of wire connections, heat generation, or electromagnetic interference are reduced. With the first substrate layer 2 and the second substrate layer 3 serving as current carriers and the base 1 serving as the main heat sink, the current-carrying capacity and heat dissipation performance of the semiconductor packaging substrate can be improved.

[0023] Further, based on the fitting connection between the base 1 and the mating through groove, the top surface of the base 1 can be exposed on the top surface of the first substrate layer 2, and the bottom surface of the base 1 can be exposed on the bottom surface of the first substrate layer 2. By directly die-bonding the chip onto the base 1, since there is no substrate material support on the front or back of the base 1, the chip can be directly die-bonded onto the base 1, shortening the heat transfer path between the chip and the base 1. Thus, direct heat dissipation can be achieved based on the base 1, effectively improving the heat dissipation effect of the packaging substrate.

[0024] Specifically, the slot size of the mouth-frame hollow through groove of the second substrate layer 3 is larger than the slot size of the first mating through groove of the first substrate layer 2, that is, the top surface of the base 1 and part of the top surface of the first substrate layer 2 can be exposed within the mouth-frame hollow through groove of the second substrate layer 3, so as to form a chip die-bonding area on the semiconductor packaging substrate, enabling the chip to be die-bonded correspondingly on the pad structures of the base 1 and the first substrate layer 2 to meet the requirements of chip die-bonding installation and different chip interconnections on the semiconductor packaging substrate.

[0025] Further, a third sub-through hole 11 is provided inside the base 1, and a metal material is deposited based on the third sub-through hole 11 to form an electrical channel, enabling the chip to access the external working circuit based on the electrical channel formed by the third sub-through hole.

[0026] Specifically, the first substrate layer 2 can be a printed circuit board, and the conductive lines are formed by copper foil etching, improving the simplicity of the line layout and simultaneously enhancing the current-carrying capacity of the semiconductor packaging substrate.

[0027] Further, based on a preset layout line that matches the line of the base 1, the base 1 can be fitted into the first substrate layer 2 and form an electrical connection with the first substrate layer 2 to meet the usage requirements of the semiconductor packaging substrate.

[0028] Specifically, the base 1 can be a metal composite ceramic plate, which can be a direct bonding copper (DBC) ceramic plate, a direct aluminium bonding (DAB) ceramic plate, or an active metal brazed (AMB) ceramic plate.

[0029] Furthermore, the direct bonding copper ceramic plate combines a copper layer with a ceramic substrate to achieve a synergistic optimization of electrical, thermal, and mechanical properties. Based on the combination of the copper layer and the ceramic substrate, the conductivity of the base 1 can be increased, the working impedance of the base 1 can be reduced, and the working reliability of the semiconductor packaging substrate can be improved.

[0030] Furthermore, the direct aluminium bonding ceramic plate combines an aluminium layer with a ceramic substrate. Based on the aluminium layer, a circuit layout structure is formed on the ceramic substrate. By using metal aluminium as the conductive circuit layer of the base 1, the electrical conduction requirements of the semiconductor packaging substrate can be met, and the manufacturing cost of the semiconductor packaging substrate can be reduced.

[0031] Specifically, the base 1 can also be an insulated metal substrate (IMS), which is a composite material composed of a metal substrate (such as aluminium or copper), an insulating layer (such as a polymer or ceramic), and a conductive layer (such as copper foil). It can be applied to electronic devices with high power and high heat dissipation requirements. Based on the structural cooperation between the metal substrate, the insulating layer, and the copper foil, the heat dissipation effect of the insulated metal substrate can be improved, achieving a synergistic design of high heat dissipation and electrical insulation.

[0032] Specifically, the semiconductor packaging substrate is also provided with a plurality of pads for mounting chips. Based on the dry film process, pads are processed on the base 1 and the first substrate layer 2. A pattern mask is set on the semiconductor packaging substrate through photoresist, and a metal material is plated on the pattern mask to form a plurality of pad structures, so that the chips can be directly die-bonded on the base 1 and the first substrate layer 2.

[0033] Furthermore, based on the preset circuit layout of the base 1 and the first substrate layer 2, the setting positions of the pads are formed on the surfaces of the base 1 and the first substrate layer 2. The copper foil is welded at the corresponding positions through a brazing process, so that pad structures can be formed on the base 1 and the first substrate layer 2, meeting the requirements for die-bonding chips on the semiconductor packaging substrate and realizing the connection between different chips.

[0034] Specifically, a plurality of through holes are provided in the semiconductor packaging substrate. A plurality of the through holes form a conductive channel based on copper plug holes, or a plurality of the through holes form a conductive channel based on a conductive layer covering. The semiconductor packaging substrate forms an internal electrical connection circuit based on a plurality of the conductive channels, which can improve the compactness of the internal circuit layout of the semiconductor packaging substrate.

[0035] Furthermore, by means of copper plug holes, the resistance of the conductive channel of the semiconductor packaging substrate can be reduced, thereby improving the stability and reliability of the conductive channel of the semiconductor packaging substrate.

[0036] Furthermore, by electroplating nickel-gold or coating silver paste in the through holes, the electrical conduction performance of the through holes can be achieved, which can meet the electrical connection requirements of the vertical structure of the semiconductor packaging substrate and reduce the manufacturing cost of the semiconductor packaging substrate.

[0037] Specifically, a plurality of the through holes include a plurality of first sub-through holes 21 provided in the first substrate layer 2 and a plurality of second sub-through holes 31 provided in the second substrate layer 3. A plurality of the first sub-through holes 21 are electrically connected to a plurality of the second sub-through holes 31 correspondingly, and / or a plurality of the first sub-through holes 21 are electrically connected to a plurality of the second sub-through holes 31 based on a layout circuit. When the first sub-through holes 21 are located in the overlapping area of the first substrate layer 2 and the second substrate layer 3, the first sub-through holes 21 and the second sub-through holes 31 can overlap at corresponding positions, so that the top surface circuit of the second substrate layer 3 can be electrically connected to the bottom surface circuit of the first substrate layer 2.

[0038] Furthermore, a vertical interconnection channel is formed on the semiconductor packaging substrate by laser drilling / chemical etching, and the electrical stability and low resistance characteristics of the vertical interconnection are ensured by electroplating or filling a conductive material, so as to meet the electrical connection conduction and electrical connection requirements of the semiconductor packaging substrate.

[0039] Specifically, the embodiment of the present invention provides a semiconductor packaging substrate. By fitting a base 1 with a preset circuit into the first substrate layer 2, based on the circuit layout structure among the base 1, the first substrate layer 2 and the second substrate layer 3, the resistivity of the electrical transmission of the circuit of the semiconductor packaging substrate is reduced, and in the circuit structure design of the base 1, the first substrate layer 2 and the second substrate layer 3, the total impedance can be further reduced by increasing the cross-sectional area of the wire, and the stability and reliability of the electrical transmission of the semiconductor packaging substrate are improved.

[0040] Embodiment 2: Figure 3The flowchart of the preparation method of the semiconductor packaging substrate in the embodiment of the present invention is shown. The preparation method is used to prepare the semiconductor packaging substrate, and the preparation method includes: S11: Perform grooving processing on the substrate raw material through a grooving process to form a first substrate layer plate and a second substrate layer plate with a hollow.

[0041] Specifically, perform grooving processing on the electronic board through a numerical control device. The grooving can be performed by a laser grooving process on the electronic board, so that after etching, the electronic board can form a hollow frame for accommodating the base 1 to meet the installation requirements of the fitting of the base 1.

[0042] Specifically, Figure 4 The structural schematic diagram of the base 1 in the embodiment of the present invention is shown; Figure 5 The schematic diagram of the fitting state of the base and the first substrate layer plate in the embodiment of the present invention is shown; the grooving processing of the substrate raw material through the grooving process to form a first substrate layer plate and a second substrate layer plate with a hollow frame includes: Deposit a sacrificial layer on the surface of the substrate raw material. The sacrificial layer material can be photoresist. Based on the photoresist as a support, the photoresist can be removed through subsequent exposure treatment; the material of the sacrificial layer can also be copper metal, which has a good support effect, and the copper metal can be etched and removed through a subsequent etching process to meet the processing of the hollow frame structure of the first substrate layer 2.

[0043] Process and form a circuit pattern on the sacrificial layer of the substrate raw material through photolithography and electroplating processes.

[0044] S12: A wiring structure is provided on the base 1, and the base 1 with the wiring structure is fitted into the hollow frame of the first substrate layer plate.

[0045] A wiring structure is provided on the base 1, so that the base 1 can meet the packaging requirements of the chip, and based on the wiring structure, the electrical connection between the base 1 and the first substrate layer 2 can be realized, thereby improving the convenience and reliability of the fitting between the first substrate layer 2 and the base 1.

[0046] Furthermore, a wiring structure adapted to the base 1 is preset in the hollow frame of the first substrate layer plate, so that when the base 1 is fitted into the hollow frame of the first substrate layer plate, the electrical connection between the base 1 and the first substrate layer 2 can be realized based on its own wiring structure and the wiring structure of the hollow frame.

[0047] S13: Process through holes in the first substrate layer based on a laser drilling process, and deposit a metal material in the through holes to form an electrical channel.

[0048] Specifically, Figure 6 FIG. shows a schematic diagram of the electrical channel processing state of the first substrate layer in an embodiment of the present invention; Figure 7 FIG. shows a schematic diagram of the state of processing pads based on a dry film process; a laser drilling operation is performed on the first substrate layer board by a laser device. Through the laser drilling operation, a plurality of through-hole structures can be processed and formed at corresponding positions of the first substrate layer board. By depositing a metal material in the through-holes, an electrical channel is formed to meet the circuit layout structure design of the first substrate layer board.

[0049] Furthermore, metal material deposition can be carried out in the through-hole structures by chemical vapor deposition, so as to meet the electrical connection requirements of the through-holes.

[0050] Specifically, conductive channels can also be formed in a plurality of through-hole structures by means of copper plug holes or coating a conductive layer, so that the circuit structure layout of the first substrate layer board can meet the electrical layout connection requirements of the chip.

[0051] Furthermore, by means of copper plug holes, the resistance of the conductive channels of the first substrate layer board can be reduced, thereby improving the stability and reliability of the conductive channels between the first substrate layer board and the chip.

[0052] Furthermore, by electroplating nickel-gold or coating silver paste in the through-holes, the electrical conduction performance of the through-holes can be achieved, which can meet the electrical channel connection requirements of the internal vertical structure of the first substrate layer board and reduce the preparation cost of the first substrate layer board.

[0053] S14: A plurality of pads 5 are arranged in the first substrate layer by a dry film process.

[0054] Specifically, a dry film medium is laminated on the surface of the substrate, and a pattern is formed by a photolithography process. A seed layer is sputtered on the surface of the dry film with the formed pattern. The material of the seed layer can be copper, nickel, titanium and other materials. The set thickness of the seed layer is between 0.1 μm and 0.5 μm, and the seed layer has sufficient adhesion so that the subsequent electroplated layer can be firmly attached. At the same time, the seed layer has good electrical conductivity and corrosion resistance to ensure the stability and reliability of the circuit.

[0055] Furthermore, by setting the seed layer, the adhesion of the substrate raw material is improved through the seed layer. During the electroplating process, it can be ensured that the electroplated copper layer can be firmly attached to the dielectric layer of the substrate raw material; by setting the seed layer as the base layer of the electroplated copper layer, the seed layer can be evenly and durably attached to the seed layer, effectively reducing the occurrence of uneven electroplating or poor adhesion during the electroplating operation.

[0056] Furthermore, by electroplating a copper layer on the surface of the seed layer, a low-resistance circuit path can be formed, improving the electrical performance of the device.

[0057] Furthermore, the dry film is peeled off to form an electrical connection pattern connecting the base and the substrate.

[0058] Figure 8 The schematic diagram of the pad structure of the first substrate in the embodiment of the present invention is shown; Figure 9 The schematic diagram of the second substrate panel structure in the embodiment of the present invention is shown; a plurality of hollow frames are formed on the first substrate layer board, and a plurality of bases 1 are respectively fitted into the plurality of hollow frames. In this embodiment, a plurality of pads 5 are formed on the first substrate layer board by a dry film process to meet the installation requirements of the chips.

[0059] Specifically, on the base 1 and the first substrate layer board, by electroplating the pad 5, the pad structure straddles between the base 1 and the first substrate layer board to meet the connection requirements of chip installation die bonding and interconnection of different chips.

[0060] Furthermore, the pad structure can also be prepared by metal sputtering. A pattern mask is covered on the surfaces of the base 1 and the first substrate layer board, so that the layout positions of the pad structure can be reserved on the surfaces of the base 1 and the first substrate layer board. Under the action of high voltage, metal particles are bombarded on the layout positions reserved by the pattern mask, so that the metal particles can adhere to the placement positions, thereby forming the pad structure.

[0061] Furthermore, the preparation method further includes: processing a plurality of first sub-through holes 21 on the first substrate layer board, processing a plurality of second sub-through holes 31 on the second substrate layer board, performing a punching operation on the first substrate layer board and the second substrate layer board by a laser drilling process, and performing a copper plug hole operation on the first sub-through holes 21 and the second sub-through holes 31, so that the first substrate layer board forms a plurality of conductive channels based on the plurality of first sub-through holes 21, and the second substrate layer board forms a plurality of conductive channels based on the plurality of second sub-through holes 31, thereby meeting the setting of the vertical circuit structure arrangement of the first substrate layer board and the second substrate layer board.

[0062] Further, a plurality of the first sub-vias 21 and a plurality of the second sub-vias 31 can be provided with a conductive channel by coating a conductive material. By electroplating a conductive material inside the first sub-via 21 and the second sub-via 31, a conductive via structure is formed. Based on the vertical structure, the conductive via can satisfy the electrical connection between the top surface circuit and the bottom surface circuit of the first substrate layer board, and also satisfy the electrical connection between the first substrate layer board and the second substrate layer board.

[0063] S15: Stack and integrate the first substrate layer board and the second substrate layer board to form a packaging substrate with a notch structure.

[0064] Figure 10 The figure shows a layout structure diagram of the fitting state of the base and the first substrate layer board in the embodiment of the present invention; the second substrate layer board and the first substrate layer board are correspondingly stacked, and the vias of the first substrate layer board and the second substrate layer board are correspondingly connected. The conductive channels arranged on the first substrate layer board are connected to the conductive channels formed on the second substrate layer board to realize the electrical connection between the first substrate layer board and the second substrate layer board.

[0065] Further, based on the corresponding stacking of the second substrate layer board and the first substrate layer board, a packaging substrate with a notch structure is formed by stacking. A chip installation position can be reserved on the top surface of the base in the notch structure, and the top surface of the chip can be flush with the top surface of the second substrate layer board. Based on the stacking connection between the first substrate layer board and the second substrate layer board, the structural compactness of the packaging device can be improved, achieving a highly integrated electrical packaging structure.

[0066] Specifically, both the first substrate layer board and the second substrate layer board are in a panel structure. By printing a conductive medium at the corresponding upper and lower electrically connected parts of the second substrate layer board and the first substrate layer board, and stacking the first substrate layer board by identifying the top pad positions of the second substrate layer, that is, the first substrate layer board is positioned based on the top pad positions of the second substrate layer board, so as to ensure the accuracy of the stacked docking.

[0067] Further, please refer to Figure 2 , the top connection pads of the first substrate layer board are arranged at the positions corresponding to the first sub-vias 21, the bottom connection pads of the second substrate layer board are arranged at the positions corresponding to the second sub-vias 31, and the top connection pads and the bottom connection pads are adhesively connected based on an adhesive material 6. The adhesive material 6 is set as a conductive adhesive material, which can satisfy the electrical connection between the electrical channels formed by the first sub-vias 21 and the electrical channels formed by the second sub-vias 31.

[0068] Further, the connection method between the first substrate layer board and the second substrate layer board includes welding connection. By means of reflow soldering or thermocompression bonding, the positions of the corresponding pads of the first substrate layer board and the second substrate layer board are welded and fixed to meet the requirements for the preparation stability of the overall structure of the semiconductor packaging substrate.

[0069] Further, the first substrate layer board and the second substrate layer board can be connected by conductive adhesive, so that the through-hole structures between the first substrate layer board and the second substrate layer board can be electrically connected correspondingly to meet the electrical connection between the first substrate layer board and the second substrate layer board.

[0070] Further, the connection between the first substrate layer board and the second substrate layer board can be a mechanical connection, that is, by providing a number of connection through-holes on the first substrate layer board and the second substrate layer board, and locking and fixing them by means of copper rivets or conductive screws, and filling a conductive medium on the contact surface between the first substrate layer board and the second substrate layer board, thereby improving the stability of the electrical connection between the first substrate layer board and the second substrate layer board.

[0071] Specifically, the lamination and integration of the first substrate layer board and the second substrate layer board include: The first substrate layer board and the second substrate layer board are pasted and welded together, and electrical connection is formed based on the through-hole structures of the first substrate layer board and the second substrate layer board.

[0072] Further, the size of the hollowed-out structure of the second substrate layer board is larger than that of the first substrate layer board. When the first substrate layer board and the second substrate layer board are laminated, a part of the top surface of the first substrate layer board and the top surface of the base 1 can be exposed in the hollowed-out structure of the second substrate layer board, and a die bonding area for accommodating the chip is formed between the hollowed-out structure area of the second substrate layer board and the top surface of the base 1, so that the thickness of the chip is the same as the thickness of the second substrate layer board, and the top surface of the chip is flush with the top surface of the second substrate layer board, so as to enable electrical connection between the chip and the second substrate layer board through the electrical connection board.

[0073] Figure 11 Fig. shows a schematic diagram of the cooperation state of the first substrate layer board and the second substrate layer board in the embodiment of the present invention; Figure 12The cross-sectional view of the through-hole position of the first substrate layer and the second substrate layer in the layout structure state in the embodiment of the present invention is shown. When preparing a semiconductor device based on the packaging substrate, a chip is fixed in the notch structure formed by the cooperation of the first substrate layer plate and the second substrate layer plate, and an electrical connection component is mounted between the top electrode of the chip and the top pad of the second substrate layer plate to realize the electrical connection between the top electrode of the chip and the second substrate layer plate, and the first substrate layer plate and the second substrate layer plate are encapsulated with packaging resin to obtain an encapsulated layout structure.

[0074] A pattern mask is set on the encapsulated layout structure, and the encapsulated layout structure is cut along the pattern mask by a cutting device, so as to obtain a plurality of the semiconductor packaging devices, which can effectively improve the preparation efficiency and quality of the semiconductor packaging devices.

[0075] The embodiment of the present invention provides a method for preparing a semiconductor packaging substrate. By setting a hollow structure with a self-supporting circuit structure on the first substrate layer plate, a base 1 with a wiring structure is embedded in the hollow structure of the first substrate layer plate, reducing the wire bonding connection operation of the semiconductor packaging substrate structure, thereby reducing the parasitic resistance of the semiconductor packaging substrate structure and effectively improving the stability of the electrical connection of the semiconductor packaging substrate.

[0076] In addition, the above has introduced in detail a semiconductor packaging substrate and a method for preparing the same provided by the embodiment of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A semiconductor package substrate, characterized in that: The packaging substrate comprises: a first substrate layer, a second substrate layer and a base, wherein a ceramic base is arranged in the first substrate layer and embedded in the substrate; A frame hollow through groove is provided in the middle of the second substrate layer, the second substrate layer is correspondingly overlapped on the first substrate layer, and the frame hollow through groove of the second substrate layer cooperates with the first substrate layer to form a notch structure; A ceramic base die-bonding region for accommodating a chip is disposed in the notch structure, and the ceramic base and a portion of the circuit structure of the first substrate layer are located in the notch structure.

2. The semiconductor package substrate according to claim 1, wherein: The first substrate layer is a printed circuit board.

3. The semiconductor package substrate according to claim 1, wherein: A plurality of top connection pads are disposed on the top of the first substrate layer, and a plurality of bottom connection pads are disposed on the bottom of the second substrate layer; The top connection pads of the first substrate layer are connected to the bottom connection pads of the second substrate layer in a one-to-one correspondence, and the top connection pads of the first substrate layer and the bottom connection pads of the second substrate layer are electrically connected based on a conductive adhesive material.

4. The semiconductor package substrate according to claim 1, wherein: A gap is formed at a non-connected position between the first substrate layer and the second substrate layer. The thickness of the gap is h, and the value range of h is 50-500 μm.

5. The semiconductor package substrate according to claim 1, wherein: The size of the opening frame of the opening frame hollow through groove of the second substrate layer is larger than the size of the ceramic base of the first substrate layer; The top surface of the base and a portion of the top surface of the first substrate layer are exposed in the hollow through groove of the opening frame of the second substrate layer.

6. The semiconductor package substrate according to claim 1, wherein: The semiconductor package substrate is provided with a plurality of through holes, and a plurality of the through holes form a conductive channel based on a copper plug hole, or a plurality of the through holes form a conductive channel based on a conductive layer covering.

7. The semiconductor package substrate according to claim 6, wherein: The plurality of through holes include a plurality of first sub-through holes arranged on the first substrate layer and a plurality of second sub-through holes arranged on the second substrate layer; A plurality of the first sub-through holes are electrically connected to a plurality of the second sub-through holes correspondingly, and / or a plurality of the first sub-through holes are electrically connected to a plurality of the second sub-through holes based on an arrangement circuit.

8. A method for preparing a semiconductor package substrate, characterized in that: The preparation method is used to prepare the semiconductor package substrate according to any one of claims 1 to 7, and the preparation method comprises: The substrate raw material is slotted by a slotting process to form a first substrate layer plate and a second substrate layer plate with a hollow frame; Processing through holes in the first substrate layer based on a laser drilling process, and depositing metal material in the through holes to form electrical channels; A wiring structure is arranged on the ceramic base, and the ceramic base with the wiring structure is embedded in the first substrate layer plate; forming a plurality of pads on the first substrate layer and the base by a dry film process; The first substrate layer plate material and the second substrate layer plate material are stacked and integrated to form a packaging substrate with a notch structure.

9. The method for preparing a semiconductor package substrate according to claim 8, wherein: The first substrate layer and the second substrate layer are both panel structures; Printing a conductive medium on the second substrate layer at the upper and lower conductive connection positions corresponding to the first substrate layer; The first substrate layer is stacked by identifying the top pad position of the second substrate layer.

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