Plasma-induced damage detection of memory dies

Abstract

The invention relates to plasma induced damage detection of memory dies. The invention relates to techniques for coupled hosts and memory dies. In some examples, an apparatus may include a memory die coupled with a substrate. In addition, the device may include a die sealing structure surrounding the memory die and coupled with the substrate. In some examples, the die sealing structure may include a plurality of layers, and the device may include an insulating material coupled with at least one layer of the plurality of layers and a conductive material coupled with the insulating material. In addition, the device may include a sensing circuit coupled with the conductive material. In some examples, the sensing circuit may be configured to generate a signal based on charge accumulated in the conductive material.

Description

[0001] Cross-reference

[0002] This patent application claims the priority of U.S. Patent Application No. 18 / 781,839, titled "PLASMA INDUCED DAMAGE DETECTION OF A MEMORY DIE," filed on July 23, 2024, by Santosa et al., and U.S. Provisional Patent Application No. 63 / 604,768, titled "PLASMA INDUCED DAMAGE DETECTION OF A MEMORY DIE," filed on November 30, 2023, by Santosa et al., each of which is assigned to its assignee and each of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] This technical field relates to one or more systems for a memory, including plasma-induced damage detection of a memory die. BACKGROUND ART

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. SUMMARY OF THE INVENTION

[0005] A memory device is described. The memory device can include: a memory die coupled to a substrate; a die seal structure surrounding the memory die and coupled to the substrate, the die seal structure including multiple layers; an insulator material coupled to at least one of the multiple layers of the die seal structure; a conductive material coupled to the insulator material; and a sensing circuit coupled to the conductive material, the sensing circuit configured to generate a signal based on charges accumulated in the conductive material.

[0006] Describe a memory device. The memory device may include: a memory die coupled to a substrate; a die seal structure surrounding the memory die and coupled to the substrate; an insulator material coupled to the die seal structure; a conductive material coupled to the insulator material and including a plurality of segments separated from each other by one or more gaps; and a plurality of sensing circuits, each sensing circuit coupled to a corresponding one of the plurality of segments and configured to generate a signal based on charge accumulated in the corresponding segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An example of a system for supporting plasma-induced damage detection of a memory die according to an example disclosed herein is shown.

[0008] Figure 2A And 2B An example of a component diagram for supporting plasma-induced damage detection of a memory die according to an example disclosed herein is shown.

[0009] Figure 3A And 3B An example of a circuit for supporting plasma-induced damage detection of a memory die according to an example disclosed herein is shown. DETAILED DESCRIPTION

[0010] In some examples, a die seal may be formed around a memory die. The die seal may include a conductive material and its purpose may be to protect the memory die from damage during the manufacture of the memory die. For example, a plurality of memory dies may be formed on a wafer, and during manufacture, the plurality of memory dies may be separated from each other by dicing along scribe lines located between the memory dies. The die seal may provide structural support between the scribe lines and the memory die such that the memory die is not damaged during dicing. Additionally, a passivation layer may be formed on top of the memory die. The passivation layer may include a dielectric material and may protect the memory die from plasma processes that may potentially damage electrical components of the memory die.

[0011] However, in some examples, the passivation layer may not completely cover the die seal (e.g., due to over-etching of the passivation layer), leaving at least a portion of the die seal exposed to the plasma process. Thus, during the plasma process, a significantly high voltage may be transmitted along the die seal. Charge in the die seal may accumulate and create a high voltage and local weaknesses in the die seal, which may negatively impact the structural integrity of the die seal and increase the chance of contaminants (e.g., ions or moisture) reaching the memory die through the die seal. Additionally or alternatively, the accumulated charge in the die seal may discharge through the die seal, damaging one or more components of the memory die, among other failure modes.

[0012] To detect lateral over-etching or misalignment of the passivation layer and potential plasma-induced charging on the die seal, a conductive antenna can be formed around the die seal. The conductive antenna can include a conductive material and can be coupled to an insulating material around the outer periphery of the die seal. In some examples, the conductive antenna can include one or more segments. If the conductive antenna includes two or more segments, the gaps between the segments of the two or more segments can be located at the corners of the die seal (e.g., a corner can refer to where two walls of the die seal meet). Additionally, each segment of the conductive antenna can be coupled to a sensing circuit. If at least a portion of the die seal is exposed to plasma, charge will accumulate in the conductive antenna, and the sensing circuit will generate a signal in response. The signal can indicate lateral over-etching or misalignment of the passivation layer and potential plasma-induced charging on the die seal. When a signal is detected, the machine or process can be adjusted so that over-etching or misalignment of the passivation layer does not occur.

[0013] The features of the present disclosure are described and illustrated in the context of systems and architectures. The features of the present disclosure are further described and illustrated in the context of component diagrams, circuits, and flowcharts.

[0014] Figure 1 An example of a system 100 that supports plasma-induced damage detection of a memory die according to an example as disclosed herein is described. System 100 can include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smart phone, a wearable device, an Internet-connected device, a vehicle controller, a system-on-chip (SoC), or other fixed or portable electronic system, and other examples. System 100 includes a host system 105, a memory system 110, and one or more channels 115 that couple the host system 105 to the memory system 110 (e.g., to support communication coupling). System 100 can include any number of one or more memory systems 110 coupled to the host system 105.

[0015] The host system 105 can include one or more components (e.g., circuitry, processing circuitry, processing components) that use the memory to perform processes, any one or more of which can be referred to as a processor 125 or be included in a processor 125. The processor 125 can include at least one of one or more processing elements that can be co-located or distributed, including a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or an SoC or a component thereof, and other examples.

[0016] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as or included in the host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operation signaling. In some instances, the host system controller 120 or the associated functionality described herein may be implemented by the processor 125 or may be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various instances, the host system 105 or the host system controller 120 may be referred to as the host.

[0017] The memory system 110 provides physical memory locations (e.g., addresses) that may be used or referenced by the system 100. The memory system 110 may include a memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) operable to store data. The memory system 110 may be configured to operate with different types of host systems 105 and may respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) may receive a write command indicating that the memory system 110 stores data received from the host system 105, or a read command indicating that the memory system 110 provides data stored in the memory device 145 to the host system 105, or a refresh command indicating that the memory system 110 refreshes data stored in the memory device 145, and other types of commands and operations.

[0018] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions to support the memory system 110 in performing various operations, and may be operable to receive, transfer, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some instances, the memory system controller 140 may cooperate with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof to control the operation of the memory system 110. Although an example of the memory system controller 140 is illustrated as a separate component of the memory system 110, in some instances, aspects of the functionality of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, one or more local controllers 150, or any combination thereof.

[0019] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., two-dimensional array, three-dimensional array), where each memory cell may be operable to store data (e.g., as one or more stored bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, and NAND memory cells, or any combination thereof.

[0020] The local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 145. In some instances, the local controller 150 may be operable to communicate with the memory system controller 140 (e.g., receive or transmit data or commands or both). In some instances, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some instances, the local controller 150 or the memory system controller 140 or both may include a decoding component operable to access addresses of the memory array 155, a sensing component operable to sense the states of the memory cells of the memory array 155, a writing component operable to write the states to the memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0021] The host system 105 (e.g., the host system controller 120) and the memory system 110 (e.g., the memory system controller 140) may use one or more channels 115 to transfer information (e.g., data, commands, control information, configuration information). Each channel 115 may be an instance of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission medium, electrical conductor, conductive path) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. The terminals may be instances of conductive input or output points of the devices of the system 100, and the terminals may operate as part of the channel 115. To support communication on the channel 115, the host system 105 (e.g., the host system controller 120) and the memory system 110 (e.g., the memory system controller 140) may include a receiver (e.g., a latch) for receiving signals, a transmitter (e.g., a driver) for transmitting signals, a decoder for decoding or demodulating received signals, or an encoder for encoding or modulating signals to be transmitted, and other components that support signaling on the channel 115, which may be included in the respective interface portions of the respective systems.

[0022] Channel 115 is dedicated to transmitting one or more types of information, and channel 115 can include unidirectional channels, bidirectional channels, or both. For example, channel 115 can include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some instances, channel 115 can be configured to provide power from one system to another system (e.g., from host system 105 to memory system 110 according to an adjusted voltage). In some instances, at least a subset of channel 115 can be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operation protocol, an industry standard), which can support the configured operations of host system 105 and memory system 110 and the interaction between host system 105 and memory system 110.

[0023] Host system 105 or memory system 110 can include one or more memory dies (e.g., memory device 145). A die seal that protects the memory die from damage during manufacturing can be around each memory die. Additionally, as described herein, a conductive antenna can be around the boundary edge of the die seal. The conductive antenna can be made of a conductive material and can include one or more segments. In some instances, the gap between segments of two or more segments of the conductive antenna can be located at a corner of the die seal (e.g., a corner can refer to where two walls of the die seal meet). Additionally, each segment of the conductive antenna can be coupled to a sensing circuit.

[0024] In some instances, each sensing circuit can further be coupled to a component of the memory die or an external test device. During or after manufacturing, the test device or the memory die can enter a test mode and detect a signal generated by the sensing circuit. If at least a portion of the die seal is not covered by a passivation layer and is exposed to a plasma process during manufacturing, charge can accumulate in the conductive antenna, and the sensing circuit will generate a signal in response. The signal can indicate a lateral over-etch or misalignment of the passivation layer deposited on the memory die and potential plasma-induced charging on the die seal. When the signal is detected, the machine or process can be adjusted so that over-etching or misalignment of the passivation layer does not occur on the next wafer.

[0025] Figure 1 Illustrate a specific use case for the disclosed plasma-induced damage detection for DRAM memory architectures. However, it should be understood that the components and methods for plasma-induced damage detection described herein can be applied to any type of integrated circuit, including but not limited to integrated circuits included in Figure 1 other memory architectures not discussed herein (e.g., NAND memory architectures or 3-D cross-point memory architectures).

[0026] In addition to its applicability in the systems as described herein, techniques for plasma-induced damage detection for memory dies can generally be implemented to improve the sustainability of various electronic devices and systems. As the use of electronic devices has become more widespread, the amount of energy used and the environmental impact associated with the production and operation of electronic devices have increased. In addition, due to various reasons, the waste associated with the disposal of electronic devices can also be harmful. Implementing the techniques described herein can reduce the impact associated with electronic devices by eliminating over-etching or misalignment of the passivation layer during the manufacture of memory dies, which can result in fewer "bad dies", thereby reducing electronic waste and other benefits.

[0027] Figure 2A and 2B illustrate examples of component diagrams 200 (e.g., component diagrams 200-a and 200-b) that support plasma-induced damage detection for memory dies according to examples disclosed herein. In some examples, component diagrams 200-a and 200-b may implement aspects of system 100 or be implemented by aspects of system 100. For example, component diagrams 200-a and 200-b may include dies 255 (e.g., dies 255-a and 255-b), which may be examples of memory devices 145 as described with reference to Figure 1 described.

[0028] As Figure 2A and 2B shown in, multiple dies 255 may be formed on a wafer 205 (e.g., wafer 205-a or wafer 205-b). The wafer 205 may be described as a semiconductor substrate composed of a material such as silicon, germanium, silicon-germanium alloy, gallium arsenide, or gallium nitride. In addition to the dies 255, other components may be formed on the wafer 205. For example, die seals 215 (e.g., die seals 215-a and 215-b) may be formed on the wafer 205. The die seals 215 may be described as structures whose purpose is to protect the dies 255 during manufacture. In some examples, during manufacture, the wafer 205 may be cut along scribe lines 210 (e.g., scribe lines 210-a or 210-b) to separate the dies 255 from each other, and the die seals 215 may provide structural support to the dies 255 such that the dies 255 do not incur any damage due to the cutting. For different applications, it may be beneficial to break the wafer 205 into smaller chunks. To reduce the stress on the wafer 205 during cutting, scribe lines 210 (or stress lines) may be formed between the dies 255 of the wafer 205. When a force is applied to the wafer 205, the stress may concentrate along the scribe lines 210, causing a fracture along the scribe lines 210, thereby separating the dies 255 from each other.

[0029] In some instances, the die seal 215 can surround the corresponding die 255. In Figure 2A and 2B instances, the die seal 215 can include four connected walls that can form a rectangular shape, and each wall of the die seal 215 can include at least four surfaces. A first surface of the die seal 215 can be adjacent to (or coupled to) the wafer 205, a second surface of the die seal 215 can be opposite the first surface, a third surface of the die seal 215 can be adjacent to (or coupled to) the corresponding die 255, and a fourth surface of the die seal 215 can be opposite the third surface. Thus, the die seal 215 can contact the corresponding die 255 via the third surfaces of the four walls of the die seal 215. Additionally, in some instances, the first surface of the die seal 215 can be flush with the bottom surface of the die 255, and the second surface of the die seal 215 can be flush with the top surface of the die 255.

[0030] In some instances, the die seal 215 can be formed in the layer 240. For example, in Figure 2A instances, the die seal 215-a can include the layer 240-a, the layer 240-b, the layer 240-c, and the layer 240-d, and in Figure 2B instances, the die seal 215-b can include the layer 240-e, the layer 240-f, the layer 240-g, and the layer 240-h. The layer 240-a and the layer 240-e can be the topmost metal layers of the die seal 215, and the layer 240-d and the layer 240-h can be the bottommost metal layers of the die seal 215. In some instances, the die 255 can also include multiple layers, and each layer 240 of the die seal 215 can correspond to one or more layers of the die 255 (or be at the same level as them). In some instances, the die seal 215 can include a conductive material, such as copper, silver, aluminum, graphite, etc., and in some instances, each layer 240 of the die seal 215 can include a different conductive material or the same conductive material. Additionally, in Figure 2A and 2B the layers 240 of the die seal 215 are shown as uniform and can be associated with the same thickness or width. However, it can be understood that the layers 240 of the die seal 215 can be non-uniform. For example, the layer 240-a can be associated with a first width, and the layer 240-b can be associated with a second width. The second width can be greater than the first width, causing the layer 240-b to extend more into the space of the die 255-a than the layer 240-a. That is, the third surfaces of the four walls of the die seal 215 can be as Figure 2A and 2B illustrated as smooth.

[0031] As described herein, another component that may be formed on the wafer 205 may be a conductive antenna 220 (e.g., conductive antenna 220-a or conductive antenna 220-b). The conductive antenna 220 may be described as a structure whose purpose is to detect the charging (e.g., plasma-induced charging) of the die seal 215, and similar to the die seal 215, the conductive antenna 220 may comprise a conductive material such as copper, silver, aluminum, graphite, etc. In some instances, the conductive antenna 220 may surround the die seal 215. However, in some instances, the conductive antenna 220 may not be in direct contact with the die seal 215. An insulator 260 (e.g., insulator 260-a or insulator 260-b) made of a dielectric material or any other type of insulating material may be between the die seal 215 and the conductive antenna 220. The insulator 260 may separate the two conductive structures such that there is no charge exchange between the two conductive structures. In some instances, the insulator 260 may be coupled to one or more layers 240 of the die seal 215 and the conductive antenna 220. Additionally, the conductive antenna 220 may comprise a plurality of segments separated from each other by a gap 225. Figure 2A and Figure 2B illustrate different segmented examples of the conductive antenna 220.

[0032] In Figure 2A it, the conductive antenna 220-a may be split into 4 segments (e.g., the first segment (segment 1), the second segment (segment 2), the third segment (segment 3), and the fourth segment (segment 4)), and each segment may be parallel to at least one wall of the die seal 215 (e.g., the fourth surface of the corresponding wall of the die seal 215) or fastened in a fixed position relative to at least one wall of the die seal 215. In some instances, the shape of the conductive antenna 220-a may generate a perimeter (e.g., square or rectangle) around the die 255-a, for example. In the case where the die 255-a is square, the first segment may be parallel to the second segment and perpendicular to the third and fourth segments. Additionally, if the shape of the conductive antenna 220-a is rectangular, the lengths of the fourth and third segments may be different from the lengths of the first and second segments. For example, the lengths of the fourth and third segments may be longer than the lengths of the first and second segments.

[0033] As Figure 2AAs shown, the gaps 225-a that separate the segments from each other may correspond to regions (e.g., 2 regions) where the third segment does not contact the insulator 260-a coupled to the corresponding wall of the die seal 215-a (e.g., at either end of the third segment) and regions (e.g., 2 regions) where the fourth segment does not contact the insulator 260-a coupled to the corresponding wall of the die seal 215-a (e.g., at either end of the fourth segment). Additionally, in some instances, one or more of the segments may contact the insulator 260-a around at least two walls of the die seal 215-a. For example, the first and second segments may wrap around 2 corners of the die seal 215. Although Figure 2A the gaps 225-a between the segments are shown at specific locations, the gaps 225-a are positioned at different locations in the conductive antenna 220-a. For example, the die 255-a in the lower left corner and the die 255-a in the lower right corner show alternative placements of the gaps 225-a. The segments of the conductive antenna can be formed by placing the gaps 225-b in any combination of positions around the die.

[0034] In Figure 2B , the conductive antenna 220-b may be split into 8 segments (e.g., a first segment (segment 1), a second segment (segment 2), a third segment (segment 3), a fourth segment (segment 4), a fifth segment (segment 5), a sixth segment (segment 6), a seventh segment (segment 7), and an eighth segment (segment 8)), and each segment may be parallel to the wall of the die seal 215-b (e.g., the fourth surface of the corresponding wall of the die seal 215-b). In some instances, a pair of segments may be adjacent to the same wall of the die seal 215-b. For example, the first and second segments may be adjacent to the same wall. In some instances, the shape of the conductive antenna 220-b may be square or rectangular. In such cases, the first and second segments may be parallel to the third and fourth segments and perpendicular to the fifth, sixth, seventh, and eighth segments. In some instances, the lengths of the first, second, third, fourth, fifth, sixth, seventh, and eighth segments may be different from each other.

[0035] As Figure 2B shown, the gaps 225-b that separate the segments from each other may correspond to regions where the segments of the conductive antenna 220-b do not contact the insulator 260-b coupled to the corresponding wall of the die seal 215-b. In some instances, one or more of the segments may contact the insulator 260-b coupled to at least two walls of the die seal 215-b. For example, the first, second, third, and fourth segments may wrap around the corners of the die seal 215. Although Figure 2A and 2B the shape of the conductive antenna 220 shown is rectangular or square, it should be understood that the conductive antenna 220 can form not only rectangular or square shapes, but other conductive antenna shapes are also possible. AlthoughFigure 2B The gap 225-b between segments at a specific location is shown, but the gap 225-b is located at different positions in the conductive antenna. For example, the die 255-b in the lower left corner and the die 255-b in the lower right corner show alternative placements of the gap 225-b. The segments of the conductive antenna can be formed by placing the gap 225-b in any combination of positions around the die.

[0036] In Figure 2A and Figure 2B both, the conductive antenna 220 (e.g., conductive antenna 220-a and conductive antenna 220-b) can be located in the topmost metal layer. For example, as Figure 2A and Figure 2B shown, the conductive antenna 220 can be at the same level as the layer 240-a or layer 240-e of the die seal 215. In some instances, the layer 240-a and layer 240-e can be flush with the topmost metal layer of the die 255.

[0037] In addition to the die seal 215 and the conductive antenna 220, a passivation layer 230 (e.g., passivation layer 230-a and passivation layer 230-b) can also be formed. The passivation layer 230 can be formed on the top surface of each die 255 and can be described as a protective barrier for the die 255. Additionally, the passivation layer 230 can include a dielectric material such as polyimide. In some instances, the passivation layer 230 can prevent the top surface of the die 255 from being exposed to plasma during manufacturing. As Figure 2A and 2B shown, at least a portion of the conductive antenna 220 may not be covered by the passivation layer 230. In such instances, during a plasma process (e.g., during etching or deposition), the conductive antenna 220 can accumulate charge due to its conductive nature. In some instances, the conductive antenna 220 can be coupled to a sensor 235 (e.g., sensor 235-a and second sensor 235-b), and the sensor 235 can generate a signal based on the charge accumulated in the conductive antenna 220. The signal can indicate that the die 255 is experiencing plasma-induced damage. In other words, the signal can indicate that charge has accumulated in the die seal 215 from the plasma process and has rapidly discharged through the wafer 205, potentially damaging one or more components of the die 255.

[0038] When the signal is detected, the die 255 or a test device coupled to the sensor 235 can determine that plasma-induced damage has occurred on the die 255. In the case where the conductive antenna 220 includes multiple segments, the die 255 or a test device coupled to the sensor 235 can also determine the location of over-etching of the passivation layer based on which segment or segments caused the signal. For example, if Figure 2AIf the first coupled sensing circuit is the only one generating the signal, then the die 255 or the test device coupled to the sensor 235 can determine that the etching of the passivation layer has shifted to the right. Using this information, the processes and machines involved in passivation layer deposition or etching can be adjusted or offset to ensure passivation layer alignment. In some instances, increasing the number of segments can allow the die 255 or the test device coupled to the sensor 235 to increase the granularity of the locations of passivation layer over-etching.

[0039] In some instances, the conductive antenna 220 may not be coupled to the insulator 260. For example, the conductive antenna 220 may be positioned at a distance (e.g., distance x) from the insulator 260, but may still be at the same level as the topmost metal layer 240, as Figure 2A and 2B illustrated by the conductive antenna 220 shown in the dashed box in. In another instance, the conductive antenna 220 may be positioned at the same level as a layer 240 below the topmost metal layer 240. For example, the conductive antenna 220 may be positioned at the same level as layer 240-b or layer 240-f of the die seal 215, as Figure 2A and 2B illustrated by the conductive antenna 220 shown in the dashed box in. As Figure 2A and 2B illustrated in, the conductive antenna positions are merely exemplary, and it is understood that the conductive antenna 220 can be positioned in any of the layers 240 of the die seal 215 or at any distance from the die seal 215.

[0040] In addition, other conductive antennas 220 may be formed around the die seal 215. The other conductive antennas 220 may also be coupled to the sensor 235, which is configured to generate a signal based on the charge accumulated in the respective conductive antennas 220. The positions of the other conductive antennas 220 relative to the die seal 215 may be slightly different from each other. For example, multiple conductive antennas 220 may be positioned at different layers 240 of the die seal 215, at different distances from the die seal 215, or a combination of both. Incorporating other conductive antennas 220 at different positions can allow for full characterization of the regions of the die seal 215 that may be vulnerable to plasma processes (e.g., may be exposed to plasma). Similar to increasing the number of segments of the conductive antenna 220, increasing the number of conductive antennas 220 can also allow the die 255 or the test device coupled to the sensor 235 to increase the granularity of the locations of over-etching.

[0041] Figure 3A and 3BAn example of a circuit 300 (e.g., circuit 300-a and circuit 300-b) that supports plasma-induced damage detection of a memory die according to an example disclosed herein is shown. In some examples, circuit 300-a and circuit 300-b may implement aspects of system 100 and component diagram 200 (e.g., component diagram 200-a and component diagram 200-b) or be implemented by them. For example, circuit 300-a and circuit 300-b may include a conductive antenna 320, which is an example of the conductive antenna 220 described with reference to Figure 2A and 2B . In addition, circuit 300-b may include a die 355, which may be an example of the memory device 145 or die 255 described with reference to Figure 1 , 2A and 2B.

[0042] As described with reference to Figure 2A and 2B , the conductive antenna 320 may be coupled to a sensing circuit, and the sensing circuit may be configured to generate a signal based on the charge accumulated in the conductive antenna 320 due to exposure to plasma during manufacturing. In some examples, the sensing circuit may include a sensing circuitry 309 (e.g., sensing circuitry 309-a and sensing circuitry 309-b). The sensing circuitry 309 may be coupled to ground and the conductive antenna 320. As shown in Figure 3A and 3B , the sensing circuitry 309 may be an example of an antifuse 310 (e.g., antifuse 310-a or antifuse 310-b). The antifuse 310 may be an example of a programmable memory and may include a fusible dielectric material (e.g., a fusible oxide material). If the conductive antenna 320 is not exposed to plasma during manufacturing, little or no charge will accumulate in the conductive antenna 320, and thus, little or no voltage will be applied to the antifuse 310. In response to no voltage being applied to the antifuse 310, the antifuse 310 will not fuse and will act as a capacitor. On the other hand, if the conductive antenna 320 is exposed to plasma during manufacturing, charge may accumulate in the conductive antenna 320 and discharge to the antifuse 310, causing the antifuse 310 to fuse. When fused, the antifuse 310 may act as a resistor. Alternatively, the sensing circuitry 309 may include a fuse or one-time programmable read-only memory (ROM) not shown in Figure 3A and 3B .

[0043] In some examples, the sensing circuit may also include a resistor 315 and a transistor 325. The input of the resistor 315 may be coupled to the conductive antenna 320, and the output of the resistor 315 may be coupled to the first input node of the transistor 325. In addition, the second input node (or gate) and the output node of the transistor 325 may be coupled to such asFigure 3A coupled to the plasma detection assembly 330 of the test device 345 shown in or the die 355 (e.g., the die surrounded by the conductive antenna 320) shown in Figure 3B When blown, the antifuse 310 can create a conductive path from the conductive antenna 320 to the resistor 315, allowing current to flow from the conductive antenna 320 to the resistor 315 in the case where charge has accumulated in the conductive antenna 320. In some instances, the resistor 315 can be an example of a current-limiting resistor (e.g., a current-limiting resistor). An example of a current-limiting resistor can be a ballast resistor, which can increase its resistance as the current increases and decrease its resistance as the current decreases. Then, the current can flow to the transistor 325. Additionally, in some instances, the transistor 325 can be an example of a triple-well transistor.

[0044] In Figure 3A , the second input (or gate) of the transistor 325-a can be coupled to the test device 345, and the output of the transistor 325-a can be coupled to the pad 340 located on the outer surface of the wafer 305. During the test mode, the test device 345 can apply a voltage to the second input of the transistor 325-a, allowing any current from the resistor 315-a to pass through to the pad 340. Then, the test device 345 can perform a probe test. During the probe test, the test device 345 can touch the pad 340 with the probe 335 and measure the current or voltage applied to the pad 340. If the voltage or current exceeds a threshold, then the test device 345 can determine that the conductive antenna 320-a has been exposed to plasma and detect potential plasma-induced damage to the die. Alternatively, if the voltage or current does not exceed the threshold, then the test device 345 can determine that the conductive antenna 320-a has not been exposed to plasma, and may not detect plasma-induced damage to the die.

[0045] In Figure 3BIn [the figure], the second input (or gate) of transistor 325-b and the output of transistor 325-b can be coupled to the plasma detection component 330 of the die. During the test mode, the plasma detection component can apply a voltage to the second input of transistor 325-b, thereby allowing any current from resistor 315-b to pass through to the plasma detection component 330. The plasma detection component 330 can then measure the current or voltage output from transistor 325-b. If the voltage or current exceeds a threshold, then the plasma detection component 330 can determine that the conductive antenna 320-b is exposed to plasma and detect potential plasma-induced damage to the die. Alternatively, if the voltage or current does not exceed the threshold, then the plasma detection component 330 can determine that the conductive antenna 320-b is not exposed to plasma and may not detect plasma-induced damage to the die. In some instances, the die seal 350 surrounding the die 355 can include a tunnel or hole such that the circuitry of the sensing circuit can pass through the die seal 350 and be coupled to the plasma detection component 330. In alternative instances, the plasma detection component 330 can be located outside the die 355. In such instances, the circuitry of the sensing circuit may not pass through the die seal 350, and the die seal 350 may not include a tunnel or gap.

[0046] As referenced Figure 2A and 2B described, the conductive antenna 320 can include multiple segments. In such cases, each segment can be coupled to a corresponding sensing circuit. The segmentation of the conductive antenna 320 can allow the test device 345 or the die 355 to determine how the passivation layer may be misaligned or over-etched. For example, if the sensing circuit associated with the conductive antenna coupled to the left wall of the die seal detects plasma-induced damage and the sensing circuits associated with the conductive antennas coupled to the right wall of the die seal, the die 355, or the test device 345 do not detect plasma-induced damage, then the die 355 or the test device 345 can determine that the deposition or etching of the passivation layer has shifted to the right. Using this information, the processes and machines involved in passivation layer deposition or etching can be adjusted to ensure passivation layer alignment (fully covering the die 355).

[0047] A device is described. An overview of aspects of the device as described herein is provided below:

[0048] Aspect 1: A memory device, comprising: a memory die coupled to a substrate; a die seal structure surrounding the memory die and coupled to the substrate, the die seal structure including multiple layers; an insulator material coupled to at least one of the multiple layers of the die seal structure; a conductive material coupled to the insulator material; and a sensing circuit coupled to the conductive material, the sensing circuit configured to generate a signal based on charge accumulated in the conductive material.

[0049] Aspect 2: The memory device according to Aspect 1, wherein the die encapsulation structure includes: a first surface adjacent to the substrate; a second surface opposite the first surface; a third surface adjacent to the memory die; and a fourth surface opposite the third surface, wherein the conductive material is coupled to the fourth surface of the die encapsulation structure.

[0050] Aspect 3: The memory device according to any one of Aspects 1 and 2, wherein the conductive material includes one or more segments separated from each other by one or more gaps.

[0051] Aspect 4: The memory device according to Aspect 3, wherein the die encapsulation structure includes a plurality of walls surrounding the memory die, and each wall of the plurality of walls includes a plurality of surfaces.

[0052] Aspect 5: The memory device according to Aspect 4, wherein the one or more segments include: a first segment fastened in a fixed position relative to a surface of a first wall of the plurality of walls of the die encapsulation structure; a second segment fastened in a fixed position relative to a surface of a second wall of the plurality of walls of the die encapsulation structure; a third segment fastened in a fixed position relative to a surface of a third wall of the plurality of walls of the die encapsulation structure; and a fourth segment fastened in a fixed position relative to a surface of a fourth wall of the plurality of walls of the die encapsulation structure.

[0053] Aspect 6: The memory device according to Aspect 5, wherein the first segment is parallel to the second segment and perpendicular to the third segment and the fourth segment, and the length of the first segment and the length of the second segment are shorter than the length of the third segment and the length of the fourth segment.

[0054] Aspect 7: The memory device according to any one of Aspects 4 to 6, wherein the one or more segments include: a first segment fastened in a fixed position relative to a surface of a first wall of the plurality of walls of the die encapsulation structure and a surface of a second wall of the plurality of walls of the die encapsulation structure; a second segment fastened in a fixed position relative to the second wall of the plurality of walls of the die encapsulation structure; a third segment fastened in a fixed position relative to a surface of a third wall of the plurality of walls of the die encapsulation structure and a surface of a fourth wall of the plurality of walls of the die encapsulation structure; and a fourth segment fastened in a fixed position relative to the surface of the fourth wall.

[0055] Aspect 8: The memory device according to any one of Aspects 3 to 7, wherein each of the one or more segments is coupled to a corresponding sensing circuit.

[0056] Aspect 9: The memory device according to any one of aspects 1 to 8, wherein the sensing circuit includes: a programmable memory coupled to ground and the conductive material; and a resistor coupled to the programmable memory and a first node of the transistor.

[0057] Aspect 10: The memory device according to aspect 9, wherein a second node and a third node of the transistor are coupled to a test device external to the memory die or a component inside the memory die.

[0058] Aspect 11: The memory device according to any one of aspects 9 and 10, wherein the programmable memory includes a fusible dielectric material.

[0059] Aspect 12: The memory device according to any one of aspects 1 to 11, wherein the memory device further includes: a dielectric material partially covering the conductive material, wherein the conductive material and the sensing circuit are configured to detect a partial coverage of the dielectric material on the die encapsulation structure based on the dielectric material partially covering the conductive material.

[0060] Aspect 13: The memory device according to any one of aspects 1 to 12, comprising: a second conductive material fastened in a fixed position relative to a second layer of the die encapsulation structure different from the at least one layer of the plurality of layers; and a second sensing circuit coupled to the second conductive material, the second sensing circuit being configured to generate a second signal based on charge accumulated in the second conductive material.

[0061] Aspect 14: The memory device according to any one of aspects 1 to 13, comprising: a second conductive material coupled to the conductive material, wherein a surface of the second conductive material oriented toward the die encapsulation structure is at a first distance from a surface of the die encapsulation structure, and a surface of the conductive material oriented toward the die encapsulation structure is at a second distance from the die encapsulation structure; and a second sensing circuit coupled to the second conductive material, the second sensing circuit being configured to generate a second signal based on charge accumulated in the second conductive material.

[0062] Aspect 15: The memory device according to any one of aspects 1 to 14, wherein the conductive material and the sensing circuit are configured to detect the charge accumulated in the conductive material based on at least a portion of the conductive material being exposed to plasma.

[0063] Aspect 16: The memory device according to any one of aspects 1 to 14, wherein the at least one layer includes the topmost metal layer of the plurality of layers.

[0064] Describe a device. An overview of aspects of the device as described herein is provided below:

[0065] Aspect 17: A memory device comprising: a memory die coupled to a substrate; a die seal structure surrounding the memory die and coupled to the substrate; an insulator material coupled to the die seal structure; a conductive material coupled to the insulator material and comprising a plurality of segments separated from each other by one or more gaps; and a plurality of sensing circuits, each sensing circuit coupled to a respective one of the plurality of segments and configured to generate a signal based on charge accumulated in the respective segment.

[0066] Aspect 18: The memory device according to aspect 17, wherein the die seal structure comprises a plurality of walls surrounding the memory die, each of the plurality of walls comprising a plurality of surfaces.

[0067] Aspect 19: The memory device according to aspect 18, wherein the plurality of segments comprises: a first segment fastened in a fixed position relative to a surface of a first wall of the plurality of walls of the die seal structure; a second segment fastened in a fixed position relative to a surface of a second wall of the plurality of walls of the die seal structure; a third segment fastened in a fixed position relative to a surface of a third wall of the plurality of walls of the die seal structure; and a fourth segment fastened in a fixed position relative to a surface of a fourth wall of the plurality of walls of the die seal structure.

[0068] Aspect 20: The memory device according to aspect 19, wherein the first segment is parallel to the second segment and perpendicular to the third segment and the fourth segment, and the length of the first segment and the length of the second segment are shorter than the length of the third segment and the length of the fourth segment.

[0069] Aspect 21: The memory device according to any one of aspects 18 to 19, wherein the plurality of segments comprises: a first segment contacting a surface of a first wall of the plurality of walls of the die seal structure and a surface of a second wall of the plurality of walls of the die seal structure; a second segment contacting the surface of the second wall of the plurality of walls of the die seal structure; a third segment contacting a surface of a third wall of the plurality of walls of the die seal structure and a surface of a fourth wall of the plurality of walls of the die seal structure; and a fourth segment contacting the surface of the fourth wall.

[0070] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0071] The terms “electrically connected,” “conductively contacted,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electrically connected (e.g., conductively contacted, connected, coupled) to each other if there is any circuit path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are electrically connected (e.g., conductively contacted, connected, coupled) to each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path that includes intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components (e.g., switches or transistors).

[0072] The term “coupled” (e.g., “electrically coupled”) may refer to a condition of transitioning from an open circuit relationship between components where signals are not currently capable of being transferred (e.g., via a conductive path) between the components to a closed circuit relationship between the components where signals are capable of being transferred (e.g., via a conductive path) between the components. When a component (e.g., a controller) couples other components together, the component may initiate a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0073] The terms “layer” and “level” may refer to an organization (e.g., strata, sheets) of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure where two dimensions are greater than the third dimension, such as a thin film. A layer or level may include different elements, components, and / or materials. In some instances, a layer or level may be composed of two or more sub-layers or sub-levels.

[0074] As used herein, the term “electrode” may refer to an electrical conductor and, in some instances, may be used as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or an analog thereof that provides a conductive path between components of a memory array.

[0075] The devices (including memory arrays) discussed in this document may be formed on a semiconductor substrate (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic.

[0076] The switching components (e.g., transistors) discussed in this document may be field-effect transistors (FETs) and may include a source (e.g., source terminal), a drain (e.g., drain terminal), a channel between the source and the drain, and a gate (e.g., gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate, which in some instances may cause the channel to become conductive. The switching components may be examples of n-type FETs or p-type FETs.

[0077] The descriptions set forth in this document describe example configurations in conjunction with the accompanying drawings and do not represent all examples that can be implemented or are within the scope of the claims. The detailed description includes specific details to provide an understanding of the described technology. However, the technology can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0078] In the figures, similar components or features may have the same reference labels. Similar components may be distinguished by one or more dashes after the reference label and additional labels that distinguish between the similar components. When only the first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label, regardless of the additional reference labels.

[0079] The functions described in this document may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described in this document may be implemented using software, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions may be physically located at various positions, including being distributed such that parts of the functions are implemented at different physical locations.

[0080] The illustrative blocks and modules described herein can be implemented or performed by a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof, designed to perform the functions described herein. The processor can be an example of a microprocessor, a controller, a microcontroller, a state machine, or other types of processors. The processor can also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0081] As used herein, and as used in the claims, the "or" used in a list of items (e.g., a list that begins with a phrase such as "at least one" or "one or more") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0082] Computer-readable media includes both non-transitory computer storage media and communication media, where the communication media includes any media that facilitates the transfer of a computer program from one place to another. The non-transitory storage media can be any available media or combination of media accessible by a computer. By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage, or other magnetic storage media devices, or any other non-transitory media or media combination that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer or a processor.

[0083] Descriptions and drawings are provided so that those of ordinary skill in the art can make or use the present disclosure. Those of ordinary skill in the art will appreciate various modifications to the present disclosure, and without departing from the scope of the present disclosure, the techniques disclosed herein can be applied to other variations. Accordingly, the present disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory die coupled to the substrate; a die sealing structure surrounding the memory die and coupled to the substrate, the die sealing structure comprising a plurality of layers; an insulator material coupled to at least one of the plurality of layers of the die encapsulation structure; a conductive material coupled to the insulator material; as well as A sensing circuit is coupled to the conductive material, the sensing circuit being configured to generate a signal based on charge accumulated in the conductive material.

2. The memory device of claim 1 , wherein the die sealing structure comprises: a first surface adjacent to the substrate; a second surface, which is opposite to the first surface; a third surface adjacent to the memory die; as well as a fourth surface opposite to the third surface, wherein the conductive material is coupled to the fourth surface of the die sealing structure.

3. The memory device of claim 1, wherein the conductive material comprises one or more segments separated from each other by one or more gaps. 4 . The memory device of claim 3 , wherein the die sealing structure comprises a plurality of walls surrounding the memory die, each of the plurality of walls comprising a plurality of surfaces.

5. The memory device of claim 4, wherein the one or more segments comprise: a first segment secured in a fixed position relative to a surface of a first wall of the plurality of walls of the die seal structure; a second segment secured in a fixed position relative to a surface of a second wall of the plurality of walls of the die seal structure; a third segment secured in a fixed position relative to a surface of a third wall of the plurality of walls of the die seal structure; as well as A fourth segment is secured in a fixed position relative to a surface of a fourth wall of the plurality of walls of the die seal structure.

6. The memory device of claim 5, wherein: The first segment is parallel to the second segment and perpendicular to the third segment and the fourth segment, and The length of the first segment and the length of the second segment are shorter than the length of the third segment and the length of the fourth segment.

7. The memory device of claim 4, wherein the one or more segments comprise: a first section secured in a fixed position relative to a surface of a first wall of the plurality of walls of the die sealing structure and a surface of a second wall of the plurality of walls of the die sealing structure; a second segment secured in a fixed position relative to the surface of the second wall of the plurality of walls of the die seal structure; a third section secured in a fixed position relative to a surface of a third wall of the plurality of walls of the die sealing structure and a surface of a fourth wall of the plurality of walls of the die sealing structure; as well as A fourth section is secured in a fixed position relative to the surface of the fourth wall.

8. The memory device of claim 3, wherein each segment of the one or more segments is coupled with a corresponding sensing circuit.

9. The memory device of claim 1 , wherein the sensing circuit comprises: a programmable memory coupled to ground and the conductive material; as well as A resistor is coupled to the programmable memory and the first node of the transistor.

10. The memory device of claim 9, wherein the second node and the third node of the transistor are coupled to a test device external to the memory die or a component internal to the memory die.

11. The memory device of claim 9, wherein the programmable memory comprises a fusible dielectric material.

12. The memory device of claim 1, wherein the memory device further comprises: A dielectric material partially covering the conductive material, wherein the conductive material and the sensing circuit are configured to detect partial coverage of the dielectric material on the die seal structure based on the dielectric material partially covering the conductive material.

13. The memory device of claim 1, comprising: a second conductive material secured in a fixed position relative to a second layer of the die encapsulation structure that is different from the at least one layer of the plurality of layers of the die encapsulation structure; as well as A second sensing circuit is coupled to the second conductive material, the second sensing circuit being configured to generate a second signal based on charge accumulated in the second conductive material.

14. The memory device of claim 1, comprising: a second conductive material coupled to the conductive material, wherein a surface of the second conductive material oriented toward the die sealing structure is a first distance from a surface of the die sealing structure, and a surface of the conductive material oriented toward the die sealing structure is a second distance from the die sealing structure; as well as A second sensing circuit is coupled to the second conductive material, the second sensing circuit being configured to generate a second signal based on charge accumulated in the second conductive material.

15. The memory device of claim 1, wherein the conductive material and the sensing circuit are configured to detect the charge accumulated in the conductive material based on exposure of at least a portion of the conductive material to a plasma.

16. A memory device comprising: a memory die coupled to the substrate; a die seal structure surrounding the memory die and coupled to the substrate; an insulator material coupled to the die sealing structure; a conductive material coupled to the insulator material and comprising a plurality of segments separated from one another by one or more gaps; as well as A plurality of sensing circuits, each sensing circuit is coupled to a respective segment of the plurality of segments and is configured to generate a signal based on charge accumulated in the respective segment.

17. The memory device of claim 16, wherein the die sealing structure comprises a plurality of walls surrounding the memory die, each of the plurality of walls comprising a plurality of surfaces.

18. The memory device of claim 17, wherein the plurality of segments comprises: a first segment secured in a fixed position relative to a surface of a first wall of the plurality of walls of the die seal structure; a second segment secured in a fixed position relative to a surface of a second wall of the plurality of walls of the die seal structure; a third segment secured in a fixed position relative to a surface of a third wall of the plurality of walls of the die seal structure; as well as A fourth segment is secured in a fixed position relative to a surface of a fourth wall of the plurality of walls of the die seal structure.

19. The memory device of claim 18, wherein: The first segment is parallel to the second segment and perpendicular to the third segment and the fourth segment, and The length of the first segment and the length of the second segment are shorter than the length of the third segment and the length of the fourth segment.

20. The memory device of claim 17, wherein the plurality of segments comprises: a first section secured in a fixed position relative to a surface of a first wall of the plurality of walls of the die sealing structure and a surface of a second wall of the plurality of walls of the die sealing structure; a second segment secured in a fixed position relative to the surface of the second wall of the plurality of walls of the die seal structure; a third section secured in a fixed position relative to a surface of a third wall of the plurality of walls of the die sealing structure and a surface of a fourth wall of the plurality of walls of the die sealing structure; as well as A fourth section is secured in a fixed position relative to the surface of the fourth wall.

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