LOD effect test structure and LOD effect test circuit structure
By setting up a LOD effect test unit with multiple common gate electrodes on the substrate, the problems of high cost of LOD effect testing and process loading effects in the prior art are solved, and efficient LOD effect testing is achieved, reducing the test time and cost.
Patent Information
- Application Number
- CN202510219586.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-05-30
AI Technical Summary
In the prior art, the full set of LOD effect testing units is large in number and the test time is long, resulting in high testing costs. Moreover, multiple LOD effect testing units are arranged at different locations to have process load effects, affecting the accuracy of the test results.
A LOD effect testing structure is provided, including providing at least two test units on the substrate, each test unit includes an active region extending in the first direction and a gate electrode extending in the second direction, a shallow trench isolation is formed between the active regions, a common gate electrode is shared, and a test voltage is provided to the source of the test unit through a control circuit, and a saturated drain current of each test unit is measured and output.
By reducing the number of test structures, one test can output the Idsat values of all test units on the LOD effect test structure, reducing test time, saving test costs, and minimizing the impact of process load effects.
Smart Images
Figure CN120072802A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a LOD effect test structure and a LOD effect test circuit structure. Background Art
[0002] LOD (Length of Diffusion) is the effect of the change in the electrical characteristics of a transistor device caused by the change in the distance between the gate electrode and the Shallow Trench Isolation (STI) in the direction of the channel extension line. When two transistor devices with the same gate electrode length and width have different currents due to different diffusion region lengths, the resulting effect is the LOD stress effect. The LOD stress effect mainly affects the saturated source-drain current (Idsat) and the threshold voltage (Vth) of the device. This effect can be described by the following two layout parameters: SA and SB, where SA is the distance between the gate electrode of the transistor device and the edge of the source (Active Area), and SB is the distance between the gate electrode of the transistor device and the edge of the drain (Active Area).
[0003] In the related art, the number of complete LOD effect test units (testkey array) is large, and the test time is long, resulting in a high test cost.
[0004] In view of the above technical problems, this application provides a new LOD effect test structure and a LOD effect test circuit structure. Summary of the Invention
[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.
[0006] In view of the existing problems, on the one hand, this application provides a LOD effect test structure, including:
[0007] A substrate;
[0008] At least two test units located on the substrate, each test unit including: an active area extending in a first direction and a gate electrode located on the active area and extending in a second direction perpendicular to the first direction;
[0009] The at least two test units are arranged in the second direction, a shallow trench isolation is formed between their active areas, and they share the same gate electrode;
[0010] At least one of the length of the active region of the at least two test units in the first direction, the width of the active region in the second direction, and the width of the gate electrode in the first direction is different.
[0011] Exemplarily, it further includes at least four first virtual active regions. One of the first virtual active regions is disposed on each side of the active region of each test unit in the first direction. The first virtual active regions extend in the first direction and the spacing between adjacent first virtual active regions and the active region in the second direction is equal.
[0012] Exemplarily, the boundaries of the first virtual active regions on the same side away from the active region are aligned in the second direction.
[0013] Exemplarily, it further includes at least two second virtual active regions, which are respectively disposed on one side of the at least two test units away from the adjacent test units in the second direction, and the at least two second virtual active regions extend in the first direction and the spacing between the adjacent second virtual active regions and the active region in the second direction is equal.
[0014] Exemplarily, the lengths of the active regions of the at least two test units in the first direction are the same, and the widths in the second direction are different;
[0015] The widths of the gate electrodes of the at least two test units in the first direction are the same.
[0016] Exemplarily, the lengths of the active regions of the at least two test units in the first direction are different, and the widths in the second direction are the same;
[0017] The widths of the gate electrodes of the at least two test units in the first direction are the same.
[0018] Exemplarily, the lengths of the active regions of the at least two test units in the first direction are the same, and the widths in the second direction are the same;
[0019] The widths of the gate electrodes of the at least two test units in the first direction are different.
[0020] Exemplarily, it further includes virtual gate electrodes disposed on both sides of the gate electrode and spaced apart from the gate electrode.
[0021] Exemplarily, the LOD effect test structure is disposed in a dicing channel.
[0022] On the other hand, the present application provides a LOD effect test circuit structure, including:
[0023] The LOD effect test structure according to any one of the above;
[0024] A control circuit;
[0025] Among them, the control circuit is configured to sequentially provide a test voltage to the source electrode of each test unit in the LOD effect test structure and turn on the transistor of the test unit, so as to measure and output the saturation drain current of each test unit.
[0026] The LOD effect test structure and the LOD effect test circuit structure of the present application reduce the number of test structures. The Idsat values of all test units on the LOD effect test structure can be output in one test, reducing the test time and saving the test cost. Description of the Drawings
[0027] The following drawings of the present application are hereby incorporated as part of the present application for understanding the present application. The embodiments of the present application and their descriptions shown in the drawings are used to explain the principles of the present application.
[0028] In the drawings:
[0029] Figure 1 Shows the layout of the LOD effect test structure of a specific embodiment of the present application;
[0030] Figure 2 Shows the layout of the LOD effect test structure of another specific embodiment of the present application;
[0031] Figure 3 Shows the layout of the LOD effect test structure of another specific embodiment of the present application;
[0032] Figure 4 Shows the layout of the LOD effect test structure of another specific embodiment of the present application;
[0033] Figure 5 Shows the schematic diagram of the LOD effect test circuit structure of a specific embodiment of the present application. Specific Embodiments
[0034] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present application.
[0035] It should be understood that the present application can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals throughout the drawings denote like elements.
[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be denoted as the second element, component, region, layer or part.
[0037] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein are to be interpreted accordingly.
[0038] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0039] To fully understand the present application, detailed steps and structures will be set forth in the following description in order to explain the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.
[0040] In the related art, there are about 320 complete LOD effect test units (testkey array), and the test time is 5 h / slice, resulting in a relatively high test cost.
[0041] The above-mentioned LOD effect test units can usually only be set in the scribing lane. The LOD effect test units will occupy the space of other monitoring units, and there is a process loading effect when multiple LOD effect test units are set at different positions, which affects the accuracy of the test results and has a great impact on subsequent circuit stress troubleshooting and simulation model data calibration.
[0042] Therefore, in view of the existence of the foregoing technical problems, the present application proposes a LOD effect test structure, including:
[0043] A substrate;
[0044] At least two test units located on the substrate, each test unit includes: an active region extending in a first direction and a gate electrode located on the active region and extending in a second direction perpendicular to the first direction;
[0045] The at least two test units are arranged and set along the second direction, a shallow trench isolation is formed between the active regions of the two, and the two share the same gate electrode;
[0046] Wherein at least one of the length of the active region of the at least two test units in the first direction, the width in the second direction, and the width of the gate electrode in the first direction is different.
[0047] The LOD effect test structure of the present application reduces the number of test structures by setting at least two test units on the substrate, and the Idsat values of all test units on the LOD effect test structure can be output in one test, reducing the test time and saving the test cost.
[0048] Moreover, at least two test units formed in the present application share a gate electrode, which can minimize the influence of the process load effect.
[0049] Embodiment 1
[0050] The following refers to Figures 1 to 4Describe the LOD effect test structure according to an embodiment of the present application. The LOD effect test structure includes: at least two test units located on the substrate, each test unit including: an active region extending in a first direction and a gate electrode located on the active region and extending in a second direction perpendicular to the first direction; the at least two test units are arranged along the second direction, a shallow trench isolation is formed between the active regions of the two, and the two share the same gate electrode; wherein at least one of the lengths of the active regions of the at least two test units in the first direction, the widths in the second direction, and the widths of the gate electrodes in the first direction is different.
[0051] Specifically, by arranging at least two test units on the substrate and making at least one of the lengths of the active regions of the at least two test units in the first direction, the widths in the second direction, and the widths of the gate electrodes in the first direction different, during the test, a voltage Vg can be applied to the gate electrode, and the drains of all test units can be connected together and grounded, and the source of each test unit can be sequentially connected through a control circuit such as a decoder for address traversal, so as to obtain the Idsat values of all test units, thereby verifying the influence of at least one of the diffusion region length, the active region width, and the gate electrode width on the Idsat value.
[0052] Moreover, the at least two test units formed in the present application share a gate electrode, which can minimize the influence of the process load effect.
[0053] In some embodiments, it further includes at least four first virtual active regions. One first virtual active region is respectively arranged on both sides of the active region of each test unit along the first direction. The first virtual active regions extend along the first direction and the spacing between adjacent first virtual active regions and the active region in the second direction is equal.
[0054] Specifically, for each test unit, by respectively arranging first virtual active regions with equal spacing on both sides of its active region along the first direction, and the spacing between all corresponding first virtual active regions and the active region is equal, it can be ensured that the STI stress effect received by each test unit in the first direction is consistent.
[0055] Furthermore, the boundaries of the first virtual active regions on the same side far from the active region are aligned along the second direction, so as to further ensure that the STI stress effect received by each test unit in the first direction is consistent.
[0056] In some embodiments, it further includes at least two second virtual active regions, which are respectively arranged on one side of the at least two test units far from the adjacent test unit along the second direction, and the at least two second virtual active regions extend along the first direction and the spacing between them and the adjacent active region in the second direction is equal.
[0057] Specifically, by setting the second virtual active region and making at least two second virtual active regions extend along the first direction and have equal distances from the adjacent active regions in the second direction, it is ensured that the STI stress effects received by each test unit in the second direction are consistent.
[0058] Furthermore, a second virtual active region is respectively arranged on both sides of the active region of each test unit along the second direction. The second virtual active region extends along the second direction, and the distances between all adjacent second virtual active regions and active regions are equal. Moreover, the same second virtual active region is shared between the active regions of two adjacent test units.
[0059] Thus, by respectively arranging first virtual active regions with equal distances on both the left and right sides of each test unit, and ensuring that the distances between all corresponding second virtual active regions and active regions are equal, and the sides of the first virtual active regions far from the corresponding active regions are aligned along the second direction, and by respectively arranging second virtual active regions with equal distances on both sides of each test unit along the second direction, and ensuring that the distances between all adjacent first virtual active regions and active regions are equal, it is ensured that the STI stress effects received by each test unit are consistent.
[0060] In some embodiments, for the active region of each of the test units, the lengths of the regions on both sides of the gate electrode along the first direction are the same. That is, for the active region of each test unit, SA and SB of this test unit are equal.
[0061] In some embodiments, the active regions of the at least two test units have the same length along the first direction and different widths along the second direction;
[0062] The gate electrodes of the at least two test units have the same width along the first direction.
[0063] In this embodiment, by making the active regions of the at least two test units have the same length along the first direction and different widths along the second direction, and ensuring that the gate electrodes of the at least two test units have the same width along the first direction, the influence of the width of the active region on the Idsat value can be verified by the method of controlling variables.
[0064] In some embodiments, the active regions of the at least two test units have different lengths along the first direction and the same width along the second direction;
[0065] The gate electrodes of the at least two test units have the same width along the first direction.
[0066] In this embodiment, by making the lengths of the active regions of at least two test units different in the first direction and the widths in the second direction consistent, and ensuring that the widths of the gate electrodes of at least two test units in the first direction are consistent, the influence of the length of the diffusion region on the Idsat value can be verified by controlling variables.
[0067] In some embodiments, the lengths of the active regions of the at least two test units are consistent in the first direction and the widths in the second direction are consistent;
[0068] The widths of the gate electrodes of the at least two test units are inconsistent in the first direction.
[0069] In this embodiment, by making the widths of the gate electrodes of at least two test units inconsistent in the first direction and ensuring that the lengths of the active regions of at least two test units are consistent in the first direction and the widths in the second direction are consistent, the influence of the width of the gate electrode on the Idsat value can be verified by controlling variables.
[0070] In some embodiments, the LOD effect test structure is arranged in the dicing channel of the wafer.
[0071] In some embodiments, the widths of the first virtual active regions arranged at the left and right ends of the active region of each test unit are the same as the width of the active region.
[0072] In some embodiments, the width of the active region of each test unit is 0.11 to 10 microns, and the specific width can be set according to the actual situation and is not limited thereto.
[0073] In some embodiments, the width of the gate electrode of each test unit is 0.06 to 2 microns, and the specific width can be set according to the actual situation and is not limited thereto.
[0074] In some embodiments, the length of the active region on either side of the gate electrode is 0.155 to 10 microns, and the specific width can be set according to the actual situation and is not limited thereto.
[0075] In some embodiments, the end of the gate electrode extends beyond the outermost active region by a specified length. Among them, the length by which the end of the gate electrode extends beyond the outermost active region can be set according to the actual situation, and the lengths by which the two ends of the gate electrode extend beyond the corresponding outermost active regions can be equal or unequal, and are not limited thereto. Exemplarily, the lengths by which the two ends of the gate electrode extend beyond the corresponding outermost active regions can both be greater than or equal to 1 micron.
[0076] In some embodiments, it further includes: contact hole structures. One contact hole structure is provided in the source region on one side of the gate electrode of the active region of each test unit, and one contact hole structure is provided in the drain region on the other side of the gate electrode of the active region of each test unit. At least one contact hole structure is respectively provided at two ends of the gate electrode.
[0077] The contact hole structures can be connected to corresponding metal leads, so as to electrically lead out the source electrode of each test unit, electrically lead out the drain electrode of each test unit, and electrically lead out the gate electrode of each test unit.
[0078] In a specific test process, a voltage Vg can be applied to the gate electrode, and the drain electrodes of all the test units after being led out are connected together and grounded. The source electrodes electrically led out of each test unit are sequentially connected through a control circuit such as a decoder for address traversal, so as to obtain the Idsat values of all the test units, thereby verifying the influence of the diffusion region length on the Idsat values.
[0079] In some embodiments, as Figure 1 shown, it further includes dummy gate electrodes located on both sides of the gate electrode and spaced from the gate electrode.
[0080] Among them, the number of dummy gate electrodes on both sides of the gate electrode can be set according to actual situations, and no limitation is imposed thereon. By setting the dummy gate electrodes, it is convenient to realize the manufacturing process of the LOD effect test structure and reduce the process difficulty.
[0081] In some embodiments, the number of test units provided on the substrate is not limited, and the number of test units can be set according to actual situations.
[0082] Exemplarily, as Figure 1As shown, a total of 10 active regions, namely A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10, are sequentially arranged on the substrate. Among them, active region A1 and active region A10 are correspondingly arranged, active region A2 and active region A9 are correspondingly arranged, active region A3 and active region A8 are correspondingly arranged, active region A4 and active region A7 are correspondingly arranged, and active region A5 and active region A6 are correspondingly arranged. The layout parameters of the test unit formed by active region A1 and the gate electrode are (W1, L1, SA1 = SB1), the layout parameters of the test unit formed by active region A2 and the gate electrode are (W1, L1, SA2 = SB2), the layout parameters of the test unit formed by active region A3 and the gate electrode are (W1, L1, SA3 = SB3), the layout parameters of the test unit formed by active region A4 and the gate electrode are (W1, L1, SA4 = SB4), the layout parameters of the test unit formed by active region A5 and the gate electrode are (W1, L1, SA5 = SB5), the layout parameters of the test unit formed by active region A6 and the gate electrode are (W2, L1, SA5 = SB5), the layout parameters of the test unit formed by active region A7 and the gate electrode are (W2, L1, SA4 = SB4), the layout parameters of the test unit formed by active region A8 and the gate electrode are (W2, L1, SA3 = SB3), the layout parameters of the test unit formed by active region A9 and the gate electrode are (W2, L1, SA2 = SB2), and the layout parameters of the test unit formed by active region A10 and the gate electrode are (W2, L1, SA1 = SB1). The width W1 of the active region is less than the width W2 of the active region.
[0083] Figure 1 In the figure, 5 test units with inconsistent diffusion region lengths, the same active region width of W1, and the same gate electrode width of L1 are formed on one side of the second virtual active region in the middle of the substrate, and 5 test units with inconsistent diffusion region lengths, the same active region width of W2, and the same gate electrode width of L1 are formed on the other side. On the one hand, the 5 test units on the same side of the second virtual active region in the middle can be tested to verify the influence of the diffusion region length on the Idsat value. On the other hand, the two corresponding test units on both sides of the second virtual active region in the middle can be tested to verify the influence of the active region width on the Idsat value.
[0084] Exemplarily, such as Figure 2As shown, a total of 10 active regions, namely A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10, are sequentially arranged on the substrate. Among them, A1, A2, A3, A4, and A5 are active regions, and A6, A7, A8, A9, and A10 are active regions. The active region A1 and the active region A10 are correspondingly arranged, the active region A2 and the active region A9 are correspondingly arranged, the active region A3 and the active region A8 are correspondingly arranged, the active region A4 and the active region A7 are correspondingly arranged, the active region A5 and the active region A6 are correspondingly arranged. The layout parameters of the test unit formed by the active region A1 and the gate electrode are (W1, L2, SA1 = SB1), the layout parameters of the test unit formed by the active region A2 and the gate electrode are (W1, L2, SA2 = SB2), the layout parameters of the test unit formed by the active region A3 and the gate electrode are (W1, L2, SA3 = SB3), the layout parameters of the test unit formed by the active region A4 and the gate electrode are (W1, L2, SA4 = SB4), the layout parameters of the test unit formed by the active region A5 and the gate electrode are (W1, L2, SA5 = SB5), the layout parameters of the test unit formed by the active region A6 and the gate electrode are (W2, L2, SA5 = SB5), the layout parameters of the test unit formed by the active region A7 and the gate electrode are (W2, L2, SA4 = SB4), the layout parameters of the test unit formed by the active region A8 and the gate electrode are (W2, L2, SA3 = SB3), the layout parameters of the test unit formed by the active region A9 and the gate electrode are (W2, L2, SA2 = SB2), the layout parameters of the test unit formed by the active region A10 and the gate electrode are (W2, L2, SA1 = SB1). The width W1 of the active region is less than the width W2 of the active region.
[0085] Figure 2 In the middle, 5 test units with inconsistent diffusion region lengths, the same active region width of W1, and the same gate electrode width of L2 are formed on one side of the second virtual active region in the middle of the substrate, and 5 test units with inconsistent diffusion region lengths, the same active region width of W2, and the same gate electrode width of L2 are formed on the other side. On the one hand, the 5 test units on the same side of the second virtual active region in the middle can be tested to verify the influence of the diffusion region length on the Idsat value. On the other hand, the two corresponding test units on both sides of the second virtual active region in the middle can be tested to verify the influence of the active region width on the Idsat value.
[0086] In addition, Figure 2 and Figure 1 compared with, the width of the gate electrode is changed from L1 to L2, increasing the width of the gate electrode (it should be noted that, Figure 2 and Figure 1 compared with, SA and SB have not changed. Therefore, on the basis of the increased width of the gate electrode, Figure 2 the overall length of the active region in is greater than that inFigure 2 the overall length of the active region), so by Figure 1 and Figure 2 the influence of the gate electrode width on the Idsat value can be further verified.
[0087] Exemplarily, as Figure 3 shown, a total of 10 active regions A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10 are sequentially arranged on the substrate. Among them, A1, A2, A3, A4, and A5 are active regions, and A6, A7, A8, A9, and A10 are active regions. The active region A1 and the active region A10 are correspondingly arranged, the active region A2 and the active region A9 are correspondingly arranged, the active region A3 and the active region A8 are correspondingly arranged, the active region A4 and the active region A7 are correspondingly arranged, the active region A5 and the active region A6 are correspondingly arranged. The layout parameters of the test unit formed by the active region A1 and the gate electrode are (W1, L1, SA1 = SB1), the layout parameters of the test unit formed by the active region A2 and the gate electrode are (W1, L1, SA2 = SB2), the layout parameters of the test unit formed by the active region A3 and the gate electrode are (W1, L1, SA3 = SB3), the layout parameters of the test unit formed by the active region A4 and the gate electrode are (W1, L1, SA4 = SB4), the layout parameters of the test unit formed by the active region A5 and the gate electrode are (W1, L1, SA5 = SB5), the layout parameters of the test unit formed by the active region A6 and the gate electrode are (W1, L2, SA5 = SB5), the layout parameters of the test unit formed by the active region A7 and the gate electrode are (W1, L2, SA4 = SB4), the layout parameters of the test unit formed by the active region A8 and the gate electrode are (W1, L2, SA3 = SB3), the layout parameters of the test unit formed by the active region A9 and the gate electrode are (W1, L2, SA2 = SB2), the layout parameters of the test unit formed by the active region A10 and the gate electrode are (W1, L2, SA1 = SB1), and the width L1 of the gate electrode region corresponding to the active region is less than the width L2 of the gate electrode region corresponding to the active region.
[0088] Figure 3 In [reference], 5 test units with inconsistent diffusion region lengths, an active region width of W1, and a gate electrode width of L1 are formed on one side of the second virtual active region in the middle of the substrate, and 5 test units with inconsistent diffusion region lengths, an active region width of W1, and a gate electrode width of L2 are formed on the other side. On the one hand, the influence of the diffusion region length on the Idsat value can be verified by testing the 5 test units on the same side of the second virtual active region in the middle, and on the other hand, the influence of the gate electrode width on the Idsat value can be verified by testing the two corresponding test units on both sides of the second virtual active region in the middle.
[0089] Exemplarily, asFigure 4 As shown, a total of 10 active regions, namely A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10, are sequentially arranged on the substrate. Among them, A1, A2, A3, A4, and A5 are active regions, and A6, A7, A8, A9, and A10 are active regions. The active region A1 and the active region A10 are correspondingly arranged, the active region A2 and the active region A9 are correspondingly arranged, the active region A3 and the active region A8 are correspondingly arranged, the active region A4 and the active region A7 are correspondingly arranged, the active region A5 and the active region A6 are correspondingly arranged. The layout parameters of the test unit formed by the active region A1 and the gate electrode are (W2, L1, SA1 = SB1), the layout parameters of the test unit formed by the active region A2 and the gate electrode are (W2, L1, SA2 = SB2), the layout parameters of the test unit formed by the active region A3 and the gate electrode are (W2, L1, SA3 = SB3), the layout parameters of the test unit formed by the active region A4 and the gate electrode are (W2, L1, SA4 = SB4), the layout parameters of the test unit formed by the active region A5 and the gate electrode are (W2, L1, SA5 = SB5), the layout parameters of the test unit formed by the active region A6 and the gate electrode are (W2, L2, SA5 = SB5), the layout parameters of the test unit formed by the active region A7 and the gate electrode are (W2, L2, SA4 = SB4), the layout parameters of the test unit formed by the active region A8 and the gate electrode are (W2, L2, SA3 = SB3), the layout parameters of the test unit formed by the active region A9 and the gate electrode are (W2, L2, SA2 = SB2), and the layout parameters of the test unit formed by the active region A10 and the gate electrode are (W2, L2, SA1 = SB1). The width L1 of the gate electrode region corresponding to the active region is less than the width L2 of the gate electrode region corresponding to the active region.
[0090] Figure 4 In [description], by forming 5 test units with inconsistent diffusion region lengths, all with an active region width of W2 and a gate electrode width of L1, on one side of the second virtual active region in the middle of the substrate, and 5 test units with inconsistent diffusion region lengths, all with an active region width of W2 and a gate electrode width of L2, on the other side. On the one hand, it is possible to test the 5 test units on the same side of the second virtual active region in the middle to verify the influence of the diffusion region length on the Idsat value. On the other hand, it is possible to test the two corresponding test units on both sides of the second virtual active region in the middle to verify the influence of the gate electrode width on the Idsat value.
[0091] In addition, Figure 4 and Figure 3 compared with [reference], the width of the active region is changed from W1 to W2, increasing the width of the active region. Therefore, through Figure 3 and Figure 4 it is possible to further verify the influence of the active region width on the Idsat value.
[0092] Embodiment 2
[0093] In another embodiment of the present application, a LOD effect test circuit structure is further provided. As Figure 5 shown, the LOD effect test circuit structure includes: a LOD effect test structure 100 and a control circuit 200; wherein, the control circuit 200 is configured to provide a test voltage to the source electrode of each test unit in the LOD effect test structure 100 and turn on the transistor of the test unit to measure and output the saturation drain current of each test unit.
[0094] Among them, the working platform of the LOD effect test structure 100 can be implemented as the LOD effect test structure in the above text, and reference can be made to the introduction in the above text, which will not be elaborated here.
[0095] In this embodiment, during the specific test process, a voltage Vg can be applied to the gate electrode, and the drain electrodes of all the test units after being led out are connected together and grounded. The control circuit 200 is sequentially connected to the electrically led-out source electrode of each test unit, and a voltage Vdd is applied for address traversal, so as to obtain the Idsat value of all test units, thereby verifying the influence of the diffusion region length, gate electrode width, active region width, etc. on the Idsat value.
[0096] In one example, the control circuit 200 can be any suitable instrument such as a decoder, and no limitation is imposed thereon.
[0097] The LOD effect test circuit structure of the present application can output the Idsat values of all test units on the LOD effect test structure in one test, reducing the test time and saving the test cost.
[0098] The present application has been described through the above embodiments. However, it should be understood that the above embodiments are only for the purpose of illustration and example, and are not intended to limit the present application to the scope of the described embodiments. In addition, those skilled in the art can understand that the present application is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present application, and these variations and modifications all fall within the scope of protection required by the present application. The scope of protection of the present application is defined by the appended claims and their equivalent scope.
Claims
1. A LOD effect test structure, characterized in that: include: substrate; At least two test units located on the substrate, each test unit comprising: an active region extending along a first direction and a gate electrode located on the active region and extending along a second direction perpendicular to the first direction; The at least two test units are arranged along the second direction, a shallow trench isolation is formed between the active regions of the two test units, and the two test units share the same gate electrode; At least one of the length of the active regions of the at least two test units along the first direction, the width along the second direction, and the width of the gate electrode along the first direction is different.
2. The LOD effect test structure according to claim 1, characterized in that: It also includes at least four first virtual active areas, and each of the active areas of the test unit is provided with a first virtual active area on both sides along the first direction. The first virtual active areas extend along the first direction, and the spacing between adjacent first virtual active areas and active areas in the second direction is equal.
3. The LOD effect test structure according to claim 2, characterized in that: Boundaries of the first dummy active regions located on the same side away from the active region are aligned along the second direction.
4. The LOD effect test structure according to claim 1, characterized in that: It also includes at least two second virtual active areas, which are respectively arranged on one side of the at least two test units away from the adjacent test units along the second direction, and the at least two second virtual active areas extend along the first direction and have an equal distance with the adjacent active areas in the second direction.
5. The LOD effect test structure according to claim 1, characterized in that: The active regions of the at least two test units have the same length along the first direction and different widths along the second direction; The gate electrodes of the at least two test units have the same width along the first direction.
6. The LOD effect test structure according to claim 1, characterized in that: The active regions of the at least two test units have different lengths along the first direction and the same widths along the second direction; The gate electrodes of the at least two test units have the same width along the first direction.
7. The LOD effect test structure according to claim 1, characterized in that: The active regions of the at least two test units have the same length along the first direction and the same width along the second direction; The gate electrodes of the at least two test units have different widths along the first direction.
8. The LOD effect test structure according to claim 1, characterized in that: It also includes virtual gate electrodes located on both sides of the gate electrode and spaced apart from the gate electrode.
9. The LOD effect test structure according to claim 1, characterized in that: The LOD effect test structure is arranged in a dicing street.
10. A LOD effect test circuit structure, characterized in that: include: The LOD effect test structure according to any one of claims 1 to 9; Control circuit; The control circuit is used to sequentially provide a test voltage to the source of each test unit in the LOD effect test structure and turn on the transistor of the test unit to measure the saturated drain current of each test unit.