Hybrid topology circuit with high step-down ratio

Abstract

The invention relates to a hybrid topology circuit with a high step-down ratio. The hybrid topology circuit comprises a first power conversion unit and a second power conversion unit, the control end of the first power conversion unit and the control end of the second power conversion unit are connected with control signals used for changing the flow direction of current in the units. The first power conversion unit comprises a switched capacitor circuit and is used for switching on or switching off a part of switching tubes in the switched capacitor circuit in response to a control signal so as to realize primary power conversion of an input voltage source to obtain a first voltage source; the second power conversion unit comprises a plurality of tapped series capacitor circuits and is used for changing the working state of each tapped series capacitor circuit in the plurality of tapped series capacitor circuits in response to a control sequence signal so as to realize secondary power conversion on the first voltage source to obtain an output voltage source; the output voltage source is within a preset voltage range. The circuit can flexibly adjust the duty ratio, and has the characteristics of high flexibility and high conversion efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a hybrid high step-down ratio topology circuit. Background Art

[0002] In recent years, with the rapid development of emerging information technologies such as 5G communications, big data, artificial intelligence, blockchain, and cloud computing, centralized computing and storage in data centers have flourished. In order to meet these growing needs, a large number of large data centers for data computing, processing, and storage have emerged, and data centers are becoming key infrastructure to support the normal operation of modern society. With the rapid rise of data centers, energy consumption is also growing sharply. By 2024, data centers consumed nearly 5% of the world's electricity production, and it is expected that by 2030, the energy consumption of global data centers will reach 8% of the world's total electricity consumption. As a major energy consumer, China's situation is not objective, with an annual growth rate of more than 30% for China's data center racks. However, only about half of the energy is delivered from the power grid to the terminal load, such as CPU, GPU, memory, and hard disk, and the rest of the energy is lost during power conversion, distribution, and cooling. Optimizing the power supply of data centers can reduce the burden on cooling systems, improve energy efficiency, and reduce carbon emissions. Therefore, it is regarded as a driving force for green data centers.

[0003] Due to the large size of server racks, high bus copper loss, complexity and increased cost of use, the 12V bus architecture of traditional data centers has shown serious deficiencies. These problems have prompted people to propose more efficient power systems. In 2016, Google proposed a new generation of 48V bus power supply system. The power supply bus voltage was increased from 12V to 48V. Since the bus voltage was increased to 48V, the current was reduced by 4 times and the loss was reduced by 1 / 16. However, the 48V bus architecture also brings some other challenges: since the load of the data center is generally CPU, GPU, memory and other devices, the required power supply range is 0.8V~1V. The use of traditional buck converters will inevitably lead to too small duty cycle. Due to the small duty cycle, the switching time is too short, the switch utilization is low, and the switching speed of the switching device is very high. At the same time, due to the low duty cycle, the high-side switching device will be subjected to higher current stress, and the overall efficiency of the converter will decrease. In other words, the traditional buck circuit can no longer meet the power supply needs of data centers using the new generation of 48V bus power supply system. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a hybrid high step-down ratio topology circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a hybrid high step-down ratio topology circuit, comprising: a first power conversion unit and a second power conversion unit; the control terminals of the first power conversion unit and the second power conversion unit are both connected to a control signal for changing the current flow direction inside the unit; the first power conversion unit includes a switched-capacitor circuit, which is configured to turn on or off some switching transistors in the switched-capacitor circuit in response to the control signal, so as to perform a primary power conversion on an input voltage source to obtain a first voltage source; the second power conversion unit includes a plurality of tapped series capacitor circuits, which are configured to change the operating state of each tapped series capacitor circuit in the plurality of tapped series capacitor circuits in response to the control timing signal, so as to perform a secondary power conversion on the first voltage source to obtain an output voltage source, and the voltage value of the output voltage source is within a preset voltage range.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0007] Aiming at the problem that the traditional step-down circuit can no longer meet the power supply requirements of a data center adopting a new generation of 48V bus power supply system, the present invention provides a hybrid high step-down ratio topology circuit. This circuit uses a control signal that can change the current flow direction inside the unit to control the first power conversion unit and the second power conversion unit, so as to perform multiple power conversions on the input voltage source and finally output the required output voltage source; the overall circuit structure is simple and easy to operate. Moreover, the preset voltage range can be flexibly set according to actual needs, and by changing the on or off of some switching transistors inside the unit, the duty cycle of the overall circuit can be changed, so that the voltage value of the output voltage source falls within the preset voltage range, which has the characteristics of high flexibility and high conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a structural block diagram of a hybrid high step-down ratio topology circuit provided by an embodiment of the present invention;

[0009] Figure 2 is a circuit connection schematic diagram of the hybrid high step-down ratio topology circuit provided by an embodiment of the present invention;

[0010] Figure 3 is an equivalent diagram of a coupled inductor provided by an embodiment of the present invention;

[0011] Figure 4 is an equivalent circuit schematic diagram of the hybrid high step-down ratio topology circuit in working state one provided by an embodiment of the present invention;

[0012] Figure 5 is an equivalent circuit schematic diagram of the hybrid high step-down ratio topology circuit in working state two provided by an embodiment of the present invention;

[0013] Figure 6 It is the circuit equivalent schematic diagram when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention is in working state three;

[0014] Figure 7 It is the circuit equivalent schematic diagram when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention is in working state four;

[0015] Figure 8 It is the working timing diagram of the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention;

[0016] Figure 9 It is the equivalent circuit simulation schematic diagram of the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention;

[0017] Figure 10 It is the waveform change simulation diagram of the output power supply, capacitor C1 and capacitor C2 obtained after the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention processes the input voltage source;

[0018] Figure 11 It is the voltage change simulation diagram of switch node Vsw1 and switch node Vsw2 when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention processes the input voltage source;

[0019] Figure 12 It is the current waveform of resonant capacitor Cr1 and resonant capacitor Cr2, and the VGS waveform change simulation diagram of switch tubes S1 and S2 when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention processes the input voltage source;

[0020] Figure 13 It is the zero-voltage turn-on simulation diagram of switch tubes S4 - S7 when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention processes the input voltage source. Specific embodiments

[0021] The following further describes the present invention in detail with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0022] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0023] In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0024] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0025] In a possible application scenario, a hybrid high step-down ratio topology circuit provided by the present invention can be connected to a 48V bus power supply system to step it down. It should be noted that the hybrid high step-down ratio topology circuit provided by the present invention is not limited to stepping down the 48V bus power supply system, and can also be used in other circuit systems that require stepping down.

[0026] Now, with reference to the accompanying drawings, a hybrid high step-down ratio topology circuit provided by an embodiment of the present invention will be described in detail.

[0027] Figure 1 is a structural block diagram of a hybrid high step-down ratio topology circuit provided by an embodiment of the present invention. As Figure 1 shown, the circuit includes: a first power conversion unit and a second power conversion unit; the control terminals of the first power conversion unit and the second power conversion unit are both connected to a control signal for changing the current flow direction inside the unit; the first power conversion unit includes a switched-capacitor circuit for responding to the control signal to turn on or off some switching transistors in the switched-capacitor circuit to achieve a primary power conversion of the input voltage source to obtain a first voltage source; the second power conversion unit includes two tapped series capacitor circuits for responding to a control timing signal to change the operating state of each tapped series capacitor circuit in the plurality of tapped series capacitor circuits to achieve a secondary power conversion of the first voltage source to obtain an output voltage source, and the output voltage source is within a preset voltage range.

[0028] Here, the ratio of the voltage amplitude of the voltage source to the value of the output voltage source is greater than a preset value, and the preset value can be 10, 100, and larger values. That is to say, the ratio of the voltage input to the hybrid high step-down ratio topology circuit to the voltage output from the hybrid high step-down ratio topology circuit has the characteristic of a high step-down ratio. Exemplarily, the voltage value of the voltage source is 48V, and the preset voltage range (i.e., the voltage value range of the output voltage source) is 0.8V to 1V. The ratio between the two fluctuates between 48 and 60 and can be adjusted according to actual needs, featuring high flexibility.

[0029] Here, the control signal is generated by a gate driver, and the control signal includes: a first timing signal and a second timing signal with different generation times; among them, the first power conversion unit is connected to the first timing signal, and the second power conversion unit is connected to the second timing signal. Specifically, the first timing signal includes: a timing signal T1 and a timing signal T2 with different generation times; the second timing signal includes: a timing signal T3 and a timing signal T4 with different generation times. The first timing signal is used to control the conduction or cutoff of some switching tubes in the first power conversion unit, and the second timing signal is used to control the conduction or cutoff of some switching tubes in the multiple tapped series capacitor circuits, changing the working state of each tapped series capacitor circuit in the multiple tapped series capacitor circuits.

[0030] Now in combination with Figure 2 , the specific structure of the hybrid high step-down ratio topology circuit provided by the embodiments of the present invention will be described in detail. Figure 2 is a schematic circuit connection diagram of the hybrid high step-down ratio topology circuit provided by the embodiments of the present invention. As Figure 2 shown, the first power conversion unit includes: a switching tube S1, a switching tube S2, a switching tube S3, a capacitor C1, and a capacitor C2; the gates of the switching tube S1 and the switching tube S3 are connected to the timing signal T1, and the gate of the switching tube S2 is connected to the timing signal T2; the drain of the switching tube S1 is connected to the voltage source, and the source is respectively connected to the drain of the switching tube S2 and the first end of the capacitor C1; the source of the switching tube S2 is respectively connected to the drain of the switching tube S3 and the first end of the capacitor C2; the second end of the capacitor C1 is connected to the source of the switching tube S3; the second end of the capacitor C2, as the first output end of the first power conversion unit, is connected to the first input end of the second power conversion unit; the source of the switching tube S3, as the second output end of the first power conversion unit, is connected to the second input end of the second power conversion unit.

[0031] And, a second power conversion unit, comprising: a first tapped series capacitor circuit, a second tapped series capacitor circuit, a capacitor Co, and a resistor RL; the first tapped series capacitor circuit is connected to a timing signal T3, and the second tapped series capacitor circuit is connected to a timing signal T4; an input end of the first tapped series capacitor circuit serves as a first input end of the second power conversion unit, and an output end is respectively connected to a first end of the capacitor Co and a first end of the resistor RL, a second end of the capacitor Co and a second end of the resistor RL are grounded; the first end of the resistor RL is further used for outputting an output voltage source; an input end of the second tapped series capacitor circuit serves as a second input end of the second power conversion unit, and an output end is connected to the output end of the first tapped series capacitor circuit.

[0032] Further, the first tapped series capacitor circuit comprises: a switching transistor S4, a switching transistor S5, a resonant capacitor Cr2, and a coupled inductor L1; a first end of the resonant capacitor Cr2 serves as the first input end of the second power conversion unit and is connected to a drain of the switching transistor S4, and a source of the switching transistor S4 is grounded; a second end of the resonant capacitor Cr2 is connected to a same-named end of a primary winding of the coupled inductor L1, a different-named end of the primary winding of the coupled inductor L1 is respectively connected to a same-named end of a secondary winding of the coupled inductor L1 and a drain of the switching transistor S5, a different-named end of the secondary winding of the coupled inductor L1 and a first end of the capacitor Co are connected, and a source of the switching transistor S5 is grounded.

[0033] Here, the circuit structures of the first tapped series capacitor circuit and the second tapped series capacitor circuit are the same. Specifically, the second tapped series capacitor circuit comprises: a switching transistor S6, a switching transistor S7, a resonant capacitor Cr1, and a coupled inductor L2; a first end of the resonant capacitor Cr1 serves as the second input end of the second power conversion unit and is connected to a drain of the switching transistor S6, and a source of the switching transistor S6 is grounded; a second end of the resonant capacitor Cr1 is connected to a same-named end of a primary winding of the coupled inductor L2, a different-named end of the primary winding of the coupled inductor L2 is respectively connected to a same-named end of a secondary winding of the coupled inductor L2 and a drain of the switching transistor S7, a different-named end of the secondary winding of the coupled inductor L2 and a first end of the capacitor Co are connected, and a source of the switching transistor S7 is grounded.

[0034] It should be noted that the coupled inductor L1 and the coupled inductor L2 have the same structural composition, and both can be further equivalently represented as a leakage inductance Lk, an exciting inductance Lm, a primary inductance (primary winding), and a secondary inductance (secondary winding), as Figure 3As shown, the first end of the leakage inductance Lk is connected to the second end of the resonant capacitor Cr, and the second end is respectively connected to the first end of the exciting inductance Lm and the same-name end of the primary inductance. The second end of the exciting inductance Lm and the different-name end of the primary inductance are respectively connected to the same-name end of the secondary inductance and the drain of the switching transistor. The different-name end of the secondary inductance is connected to the first end of the capacitor Co. Among them, the current enters from the resonant capacitor, passes through the leakage inductance, enters the exciting inductance and the primary inductance respectively, and then flows out from the secondary inductance.

[0035] Here, the control signal is a variable timing signal, whose corresponding levels are different in different cycles. Furthermore, the resonant capacitors Cr1 and Cr2 can be in the energy storage state and the resonant state respectively in different cycles, so as to reduce the adverse effect of the leakage inductance of the coupled inductance on the overall circuit, provide conditions for the switching transistor to achieve zero-voltage switching, and reduce the switching loss.

[0036] It should be noted that the type of all switching transistors is NMOS transistor.

[0037] In a possible implementation manner, the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention has four working states. Now, in combination with Figures 4 to 7 these four working states. Figure 4 is the circuit equivalent schematic diagram when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention is in the first working state; Figure 5 is the circuit equivalent schematic diagram when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention is in the second working state; Figure 6 is the circuit equivalent schematic diagram when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention is in the third working state; Figure 7 is the circuit equivalent schematic diagram when the hybrid high step-down ratio topology circuit provided by the embodiment of the present invention is in the fourth working state.

[0038] Before describing the four working states, the following assumptions are first made: (1) Assume that the capacitances of the capacitors C1 and C2 are large enough; (2) Ignore the influence of the dead time and the leakage inductance of the coupled inductance; (3) All components are ideal devices, and the turn ratio of the coupled inductance satisfies: where N 1 is the number of turns of the primary inductance in the coupled inductance L2, N 2 is the number of turns of the secondary inductance in the coupled inductance L2, N 3 is the number of turns of the primary inductance in the coupled inductance L1, N 4 is the number of turns of the secondary inductance in the coupled inductance L1.

[0039] As Figure 4As shown, in the case of operating state 1, at this time, switch transistors S1, S3 - S5 are conducting, and switch transistors S2, S6 - S7 are off. The red dotted line in the figure indicates the direction of the current in the circuit. The input voltage source (Vin) charges capacitor C1, resonant capacitor Cr1, and the lower - side coupled inductor. The magnetizing inductor Lm1 and leakage inductor Lk1 are magnetized, and the energy is transferred to the load. At the same time, capacitor C2 discharges, charging capacitor C1, resonant capacitor Cr1, and the coupled inductor. The magnetizing inductor Lm2 and leakage inductor Lk2 are demagnetized, and resonant capacitor Cr2 discharges. Resonant capacitor Cr2 and the leakage inductor Lr2 of the coupled inductor form a resonant circuit, and the energy is released to the output through the coupled inductor. The energy stored in the magnetizing inductor Lm2 is also released to the output terminal. The resonance between the leakage inductor Lk2 and resonant capacitor Cr2 can achieve zero - voltage switching (ZVS).

[0040] As Figure 5 shown, in the case of operating state 2, at this time, switch transistors S1 - S3 are off, and switch transistors S4 - S7 are conducting. The magnetizing inductor Lm1 and leakage inductor Lk1 are demagnetized, resonant capacitor Cr1 is still charged, the magnetizing inductor Lm2 and leakage inductor Lk2 are demagnetized, resonant capacitor Cr2 is still discharging, and at the same time, resonant capacitor Cr2 resonates with the leakage inductor Lk2 of the coupled inductor. By performing KVL analysis on the circuits in operating state 1 and operating state 2, the following expressions can be obtained:

[0041]

[0042] V in -V c1 =V c2 ;

[0043] Among them, v Lm1 is the voltage of the magnetizing inductor Lm1, v Lm2 is the voltage of the magnetizing inductor Lm2, V in is the input voltage source, V C1 is the voltage value of capacitor C1, V C2 is the voltage value of capacitor C2, V Cr1 is the voltage value of resonant capacitor Cr1, V Cr2 is the voltage value of resonant capacitor Cr2, V O is the output voltage source, N 1 is the number of turns of the primary - side inductor in the coupled inductor L2, N 2 is the number of turns of the secondary - side inductor in the coupled inductor L2, N 3 is the number of turns of the primary - side inductor in the coupled inductor L1, N 4 is the number of turns of the secondary - side inductor in the coupled inductor L1.

[0044] As Figure 6As shown, in the case of operating state three, at this time, the switching transistors S1, S3 - S5 are turned off, and the switching transistors S2, S6 - S7 are turned on. The capacitor C1 discharges, charging the capacitor C2, the resonant capacitor Cr2, and the upper - side coupled inductor. The exciting inductor Lm2 and the leakage inductor Lk2 are magnetized, and the energy is transferred to the load. The exciting inductor Lm1 and the leakage inductor Lk1 are demagnetized, and the resonant capacitor Cr1 discharges. The resonant capacitor Cr1 and the leakage inductor Lk1 of the coupled inductor form a resonant circuit, and the energy is released to the output through the coupled inductor. The energy stored in the exciting inductor Lm1 is also released to the output terminal. The resonance between the leakage inductor Lk1 and the resonant capacitor Cr1 can achieve zero - voltage switching (ZVS).

[0045] As Figure 7 shown, in the case of operating state four, at this time, the switching transistors S1 - S3 are turned off, and the switching transistors S4 - S7 are turned on. The exciting inductor Lm1 and the leakage inductor Lk1 are demagnetized, and the resonant capacitor Cr1 is still discharging. The exciting inductor Lm2 and the leakage inductor Lk2 are demagnetized. At this time, Cr2 is still charging, and at the same time, the resonant capacitor Cr1 resonates with the leakage inductor Lk1 of the coupled inductor.

[0046] Performing KVL analysis on the circuits in operating state three and operating state four, the following expressions can be obtained:

[0047]

[0048] Combining the multiple expressions obtained in the four operating states and performing volt - second balance on the exciting inductor Lm1 and the exciting inductor Lm2, the following can be obtained:

[0049]

[0050] where D is the duty cycle.

[0051] From the above formula, it can be seen that the duty cycle of the hybrid high - step - down ratio topology circuit is positively correlated with the ratio of the output voltage source to the input voltage source. Or rather, the duty cycle can float following the ratio of the output voltage source to the input voltage source of the output, with the characteristics of being flexibly adjustable. And the turns ratio of the coupled inductor provides high step - down ability, providing conditions for achieving high step - down. Exemplarily, when the value of the input voltage source is 48V and the output voltage source is 1V, the turns ratio of the coupled inductor is selected as 3, and the calculated duty cycle D is 25%, which is higher than the duty cycle of the existing step - down circuit. Here, a high duty cycle means that the switching time can be relatively increased, the utilization rate of the switching transistor can be improved, the requirement for the switching speed of the switching transistor can be reduced. At the same time, due to the relatively high duty cycle, the high - side switching device can be avoided from suffering higher current stress, effectively improving the overall working efficiency of the circuit.

[0052] Figure 8 is the working timing diagram of the hybrid high - step - down ratio topology circuit provided by the embodiment of the present invention. As Figure 8As shown, the time period occupied by operating state one is from t0 to t1, the time period occupied by operating state two is from t2 to t3, the time period occupied by operating state three is from t4 to t5, and the time period occupied by operating state four is from t6 to t7. The entire period is represented by the symbol Ts, the voltage output by the first power conversion unit is represented by the symbol Vsw, the gate conduction voltage of the switching transistor is represented by the symbol Vgs, the currents flowing through the resonant capacitors Cr1 and Cr2 are represented by the symbols icr1 and icr2 respectively, and the currents flowing through the switching transistors S4 - S7 are represented by the symbols is4 - is7 respectively. Among them, within the time period from t0 to t8, the changes in the gate conduction voltages of the switching transistors S1 - S7 are specifically manifested as follows: the gate conduction voltage of switching transistor S1 (Vgs1) is the same as that of switching transistor S3 (Vgs3), the gate conduction voltage of switching transistor S6 (Vgs6) is the same as that of switching transistor S7 (Vgs7), and the gate conduction voltage of switching transistor S1 (Vgs1) is in antiphase with that of switching transistor S6 (Vgs6). Also, the gate conduction voltage of switching transistor S4 (Vgs4) is the same as that of switching transistor S5 (Vgs5), and the gate conduction voltage of switching transistor S2 (Vgs2) is in antiphase with that of switching transistor S4 (Vgs4).

[0053] To verify the accuracy of the proposed circuit, simulation verification was carried out using LTSPICE simulation software. The equivalent circuit simulation schematic diagram is as Figure 9 shown, and the simulation results are as Figures 10 - 13 shown.

[0054] Specifically, Figure 10 shows the waveform change simulation diagram of the output power supply and capacitors C1 and C2 after the hybrid high step - down ratio topology circuit processes the input voltage source. Among them, the green curve represents the input voltage source, the dark blue curve represents the output voltage source of the output, the red curve represents the voltage of capacitor C1, and the light blue curve represents the voltage of capacitor C2. It can be seen that the input voltage source is maintained at 48V, and the output voltage source of the output is stably maintained at 1V, indicating that the hybrid high step - down ratio topology circuit provided by the present invention can step down efficiently and stably.

[0055] Figure 11When the hybrid high step-down ratio topology circuit processes the input voltage source, since the capacitors C1 and C2 in the first power conversion unit have DC bias and pre-step-down capabilities, they can reduce the device switching stress, and then effectively reduce the voltage values at the two output terminals (switch nodes Vsw1 and Vsw2) of the first power conversion unit. Among them, the green curve represents the input voltage source, the red curve represents the voltage of capacitor C1, the light blue curve represents the voltage of capacitor C2, the dark blue curve represents the voltage of Vsw1, and the pink curve represents the voltage of Vsw2. According to the simulation results, based on the voltage clamping effect of the first power conversion unit, the switch node before the coupled inductor is clamped to 1 / 3Vin, effectively improving the overall duty cycle and conversion efficiency of the circuit.

[0056] Figure 12 It is a simulation diagram of the current waveforms of the resonant capacitors Cr1 and Cr2, and the VGS waveform changes of the switching transistors S1 and S2 when the hybrid high step-down ratio topology circuit processes the input voltage source. Among them, the red curve represents the gate conduction voltage (Vgs1) of the switching transistor S1, the green curve represents the gate conduction voltage (Vgs2) of the switching transistor S2, the light blue curve is the voltage of the capacitor Cr1, and the dark blue curve is the voltage of the capacitor Cr2. According to the simulation results, when the switching transistors S1, S3, S4, and S5 are conducting and the switching transistors S2, S6, and S7 are turned off, the capacitor Cr1 is charged. When the switching transistors S2, S6, and S7 are conducting and the switching transistors S1, S3, S4, and S5 are turned off, the capacitor Cr2 is charged. The capacitor is in a resonant state for the rest of the time, recovering the leakage inductance energy of the coupled inductor.

[0057] Figure 13 It is a zero-voltage turn-on simulation diagram of the switching transistors S4 - S7 when the hybrid high step-down ratio topology circuit processes the input voltage source. Among them, the light green curve is the gate conduction voltage (Vgs4) of the switching transistor S4, the blue curve is the drain-source voltage Vds4 of the switching transistor S4, the red curve is the gate conduction voltage (Vgs6) of the switching transistor S6, the light blue curve is the drain-source voltage Vds6 of the switching transistor S6, the pink curve is the gate conduction voltage (Vgs5) of the switching transistor S5, the gray curve is the drain-source voltage Vds5 of the switching transistor S5, the dark green curve is the gate conduction voltage (Vgs7) of the switching transistor S7, and the brown curve is the drain-source voltage Vds7 of the switching transistor S7. According to the simulation results, the switching transistors S4, S5, S6, and S7 all have the ability of zero-voltage turn-on. Combining the switched capacitor with the coupled inductor not only improves the duty cycle but also effectively utilizes the leakage inductance of the coupled inductor, providing conditions for the ZVS conduction of the switching devices, reducing the turn-on loss, and improving the overall efficiency of the circuit.

[0058] In view of the problem that the traditional buck circuit can no longer meet the power supply requirements of data centers adopting the new generation of 48V bus power supply system, the present invention provides a hybrid high buck ratio topology circuit. This circuit uses a first power conversion unit and a second power conversion unit to perform multiple power conversions on the input voltage source, so that its final output is the required output voltage source. By combining the DC bias and pre-buck ability of the switched capacitor with the high buck ratio characteristic of the coupled inductor, it can not only reduce the adverse effects brought by the leakage inductance of the coupled inductor, but also provide the corresponding soft-switching ability for the switching devices, achieve a higher buck ratio, and effectively improve the duty cycle of the converter. In addition, there are no special requirements for the main electronic devices in the hybrid high buck ratio topology circuit provided by the present invention, nor are there special requirements for the PCB design. It has the characteristics of simple circuit structure, easy to implement, low cost, low industrial requirements, and strong practicability.

[0059] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A hybrid high step-down ratio topology circuit, characterized in that: The circuit comprises: a first power conversion unit and a second power conversion unit; the control end of the first power conversion unit and the control end of the second power conversion unit are both connected to a control signal for changing the flow direction of the current inside the unit; The first power conversion unit includes a switch capacitor circuit, which is used to turn on or off some switches in the switch capacitor circuit in response to the control signal, so as to achieve a power conversion of the input voltage source and obtain a first voltage source; The second power conversion unit includes a plurality of tapped series capacitor circuits, which are used to change the working state of each of the plurality of tapped series capacitor circuits in response to the control timing signal, so as to realize secondary power conversion of the first voltage source to obtain an output voltage source, and the voltage value of the output voltage source is within a preset voltage range.

2. The hybrid high step-down ratio topology circuit according to claim 1, characterized in that: The control signal is generated by a gate driver, and the control signal includes: a first timing signal and a second timing signal that are generated asynchronously; wherein the first power conversion unit is connected to the first timing signal, and the second power conversion unit is connected to the second timing signal.

3. The hybrid high step-down ratio topology circuit according to claim 2, characterized in that: The first timing signal includes: a timing signal T1 and a timing signal T2 that are generated asynchronously; The first power conversion unit includes: a switch tube S1, a switch tube S2, a switch tube S3, a capacitor C1 and a capacitor C2; The gates of the switch tube S1 and the switch tube S3 are connected to the timing signal T1, and the gate of the switch tube S2 is connected to the timing signal T2; The drain of the switch tube S1 is connected to the voltage source, and the source is connected to the drain of the switch tube S2 and the first end of the capacitor C1 respectively; the source of the switch tube S2 is connected to the drain of the switch tube S3 and the first end of the capacitor C2 respectively; the second end of the capacitor C1 is connected to the source of the switch tube S3; The second end of the capacitor C2, as the first output end of the first power conversion unit, is connected to the first input end of the second power conversion unit; The source of the switch tube S3, serving as the second output end of the first power conversion unit, is connected to the second input end of the second power conversion unit.

4. The hybrid high step-down ratio topology circuit according to claim 2, characterized in that: The second timing signal includes: a timing signal T3 and a timing signal T4 that are generated asynchronously; The second power conversion unit includes: a first tapped series capacitor circuit, a second tapped series capacitor circuit, a capacitor Co and a resistor RL; The first tapped series capacitor circuit is connected to the timing signal T3, and the second tapped series capacitor circuit is connected to the timing signal T4; The input end of the first tapped series capacitor circuit serves as the first input end of the second power conversion unit, and the output end is connected to the first end of the capacitor Co and the first end of the resistor RL respectively, and the second end of the capacitor Co and the second end of the resistor RL are grounded; the first end of the resistor RL is also used to output the output voltage source; The input end of the second tapped series capacitor circuit serves as the second input end of the second power conversion unit, and the output end is connected to the output end of the first tapped series capacitor circuit.

5. The hybrid high step-down ratio topology circuit according to claim 4, characterized in that: The first tapped series capacitor circuit includes: a switch tube S4, a switch tube S5, a resonant capacitor Cr2 and a coupling inductor L1; The first end of the resonant capacitor Cr2 serves as the first input end of the second power conversion unit and is connected to the drain of the switch tube S4, and the source of the switch tube S4 is grounded; The second end of the resonant capacitor Cr2 is connected to the same-name end of the primary winding of the coupling inductor L1, the opposite-name end of the primary winding of the coupling inductor L1 is respectively connected to the same-name end of the secondary winding of the coupling inductor L1 and the drain of the switching tube S5, the opposite-name end of the secondary winding of the coupling inductor L1 is connected to the first end of the capacitor Co, and the source of the switching tube S5 is grounded.

6. The hybrid high step-down ratio topology circuit according to claim 4, characterized in that: The second tapped series capacitor circuit includes: a switch tube S6, a switch tube S7, a resonant capacitor Cr1 and a coupling inductor L2; The first end of the resonant capacitor Cr1 serves as the second input end of the second power conversion unit and is connected to the drain of the switch tube S6, and the source of the switch tube S6 is grounded; The second end of the resonant capacitor Cr1 is connected to the same-name end of the primary winding of the coupling inductor L2, the opposite-name end of the primary winding of the coupling inductor L2 is respectively connected to the same-name end of the secondary winding of the coupling inductor L2 and the drain of the switching tube S7, the opposite-name end of the secondary winding of the coupling inductor L2 is connected to the first end of the capacitor Co, and the source of the switching tube S7 is grounded.

7. The hybrid high step-down ratio topology circuit according to claim 1, characterized in that: The duty cycle of the hybrid high step-down ratio topology circuit is positively correlated with the ratio of the output voltage source to the input voltage source.

8. The hybrid high step-down ratio topology circuit according to claim 1, characterized in that: The voltage value of the input voltage source is 48V.

9. The hybrid high step-down ratio topology circuit according to claim 1, characterized in that: The preset voltage range is 0.8V to 1V.

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