Control method, chip, power supply circuit and charger for asymmetric half-bridge circuit

Abstract

The present invention discloses a control method, chip, power supply circuit, and charger for an asymmetric half-bridge circuit. The asymmetric half-bridge circuit includes a resonant circuit, a transformer, and an auxiliary winding. The auxiliary winding is coupled to the secondary winding of the transformer. The primary winding of the transformer is connected to the resonant circuit to form a resonant cavity. The control method includes: determining a starting detection time and collecting a resonant cavity current corresponding to the resonant cavity; determining a target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity; and collecting a sampling voltage corresponding to the auxiliary winding when the current time is the target sampling time. This control method for an asymmetric half-bridge circuit can cause the target sampling time to change with changes in the resonant cavity current, avoid sampling voltage errors caused by fluctuations in the resonant capacitor voltage, and improve the primary-side detection accuracy of the output voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and in particular to a control method, a chip, a power supply circuit, and a charger for an asymmetric half-bridge circuit. Background Art

[0002] Asymmetric half-bridge circuits are typically used in power supply designs with a wide output range. Since the voltage gain range of an asymmetric half-bridge circuit is limited, a control chip connected to the asymmetric half-bridge circuit is required to accurately collect the output voltage and perform primary-side feedback control based on the output voltage.

[0003] In the prior art, a set of auxiliary windings coupled to the transformer is typically added to perform primary-side detection of the output voltage. The same-named terminals of the auxiliary windings are aligned with the same-named terminals of the output windings. After the upper transistor in the asymmetric half-bridge circuit is turned off and the lower transistor is turned on, and power begins to be transferred to the secondary side of the transformer, the control begins to collect voltage through the auxiliary windings, thereby obtaining the output voltage. However, the transformer windings of the asymmetric half-bridge circuit are connected to the resonant inductor and resonant capacitor. The disturbance component of the resonant capacitor voltage is superimposed on the transformer windings. The output voltage collected through the auxiliary windings actually reflects the sum of the current output voltage and the disturbance component. Therefore, it is necessary to continue to delay for a period of time after the upper transistor in the asymmetric half-bridge circuit is turned off and the lower transistor is turned on before collecting the voltage of the auxiliary winding to avoid the time when the disturbance component appears. In the prior art, the delay time is usually a preset fixed value. Since the size of the disturbance component is different under light load and heavy load conditions, the required delay time will also be different. Therefore, the output voltage collected under the fixed delay time will still contain a certain disturbance component, which will lead to inaccurate output voltage sampling and thus cause abnormal primary side feedback control. Summary of the Invention

[0004] Embodiments of the present invention provide a control method, chip, power supply circuit, and charger for an asymmetric half-bridge circuit to solve the problem of inaccurate output voltage sampling in the asymmetric half-bridge circuit, which easily causes control abnormality.

[0005] An embodiment of the present invention provides a control method for an asymmetric half-bridge circuit, wherein the asymmetric half-bridge circuit includes a resonant circuit, a transformer, and an auxiliary winding; the auxiliary winding is coupled to a primary winding of the transformer; the primary winding of the transformer is connected to the resonant circuit to form a resonant cavity, and the control method includes:

[0006] When the resonant state of the asymmetric half-bridge circuit meets a preset sampling condition, determining a starting detection time and collecting a resonant cavity current corresponding to the resonant cavity;

[0007] determining a target sampling time based on the starting detection time and a resonant cavity current corresponding to the resonant cavity;

[0008] When the current moment is the target sampling moment, a sampling voltage corresponding to the auxiliary winding is collected.

[0009] Preferably, the resonant circuit includes a first switching transistor, a second switching transistor, a resonant inductor, and a resonant capacitor, wherein the first switching transistor and the second switching transistor are connected in series between the signal input terminal and the ground; the resonant inductor, the resonant capacitor, and the primary winding of the transformer are connected in series between the connection node between the first switching transistor and the second switching transistor and the ground to form the resonant cavity;

[0010] The control method further includes:

[0011] The first switch tube and the second switch tube are alternately controlled to turn on any one of them and turn off the other. When the first switch tube is turned off and the second switch tube is turned on, it is determined that the resonant state of the asymmetric half-bridge circuit meets the preset sampling condition.

[0012] Preferably, determining the target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity includes:

[0013] Determining a target delay time according to a resonant cavity current corresponding to the resonant cavity;

[0014] A target sampling time is determined based on the start detection time and the target delay time.

[0015] Preferably, determining the target delay time according to the resonant cavity current corresponding to the resonant cavity includes:

[0016] Obtaining a peak current corresponding to the resonant cavity based on a resonant cavity current corresponding to the resonant cavity;

[0017] A target delay time is determined based on a peak current corresponding to the resonant cavity.

[0018] Preferably, the peak current corresponding to the resonant cavity is the resonant cavity current collected at the start detection moment.

[0019] Preferably, determining the target delay time based on the peak current corresponding to the resonant cavity includes:

[0020] The target delay time is determined based on a peak current corresponding to the resonant cavity and a preset current-time mapping relationship, wherein the preset current-time mapping relationship is used to reflect a mapping relationship between the peak current and the delay time.

[0021] Preferably, the preset current-time mapping relationship includes a plurality of preset current intervals, and each of the preset current intervals corresponds to a preset delay time;

[0022] The determining of the target delay time based on the peak current corresponding to the resonant cavity and the preset current-time mapping relationship includes:

[0023] A preset current interval in which the peak current corresponding to the resonant cavity is located is determined as a target current interval, and a preset delay time corresponding to the target current interval is determined as a target delay time.

[0024] Preferably, determining the target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity includes:

[0025] determining a current change rate based on a resonant cavity current corresponding to the resonant cavity;

[0026] The sampling moment when the current change rate is 0 is determined as the target sampling moment.

[0027] An embodiment of the present invention also provides a control chip, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor. The control chip is applied in an asymmetric half-bridge circuit, and when the processor executes the computer program, it implements the control method of the asymmetric half-bridge circuit according to any one of the above items.

[0028] An embodiment of the present invention further provides a power supply circuit, comprising a primary-side rectifier and filter circuit, a secondary-side rectifier and filter circuit, a current sampling unit, the asymmetric half-bridge circuit described in any one of the above items, and the above control chip;

[0029] The input end of the primary rectifier and filter circuit is used to connect to the mains circuit, the output end of the primary rectifier and filter circuit is connected to the resonant circuit of the asymmetric half-bridge circuit, the secondary winding of the transformer of the asymmetric half-bridge circuit is connected to the input end of the secondary rectifier and filter circuit, and the output end of the secondary rectifier and filter circuit is used to connect to an external load to supply power to the external load;

[0030] The current sampling unit is connected to the resonant cavity of the asymmetric half-bridge circuit and is also connected to the control chip, and is used to collect the resonant cavity current corresponding to the resonant cavity and output the resonant cavity current to the control chip;

[0031] The control chip is connected to the auxiliary winding, and is used to determine a target sampling moment based on the resonant cavity current corresponding to the resonant cavity, and to collect a sampling voltage corresponding to the auxiliary winding when the current moment is the target sampling moment.

[0032] An embodiment of the present invention further provides a charger including the above-mentioned power supply circuit.

[0033] Embodiments of the present invention provide a control method, chip, power supply circuit, and charger for an asymmetric half-bridge circuit. The control method for the asymmetric half-bridge circuit can adjust the sampling moment for sampling the auxiliary winding voltage in real time based on the resonant cavity current. The target sampling moment can be changed in accordance with the change in the resonant cavity current, so that the sampled voltage collected at the target sampling moment is closer to k times the output voltage. This can avoid sampling voltage errors caused by fluctuations in the resonant capacitor voltage, improve the primary-side detection accuracy of the output voltage, and make primary-side feedback control more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 1 is a schematic diagram of the circuit structure of an asymmetric half-bridge circuit in one embodiment of the present invention;

[0036] Figure 2 is a flow chart of a control method for an asymmetric half-bridge circuit according to an embodiment of the present invention;

[0037] Figure 3 is a working waveform diagram of an asymmetric half-bridge circuit in one embodiment of the present invention;

[0038] Figure 4 is another operating waveform diagram of the asymmetric half-bridge circuit in one embodiment of the present invention;

[0039] Figure 5 is a flow chart of another control method for an asymmetric half-bridge circuit in one embodiment of the present invention;

[0040] Figure 6 is a flow chart of another control method for an asymmetric half-bridge circuit in one embodiment of the present invention;

[0041] Figure 7 FIG. 4 is a flow chart of another control method of an asymmetric half-bridge circuit according to an embodiment of the present invention.

[0042] In the figure: 1. Current sampling unit. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] It should be understood that the present invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0045] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] In order to fully understand the present invention, detailed structures and steps will be provided in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may also have other implementations.

[0049] The embodiment of the present invention provides a control method for an asymmetric half-bridge circuit. Figure 1 As shown, the asymmetric half-bridge circuit may include a resonant circuit, a transformer T1 and an auxiliary winding Taux. The resonant circuit may include a resonant inductor L1 and a resonant capacitor Cr; the auxiliary winding Taux is coupled to the secondary winding Ts of the transformer T1; the primary winding Tp of the transformer T1 is connected to the resonant circuit to form a resonant cavity, wherein the resonant circuit, the transformer T1 and the auxiliary winding Taux are used to connect a control chip U1. The control chip U1 can control the periodic resonance in the resonant cavity. Based on the principle of electromagnetic induction, during resonance, electric energy can be transferred from the primary side of the transformer T1 to the secondary side of the transformer T1, and an output voltage is periodically formed on the secondary side of the transformer T1. In the process of transferring electric energy to the secondary side, the control chip U1 can obtain a sampling voltage through the auxiliary winding Taux to perform primary-side detection on the current output voltage. The control method of the asymmetric half-bridge circuit is applied to the control chip U1 connected to the asymmetric half-bridge circuit, as shown in FIG. Figure 2 As shown, including:

[0050] S201: When the resonant state of the asymmetric half-bridge circuit meets a preset sampling condition, determining a start detection time, and collecting a resonant cavity current corresponding to the resonant cavity;

[0051] S202: Determine a target sampling time based on the start detection time and the resonant cavity current corresponding to the resonant cavity;

[0052] S203: When the current moment is the target sampling moment, a sampling voltage corresponding to the auxiliary winding is collected.

[0053] Among them, the starting detection time To is the moment when the control chip U1 starts to obtain the resonant cavity current Ip in each voltage output cycle of the asymmetric half-bridge circuit. Specifically, the moment when the asymmetric half-bridge circuit starts to transfer energy to the secondary side of the transformer T1 and generate output voltage can be used as the starting detection time To.

[0054] As an example, in step S201, in a voltage output cycle of the asymmetric half-bridge circuit, when the resonant state of the asymmetric half-bridge circuit meets the preset sampling conditions, for example, when the energy on the primary side of the asymmetric half-bridge circuit is stored and is ready to be transferred to the secondary side of the transformer T1, the moment when the asymmetric half-bridge circuit starts to transfer energy to the secondary side of the transformer T1 and generates the output voltage is taken as the starting detection moment To, and starting from the starting detection moment To, the control chip U1 continuously obtains the resonant cavity current Ip corresponding to the resonant cavity.

[0055] Among them, Figure 1 In the asymmetric half-bridge circuit shown, the resonant cavity current Ip changes as follows Figure 3 As shown, during the time period t0~t2, the resonant cavity current Ip flows through the resonant inductor L1, the primary winding Tp of the transformer T1 and the resonant capacitor Cr, which is recorded as Imagpos. At this time, the resonant cavity current Ip rises linearly and stores energy in the resonant cavity. During the time period t3~t5, the energy stored in the resonant cavity is released to the secondary side through electromagnetic induction between the primary and secondary sides of the transformer T1 to form the output voltage Vo. At this time, the resonant cavity current Ip will actually oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1. The voltage actually superimposed on the excitation inductance LM of the primary winding Tp of the transformer T1 is n times the average value of the output voltage Vo and the resonant capacitor Cr voltage, where n represents the ratio of the number of turns Np of the primary side of the transformer T1 to the number of turns Ns of the secondary side. Since the voltage across the resonant capacitor Cr is limited by the capacitance value, it will fluctuate during oscillation, and the auxiliary winding Taux is actually coupled with the excitation inductance LM on the primary winding Tp of the transformer T1. Therefore, as shown in Figure 4 As shown, sampling needs to be delayed until the target sampling time ts after time t3. At the target sampling time ts, the voltage across the resonant capacitor Cr should change to a value close to or even equal to the voltage across the excitation inductance LM of the primary winding Tp of the transformer T1, that is, the voltage across the resonant capacitor Cr should be n times the output voltage Vo. At this time, the voltage on the auxiliary winding Taux is sampled. The obtained sampled voltage can accurately reflect the size of the output voltage of the secondary side, avoid the sampling voltage error caused by the voltage fluctuation of the resonant capacitor Cr, and improve the primary side detection accuracy of the output voltage.

[0056] As an example, in step S202 , the control chip U1 determines the target sampling time ts based on the resonant cavity current Ip obtained in the current voltage output cycle, so that the target sampling time ts changes with the change of the resonant cavity current Ip. It can be understood that when the asymmetric half-bridge circuit is in a heavy-load state, the resonant cavity current Ip in the current voltage output cycle is larger than that in a normal state, and the time for the resonant cavity current Ip to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1 is longer. In order to avoid voltage fluctuations of the resonant capacitor Cr and make the voltage across the resonant capacitor Cr closer to n times the output voltage Vo at the target sampling time ts, the target sampling time ts determined based on the resonant cavity current Ip should also be later; when the asymmetric half-bridge circuit is in a light-load state, the resonant cavity current Ip in the current voltage output cycle is smaller than that in a normal state, and the time for the resonant cavity current Ip to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1 is shorter. In order to avoid voltage fluctuations of the resonant capacitor Cr and make the voltage across the resonant capacitor Cr closer to n times the output voltage Vo at the target sampling time ts, the target sampling time ts determined based on the resonant cavity current Ip should also be earlier. Therefore, based on the resonant cavity current Ip obtained in the current voltage output cycle, the target sampling time ts is determined, and the target sampling time ts can be changed with the change of the resonant cavity current Ip, so that the sampled voltage collected at the target sampling time ts is closer to k times the output voltage Vo, where k=(Naux / Ns)*R3 / (R2+R3), where Ns represents the number of turns of the secondary winding of the transformer T1, Naux represents the number of turns of the auxiliary winding, and R2 and R3 represent Figure 1 The resistance values ​​of resistors R2 and R3 shown can avoid sampling voltage errors caused by voltage fluctuations of the resonant capacitor Cr and improve the primary-side detection accuracy of the output voltage.

[0057] As an example, in step S203, in the current voltage output cycle, when the current moment is the target sampling moment ts, the control chip U1 obtains the sampling voltage through the auxiliary winding Taux, and then determines the output voltage based on the sampling voltage and the transformation ratio between the auxiliary winding Taux and the secondary winding Ts of the transformer T1, so as to further adjust the output of the asymmetric half-bridge circuit and realize accurate primary-side feedback control.

[0058] In this example, the control method of the asymmetric half-bridge circuit can adjust the sampling time of the auxiliary winding Taux voltage in real time based on the resonant cavity current Ip, so that the target sampling time ts can change with the change of the resonant cavity current Ip, so that the sampling voltage collected at the target sampling time ts is closer to k times the output voltage Vo, which can avoid the sampling voltage error caused by the voltage fluctuation of the resonant capacitor Cr, improve the primary side detection accuracy of the output voltage, and make the primary side feedback control more accurate.

[0059] In one embodiment, the resonant circuit includes a first switching tube Q1, a second switching tube Q2, a resonant inductor L1, and a resonant capacitor Cr. The first switching tube Q1 and the second switching tube Q2 are connected in series between a signal input terminal and ground. The resonant inductor L1, the resonant capacitor Cr, and the primary winding Tp of the transformer T1 are arranged in series between a connection node between the first switching tube Q1 and the second switching tube Q2 and ground to form a resonant cavity. The control method further includes: alternately controlling either the first switching tube or the second switching tube to turn on and the other to turn off, and when the first switching tube is turned off and the second switching tube is turned on, determining that the resonant state of the asymmetric half-bridge circuit meets a preset sampling condition.

[0060] As an example, Figure 1 As shown, the resonant circuit includes a first switch tube Q1, a second switch tube Q2, a resonant inductor L1 and a resonant capacitor Cr. The first switch tube Q1 and the second switch tube Q2 are connected in series between the signal input terminal and the ground; the resonant inductor L1, the resonant capacitor Cr and the primary winding Tp of the transformer T1 are arranged in series between the connection node between the first switch tube Q1 and the second switch tube Q2 and the ground to form a resonant cavity. The control chip U1 is used to connect the control terminals of the first switch tube Q1 and the second switch tube Q2. By alternately controlling either one of the first switch tube Q1 and the second switch tube Q2 to be turned on and the other to be turned off, the flow direction of the resonant cavity current Ip in the resonant cavity can be controlled, so that electric energy is first accumulated in the resonant cavity and then transferred to the secondary side of the transformer T1. For example, Figure 3 As shown, the control chip U1 can control the first switch tube Q1 to turn on and the second switch tube Q2 to turn off during the time period t1~t2, so that the resonant cavity current Ip flows through the resonant inductor L1, the primary winding Tp of the transformer T1 and the resonant capacitor Cr. At this time, the resonant cavity current Ip rises linearly, and the energy is stored in the resonant cavity; during the time period t3~t5, the control chip U1 controls the first switch tube Q1 to turn off and the second switch tube Q2 to turn on, so that the energy stored in the resonant cavity is released to the secondary side through electromagnetic induction between the primary and secondary sides of the transformer T1 to form the output voltage Vo. In the control method of the asymmetric half-bridge circuit, when the first switch tube Q1 is turned off and the second switch tube Q2 is on, it can be determined that the resonant state of the asymmetric half-bridge circuit meets the preset sampling conditions, and the moment when the first switch tube Q1 is turned off and the second switch tube Q2 is turned on is used as the starting detection moment To, that is, Figure 3At time t3 in the example, before time t3, the resonant cavity current Ip rises linearly. At time t3, the resonant cavity current Ip corresponding to the resonant cavity begins to be sampled. At this point, the resonant cavity current Ip reaches its peak value. The resonant cavity current Ip sampled at time t3 can be marked as the peak current. After time t3, the resonant cavity current Ip begins to oscillate between the resonant capacitor Cr and the magnetizing inductance on the primary winding Tp of the transformer T1. In this example, by sampling only the resonant cavity current Ip at and after time t3 and adjusting the target sampling time ts based on the resonant cavity current Ip at and after time t3, the maximum value of the resonant cavity current Ip in the current voltage output cycle can be obtained. The resonant cavity current Ip during the voltage output phase can then be monitored in real time to effectively adjust the target sampling time ts, while also conserving resources in the control chip U1.

[0061] In one embodiment, if Figure 5 As shown, step S202, that is, determining the target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity, includes:

[0062] S501: Determine a target delay time according to a resonant cavity current corresponding to the resonant cavity;

[0063] S502: Determine a target sampling time based on the start detection time and the target delay time.

[0064] The target delay time td is the time the control chip U1 delays after turning off the first switch Q1 and turning on the second switch Q2, waiting to sample the voltage corresponding to the auxiliary winding Taux. The target sampling time ts is reached after the target delay time td has elapsed from the initial detection time To.

[0065] As an example, in step S501, the control chip U1 can determine the length of the target delay time td based on the resonant cavity current Ip corresponding to the acquired resonant cavity. It can be understood that when the asymmetric half-bridge circuit is in a heavy load state, the resonant cavity current Ip of the current voltage output cycle is larger than that under normal circumstances, and the resonant cavity current Ip takes a longer time to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1. In order to avoid the voltage fluctuation of the resonant capacitor Cr, the voltage across the resonant capacitor Cr at the target sampling time ts is made closer to n times. The target delay time td determined based on the resonant cavity current Ip should be longer for the output voltage Vo. When the asymmetric half-bridge circuit is in a light-load state, the resonant cavity current Ip in the current voltage output cycle is smaller than in normal conditions. The time for the resonant cavity current Ip to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1 is shorter. To avoid voltage fluctuations in the resonant capacitor Cr and make the voltage across the resonant capacitor Cr closer to n times the output voltage Vo at the target sampling time ts, the target delay time td determined based on the resonant cavity current Ip should be shorter. Therefore, by determining the target delay time td based on the resonant cavity current Ip obtained in the current voltage output cycle, the length of the target delay time td can be changed in accordance with the changes in the resonant cavity current Ip, so that the sampled voltage collected at the target sampling time ts is closer to k times the output voltage Vo. This can avoid sampling voltage errors caused by voltage fluctuations in the resonant capacitor Cr and improve the primary side detection accuracy of the output voltage.

[0066] As an example, in step S502, based on the starting detection time To and the obtained target delay time td, the control chip U1 can record the time after the target delay time td from the starting detection time To as the target sampling time ts, and obtain the sampling voltage corresponding to the auxiliary winding Taux at the target sampling time ts.

[0067] In one embodiment, if Figure 6 As shown, step S501, that is, determining the target delay time according to the resonant cavity current corresponding to the resonant cavity, includes:

[0068] S601: Obtaining a peak current corresponding to the resonant cavity based on a resonant cavity current corresponding to the resonant cavity;

[0069] S602: Determine a target delay time based on a peak current corresponding to the resonant cavity.

[0070] As an example, in step S601, in the control method of the asymmetric half-bridge circuit, the starting detection time To is the time when the control chip U1 starts to obtain the resonant cavity current Ip in each voltage output cycle of the asymmetric half-bridge circuit. Specifically, the time when the asymmetric half-bridge circuit starts to transfer energy to the secondary side of the transformer T1 and generates the output voltage can be used as the starting detection time To. When the primary side electrical energy of the transformer T1 is fully stored. When the asymmetric half-bridge circuit starts to transfer energy to the secondary side of the transformer T1, the resonant cavity current Ip is at the peak value of this voltage output cycle. The control chip U1 can use the resonant cavity current Ip detected at the starting detection time To as the peak current corresponding to the resonant cavity.

[0071] As an example, in step S602, the control chip U1 can determine the length of the target delay time td based on the peak current corresponding to the resonant cavity obtained. It can be understood that when the asymmetric half-bridge circuit is in a heavy-load state, the peak current corresponding to the resonant cavity in the current voltage output cycle is larger than that in normal circumstances. After time t3, the time for the resonant cavity current Ip to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1 will be longer. In order to avoid voltage fluctuations of the resonant capacitor Cr, the voltage across the resonant capacitor Cr at the target sampling time ts is set to 0. When the voltage across the resonant capacitor Cr is closer to n times the output voltage Vo, the determined target delay time td should be longer; when the asymmetric half-bridge circuit is in a light-load state, the peak current corresponding to the resonant cavity in the current voltage output cycle is smaller than that in normal circumstances. After time t3, the time for the resonant cavity current Ip to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1 will be shorter. In order to avoid voltage fluctuations on the resonant capacitor Cr and make the voltage across the resonant capacitor Cr at the target sampling time ts closer to n times the output voltage Vo, the determined target delay time td should be shorter.

[0072] Specifically, if Figure 1 The working waveform of the asymmetric half-bridge circuit shown in the figure during one voltage output cycle is as follows: Figure 3 As shown,

[0073] (1) t0~t2 stage

[0074] Before t0, the body diode of the first switch tube Q1 gradually turns on, and the midpoint voltage VHB gradually rises from 0V to Vbus, providing conditions for the first switch tube Q1 to achieve ZVS. At time t0, the control chip U1 outputs a high level to the first switch tube Q1, causing the current to transfer from the body diode of the first switch tube Q1 to the channel.

[0075] During the time period t1 to t2, the resonant cavity current Ip flows through the resonant inductor L1, the excitation inductance LM of the primary winding Tp of the transformer T1, and the resonant capacitor Cr. The current is recorded as Imagpos and rises linearly, storing energy in the resonant cavity. The current expression of this process is as follows:

[0076] ;

[0077] Where Ip is the resonant cavity current Ip.

[0078] Define Ton=t2-t1. At t=t2, define Ip(t2)=Imagpos, which is the peak current. Define duty cycle D=ton / T. The output voltage is Vo. The primary-to-secondary ratio of transformer T1 is n. Then Vcr approximately satisfies the following relationship:

[0079] ;

[0080] Solving the differential equations of Equation 1 and Equation 2 simultaneously, we can obtain the exact expression of Vcr as follows:

[0081] ;

[0082] in, is the resonant angular frequency of (L1+LM) and Cr, is the resonant impedance of (L1+LM) and Cr.

[0083] In order to simplify the analysis, it can be considered that Then Equation 4 is simplified to

[0084]

[0085] (2) T2-T3 stage

[0086] At time t2, the control chip U1 outputs a low level to the first switch tube Q1, and the peak current flows through the body diode of the second switch tube Q2. VHB drops from Vbus to 0, providing conditions for the second switch tube Q2 to achieve ZVS. At time t3, the control chip U1 outputs a high level to the second switch tube Q2, and the current is transferred from the body diode of the second switch tube Q2 to the channel.

[0087] (3) T3~T5 stage

[0088] During the time period t3 to t5, the energy stored in the resonant cavity is released to the secondary side. At this time, the freewheeling diode D1 connected to the secondary winding Ts of the output transformer T1 is turned on. During this time period, the voltage across the excitation inductor LM of the primary winding Tp of the transformer T1 is approximately clamped to nVo, as shown in Expression 6, where n represents the ratio of the number of turns Np of the primary side of the transformer T1 to the number of turns Ns of the secondary side, Vo represents the output voltage, and the excitation current decreases linearly according to the slope of nVo / LM. Figure 3 As shown by the dotted line Imag;

[0089] ;

[0090] In the above formula , the resonant cavity current Ip changes according to the following formula.

[0091] ;

[0092] Combining Equation 8 and Equation 2 can yield relatively accurate expressions for the resonant cavity current Ip and voltage Vcr:

[0093] ;

[0094] in, .

[0095] For Equation 10, if The voltage on the auxiliary winding Taux is sampled at all times, so that the voltage on the auxiliary winding Taux at this time can accurately reflect the output voltage, thereby achieving high-precision sampling.

[0096] At this time, the target sampling time ts needs to satisfy the following formula:

[0097] ;

[0098] Furthermore, the target sampling time ts needs to satisfy the following formula:

[0099] ;

[0100] because , for the convenience of analysis, it is converted into the following formula:

[0101] ;

[0102] According to Equation 19, the peak current When the value is larger, the target sampling time ts needs to be delayed to meet .

[0103] In this example, by quantitatively obtaining the peak current corresponding to the resonant cavity, it is possible to conveniently compare the time it takes for the resonant cavity current Ip to oscillate between the resonant capacitor Cr and the excitation inductance LM on the primary winding Tp of the transformer T1 in different voltage output cycles, so as to appropriately extend or shorten the target delay time td. This allows the target delay time td to change with the resonant cavity current Ip, thereby improving the primary-side detection accuracy of the output voltage.

[0104] In one embodiment, the peak current corresponding to the resonant cavity is the resonant cavity current Ip collected at the start detection time To.

[0105] As an example, in the control method of the asymmetric half-bridge circuit, the starting detection time To may be the time when the first switch tube Q1 is turned off and the second switch tube Q2 is turned on. Figure 3 Before time t3, the resonant cavity current Ip rises linearly until it reaches its peak at time t2 when the first switch tube Q1 turns off. At time t3, when the second switch tube Q2 turns on, the resonant cavity current Ip is the same as at time t2. The control chip U1 can use the resonant cavity current Ip collected at the starting detection time To as the peak current corresponding to the resonant cavity in the current voltage output cycle.

[0106] In one embodiment, step S602, i.e., determining the target delay time based on the peak current corresponding to the resonant cavity, includes: determining the target delay time based on the peak current corresponding to the resonant cavity and a preset current-time mapping relationship, wherein the preset voltage-time mapping relationship is used to reflect the mapping relationship between the peak current and the delay time.

[0107] As an example, the preset current-time mapping relationship can be a pre-set linear / non-linear calculation formula with the peak current as the independent variable and the target delay time td as the dependent variable. The peak current of the current voltage output cycle is substituted into the calculation formula to calculate the delay time corresponding to the peak current, and then the delay time is determined as the target delay time td for voltage sampling; or, the preset current-time mapping relationship can also be a pre-set current-time mapping relationship table corresponding to the peak current and the target delay time td. The corresponding delay time can be obtained by looking up the table based on the peak current of the current voltage output cycle, and then the delay time is determined as the target delay time td for voltage sampling.

[0108] In one embodiment, the preset current-time mapping relationship includes multiple preset current intervals, each preset current interval corresponds to a preset delay time; based on the peak current corresponding to the resonant cavity and the preset current-time mapping relationship, the target delay time is determined, including: determining the preset current interval in which the peak current corresponding to the resonant cavity is located as the target current interval, and determining the preset delay time corresponding to the target current interval as the target delay time.

[0109] As an example, the preset current-time mapping relationship includes multiple preset current intervals, which can be multiple continuous intervals, such as 0~I1, I1~I2..., or multiple discontinuous intervals, such as 0~I1, I2~I3... Each preset current interval corresponds to a preset delay time. When the peak current of the current voltage output cycle obtained is within a certain preset current interval, the preset delay time corresponding to the preset current interval is used as the target delay time td.

[0110] In one embodiment, if Figure 7 As shown, step S202, that is, determining the target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity, includes:

[0111] S701: Determine a current change rate based on a resonant cavity current corresponding to the resonant cavity;

[0112] S702: Determine the sampling time when the current change rate is 0 as the target sampling time.

[0113] As an example, in step S701 , the control chip U1 may determine the current change rate corresponding to the resonant cavity current Ip based on the resonant cavity current Ip continuously acquired since the start detection time To and the sampling time.

[0114] As an example, in step S702, combined with Formula 9 in the above example: , and Equation 18: . Take the derivative of Equation 9 to obtain And order , we can solve Equation 18. Therefore, when the derivative of Equation 9 is 0, Equation 18 is valid. The validity of Equation 18 indicates that the moment when the derivative of Equation 9 is 0 is when the voltage across the resonant capacitor Cr is n times the output voltage Vo. Equation 9 is the expression of the resonant cavity current Ip. The derivative of Equation 9 is 0, which is equivalent to the current change rate corresponding to the resonant cavity current Ip being 0. Therefore, the moment when the current change rate corresponding to the resonant cavity current Ip is 0 is exactly the moment when the voltage across the resonant capacitor Cr is n times the output voltage Vo at the target sampling time ts. The sampling time when the current change rate is 0 is determined as the target sampling time ts. The control chip U1 detects the sampling voltage on the auxiliary winding Taux according to the target sampling time ts, and can accurately obtain the output voltage of the current voltage output cycle to eliminate errors.

[0115] An embodiment of the present invention also provides a control chip U1, including a memory, a processor, and a computer program stored in the memory and runnable on the processor. The control chip U1 is characterized in that the control chip U1 is applied in an asymmetric half-bridge circuit, and when the processor executes the computer program, it implements the control method of the asymmetric half-bridge circuit according to any of the above items.

[0116] An embodiment of the present invention also provides a power supply circuit, including a primary-side rectifier and filter circuit, a secondary-side rectifier and filter circuit, a current sampling unit 1, any of the above-mentioned asymmetric half-bridge circuits, and the above-mentioned control chip U1; the input end of the primary-side rectifier and filter circuit is used to connect to the mains circuit, the output end of the primary-side rectifier and filter circuit is connected to the resonant circuit of the asymmetric half-bridge circuit, the secondary winding Ts of the transformer T1 of the asymmetric half-bridge circuit is connected to the input end of the secondary-side rectifier and filter circuit, and the output end of the secondary-side rectifier and filter circuit is used to connect to an external load and supply power to the external load; the current sampling unit 1 is connected to the resonant cavity of the asymmetric half-bridge circuit and is also connected to the control chip, and is used to collect the resonant cavity current Ip corresponding to the resonant cavity and output the resonant cavity current Ip to the control chip U1; the control chip U1 is connected to the auxiliary winding Taux, and is used to determine the target sampling time ts based on the resonant cavity current Ip corresponding to the resonant cavity, and when the current time is the target sampling time ts, collect the sampling voltage corresponding to the auxiliary winding Taux.

[0117] As an example, the power supply circuit includes a primary-side rectifier and filter circuit, a secondary-side rectifier and filter circuit, a current sampling unit 1, any of the aforementioned asymmetric half-bridge circuits, and the aforementioned control chip U1. The input end of the primary-side rectifier and filter circuit is used to connect to the mains circuit, the output end of the primary-side rectifier and filter circuit is connected to the resonant circuit of the asymmetric half-bridge circuit, the secondary winding Ts of the transformer T1 of the asymmetric half-bridge circuit is connected to the input end of the secondary-side rectifier and filter circuit, and the output end of the secondary-side rectifier and filter circuit is used to connect to an external load to supply power to the external load. The control chip U1 is connected to the resonant cavity of the asymmetric half-bridge circuit via the current sampling unit 1 and is also connected to the auxiliary winding Taux. It is used to obtain the resonant cavity current Ip corresponding to the resonant cavity and obtain a target sampling time ts based on the resonant cavity current Ip. When the current time is the target sampling time ts, the sampled voltage corresponding to the auxiliary winding Taux is collected, and the current output voltage is calculated based on the sampled voltage to complete primary-side feedback control.

[0118] In this example, by adjusting the sampling moment of the auxiliary winding Taux voltage in real time based on the resonant cavity current Ip, the target sampling moment ts can be changed following the change of the resonant cavity current Ip, so that the sampling voltage collected at the target sampling moment ts is closer to k times the output voltage Vo, which can avoid the sampling voltage error caused by the voltage fluctuation of the resonant capacitor Cr, improve the primary side detection accuracy of the output voltage, and make the primary side feedback control more accurate.

[0119] An embodiment of the present invention further provides a charger including the above-mentioned power supply circuit.

[0120] As an example, the charger includes the aforementioned power supply circuit. In this example, by adjusting the sampling time of the auxiliary winding Taux voltage in real time based on the resonant cavity current Ip, the target sampling time ts can be adjusted to follow the changes in the resonant cavity current Ip. This allows the sampled voltage acquired at the target sampling time ts to be closer to k times the output voltage Vo. This avoids sampling voltage errors caused by voltage fluctuations on the resonant capacitor Cr, improves primary-side detection accuracy of the output voltage, and enhances primary-side feedback control accuracy.

[0121] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A control method for an asymmetric half-bridge circuit, characterized in that: The asymmetric half-bridge circuit includes a resonant circuit, a transformer and an auxiliary winding; the auxiliary winding is coupled to the primary winding of the transformer; The primary winding of the transformer is connected to the resonant circuit to form a resonant cavity, and the control method includes: When the resonant state of the asymmetric half-bridge circuit meets a preset sampling condition, determining a starting detection time and collecting a resonant cavity current corresponding to the resonant cavity; determining a target sampling time based on the starting detection time and a resonant cavity current corresponding to the resonant cavity; When the current moment is the target sampling moment, collecting the sample voltage corresponding to the auxiliary winding; The determining of the target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity includes: Determining a target delay time according to a resonant cavity current corresponding to the resonant cavity; Determining a target sampling time based on the starting detection time and the target delay time; The resonant circuit includes a first switching transistor, a second switching transistor, a resonant inductor, and a resonant capacitor, wherein the first switching transistor and the second switching transistor are connected in series between a signal input terminal and ground; the resonant inductor, the resonant capacitor, and the primary winding of the transformer are connected in series between a connection node between the first switching transistor and the second switching transistor and ground to form the resonant cavity. The control method further includes: staggeredly controlling either the first switch tube or the second switch tube to turn on and the other to turn off, and determining that the resonant state of the asymmetric half-bridge circuit meets a preset sampling condition when the first switch tube is turned off and the second switch tube is turned on; The determining of the target sampling time based on the starting detection time and the resonant cavity current corresponding to the resonant cavity includes: determining a current change rate based on a resonant cavity current corresponding to the resonant cavity; The sampling moment when the current change rate is 0 is determined as the target sampling moment.

2. The control method of the asymmetric half-bridge circuit according to claim 1, characterized in that: The determining of the target delay time according to the resonant cavity current corresponding to the resonant cavity includes: Obtaining a peak current corresponding to the resonant cavity based on a resonant cavity current corresponding to the resonant cavity; A target delay time is determined based on a peak current corresponding to the resonant cavity.

3. The control method of the asymmetric half-bridge circuit according to claim 2, characterized in that: The peak current corresponding to the resonant cavity is the resonant cavity current collected at the start detection moment.

4. The control method of the asymmetric half-bridge circuit according to claim 2, characterized in that: The determining of the target delay time based on the peak current corresponding to the resonant cavity includes: The target delay time is determined based on a peak current corresponding to the resonant cavity and a preset current-time mapping relationship, wherein the preset current-time mapping relationship is used to reflect a mapping relationship between the peak current and the delay time.

5. The control method of the asymmetric half-bridge circuit according to claim 4, characterized in that: The preset current-time mapping relationship includes a plurality of preset current intervals, each of the preset current intervals corresponding to a preset delay time; The determining of the target delay time based on the peak current corresponding to the resonant cavity and the preset current-time mapping relationship includes: A preset current interval in which the peak current corresponding to the resonant cavity is located is determined as a target current interval, and a preset delay time corresponding to the target current interval is determined as a target delay time.

6. A control chip comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The control chip is applied in an asymmetric half-bridge circuit, and the processor implements the control method of the asymmetric half-bridge circuit according to any one of claims 1 to 5 when executing the computer program.

7. A power supply circuit, characterized in that: It comprises a primary-side rectifier and filter circuit, a secondary-side rectifier and filter circuit, a current sampling unit, the asymmetric half-bridge circuit according to any one of claims 1 to 5, and the control chip according to claim 6; The input end of the primary rectifier and filter circuit is used to connect to the mains circuit, the output end of the primary rectifier and filter circuit is connected to the resonant circuit of the asymmetric half-bridge circuit, the secondary winding of the transformer of the asymmetric half-bridge circuit is connected to the input end of the secondary rectifier and filter circuit, and the output end of the secondary rectifier and filter circuit is used to connect to an external load to supply power to the external load; The current sampling unit is connected to the resonant cavity of the asymmetric half-bridge circuit and is also connected to the control chip, and is used to collect the resonant cavity current corresponding to the resonant cavity and output the resonant cavity current to the control chip; The control chip is connected to the auxiliary winding, and is used to determine a target sampling moment based on the resonant cavity current corresponding to the resonant cavity, and to collect a sampling voltage corresponding to the auxiliary winding when the current moment is the target sampling moment.

8. A charger, characterized in that: Includes the power supply circuit according to claim 7.

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