Comparator-based CMOS oscillator

Abstract

The invention discloses a design of an integrated CMOS oscillator. The integrated CMOS oscillator comprises first to eighth N-type transistors, first to eleventh P-type transistors, first to fourth phase inverters, a first resistor, and first to second capacitors. The duty ratio of the oscillation signal output by the circuit structure is easy to design, and the requirements of actual circuit application can be met.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and particularly to a comparator-based CMOS oscillator. Background Art

[0002] As an indispensable module of the switching power supply, the oscillator is required to have low cost, high efficiency, wide temperature range, and strong process and power supply deviation tolerance. Compared with crystal and ceramic resonators, the CMOS oscillator has a small volume, high integration, and is insensitive to vibration, shock, and electromagnetic interference (EMI). In most existing application scenarios, it is required that the frequency and duty cycle of the oscillator be stable to provide a clock signal for other modules. Summary of the Invention

[0003] The present invention proposes a comparator-based CMOS oscillator, which can provide a square wave signal with a fixed oscillation frequency and duty cycle in the system, and the frequency and duty cycle are easy to design, with high precision and high flexibility.

[0004] The present invention provides a comparator-based CMOS oscillator, including a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a first charge and discharge capacitor, a second charge and discharge capacitor, and a first resistor. The duty cycle of the oscillation signal output by the circuit structure is easy to design and can meet the requirements of actual circuit applications.

[0005] In an exemplary embodiment, the comparator-based CMOS oscillator includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a first charge-discharge capacitor, a second charge-discharge capacitor, and a first resistor. The first charge-discharge capacitor is connected to the drain of the first N-type transistor, the gate of the second P-type transistor, and the drain of the eleventh P-type transistor. The other end of the first capacitor is grounded together with the source of the first N-type transistor, the source of the second N-type transistor, the source of the third N-type transistor, the source of the sixth N-type transistor, the source of the seventh N-type transistor, and the source of the eighth N-type transistor. The source of the first P-type transistor is connected to the power supply together with the source of the fourth P-type transistor, the source of the seventh P-type transistor, the source of the eighth P-type transistor, the source of the ninth P-type transistor, the source of the tenth P-type transistor, and the source of the eleventh P-type transistor. The gate of the eleventh P-type transistor is connected to an external bias voltage. The gate of the third P-type transistor is connected to an external voltage signal. The gate of the first P-type transistor is connected to the gates of the fourth P-type transistor, the seventh P-type transistor, the eighth P-type transistor, the ninth P-type transistor, and the tenth P-type transistor. The drain of the first P-type transistor is connected to the source of the second P-type transistor and the source of the third P-type transistor. The drain of the second P-type transistor is connected to the gate of the second N-type transistor, the drain of the second N-type transistor, and the gate of the fifth P-type transistor. The drain of the third P-type transistor is connected to the drain of the third N-type transistor, the gate of the third N-type transistor, and the gate of the sixth P-type transistor.The drain of the fourth P-type transistor is connected to the sources of the fifth P-type transistor and the sixth P-type transistor. The drain of the fifth P-type transistor is connected to the gate and drain of the seventh N-type transistor and the source of the fifth N-type transistor. The drain of the sixth P-type transistor is connected to the source of the fourth N-type transistor, the drain of the sixth N-type transistor, and the gate of the sixth N-type transistor. The gate of the fourth N-type transistor is connected to the drain of the fourth N-type transistor, the gate of the fifth N-type transistor, and the drain of the seventh P-type transistor. The drain of the fifth N-type transistor is connected to the drain of the eighth P-type transistor and the gate of the eighth N-type transistor. The drain of the ninth P-type transistor is connected to the drain of the eighth N-type transistor, one end of the second charge and discharge capacitor, the input terminal of the first inverter, and one end of the first resistor. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the other end of the second charge and discharge capacitor and the input terminal of the third inverter. The output terminal of the third inverter is connected to the gate of the first N-type transistor and the input terminal of the fourth inverter. The other end of the first resistor is connected to the drain of the tenth P-type transistor. The output terminal of the fourth inverter is connected to the gate of the tenth P-type transistor and outputs an oscillation signal.;

[0006] The present invention includes the following features and advantages:

[0007] A comparator-based CMOS oscillator provided by the present invention can provide a square wave signal with a fixed oscillation frequency and duty cycle in a system, and the frequency and duty cycle are easy to design.

[0008] The low-level time and frequency of the oscillation signal output by the oscillator can be controlled by the second charge and discharge capacitor. When the capacitance value of the second charge and discharge capacitor is larger, the low-level time is longer, the period is longer, and the frequency is lower.

[0009] The magnitude of the charge of the first charge and discharge capacitor of the CMOS oscillator affects the rise time of the input signal of the first-stage comparator.

[0010] Of course, it is not necessary for any circuit applying the present invention to achieve all the above-mentioned advantages simultaneously. Other features and advantages of the present invention will be described in the subsequent specification. Moreover, other advantages of the present application can be realized and obtained through the solutions described in the specification. Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0012] Figure 1 Schematic diagram of a comparator-based CMOS oscillator in an embodiment of the present application; Detailed implementation manner

[0013] The accompanying drawings that form a part of the present invention are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0014] As Figure 1 shown, it is a schematic diagram of the structure of a CMOS oscillator in an embodiment of the present application. This embodiment provides a comparator-based CMOS oscillator, including: PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, inverters INV1, INV2, INV3, INV4, charge and discharge capacitors C1, C2, resistor R1. The external input signal is the power supply connected to VDD, the ground is connected to GND, the input voltage signal is connected to V1, the external bias voltage is connected to Vb, and the output signal is connected to OUT.

[0015] C1 is connected to the drain of MN1, the gate of MP2, and the drain of MP11. The other end of C1 is grounded to GND together with the sources of MN1, MN2, MN3, MN6, MN7, and MN8; the sources of MP1 are connected to the sources of MP4, MP7, MP8, MP9, and MP10 and are all connected to the power supply VDD. The gate of MP3 is connected to the external voltage signal V1. The gates of MP1 are connected to the gates of MP4, MP7, MP8, MP9, and MP10. The drain of MP1 is connected to the source of MP2 and the source of MP3. The drain of MP2 is connected to the gate of MN2, the drain of MN2, and the gate of MP5. The drain of MP3 is connected to the drain of MN3, the gate of MN3, and the gate of MP6; the drain of MP4 is connected to the source of MP5 and the source of MP6. The drain of MP5 is connected to the gate of MN7, the drain of MN7, and the source of MN5. The drain of MP6 is connected to the source of MN4, the drain of MN6, and the gate of MN6. The gate of MN4 is connected to the drain of MN4, the gate of MN5, and the drain of MP7. The drain of MN5 is connected to the drain of MP8 and the gate of MN8. The drain of MP9 is connected to the drain of MN8, one end of C2, the input terminal of INV1, and one end of R1. The output terminal of INV1 is connected to the input terminal of INV2. The output terminal of INV2 is connected to the other end of C2 and the input terminal of INV3. The output terminal of INV3 is connected to the gate of MN1 and the input terminal of INV4. The other end of R1 is connected to the drain of MP10. The output terminal of INV4 is connected to the gate of MP10 and outputs the oscillation signal OUT.

[0016] The specific working process of this circuit is as follows: The current generated by the MP11 branch charges the capacitor C1, and the voltage V2 rises slowly. When V2 rises to V1, the output terminal of the first-stage comparator composed of MP1, MP2, MP3, MN2, and MN3 outputs a high or low level signal, and transmits it to the input terminal of the second-stage folded operational amplifier composed of MP4, MP5, MP6, MP7, MP8, MN4, MN5, MN6, and MN7. The output signal of the second-stage operational amplifier is transmitted to the third-stage common-source amplifier composed of MP9 and MN8. The output signal of the third-stage amplifier is a low level signal, which is transmitted to the output terminal OUT through four inverters; when the output signal OUT is at a low level, the MN1 transistor conducts, the capacitor C1 discharges and V2 drops, the MP10 transistor conducts, and the capacitor C2 is charged. After C2 is charged to the inversion voltage of INV1, INV1 outputs a low level, and the output terminal OUT flips to a high level. At the same time, INV3 outputs a low level to turn off the MN1 transistor, and the capacitor C1 starts to be charged, and the voltage V2 rises. After passing through three operational amplifiers and four inverters, the output terminal OUT outputs a low level signal, completing an oscillation cycle.

[0017] In summary, the present disclosure provides a comparator-based CMOS oscillator, which can provide a square wave signal with a fixed oscillation frequency and duty cycle in the system, and the frequency and duty cycle are easy to design.

[0018] It should be noted that the ordinal numbers such as "first", "second", "third", etc. used in the specification and claims are used to modify the corresponding elements. They do not themselves imply any ordinal number of the element, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish an element with a certain name from another element with the same name.

[0019] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A CMOS oscillator based on a comparator, characterized in that: It includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a first charge and discharge capacitor, a second charge and discharge capacitor, and a first resistor.

2. A comparator-based cMOS oscillator according to claim 1, characterized in that: The first charge-discharge capacitor is connected to the drain of the first N-type transistor, the gate of the second P-type transistor, and the drain of the eleventh P-type transistor; the other end of the first capacitor is connected to the source of the first N-type transistor, the source of the second N-type transistor, the source of the third N-type transistor, the source of the sixth N-type transistor, the source of the seventh N-type transistor, and the source of the eighth N-type transistor, and the gate of the eleventh P-type transistor is connected to an external bias voltage; The source of the first P-type transistor and the source of the fourth P-type transistor, the source of the seventh P-type transistor, the source of the eighth P-type transistor, the source of the ninth P-type transistor, the source of the tenth P-type transistor, and the source of the eleventh P-type transistor are all connected to a power supply, the gate of the third P-type transistor is connected to an external voltage signal, the gate of the first P-type transistor is connected to the gate of the fourth P-type transistor, the gate of the seventh P-type transistor, the gate of the eighth P-type transistor, and the gate of the ninth P-type transistor, the drain of the first P-type transistor is connected to the source of the second P-type transistor and the source of the third P-type transistor, the drain of the second P-type transistor is connected to the gate of the second N-type transistor, the drain of the second N-type transistor, and the gate of the fifth P-type transistor, and the drain of the third P-type transistor is connected to the drain of the third N-type transistor, the gate of the third N-type transistor, and the gate of the sixth P-type transistor; The drain of the fourth P-type transistor is connected to the source of the fifth P-type transistor and the source of the sixth P-type transistor, the drain of the fifth P-type transistor is connected to the gate of the seventh N-type transistor, the drain of the seventh N-type transistor, and the source of the fifth N-type transistor, the drain of the sixth P-type transistor is connected to the source of the fourth N-type transistor, the drain of the sixth N-type transistor, and the gate of the sixth N-type transistor, the gate of the fourth N-type transistor is connected to the drain of the fourth N-type transistor, the gate of the fifth N-type transistor, and the drain of the seventh P-type transistor, the drain of the fifth N-type transistor is connected to the drain of the eighth P-type transistor, the drain of the eighth N-type transistor The ninth P-type transistor is connected to the gate of the transistor, the drain of the ninth P-type transistor is connected to the drain of the eighth N-type transistor, one end of the second charge and discharge capacitor, the input end of the first inverter, and one end of the first resistor, the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the other end of the second charge and discharge capacitor and the input end of the third inverter, the output end of the third inverter is connected to the gate of the first N-type transistor and the input end of the fourth inverter, the other end of the first resistor is connected to the drain of the tenth P-type transistor, and the output end of the fourth inverter is connected to the gate of the tenth P-type transistor and outputs an oscillation signal.

3. A comparator-based CMOS oscillator according to claim 1, characterized in that: The low level time of the output oscillation signal is adjusted by the tenth P-type transistor, the first resistor, the second charge-discharge capacitor, the first inverter, and the second inverter.

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