Integrated circuit with multiple clocks and method of operation thereof

Abstract

An integrated circuit with multiple clocks comprises a crystal oscillator circuit, a first functional circuit, a phase-locked loop circuit and a second functional circuit. The crystal oscillator circuit is used for generating a first clock signal. The first functional circuit is configured to receive a first clock signal and operate according to the first clock signal. The phase-locked loop circuit is used for generating a second clock signal according to the first clock signal. The second functional circuit is configured to receive a second clock signal and operate according to the second clock signal.

Description

Technical Field

[0001] The present disclosure relates to technologies related to clock signals. In particular, it relates to an integrated circuit with multiple clocks and an operation method thereof. Background Art

[0002] With the development of technology, various integrated circuits have been developed. In the known technology, when two circuits are provided on a system-on-chip and the two circuits operate based on two different clock signals respectively, two crystal oscillator circuits need to be provided on the system-on-chip to generate the above two different clock signals respectively. However, this will increase the cost and occupy a large space on the printed circuit board. Summary of the Invention

[0003] Some embodiments of the present disclosure relate to an integrated circuit with multiple clocks. The integrated circuit includes a crystal oscillator circuit, a first functional circuit, a phase-locked loop circuit, and a second functional circuit. The crystal oscillator circuit is used to generate a first clock signal. The first functional circuit is used to receive the first clock signal and operate according to the first clock signal. The phase-locked loop circuit is used to generate a second clock signal according to the first clock signal. The second functional circuit is used to receive the second clock signal and operate according to the second clock signal.

[0004] Some embodiments of the present disclosure relate to an operation method of an integrated circuit with multiple clocks. The operation method includes the following operations: generating a first clock signal via the crystal oscillator circuit; receiving the first clock signal via the first functional circuit and operating according to the first clock signal; generating a second clock signal via the phase-locked loop circuit according to the first clock signal; and receiving the second clock signal via the second functional circuit and operating according to the second clock signal. Brief Description of the Drawings

[0005] To make the above and other purposes, features, advantages, and embodiments of the present disclosure more obvious and understandable, the descriptions of the accompanying drawings are as follows:

[0006] Figure 1 is a schematic diagram of an integrated circuit with multiple clocks illustrated according to some embodiments of the present disclosure;

[0007] Figure 2 is a schematic diagram of an integrated circuit with multiple clocks illustrated according to some embodiments of the present disclosure;

[0008] Figure 3 is a waveform diagram of a clock signal and a reference clock signal illustrated according to some embodiments of the present disclosure;

[0009] Figure 4 is a flowchart of a method for generating a count value illustrated according to some embodiments of the present disclosure;

[0010] Figure 5 is a schematic diagram of an integrated circuit with multiple clocks according to some embodiments of the present disclosure;

[0011] Figure 6 is a schematic diagram of an integrated circuit with multiple clocks according to some embodiments of the present disclosure;

[0012] Figure 7 is a schematic diagram of a phase-locked loop circuit according to some embodiments of the present disclosure;

[0013] Figure 8 is a schematic diagram of a reference clock signal generation circuit according to some embodiments of the present disclosure; and

[0014] Figure 9 is a flowchart of an operation method according to some embodiments of the present disclosure. Detailed Embodiments

[0015] As used herein, the term "coupled" may also refer to "electrically coupled", and the term "connected" may also refer to "electrically connected". "Coupled" and "connected" may also refer to two or more components cooperating or interacting with each other.

[0016] Reference Figure 1 。 Figure 1 is a schematic diagram of an integrated circuit 100 with multiple clocks according to some embodiments of the present disclosure. The integrated circuit 100 may operate based on two clock signals CLK1 and CLK2. In some embodiments, the integrated circuit 100 may be implemented by a system on a chip (SoC).

[0017] For Figure 1 example, the integrated circuit 100 includes a crystal oscillator circuit 110, a functional circuit 120, a phase-locked loop circuit 130, and a functional circuit 140. In terms of the coupling relationship, the crystal oscillator circuit 110 is coupled to the functional circuit 120 and the phase-locked loop circuit 130. The phase-locked loop circuit 130 is coupled to the functional circuit 140.

[0018] The crystal oscillator circuit 110 may generate the clock signal CLK1 and transmit the clock signal CLK1 to the functional circuit 120 and the phase-locked loop circuit 130. In some embodiments, the crystal oscillator circuit 110 may include a quartz crystal and two capacitors.

[0019] The functional circuit 120 may receive the clock signal CLK1 and operate according to the clock signal CLK1. In some embodiments, the functional circuit 120 includes a real time clock (RTC) circuit, but the present disclosure is not limited thereto. The real time clock circuit may provide an accurate actual time.

[0020] A phase-locked loop (PLL) circuit 130 can generate a clock signal CLK2 based on a clock signal CLK1 and transmit the clock signal CLK2 to a functional circuit 140. Generally, the frequency of the clock signal CLK2 is different from that of the clock signal CLK1. For example, the frequency of the clock signal CLK1 can be 32.768 kilohertz (KHz) while the frequency of the clock signal CLK2 can be 900 megahertz (MHz), but the present disclosure is not limited thereto.

[0021] The functional circuit 140 can receive the clock signal CLK2 and operate based on the clock signal CLK2. In some embodiments, the functional circuit 140 includes a central processing unit circuit, a universal serial bus circuit, or an Ethernet circuit, but the present disclosure is not limited to these.

[0022] In the prior art, when there are two circuits provided on a system-on-chip and the two circuits operate based on two different clock signals respectively, it is necessary to provide two crystal oscillator circuits on the system-on-chip to generate the above two different clock signals respectively, that is, there will be two quartz crystals and four capacitors provided on the system-on-chip of the prior art. However, this will increase the cost and occupy a large space on the printed circuit board.

[0023] Compared with the prior art, in the present disclosure, only a single crystal oscillator circuit 110 needs to be provided to enable the functional circuit 120 and the functional circuit 140 to operate based on different clock signals CLK1 and CLK2 respectively. Accordingly, the present disclosure can not only reduce the cost, but also occupy a smaller space on the printed circuit board to improve the space utilization rate of the printed circuit board.

[0024] Reference Figure 2 。 Figure 2 is a schematic diagram of an integrated circuit 200 with multiple clocks according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 200 can be used to implement Figure 1 the integrated circuit 100 in

[0025] Taking Figure 2 as an example, in addition to the crystal oscillator circuit 210, the functional circuit 220, the phase-locked loop circuit 230, and the functional circuit 240, the integrated circuit 200 further includes a reference clock signal generation circuit 250 and a counting circuit 260.

[0026] In terms of the coupling relationship, the crystal oscillator circuit 210 is coupled to the functional circuit 220 and the counting circuit 260. The phase-locked loop circuit 230 is coupled to the functional circuit 240, the reference clock signal generation circuit 250, and the counting circuit 260. The reference clock signal generation circuit 250 is coupled to the counting circuit 260.

[0027] The implementation and operation of the crystal oscillator circuit 210 and the functional circuit 220 are respectively similar to those of Figure 1 the crystal oscillator circuit 110 and the functional circuit 120 therein. The crystal oscillator circuit 210 can further transmit the clock signal CLK1 to the counting circuit 260. Generally, the clock signal CLK1 is stable.

[0028] The reference clock signal generation circuit 250 can generate a reference clock signal CLK_REF and transmit the reference clock signal CLK_REF to the counting circuit 260 and the phase-locked loop circuit 230. In some embodiments, the reference clock signal generation circuit 250 includes components such as resistors, capacitors, or inductors. These components can form an oscillation circuit. And this oscillation circuit can generate the reference clock signal CLK_REF. However, due to process factors or other factors, the reference clock signal CLK_REF is generally unstable.

[0029] The counting circuit 260 can receive the stable clock signal CLK1 and the unstable reference clock signal CLK_REF, and generate a count value CNT based on the clock signal CLK1 and the reference clock signal CLK_REF. Then, the counting circuit 260 can transmit the count value CNT to the phase-locked loop circuit 230. The detailed content of how the counting circuit 260 generates the count value CNT will be described in the following paragraphs in conjunction with Figure 3 and Figure 4 is described.

[0030] The phase-locked loop circuit 230 can receive the reference clock signal CLK_REF and the count value CNT, and generate a clock signal CLK2 based on the reference clock signal CLK_REF and the count value CNT. Then, the phase-locked loop circuit 230 can transmit the clock signal CLK2 to the functional circuit 240.

[0031] The implementation and operation of the phase-locked loop circuit 230 and the functional circuit 240 are respectively similar to those of Figure 1 the phase-locked loop circuit 130 and the functional circuit 140 therein. In such an architecture, the functional circuit 220 and the functional circuit 240 can operate respectively based on different clock signals CLK1 and CLK2.

[0032] The detailed content of how the counting circuit 260 generates the count value CNT will be described in the following paragraphs in conjunction with Figure 3 and Figure 4 is described.

[0033] Refer to Figure 3 . Figure 3 is a waveform diagram of the clock signal CLK1 and the reference clock signal CLK_REF shown according to some embodiments of the present disclosure.

[0034] As described above, the clock signal CLK1 is generally stable while the reference clock signal CLK_REF is generally unstable. That is to say, the clock signal CLK1 has a stable period T. For example, the frequency of the clock signal CLK1 can be 32.768 kilohertz and the period T can be 1 / 3276.8 milliseconds (ms), while the frequency of the reference clock signal CLK_REF can be 3.2768 megahertz. However, the present disclosure is not limited to these frequencies and periods. In other words, the clock of the unstable reference clock signal CLK_REF is higher than the frequency of the stable frequency signal CLK1. And Figure 2 the counting circuit 260 in

[0035] Reference Figure 4 . Figure 4 is a flowchart of a method 400 for generating a count value CNT illustrated according to some embodiments of the present disclosure.

[0036] It should be specifically noted here that the generating method 400 takes Figure 2 the counting circuit 260 in

[0037] counting the number of rising edges RE of the reference clock signal CLK_REF within the period T to generate a count value CNT as an example. The counting circuit 260 counting the number of falling edges FE of the reference clock signal CLK_REF within the period T, the number of occurrences of the high logic level L1 (e.g., logic level 1), or the number of occurrences of the low logic level L0 (e.g., logic level 0) to generate a count value CNT has a similar principle, so it will not be elaborated here. Figure 4 For

[0038] example, the generating method 400 includes operation S402, operation S404, operation S406, operation S408, operation S410, operation S412, operation S414, operation S416, operation S418, operation S420, and operation S422.

[0039] In operation S402, the counting circuit 260 checks the state of the reference clock signal CLK_REF. At this time, the count value CNT can be set to an initial value (e.g., 0). Then, it proceeds to operation S404.

[0040] For Figure 3For example, at time point TP1, the state of the reference clock signal CLK_REF is the rising edge RE. Therefore, the determination in operation S404 is "Yes" and the process proceeds to operation S406. If the determination in operation S404 is "No", the process returns to operation S402 to enable the counting circuit 260 to continue checking the state of the reference clock signal CLK_REF.

[0041] In operation S406, the counting circuit 260 checks the state of the clock signal CLK1. Then, the process proceeds to operation S408.

[0042] In operation S408, the counting circuit 260 determines whether the state of the clock signal CLK1 changes from the low logic level L0 to the high logic level L1.

[0043] For Figure 3 example, at time point TP1, the state of the clock signal CLK1 changes from the low logic level L0 to the high logic level L1. Therefore, the determination in operation S408 is "Yes" and the process proceeds to operation S410. The determination in operation S408 being "Yes" at time point TP1 indicates that time point TP1 is the starting point of the period T of the clock signal CLK1. If the determination in operation S408 is "No", the process returns to operation S402 to enable the counting circuit 260 to continue checking the state of the reference clock signal CLK_REF.

[0044] In operation S410, the counting circuit 260 starts counting and the count value CNT is incremented by 1. Then, the process proceeds to operation S412.

[0045] In operation S412, the counting circuit 260 checks the state of the reference clock signal CLK_REF. Then, the process proceeds to operation S414.

[0046] In operation S414, the counting circuit 260 determines whether the state of the reference clock signal CLK_REF is the rising edge RE.

[0047] For Figure 3 example, at time point TP2, the state of the reference clock signal CLK_REF is the rising edge RE. Therefore, the determination in operation S414 is "Yes" and the process proceeds to operation S416. If the determination in operation S414 is "No", the process returns to operation S412 to enable the counting circuit 260 to continue checking the state of the reference clock signal CLK_REF.

[0048] In operation S416, the counting circuit 260 checks the state of the clock signal CLK1. Then, the process proceeds to operation S418.

[0049] In operation S418, the counting circuit 260 determines whether the state of the clock signal CLK1 changes from the low logic level L0 to the high logic level L1.

[0050] For Figure 3 example, at time point TP2, the state of the clock signal CLK1 does not change from the low logic level L0 to the high logic level L1. Therefore, the determination in operation S418 is "No" and the process proceeds to operation S420.

[0051] In operation S420, the counting circuit 260 increments the count value CNT by 1. That is, the count value CNT at this time is incremented to 2, and the count value CNT at this time represents that the reference clock signal CLK_REF has two rising edges RE from time point TP1 to time point TP2. Then, the process returns to operation S412 to enable the counting circuit 260 to continue monitoring the state of the reference clock signal CLK_REF.

[0052] When the generation method 400 enters operation S418 again at time point TP3, the counting circuit 260 also determines whether the state of the clock signal CLK1 changes from the low logic level L0 to the high logic level L1.

[0053] For Figure 3 example, at time point TP3, the state of the clock signal CLK1 changes from the low logic level L0 to the high logic level L1. Therefore, the determination in operation S418 is "Yes" and the process proceeds to operation S422. The determination of "Yes" in operation S418 at time point TP3 represents that time point TP3 is the termination point of the period T of the clock signal CLK1. The count value CNT at this time represents the number of rising edges RE of the reference clock signal CLK_REF from time point TP1 to time point TP3 (i.e., within the period T of the clock signal CLK1). Then, the process proceeds to operation S422.

[0054] In operation S422, the counting circuit 260 stops counting and outputs the count value CNT. On the other hand, the counting circuit 260 sets the count value CNT to the initial value (e.g., 0) to start counting again.

[0055] Refer again to Figure 2When the count value CNT is different from the threshold value, the phase-locked loop circuit 230 is controlled to adjust the frequency of the clock signal CLK2. Taking the frequency of the clock signal CLK1 as 32.768 kHz and the frequency of the reference clock signal CLK_REF being 3.2768 MHz as an example, the threshold value can be set to 100. Specifically, when the count value CNT is greater than the threshold value, it means that the frequency of the reference clock signal CLK_REF input to the phase-locked loop circuit 230 is on the high side. Accordingly, the phase-locked loop circuit 230 will be controlled to lower the frequency of the clock signal CLK2. Conversely, when the count value CNT is less than the threshold value, it means that the frequency of the reference clock signal CLK_REF input to the phase-locked loop circuit 230 is on the low side. Accordingly, the phase-locked loop circuit 230 will be controlled to increase the frequency of the clock signal CLK2. Details on how the phase-locked loop circuit 230 is controlled will be described in the following paragraphs in conjunction with Figure 7 are described.

[0056] As described above, due to process factors or other factors, the reference clock signal CLK_REF is generally unstable. However, when the reference clock signal CLK_REF is unstable, the clock signal CLK2 generated by the phase-locked loop circuit 230 based on the unstable reference clock signal CLK_REF will also be unstable. However, through the above operations (using the stable clock signal CLK1 to generate the count value CNT to adjust the frequency of the clock signal CLK2), the frequency of the clock signal CLK2 can be made (almost) equal to the target frequency to generate a stable clock signal CLK2. Accordingly, not only can the functional circuit 220 operate based on the stable clock signal CLK1, but the functional circuit 240 can also operate based on the stable clock signal CLK2.

[0057] In some embodiments, assume that the target frequency of the clock signal CLK2 is 900 MHz while the reference clock signal CLK_REF is 900.1 MHz or 899.9 MHz. Through the above operations, the fractional part (components or circuits) in the phase-locked loop circuit 230 can be adjusted so that the frequency of the clock signal CLK2 can be closer to its target frequency.

[0058] Reference Figure 5 。 Figure 5 is a schematic diagram of an integrated circuit 500 with multiple clocks according to some embodiments of the present disclosure.

[0059] For Figure 5 example, the integrated circuit 500 includes a crystal oscillator circuit 510, a functional circuit 520, a phase-locked loop circuit 530, a functional circuit 540, a reference clock signal generation circuit 550, a counting circuit 560, and a sensitivity factor adjustment circuit 570.

[0060] Similar to Figure 2In the integrated circuit 200, the reference clock signal generation circuit 550 can generate a reference clock signal CLK_REF and transmit the reference clock signal CLK_REF to the counting circuit 560. The counting circuit 560 can receive the clock signal CLK1 and the reference clock signal CLK_REF, and generate a count value CNT based on the clock signal CLK1 and the reference clock signal CLK_REF.

[0061] The main difference between the integrated circuit 500 and Figure 2 the integrated circuit 200 in

[0062] is that the counting circuit 560 transmits the generated count value CNT to the sensitivity factor adjustment circuit 570. The sensitivity factor adjustment circuit 570 can receive the count value CNT, and control the reference clock signal generation circuit 550 according to the count value CNT to adjust the reference clock signal CLK_REF. Figure 8 When the count value CNT is different from the threshold value, the sensitivity factor adjustment circuit 570 controls the reference clock signal generation circuit 550 to adjust the frequency of the originally unstable reference clock signal CLK_REF, thereby generating a stable reference clock signal CLK_REF. Then, the reference clock signal generation circuit 550 can transmit the stable reference clock signal CLK_REF to the phase-locked loop circuit 530. Specifically, when the count value CNT is greater than the threshold value, it means that the frequency of the reference clock signal CLK_REF is too high. Accordingly, the sensitivity factor adjustment circuit 570 controls the reference clock signal generation circuit 550 to lower the frequency of the reference clock signal CLK_REF. On the contrary, when the count value CNT is less than the threshold value, it means that the frequency of the reference clock signal CLK_REF is too low. Accordingly, the sensitivity factor adjustment circuit 570 controls the reference clock signal generation circuit 550 to increase the frequency of the reference clock signal CLK_REF. Then, the phase-locked loop circuit 530 can receive the adjusted (stable) reference clock signal CLK_REF, generate a stable clock signal CLK2 based on the adjusted (stable) reference clock signal CLK_REF, and transmit the stable clock signal CLK2 to the functional circuit 540. Accordingly, not only can the functional circuit 520 operate according to the stable clock signal CLK1, but the functional circuit 540 can also operate according to the stable clock signal CLK2. Details of how the sensitivity factor adjustment circuit 570 controls the reference clock signal generation circuit 550 will be described later in conjunction with

[0063] Reference Figure 6 。 Figure 6 is a schematic diagram of an integrated circuit 600 with multiple clocks according to some embodiments of the present disclosure.

[0064] Similar to Figure 5In the integrated circuit 500, the sensitivity factor adjustment circuit 570 in the integrated circuit 600 can control the reference clock signal generation circuit 550 according to the count value CNT to adjust the frequency of the reference clock signal CLK_REF. Additionally, similar to Figure 2 in the integrated circuit 200, the phase-locked loop circuit 630 in the integrated circuit 600 can be controlled according to the count value CNT to adjust the frequency of the clock signal CLK2.

[0065] Compared with Figure 5 the integrated circuit 500 in Figure 2 or the integrated circuit 200 in

[0066] Reference Figure 7 . Figure 7 is a schematic diagram of a phase-locked loop circuit 700 illustrated according to some embodiments of the present disclosure. In some embodiments, the phase-locked loop circuit 700 can be used to implement Figure 2 the phase-locked loop circuit 230 in Figure 6 or the phase-locked loop circuit 630 in

[0067] Taking Figure 7 as an example, the phase-locked loop circuit 700 includes a phase-frequency detector 710, a charge pump 720, a low-pass filter 730, a voltage-controlled oscillator 740, a divider 750, and a controller 760.

[0068] The phase-frequency detector 710 can receive the reference clock signal CLK_REF and is coupled to the charge pump 720. The charge pump 720 is coupled to the low-pass filter 730. The low-pass filter 730 is coupled to the voltage-controlled oscillator 740. The voltage-controlled oscillator 740 can output the clock signal CLK2 and is coupled to the divider 750. The divider 750 is coupled to the phase-frequency detector 710 and the controller 760. The controller 760 is coupled to the divider 750.

[0069] As described above, Figure 2 the phase-locked loop circuit 230 in Figure 6 or the phase-locked loop circuit 630 in Figure 7 can be controlled according to the count value CNT. Taking

[0070] Reference Figure 8 . Figure 8 is a schematic diagram of a reference clock signal generation circuit 800 illustrated according to some embodiments of the present disclosure. In some embodiments, the reference clock signal generation circuit 800 can be used to implement Figure 5 or Figure 6The reference clock signal generation circuit 550 therein. It should be understood that the reference clock signal generation circuit 800 is only one way to implement the reference clock signal generation circuit 550. The present disclosure is not limited to implementing the reference clock signal generation circuit 550 with the reference clock signal generation circuit 800.

[0071] For Figure 8 example, the reference clock signal generation circuit 800 includes a charging switch M1, a discharging switch M2, an adjustment circuit 810, an adjustment circuit 820, a reference voltage generation circuit 830, a comparator 840, an inverter 850, and a buffer 860.

[0072] In some embodiments, the adjustment circuit 810 may include a variable resistor R1 and the adjustment circuit 820 may include a variable capacitor C1, but the present disclosure is not limited thereto.

[0073] When operating, the charging switch M1 is first turned on, so that the power supply voltage VDD can charge the positive input terminal of the comparator 840 through the charging switch M1 and the adjustment circuit 810 to increase the charging voltage VP. When the charging voltage VP is higher than the reference voltage generated by the reference voltage generation circuit 830 (at the negative input terminal of the comparator 840), the comparator 840 outputs a control signal CS with a high logic level. The inverter 850 can generate an inverted control signal CS' with a low logic level according to the control signal CS with a high logic level. The inverted control signal CS' with a low (high) logic level can turn off (turn on) the charging switch M1, and the control signal CS with a high (low) logic level can turn on (turn off) the discharging switch M2. Accordingly, the charging voltage VP is discharged to the ground terminal GND through the discharging switch M2 to reduce the charging voltage VP. When the charging voltage VP is lower than the reference voltage generated by the reference voltage generation circuit 830 (at the negative input terminal of the comparator 840), the comparator 840 outputs a control signal CS with a low logic level. Through the above repeated operations, the buffer 860 can generate a reference clock signal CLK_REF according to the control signal CS.

[0074] As described above, Figure 5 or Figure 6 the sensitivity factor adjustment circuit 570 therein can control the equivalent resistance value of the adjustment circuit 810 in the reference clock signal generation circuit 800 according to the count value CNT to adjust the charging current or control the equivalent capacitance value of the adjustment circuit 820 in the reference clock signal generation circuit 800 to adjust the number of parallel capacitors, thereby adjusting the frequency of the reference clock signal CLK_REF.

[0075] Reference Figure 9 . Figure 9 is a flowchart of an operation method 900 illustrated according to some embodiments of the present disclosure. For Figure 9For example, the operation method 900 includes operation S910, operation S920, operation S930, and operation S940.

[0076] In some embodiments, the operation method 900 is applied to Figure 1 the integrated circuit 100 in Figure 1 but the present disclosure is not limited thereto. However, for ease of understanding, the operation method 900 will be described below in conjunction with

[0077] the integrated circuit 100 in

[0078] In operation S910, a clock signal CLK1 is generated via the crystal oscillator circuit 110. In operation S920, the clock signal CLK1 is received via the functional circuit 120 and operates according to the clock signal CLK1. In operation S930, a clock signal CLK2 is generated via the phase-locked loop circuit 130 according to the clock signal CLK1. In operation S940, the clock signal CLK2 is received via the functional circuit 140 and operates according to the clock signal CLK2.

[0079] The details of the above-mentioned operations have been described in the previous embodiments, so they will not be repeated here.

[0080] In summary, the present disclosure has the advantages of low cost and small occupied space.

[0081]

Symbol Description

[0082] 100, 200, 500, 600: Integrated circuit

[0083] 110, 210, 510: Crystal oscillator circuit

[0084] 120, 220, 520: Functional circuit

[0085] 130, 230, 530, 630, 700: Phase-locked loop circuit

[0086] 140, 240, 540: Functional circuit

[0087] 250, 550, 800: Reference clock signal generation circuit

[0088] 260, 560: Counting circuit

[0089] 400: Generation method

[0090] 570: Sensitivity factor adjustment circuit

[0091] 710: Phase Frequency Detector

[0092] 720: Charge Pump

[0093] 730: Low Pass Filter

[0094] 740: Voltage Controlled Oscillator

[0095] 750: Divider

[0096] 760: Controller

[0097] 810, 820: Adjustment Circuit

[0098] 830: Reference Voltage Generation Circuit

[0099] 840: Comparator

[0100] 850: Inverter

[0101] 860: Buffer

[0102] 900: Operating Method

[0103] CLK1, CLK2: Clock Signal

[0104] CLK_REF: Reference Clock Signal

[0105] CNT: Count Value

[0106] T: Period

[0107] RE: Rising Edge

[0108] FE: Falling Edge

[0109] L1: High Logic Level

[0110] L0: Low Logic Level

[0111] TP1, TP2, TP3: Time Point

[0112] M1: Charge Switch

[0113] M2: Discharge Switch

[0114] R1: Variable Resistor

[0115] C1: Variable Capacitor

[0116] VDD: Power Supply Voltage

[0117] VP: Charge Voltage

[0118] CS: Control Signal

[0119] CS’: Inverted Control Signal

[0120] GND: Ground terminal

[0121] S402, S404, S406, S408, S410, S412, S414, S416, S418, S420, S422, S910, S920, S930, S940: Operations

Claims

1. An integrated circuit with multiple clocks, comprising: a crystal oscillator circuit for generating a first clock signal; a first functional circuit for receiving the first clock signal and operating according to the first clock signal; a phase-locked loop circuit for generating a second clock signal according to the first clock signal; and a second functional circuit for receiving the second clock signal and operating according to the second clock signal.

2. The integrated circuit with multiple clocks according to claim 1, further comprising: a reference clock signal generation circuit for generating a reference clock signal; and a counting circuit for generating a count value according to the first clock signal and the reference clock signal, wherein the phase-locked loop circuit is used to generate the second clock signal according to the reference clock signal and the count value.

3. The integrated circuit with multiple clocks according to claim 2, wherein the first clock signal has a period, and the counting circuit is used to count the number of rising edges, the number of falling edges, the first occurrence number of a first logic level, or the second occurrence number of a second logic level of the reference clock signal within the period to generate the count value.

4. The integrated circuit with multiple clocks according to claim 3, wherein when the count value is different from a threshold value, the phase-locked loop circuit is controlled to adjust the frequency of the second clock signal, wherein when the count value is greater than the threshold value, the phase-locked loop circuit is controlled to reduce the frequency of the second clock signal, and wherein when the count value is less than the threshold value, the phase-locked loop circuit is controlled to increase the frequency of the second clock signal.

5. The integrated circuit with multiple clocks according to claim 3, further comprising: a sensitivity factor adjustment circuit for controlling the reference clock signal generation circuit according to the count value to adjust the reference clock signal.

6. The integrated circuit with multiple clocks according to claim 5, wherein when the count value is different from the threshold value, the sensitivity factor adjustment circuit controls the reference clock signal generation circuit to adjust the frequency of the reference clock signal, wherein when the count value is greater than the threshold value, the sensitivity factor adjustment circuit controls the reference clock signal generation circuit to reduce the frequency of the reference clock signal, and wherein when the count value is less than the threshold value, the sensitivity factor adjustment circuit controls the reference clock signal generation circuit to increase the frequency of the reference clock signal.

7. The integrated circuit with multiple clocks according to claim 1, further comprising: a reference clock signal generation circuit for generating a reference clock signal; a counting circuit for generating a count value according to the first clock signal and the reference clock signal; and a sensitivity factor adjustment circuit for controlling the reference clock signal generation circuit according to the count value to adjust the reference clock signal to generate an adjusted reference clock signal, wherein the phase-locked loop circuit is used to generate the second clock signal according to the adjusted reference clock signal.

8. The integrated circuit with multiple clocks according to claim 7, wherein the first clock signal has a period, and the counting circuit is configured to count the number of rising edges, the number of falling edges, the first occurrence number of a first logic level, or the second occurrence number of a second logic level of the reference clock signal within the period to generate the count value.

9. The integrated circuit with multiple clocks according to claim 8, wherein when the count value is different from the threshold value, the sensitivity factor adjustment circuit adjusts the reference clock signal generation circuit to adjust the frequency of the reference clock signal, wherein when the count value is greater than the threshold value, the sensitivity factor adjustment circuit controls the reference clock signal generation circuit to decrease the frequency of the reference clock signal, and wherein when the count value is less than the threshold value, the sensitivity factor adjustment circuit controls the reference clock signal generation circuit to increase the frequency of the reference clock signal.

10. An operating method for an integrated circuit with multiple clocks, comprising: generating a first clock signal via a crystal oscillator circuit; receiving the first clock signal via a first functional circuit and operating according to the first clock signal; generating a second clock signal via a phase-locked loop circuit based on the first clock signal; and receiving the second clock signal via a second functional circuit and operating according to the second clock signal.

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