Pulse width modulation control circuit with double loops

Abstract

A pulse width modulation control circuit with double loops is used for controlling a power conversion circuit and comprises a main loop control circuit, a main loop control circuit and a main loop control circuit, and a light load loop control circuit. The light load loop control circuit comprises a current synthesis circuit used for generating a synthesis current signal according to target values of the input voltage and the output voltage and an inductance value of an inductor of a power level circuit of the power conversion circuit, and the light load loop control circuit generates a pulse width modulation signal in a light load mode according to the synthesis current signal. The duty ratio of the power level circuit is controlled; in the light load mode, the major loop control circuit enters a power saving state to reduce power consumption of the pulse width modulation control circuit, the power saving state including reducing power consumption of the current sensing circuit or stopping operation of the current sensing circuit.

Description

Technical Field

[0001] The present invention relates to a pulse width modulation control circuit, and particularly to a pulse width modulation control circuit that can achieve dual-loop and low power consumption by synthesizing a current signal. Background Art

[0002] Figure 1 FIG. is a circuit schematic diagram showing a known pulse width modulation control circuit. In this known pulse width modulation control circuit, the signal to be sensed is converted to the digital domain via an analog-to-digital converter (ADC), and pulse width modulation control is performed by all-digital operations. Since a digital on-time generator with high time resolution is used, that is, the starting on-time point is determined by the digital loop, and the on-time length is also determined by the digital counter, both implemented digitally. Therefore, in multi-phase and high-precision applications, a clock signal CK0 with extremely high frequency is required. Especially for determining the high-resolution on-time, this results in the pulse width modulation control circuit consuming a considerable amount of power. In addition, when this prior art is expanded to multi-phase applications, multiple analog-to-digital converters corresponding to multiple phases are also required to separately convert the sensed currents of each phase, which also increases the power consumption and cost.

[0003] In view of this, the present invention proposes a pulse width modulation control circuit with dual-loop, combining the advantages of the hybrid type of digital domain and analog domain, capable of reducing the clock frequency, and using synthesized current to achieve low power consumption. Summary of the Invention

[0004] In one aspect, the present invention provides a pulse width modulation control circuit for controlling a power conversion circuit. The power conversion circuit includes N power stage circuits, where N is an integer greater than or equal to 1. The pulse width modulation control circuit includes: a main loop control circuit; and a light load loop control circuit. The main loop control circuit includes N current sensing circuits for sensing the N-phase currents of the corresponding N power stage circuits to generate corresponding N current sensing signals. The main loop control circuit generates corresponding N pulse width modulation signals in the main loop mode according to the corresponding N current sensing signals to respectively control the duty cycles of the N power stage circuits. The light load loop control circuit includes a current synthesis circuit for generating a synthesized current signal according to an input voltage, a target value of an output voltage, and the inductance value of at least one inductor of the N power stage circuits. The light load loop control circuit generates at least one corresponding pulse width modulation signal among the N pulse width modulation signals in the light load mode according to the synthesized current signal to control the duty cycle of the corresponding power stage circuit. In the light load mode, the main loop control circuit enters a power-saving state to reduce the power consumption of the pulse width modulation control circuit, and the power-saving state includes: reducing the power consumption of the current sensing circuit or stopping the operation of the current sensing circuit.

[0005] In a preferred embodiment, the power consumption of the current synthesis circuit is less than that of the current sensing circuit.

[0006] In a preferred embodiment, in the light load mode, the synthesized current signal is used to control the output voltage of the power conversion circuit, so that the output voltage changes with a load current according to a predetermined load line.

[0007] In a preferred embodiment, in a transition mode from the light load mode to the main circuit mode, the main circuit control circuit exits the power saving state and uses the synthesized current signal to replace the current sensing signal to generate the pulse width modulation signal.

[0008] In a preferred embodiment, in the main circuit mode, the current sensing signal is used to control the output voltage of the power conversion circuit, so that the output voltage changes with a load current according to a predetermined load line.

[0009] In a preferred embodiment, the main circuit mode is switched to the light load mode according to any of the following situations: when an output current determined by the sum of all corresponding current sensing signals decreases to be lower than a predetermined threshold; or when the switching cycle time of the pulse width modulation signal exceeds the predetermined time and continuously exceeds a predetermined number of times, where the pulse width modulation control circuit controls the power conversion circuit in a constant on-time control manner; where the predetermined number of times is greater than or equal to 1.

[0010] In a preferred embodiment, in the light load mode, the pulse width modulation control circuit switches from the light load mode to the main circuit mode according to any of the following situations: the pulse width modulation control circuit receives an instruction; or when an output current of the power conversion circuit exceeds a predetermined level; when a target value of the output voltage changes; or when a change rate of the output voltage exceeds a predetermined level.

[0011] In a preferred embodiment, the pulse width modulation control circuit further includes: a first analog-to-digital converter for converting an output voltage-related signal related to the output voltage into a digital output voltage-related signal in the digital domain; a second analog-to-digital converter for converting a total current-related signal into a digital total current-related signal in the digital domain, where the total current-related signal is the sum of the N current sensing signals; and N conduction time generation circuits for timing corresponding N fixed conduction times in the analog domain according to the triggering of corresponding N trigger signals, and generating corresponding N pulse width modulation signals, thereby reducing the frequency of at least one clock signal in the pulse width modulation control circuit; wherein the main circuit control circuit operates in the digital domain based on a first clock signal in the main circuit mode, and the main circuit control circuit generates the N trigger signals according to the digital output voltage-related signal and the digital total current-related signal; wherein the at least one clock signal includes the first clock signal.

[0012] In a preferred embodiment, the frequency of the first clock signal is reduced by timing the fixed conduction time in the analog domain.

[0013] In a preferred embodiment, the output voltage-related signal is the difference between the output voltage and the target value of the output voltage.

[0014] In a preferred embodiment, the end time of the pulse width modulation signal is not synchronized by the first clock signal.

[0015] In a preferred embodiment, the N current sensing circuits are used to sense corresponding N phase currents in the analog domain and generate corresponding N current sensing signals, thereby reducing the frequency of the at least one clock signal.

[0016] In a preferred embodiment, N is an integer greater than or equal to 2, and the main circuit control circuit further includes: a current balance circuit that operates in the analog domain, where the current balance circuit is used to generate corresponding N current balance signals according to the difference between the average value of the total current-related signal and the N current sensing signals, and the N current balance signals are used to adjust corresponding N fixed conduction times to achieve current balance between corresponding N phase currents, thereby reducing the frequency of the at least one clock signal; wherein the N current balance signals are used to adjust corresponding N fixed conduction times respectively to achieve current balance between corresponding N phase currents, thereby reducing the frequency of the at least one clock signal, and the power saving state further includes: reducing the power consumption of the current balance circuit or stopping the operation of the current balance circuit.

[0017] In a preferred embodiment, the light load circuit control circuit further includes a light load trigger circuit; wherein the synthesized current signal includes a first synthesized current signal; in the light load mode, the current synthesizing circuit generates the first synthesized current signal in the digital domain based on a second clock signal and further according to at least one of the N fixed conduction times, and the light load trigger circuit generates a corresponding trigger signal in the digital domain based on the second clock signal according to the digital output voltage related signal and the first synthesized current signal; wherein the at least one clock signal includes the second clock signal.

[0018] In a preferred embodiment, the frequency of the second clock signal is lower than that of the first clock signal, whereby in the power saving state, the power consumption of the pulse width modulation control circuit is reduced.

[0019] In a preferred embodiment, the synthesized current signal further includes a second synthesized current signal; in the transition mode, the current synthesizing circuit generates the second synthesized current signal in the digital domain based on the first clock signal, and in the transition mode, the main circuit control circuit generates the N trigger signals based on the first clock signal according to the digital output voltage related signal and the second synthesized current signal to replace the digital sum current related signal.

[0020] In a preferred embodiment, the second synthesized current signal is updated based on the period of the first clock signal to mimic the corresponding N phase currents in real time or to mimic the sum of the N current sensing signals in real time.

[0021] In a preferred embodiment, N is an integer greater than or equal to 2, the second synthesized current signal includes corresponding N sub-synthesized current signals, wherein the main circuit control circuit includes a second current balancing circuit, the second current balancing circuit operates in the digital domain, and is used to generate corresponding N current balancing signals in the digital domain according to the difference between the average value of the sum of the second synthesized current signals and the N sub-synthesized current signals in the transition mode, wherein the N current balancing signals are used to adjust the corresponding N fixed conduction times to achieve current balance between the corresponding N phase currents.

[0022] In a preferred embodiment, the first synthesized current signal is updated based on the period of the second clock signal to mimic the average value of the corresponding phase current.

[0023] In a preferred embodiment, the power saving state further includes: reducing the power consumption of a main trigger circuit of the main circuit control circuit or stopping the operation of the main trigger circuit.

[0024] In a preferred embodiment, the transition mode is exited and the main circuit mode is entered according to any of the following situations: after delaying a preset transition delay time; or when it is determined that the N current sensing circuits and the current balancing circuit have entered a ready and operable state.

[0025] In another aspect, the present invention provides a pulse width modulation control circuit for controlling a power conversion circuit. The power conversion circuit includes N power stage circuits, where N is an integer greater than or equal to 1. The pulse width modulation control circuit includes: a loop control circuit; a first analog-to-digital converter for converting an output voltage-related signal related to an output voltage into a digital output voltage-related signal in the digital domain; a second analog-to-digital converter for converting a summed current-related signal into a digital summed current-related signal in the digital domain, where the summed current-related signal is the sum of the N current sensing signals; and N on-time generation circuits for timing corresponding N fixed on-times in the analog domain according to the triggering of corresponding N trigger signals, and generating corresponding N pulse width modulation signals, thereby reducing the frequency of at least one clock signal in the pulse width modulation control circuit; where the loop control circuit includes N current sensing circuits and a digital trigger circuit. The N current sensing circuits are used to sense N phase currents of corresponding N power stage circuits to generate corresponding N current sensing signals. The loop control circuit generates corresponding N pulse width modulation signals according to the corresponding N current sensing signals to respectively control the duty cycles of the N power stage circuits; the digital trigger circuit generates the N trigger signals in the digital domain based on a first clock signal according to the digital output voltage-related signal and the digital summed current-related signal; where the at least one clock signal includes the first clock signal.

[0026] The dual-loop hybrid pulse width modulation control circuit of the present invention combines the advantages of the digital domain and the analog domain, and achieves the effect of low power consumption by reducing the clock frequency and using synthetic current.

[0027] The following is a detailed description through specific embodiments, and it will be easier to understand the purpose, technical content, features and achieved effects of the present invention. Description of the Drawings

[0028] Figure 1 is a circuit schematic diagram showing a known pulse width modulation control circuit.

[0029] Figure 2 is a circuit block diagram showing a pulse width modulation control circuit according to an embodiment of the present invention.

[0030] Figure 3 is a circuit schematic diagram showing a power stage circuit of a power conversion circuit applied by a pulse width modulation control circuit according to an embodiment of the present invention.

[0031] Figure 4 is a circuit block diagram showing a pulse width modulation control circuit according to an embodiment of the present invention.

[0032] Figure 5 is a graph showing the relationship between the output voltage and the load current of a pulse width modulation control circuit according to an embodiment of the present invention.

[0033] Figure 6 is a circuit block diagram showing the main circuit control circuit and the light load circuit control circuit of a pulse width modulation control circuit according to another embodiment of the present invention.

[0034] Figure 7 is a circuit block diagram showing the main circuit control circuit and the light load circuit control circuit of a pulse width modulation control circuit according to still another embodiment of the present invention.

[0035] Figure 8 is a circuit block diagram showing the main circuit control circuit of a pulse width modulation control circuit according to yet another embodiment of the present invention.

[0036] Figure 9 is a circuit schematic diagram showing the current balance circuit of the main circuit control circuit of a pulse width modulation control circuit according to an embodiment of the present invention.

[0037] Figure 10 is a circuit schematic diagram showing the conduction time generation circuit of a pulse width modulation control circuit according to an embodiment of the present invention.

[0038] Figures 11 to 13 is a signal waveform schematic diagram showing the relevant signals of a pulse width modulation control circuit and a power conversion circuit according to an embodiment of the present invention.

[0039] Figure 14 is a step flow chart showing a pulse width modulation control method according to an embodiment of the present invention.

[0040] Figure 15 is a step flow chart showing a pulse width modulation control method according to another embodiment of the present invention.

[0041] Figure 16 is a step flow chart showing a pulse width modulation control method according to still another embodiment of the present invention.

[0042] Description of symbols in the figure

[0043] 20: Pulse width modulation control circuit

[0044] 201: Main circuit control circuit

[0045] 2011: Main trigger circuit

[0046] 2012: Current balance circuit

[0047] 2012b: Second current balance circuit

[0048] 20121: Summing circuit

[0049] 20122: Division circuit

[0050] 20123: Error circuit

[0051] 2013[1] to 2013[N]: Current sensing circuit

[0052] 2014: Error amplification compensation circuit

[0053] 2015: Addition circuit

[0054] 202: Light load loop control circuit

[0055] 2021: Light load trigger circuit

[0056] 2022: Current synthesis circuit

[0057] 203[1] to 203[N]: Conduction time generation circuit

[0058] 2031: Comparison circuit

[0059] 204a: First analog-to-digital converter

[0060] 204b: Second analog-to-digital converter

[0061] 204c: Third analog-to-digital converter

[0062] 205: Mode control circuit

[0063] 30: Power conversion circuit

[0064] 301[1] to 301[N]: Power stage circuit

[0065] 3011: Driver circuit

[0066] 40: Pulse width modulation control method

[0067] 401, 402, 404, 405: Steps

[0068] 410: Main circuit mode

[0069] 420: Light load mode

[0070] 430: Transition mode

[0071] C: Capacitor

[0072] CK0, CK1, CK2: Clock signals

[0073] DEL: Inhibition level

[0074] HEL: Upper bridge enable level

[0075] Ich: Charging current

[0076] IL1~ILN: Phase current

[0077] ILsum: Total phase current

[0078] Iout: Load current

[0079] Isum: Total current related signal

[0080] Isum_digi: Digital total current related signal

[0081] Isum_syn: Total synthesized current signal

[0082] Isynth: Synthesized current signal

[0083] Isynth1_digi: First synthesized current signal

[0084] Isynth2_digi, Isynth2_digi1~Isynth2_digiN: Second synthesized current signal

[0085] L: Inductor

[0086] LEL: Lower bridge enable level

[0087] LX: Switching node

[0088] R: Resistor

[0089] QA: Upper bridge switch

[0090] QB: Lower bridge switch

[0091] Sadj1~SadjN: Current balance signal

[0092] Savg: Average value

[0093] Scs1~ScsN: Current sensing signal

[0094] Smc: Mode control signal

[0095] Spw1~SpwN: Pulse width modulation signal

[0096] SpwH: Upper bridge control signal

[0097] SpwL: Lower bridge control signal

[0098] Strl, Strm, Strm1 to StrmN: Trigger signals

[0099] t0, t0’, t1, t2, t3: Time points

[0100] Vcomp_digi: Digital comparison result

[0101] Verr: Output voltage related signal

[0102] Verr_digi: Digital output voltage related signal

[0103] Vin: Input voltage

[0104] Vin_digi: Input voltage in the digital domain

[0105] Vout: Output voltage

[0106] Vout_LL_digi: Digital light load output related signal

[0107] Vramp: Ramp signal

[0108] Vref: Target value of the output voltage

[0109] Vref_LL_digi: Digital light load reference related signal

[0110] ZCD_synth: Synthesized zero current signal Detailed implementation manners

[0111] The drawings in the present invention are all schematic, mainly intended to show the coupling relationships between circuits and the relationships between various signal waveforms. As for circuits, signal waveforms and frequencies, they are not drawn to scale.

[0112] Figure 2 is a circuit block diagram showing a pulse width modulation control circuit according to an embodiment of the present invention. As Figure 2As shown, the pulse width modulation control circuit 20 of the present invention is used to control the power conversion circuit 30. The pulse width modulation control circuit 20 includes a main loop control circuit 201, a light load loop control circuit 202, N on-time generation circuits 203[1]-203[N] corresponding to N phases, and a mode control circuit 205; the power conversion circuit 30 includes N power stage circuits 301[1]-301[N], where N is an integer greater than or equal to 1; in a preferred embodiment, N is an integer greater than or equal to 2, that is, multiple. In an embodiment, the on-time generation circuits 203[1]-203[N] respectively correspond to the power stage circuits 301[1]-301[N]. The mode control circuit 205 is used to generate a mode control signal Smc to indicate entering the main loop mode or the light load mode. The main loop control circuit 201 and the light load loop control circuit 202 are respectively used to generate trigger signals Strm1~StrmN and a trigger signal Strl according to the mode control signal Smc.

[0113] In an embodiment, the pulse width modulation control circuit 20 controls the power conversion circuit 30 in a constant on-time (COT) control manner. The on-time generation circuits 203[1]-203[N] operate in the analog domain, where the on-time generation circuits 203[1]-203[N] are respectively used to time N fixed on-times in the analog domain according to the triggering of the corresponding trigger signals Strm1~StrmN or Strl, and generate corresponding pulse width modulation signals Spw1~SpwN to control the duty cycles of the power stage circuits 301[1]-301[N].

[0114] It is worth noting that since the on-time generation circuits 203[1]-203[N] operate in the analog domain, therefore, compared with the digital time generation circuit implemented in the digital domain in the prior art, the frequency of the clock signal in the pulse width modulation control circuit 20 of the present invention can be greatly reduced, thereby reducing power consumption and improving conversion efficiency.

[0115] In one embodiment, the mode control circuit 205 is configured to determine whether the pulse width modulation control circuit 20 controls the power conversion circuit 30 in the main circuit mode or the light load mode according to, for example, the load current Iout. When the load current Iout is medium or heavy, the pulse width modulation control circuit 20 operates in the main circuit mode. When the load current Iout is light, the pulse width modulation control circuit 20 operates in the light load mode. The main circuit control circuit 201 is configured to generate corresponding pulse width modulation signals Spw1 to SpwN according to the phase currents IL1 to ILN in the main circuit mode. In the light load mode, the main circuit control circuit 201 enters a power saving state to reduce the power consumption of the pulse width modulation control circuit 20. At the same time, the light load circuit control circuit 202 generates the pulse width modulation signals Spw1 to SpwN in the light load mode in a more power-saving manner than the main circuit control circuit 201 to perform circuit control. The configuration and operation details of the power saving state and the circuit control circuit will be described in detail later. In one embodiment, in the light load mode, the power conversion circuit may operate with only a single phase. In this case, the light load circuit control circuit 202 may, for example, generate only the pulse width modulation signal Spw1 to control the power stage circuit 301[1].

[0116] Figure 3 FIG. is a circuit schematic diagram of a power stage circuit of a power conversion circuit to which a pulse width modulation control circuit is applied according to an embodiment of the present invention. This embodiment shows Figure 2 a exemplary embodiment of the power stage circuits 301[1]-301[N]. As Figure 3 shown, each of the power stage circuits 301[1]-301[N] includes a driving circuit 3011, an upper bridge switch QA, a lower bridge switch QB, and an inductor L. The upper bridge switch QA is coupled between the input voltage Vin and the switching node LX, and the lower bridge switch QB is coupled between the switching node LX and the ground potential. The inductor L is coupled between the switching node LX and the output voltage Vout. The driving circuit 3011 is configured to generate corresponding upper bridge control signal SpwH and lower bridge control signal SpwL according to the corresponding pulse width modulation signals (Spw1 to SpwN) to control the upper bridge switch QA and the lower bridge switch QB respectively.

[0117] Figure 4 FIG. is a circuit block diagram of a pulse width modulation control circuit according to an embodiment of the present invention. This embodiment corresponds to Figure 2 a specific embodiment. As Figure 4As shown, the main circuit control circuit 201 includes a main trigger circuit 2011, a current balance circuit 2012, current sensing circuits 2013[1] to 2013[N], and an addition circuit 2015. It should be noted that in this embodiment, N is a plurality, so the following current balance operation needs to be performed. The current sensing circuits 2013[1] to 2013[N] operate in the analog domain and are respectively used to sense the phase currents IL1 to ILN (i.e., the inductor currents of each phase) of the corresponding power stage circuits 301[1] to 301[N] in the analog domain to generate corresponding current sensing signals Scs1 to ScsN. The addition circuit 2015 is used to sum the current sensing signals Scs1 to ScsN to generate a summed current related signal Isum. The current balance circuit 2012 operates in the analog domain and is used to generate corresponding current balance signals Sadj1 to SadjN respectively according to the difference between the average value of the summed current related signal Isum and the corresponding current sensing signals Scs1 to ScsN. The plurality of current balance signals Sadj1 to SadjN are respectively used to adjust the fixed conduction time generated by the corresponding conduction circuit generation circuits 203[1] - 203[N] to achieve current balance between the phase currents IL1 to ILN.

[0118] The main circuit control circuit 201 generates corresponding pulse width modulation signals Spw1 to SpwN in the main circuit mode according to the current sensing signals Scs1 to ScsN. Specifically, the main trigger circuit 2011 generates corresponding trigger signals Strm1 to StrmN in the main circuit mode according to the summed current related signal Isum, the target value Vref of the output voltage, and the output voltage Vout, and then generates corresponding pulse width modulation signals Spw1 to SpwN through the conduction time generation circuits 203[1] - 203[N] to respectively control the duty cycles of the power stage circuits 301[1] - 301[N]. As described above, in the main circuit mode of the present invention, current sensing and current balance are performed in the analog domain through the analog current sensing circuit, addition circuit, current balance circuit, and conduction circuit generation circuit, thereby reducing the frequency of the at least one clock signal described above, and further reducing power consumption.

[0119] Please continue to refer to Figure 4 , the light load circuit control circuit 202 includes a current synthesis circuit 2022 and a light load trigger circuit 2021. The current synthesis circuit 2022 is used to generate a synthesized current signal Isynth according to the input voltage Vin, the target value Vref of the output voltage, and the inductance values of the inductors of the power stage circuits 301[1] to 301[N]. The light load circuit control circuit 202 generates pulse width modulation signals Spw1 to SpwN in the light load mode according to the synthesized current signal Isynth.

[0120] It should be noted that in the present invention, the synthesized current Isynth includes a first synthesized current signal Isynth1_digi for mimicking the average current and a second synthesized current signal Isynth2_digi1 for mimicking the real-time current. The following paragraphs will detail the specific generation methods, functions, and operation modes of these synthesized currents.

[0121] Specifically, in one embodiment, in the light load mode, the light load trigger circuit 2021 generates a trigger signal Strl based on the synthesized current signal Isynth, the digital light load reference related signal Vref_LL_digi, and the digital light load output related signal Vout_LL_digi. Then, a pulse width modulation signal Spw1 is generated by the on-time generation circuit 203[1] and its on-time is determined to control the duty cycle of the power stage circuit 301[1]. The aforementioned digital light load reference related signal Vref_LL_digi is related to the target value Vref of the output voltage, and the digital light load output related signal Vout_LL_digi is related to the output voltage Vout.

[0122] In one embodiment, in the light load mode, the aforementioned power-saving state may include at least one of the following: reducing the power consumption of the current sensing circuits 2013[1] to 2013[N], reducing the power consumption of the current balancing circuit 2012, or reducing the power consumption of the main trigger circuit 2011. Specifically, the methods for reducing power consumption can be achieved by, for example but not limited to, stopping the operation of the current sensing circuits 2013[1] to 2013[N], stopping the operation of the current balancing circuit 2012, or stopping the operation of the main trigger circuit 2011. In one embodiment, the power consumption of the operation of the current synthesis circuit 2022 is less than the power consumption of the operation of the current sensing circuits 2013[1] to 2013[N]. Therefore, in the light load mode of the present invention, the current synthesis circuit 2022 can replace the above-mentioned partial circuits in the main circuit to achieve the effect of power saving. It is also worth noting that the aforementioned stopping operation can further include, for example, stopping the supply of the bias current to these circuits to further save power. Before returning to the main circuit mode, the bias current of these circuits is re-supplied to start to the ready state.

[0123] It should be noted that at least part of the main circuit control circuit 201 operates in the digital domain based on the first clock signal CK1 in the main circuit mode, and at least part of the light load circuit control circuit 202 operates in the digital domain based on the second clock signal CK2 in the light load mode. In one embodiment, the frequency of the second clock signal CK2 is lower than that of the first clock signal CK1. Therefore, the light load circuit control circuit 202 operating in the light load mode can further save power. On the other hand, since the present invention adopts an analog-digital hybrid architecture, especially an on-time generation circuit operating in the analog domain, the frequencies of the first clock signal CK1 and the second clock signal CK2 of the pulse width modulation control circuit of the present invention are much lower (e.g., 1 / 20) than the frequency of the clock signal CK0 required in the prior art. Therefore, the present invention has the advantage of power consumption saving compared with the prior art.

[0124] Figure 5 FIG. is a graph showing the relationship between the output voltage of the pulse width modulation control circuit and the load current according to an embodiment of the present invention. Please also refer to Figure 5 and Figure 4 , in one embodiment, in the light load mode, the synthesized current signal Isynth is used to control the output voltage Vout of the power conversion circuit 30, so that the output voltage Vout changes with the load current Iout according to the predetermined load line Zo, that is, there is a non-zero predetermined load line Zo between the output voltage Vout and the load current Iout. Please also refer to Figure 5 and Figure 4 , in another embodiment, in the main circuit mode, the current sensing signals Scs1 to ScsN are used to control the output voltage Vout of the power conversion circuit 30, so that the output voltage Vout changes with the load current Iout according to the predetermined load line Zo.

[0125] Figure 6 FIG. is a circuit block diagram showing the main circuit control circuit and the light load circuit control circuit of the pulse width modulation control circuit according to another embodiment of the present invention. In this embodiment, the main circuit control circuit 201 and the light load circuit control circuit 202 are implemented partially in digital form. As Figure 6As shown, the first analog-to-digital converter 204a is used to convert an output voltage-related signal Verr related to the output voltage Vout into a digital output voltage-related signal Verr_digi in the digital domain. The output voltage-related signal Verr is the difference between the output voltage Vout and the target value Vref of the output voltage. The second analog-to-digital converter 204b is used to convert the summed current-related signal Isum into a digital summed current-related signal Isum_digi in the digital domain. The third analog-to-digital converter 204c is used to convert the input voltage Vin into a digital input voltage Vin_digi in the digital domain. The summed current-related signal Isum is the sum of the current sensing signals Scs1 to ScsN.

[0126] In one embodiment, the pulse width modulation control circuit 20 of the present invention further includes a transition mode, which is used to enable the light load mode to seamlessly transition to the main circuit mode. Specifically, in the light load mode, when, for example, the load changes to a heavy load or the output voltage target changes, the pulse width modulation control circuit 20 needs to switch to the main circuit mode operation. At this time, since in the main circuit control circuit 201, the aforementioned analog circuit that stops operating in the light load mode needs time to restart, therefore, before officially entering the main circuit mode, the main circuit control circuit 201 needs to be allowed a sufficient long time to restart to the ready state. In view of this, in one embodiment of the present invention, before switching to the main circuit mode, it will first enter the transition mode. In the transition mode, the main circuit control circuit 201 exits the power-saving state to start the aforementioned stopped operating analog circuit, and in the transition mode, the second synthesized current signal Isynth2_digi is used to replace the digital summed current-related signal Isum_digi to perform loop control, generate trigger signals Strm1 to StrmN, and then generate pulse width modulation signals Spw1 to SpwN through the on-time generation circuits 203[1]-203[N]. Thus, the multi-phase control loop can be started earlier, and through the synthesized current information, loop control such as current mode can be performed, or the output voltage can be adjusted to conform to the aforementioned predetermined load line.

[0127] Specifically, in the transition mode, the current synthesis circuit 2022 generates a second synthesized current signal Isynth2_digi in the digital domain based on the first clock signal CK1. And in the transition mode, the error amplification compensation circuit 2014 of the main loop control circuit 201 generates a digital comparison result Vcomp_digi based on the first clock signal CK1 according to the digital output voltage related signal Verr_digi. The main trigger circuit 2011 generates trigger signals Strm1 to StrmN according to the digital comparison result Vcomp_digi and the second synthesized current signal Isynth2_digi that replaces the digital sum current related signal Isum_digi, and then generates pulse width modulation signals Spw1 to SpwN through the conduction time generation circuits 203[1] - 203[N].

[0128] Figure 7 FIG. is a circuit block diagram showing the main loop control circuit and the light load loop control circuit of the pulse width modulation control circuit according to another embodiment of the present invention. The current sensing circuits 2013[1] to 2013[N], the current balancing circuit 2012, the addition circuit 2015, the error amplification compensation circuit 2014, the main trigger circuit 2011, the first analog-to-digital converter 204a, and the second analog-to-digital converter 204b of this embodiment are similar to Figure 4 the current sensing circuits 2013[1] to 2013[N], the current balancing circuit 2012, the addition circuit 2015, Figure 6 the error amplification compensation circuit 2014, the main trigger circuit 2011, the first analog-to-digital converter 204a, and the second analog-to-digital converter 204b of Figure 4 and Figure 6 the embodiment of, so the description thereof is omitted. In this embodiment, according to

[0129] This embodiment partially implements the main loop control circuit 201 and the light load loop control circuit 202 digitally. In the main loop mode, the main loop control circuit 201 operates in the digital domain based on the first clock signal CK1. The main loop control circuit 201 generates trigger signals Strm1 to StrmN according to the digital output voltage related signal Verr_digi and the digital sum current related signal Isum_digi.

[0130] In the light load mode, the current synthesis circuit 2022 generates a first synthesized current signal Isynth1_digi in the digital domain based on the second clock signal CK2, and also according to the fixed conduction time, the input voltage Vin, the target value Vref of the output voltage, the inductance value of the inductor, and the switching period information. And the light load trigger circuit 2021 generates a trigger signal Strl in the digital domain based on the second clock signal CK2 according to the digital output voltage related signal Verr_digi and the first synthesized current signal Isynth1_digi. In one embodiment, the frequency of the second clock signal CK2 is lower than the frequency of the first clock signal CK1, whereby the power consumption of the pulse width modulation control circuit 20 is reduced in the power saving state. In one embodiment, since the pulse widths of the pulse width modulation signals Spw1 to SpwN are determined by the conduction time generation circuit in the analog domain, the end times of the pulse width modulation signals Spw1 to SpwN are not synchronized by the first clock signal CK1.

[0131] It should be noted that the current synthesis circuit 2022 generates a second synthesized current signal Isynth2_digi in the digital domain according to the foregoing parameters by means of digital estimation to simulate the real-time total current related signal Isum, and generates a first synthesized current signal Isynth1_digi in the digital domain to simulate the average value of the total current related signal Isum.

[0132] Figure 8 It is a circuit block diagram showing the main circuit control circuit of the pulse width modulation control circuit according to still another embodiment of the present invention. The error amplification compensation circuit 2014 and the main trigger circuit 2011 of this embodiment are similar to Figure 7 the error amplification compensation circuit 2014 and the main trigger circuit 2011, so their descriptions are omitted. The difference between this embodiment and Figure 7 the embodiment of is that in this embodiment, in the transition mode, the current balance circuit is implemented digitally, whereby the main circuit control circuit 201 performs switching trigger control of the circuit in a fully digital manner. As Figure 8 shown, the main circuit control circuit 201 includes a second current balance circuit 2012b. The second current balance circuit 2012b operates in the digital domain and is used to generate corresponding current balance signals Sadj1 to SadjN in the digital domain according to the sum of all the second synthesized current signals (that is, the difference between the average value of the total synthesized current signal Isum_syn and the second synthesized current signals Isynth2_digi1 to Isynth2_digiN) in the transition mode. The current balance signals Sadj1 to SadjN are respectively used to adjust the fixed conduction time of the corresponding phase to achieve current balance between the phase currents IL1 to ILN.

[0133] Figure 9It is a circuit schematic diagram of the current balance circuit of the main circuit control circuit of the pulse width modulation control circuit according to an embodiment of the present invention. This embodiment is, for example, an exemplary embodiment of the aforementioned current balance circuit 2012. This embodiment only shows the current balance circuit 2012 of one phase, and the rest of the phases are the same by analogy. As Figure 9 shown, the current balance circuit 2012 includes a summing circuit 20121, a division circuit 20122, and an error circuit 20123, all operating in the analog domain. The current sensing signals Scs1~ScsN in the analog domain are summed by the summing circuit 20121, and then averaged by the division circuit 20122 to generate an average value Savg of the summed current related signal. The error circuit 20123 is used to generate a current balance signal Sadj1 based on the difference between the average value Savg of the summed current related signal and the current sensing signal Scs1, and further adjust the pulse width of the pulse width modulation signal Spw1 generated by the conduction time generation circuit 203[1].

[0134] Figure 10 It is a circuit schematic diagram of the conduction time generation circuit of the pulse width modulation control circuit according to an embodiment of the present invention. This embodiment is an exemplary embodiment showing the conduction time generation circuits 203[1]~203[N]. This embodiment only shows the conduction time generation circuit 203[1] of one phase, and the rest of the phases are the same by analogy. As Figure 10 shown, the conduction time generation circuit 203[1] includes a comparison circuit 2031. The charging current Ich charges the capacitor C to generate a ramp signal Vramp. The comparison circuit 2031 is used to compare the target value Vref of the output voltage with the ramp signal Vramp having a fixed period to determine the pulse width of the pulse width modulation signal Spw1. In one embodiment, the charging current Ich is related to the resistor R and / or the input voltage Vin. In one embodiment, at least one of the resistance value of the resistor R, the capacitance value of the capacitor C, the target value Vref of the output voltage, or the input voltage Vin sensing signal k*Vin can be adjusted according to the aforementioned current balance signal Sadj1, thereby adjusting the pulse width of the pulse width modulation signal Spw1.

[0135] Figure 11 It is a signal waveform schematic diagram showing the related signals of the pulse width modulation control circuit and the power conversion circuit operating in a steady state according to an embodiment of the present invention. In this embodiment, the number of phases N of the power conversion circuit is 8, Figure 11 which shows the target value Vref of the output voltage, the output voltage Vout, the phase currents IL1~IL8, the trigger signals Strm1~Strm8, and the pulse width modulation signals Spw1~Spw8. As Figure 11As shown, the pulses of the trigger signals Strm1 to Strm8 are used to trigger the switching of the pulse width modulation signals Spw1 to Spw8 to the enabled level, and the upper-bridge switches of the corresponding phases are turned on alternately in a staggered phase, and the conduction times are respectively determined by the conduction time generation circuits of the corresponding phases.

[0136] Figure 12 It is a schematic diagram of signal waveforms showing relevant signals of a pulse width modulation control circuit and a power conversion circuit according to an embodiment of the present invention. The target value Vref of the output voltage, the output voltage Vout, the pulse width modulation signals Spw1 to Spw8, the phase currents IL1 to IL8, the first synthesized current signal Isynth1_digi, the total current related signal Isum, the total phase current ILsum, the trigger signals Strm1 to Strm8, and the second synthesized current signal Isynth2_digi are shown in Figure 12 wherein the total phase current ILsum = the sum of the phase currents IL1 to ILN.

[0137] As Figure 12 shown, before time point t1, the power conversion circuit of this embodiment operates in a light load mode, wherein the first synthesized current signal Isynth1_digi is updated based on the period of the second clock signal CK2 to simulate the average value of the corresponding phase current IL1 for performing the power conversion in the light load mode as described above. In addition, in this embodiment, in the light load mode, only the first phase pulse width modulation signal Spw1 is triggered by the trigger signal Strl generated by the light load loop control circuit 202 according to the first synthesized current signal Isynth1_digi and operates in a discontinuous conduction mode. On the other hand, in this embodiment, in the light load mode, the main loop control circuit is in a power-saving state, so the total current related signal Isum and the trigger signals Strm1 to Strm8 are not generated, and the pulse width modulation signals Spw2 to Spw8 are all at the disabled level, that is, for example, a high impedance state or an intermediate potential, to control that the upper and lower bridge switches of the corresponding phases are all turned off, so the phase currents IL2 to IL8 are also all 0. In other words, only the phase current IL1 supplies power to the load.

[0138] Next, as Figure 12As shown, it enters the transition mode at time point t1. In the transition mode from time point t1 to t2, the second synthesized current signal Isynth2_digi is used to mimic the total phase current ILsum in real time. Specifically, in the transition mode, the second synthesized current signal Isynth2_digi is updated based on the period of the first clock signal CK1 to mimic the total phase current ILsum and / or phase currents IL1 to IL8 in real time. Thus, the main circuit control circuit generates trigger signals Strm1 to Strm8 and pulse width modulation signals Spw1 to Spw8 according to the second synthesized current signal Isynth2_digi in the transition mode to perform circuit control and current balance, achieving power supply conversion.

[0139] Next, in this embodiment, it enters the main circuit mode at time point t2. Since all the circuits of the main circuit are restarted to the ready state before time point t2, in the main circuit mode after time point t2, the total current related signal Isum can already reflect the total phase current ILsum in real time, and the main circuit control circuit 201 generates corresponding trigger signals Strm1 to Strm8 and pulse width modulation signals Spw1 to Spw8 according to the aforementioned main circuit to perform circuit control and achieve power supply conversion.

[0140] In one embodiment, in the transition mode, the first synthesized current signal Isynth1_digi can stop being generated, and in the light load mode and the main circuit mode, the second synthesized current signal Isynth2_digi can stop being generated, thereby further reducing power consumption.

[0141] Figure 13 It is a schematic diagram of signal waveforms showing relevant signals of the pulse width modulation control circuit and the power supply conversion circuit according to an embodiment of the present invention. The target value Vref of the output voltage, the output voltage Vout, the total phase current ILsum, the digital light load output related signal Vout_LL_digi, the digital light load reference related signal Vref_LL_digi, the first synthesized current signal Isynth1_digi, the trigger signal Strl, the synthesized zero current signal ZCD_synth, and the pulse width modulation signals Spw1 to Spw8 are shown in Figure 13 it.

[0142] Specifically, Figure 13 shows the operation waveforms of relevant signals when entering the light load mode from the main circuit mode. Please refer to Figure 13 , Figure 3 and Figure 4, before time point t0', the power conversion circuit of this embodiment operates in the main circuit mode. Among them, before time point t0, multi-phase power conversion is performed by the main circuit control circuit 201. Then, starting at time point t0, due to the extremely light load, only the power stage circuit of one phase performs switching conversion (corresponding to the pulse width modulation signal Spw1). Then, between time point t0 and time point t0', it is determined whether the output current (i.e., the total current-related signal Isum) determined by the sum of all corresponding current sensing signals Scs1~ScsN decreases below a predetermined threshold, or whether the switching cycle time Tsw of the pulse width modulation signals Spw1~SpwN exceeds a predetermined time and continuously exceeds a predetermined number of times, that is, it is determined whether the load decreases to a corresponding threshold through the switching cycle. Among them, at time point t0', it is determined that the current is lower than the predetermined threshold and continuously exceeds the predetermined number of times, so it enters the light load mode, and the light load circuit control circuit 202 takes over the circuit control, and the digital light load output-related signal Vout_LL_digi, the digital light load reference-related signal Vref_LL_digi, and the first synthesized current Isynth1_digi start to be generated successively.

[0143] For example, at time point t1, when the digital light load output-related signal Vout_LL_digi in the digital domain reaches the digital light load reference-related signal Vref_LL_digi, the trigger signal Strl issues a trigger pulse to trigger the pulse width modulation signal Spw1 to switch to the upper bridge enable level HEL to turn on the upper bridge switch QA of the power stage circuit 301[1]. The conduction time is determined by the conduction time generation circuit 203[1] for example. Please refer to Figure 3 and Figure 13 , at time point t2, when the conduction time ends, the pulse width modulation signal Spw1 switches to the lower bridge enable level LEL to turn on the lower bridge switch QB of the power stage circuit 301[1], and the phase current IL1 (which is the same as the total phase current ILsum at this time) correspondingly switches from rising to falling. At time point t3, the synthesized zero current signal ZCD_synth generated by the light load circuit control circuit 202 is used to simulate and estimate that the phase current IL1 reaches 0, and then the pulse width modulation signal Spw1 is switched to the disable level DEL to turn off the upper bridge switch QA and the lower bridge switch QB of the power stage circuit 301[1]. The upper bridge switch QA and the lower bridge switch QB of the power stage circuits 301[2]~301[8] have been switched to the disable level DEL when entering single-phase switching earlier.

[0144] Figure 14 is a step flowchart showing the pulse width modulation control method according to an embodiment of the present invention. As Figure 14As shown, after the power supply is started, the pulse width modulation control method 40 of the present invention first enters the operation of the main circuit mode 410, for example, and performs the power supply conversion of the main circuit mode with the aforementioned main circuit control circuit. At the same time, in the main circuit mode 410, it enters step 401 to determine whether the output current (i.e., the total current-related signal Isum) determined by the sum of all corresponding current sensing signals Scs1 to ScsN decreases to below a predetermined threshold, or whether the switching cycle time Tsw of the pulse width modulation signals Spw1 to SpwN exceeds a predetermined time and continuously exceeds a predetermined number of times, that is, to determine whether the load has decreased to a corresponding threshold through the switching cycle. If any of the above judgments is yes, that is, the load has indeed decreased to the corresponding threshold, the pulse width modulation control circuit 20 switches from the main circuit mode 410 to the light load mode 420. If not, the pulse width modulation control circuit 20 continues to perform the power supply conversion in the main circuit mode. Wherein the predetermined number of times is greater than or equal to 1.

[0145] Specifically, in the light load mode 420, the power supply conversion of the light load mode is performed with the aforementioned light load circuit control circuit. At the same time, in the light load mode 420, it enters step 402 to determine whether the pulse width modulation control circuit 20 needs to leave the light load mode 420 and enter the main circuit mode 410. In one embodiment, step 402 includes determining whether an instruction is received, or whether the output current (i.e., the total current-related signal Isum) of the power supply conversion circuit 30 exceeds a predetermined level, or whether the change rate of the output voltage Vout exceeds a predetermined level, or whether the target value Vref of the output voltage changes. If any of the above judgments is yes, the pulse width modulation control circuit 20 switches from the light load mode 420 to the main circuit mode 410. If not, the pulse width modulation control circuit 20 continues to perform the power supply conversion in the light load mode.

[0146] Figure 15 is a flowchart showing the steps of the pulse width modulation control method according to another embodiment of the present invention. This embodiment is similar to Figure 14 the embodiment, except that the pulse width modulation control method 40 of this embodiment further includes that if the result of step 402 is yes, it enters the transition mode 430. Wherein in the transition mode 430, the aforementioned transition mode operation is performed to perform the power supply conversion. Then, in step 404, a preset transition delay time is delayed to wait for the part of the analog circuit in the main circuit whose current has been reduced or operation has been stopped to start to the ready state, and then enter the main circuit mode 410.

[0147] Figure 16 is a flowchart showing the steps of the pulse width modulation control method according to still another embodiment of the present invention. This embodiment is similar to Figure 15An embodiment, which is different in that the pulse width modulation control method 40 of this embodiment replaces step 404 with step 405. Specifically, step 405 is used to determine whether the current sensing circuit and the current balancing circuit have entered a ready-to-operate state. If so, enter the main circuit mode 410. If not, return to the transition mode 430.

[0148] In summary, the present invention proposes a dual-loop hybrid pulse width modulation control circuit that combines the advantages of the digital domain and the analog domain, achieving a low-power effect by reducing the clock frequency and using synthesized current.

[0149] The above has described the present invention with reference to the preferred embodiments. However, the above description is only for making those skilled in the art easily understand the content of the present invention and is not used to limit the scope of the rights of the present invention. Each of the described embodiments is not limited to being applied alone and can also be combined. For example, two or more embodiments can be combined, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "processing or operating on a certain signal or generating a certain output result" in the present invention is not limited to the signal itself, but also includes, when necessary, converting the signal between voltage and current, current and voltage, and / or proportional conversion, and then processing or operating on the converted signal to generate a certain output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A pulse width modulation control circuit for controlling a power conversion circuit, the power conversion circuit comprising N power stage circuits, wherein N is an integer greater than or equal to 1, the pulse width modulation control circuit comprising: a main loop control circuit; and A light load loop control circuit; The main loop control circuit includes N current sensing circuits, the N current sensing circuits are used to sense N phase currents of the corresponding N power stage circuits to generate corresponding N current sensing signals, and the main loop control circuit generates corresponding N pulse width modulation signals in the main loop mode according to the corresponding N current sensing signals to control the duty cycle of the N power stage circuits respectively; The light-load loop control circuit includes a current synthesis circuit for generating a synthesis current signal according to an input voltage, a target value of an output voltage, and an inductance value of an inductor in at least one of the N power stage circuits. The light-load loop control circuit generates at least one pulse width modulation signal corresponding to the N pulse width modulation signals in a light-load mode according to the synthesis current signal to control the duty cycle of the corresponding power stage circuit. In the light load mode, the main loop control circuit enters a power saving state to reduce the power consumption of the pulse width modulation control circuit, wherein the power saving state includes: reducing the power consumption of the N current sensing circuits or stopping the operation of the N current sensing circuits.

2. The pulse width modulation control circuit according to claim 1, wherein: The power consumption of the current synthesis circuit is smaller than the power consumption of the current sensing circuit.

3. The pulse width modulation control circuit according to claim 1, wherein: In the light load mode, the synthetic current signal is used to control the output voltage of the power conversion circuit so that the output voltage varies with a load current according to a predetermined load line.

4. The pulse width modulation control circuit according to claim 1, wherein: In a transition mode from the light-load mode to the main-loop mode, the main-loop control circuit exits the power-saving state and replaces the corresponding current sensing signal with the synthetic current signal to generate the corresponding pulse-width modulation signal.

5. The pulse width modulation control circuit according to claim 1, wherein: In the main loop mode, the N current sensing signals are used to control the output voltage of the power conversion circuit so that the output voltage varies with a load current according to a predetermined load line.

6. The pulse width modulation control circuit according to claim 1, wherein: The main circuit mode switches to the light load mode according to any of the following situations: When an output current determined by the sum of all corresponding N current sensing signals decreases below a predetermined threshold; or When the switching cycle time of the N PWM signals exceeds the predetermined time and continuously exceeds a predetermined number of times, the PWM control circuit controls the power conversion circuit in a constant on-time control mode; wherein the predetermined number of times is greater than or equal to 1.

7. The pulse width modulation control circuit according to claim 1, wherein: In the light load mode, the pulse width modulation control circuit switches from the light load mode to the main loop mode according to any of the following situations: The pulse width modulation control circuit receives a command; or When an output current of the power conversion circuit exceeds a predetermined level; When the target value of the output voltage changes; or When the rate of change of the output voltage exceeds a predetermined level.

8. The pulse width modulation control circuit according to claim 4, wherein: Also includes: a first analog-to-digital converter, configured to convert an output voltage-related signal related to the output voltage into a digital output voltage-related signal in a digital domain; a second analog-to-digital converter, configured to convert a summed current-related signal into a digital summed current-related signal in a digital domain, wherein the summed current-related signal is a sum of the N current sensing signals; and N on-time generating circuits, for timing corresponding N fixed on-times in an analog domain according to the triggering of corresponding N trigger signals, and generating corresponding N pulse width modulation signals, thereby reducing the frequency of at least one clock signal in the pulse width modulation control circuit; wherein the main loop control circuit operates in the digital domain based on a first clock signal in the main loop mode, and generates the N trigger signals according to the digital output voltage related signal and the digital summed current related signal; The at least one clock signal includes the first clock signal.

9. The pulse width modulation control circuit as claimed in claim 8, wherein: The frequency of the first clock signal is reduced by clocking the N fixed on-times in an analog domain.

10. The pulse width modulation control circuit according to claim 8, wherein: The output voltage related signal is a difference between the output voltage and the target value of the output voltage.

11. The pulse width modulation control circuit according to claim 8, wherein: The end times of the N pulse width modulation signals are not synchronized by the first clock signal.

12. The pulse width modulation control circuit according to claim 8, wherein: The N current sensing circuits are used to sense the corresponding N phase currents in an analog domain and generate the corresponding N current sensing signals, thereby reducing the frequency of the at least one clock signal.

13. The pulse width modulation control circuit according to claim 8, wherein: N is an integer greater than or equal to 2, wherein the main loop control circuit further includes: a current balancing circuit operating in an analog domain, wherein the current balancing circuit is used to generate corresponding N current balancing signals according to a difference between an average value of the summed current-related signal and the N current sensing signals, wherein the N current balancing signals are used to adjust the corresponding N fixed on-times respectively to achieve current balancing between the corresponding N phase currents, thereby reducing the frequency of the at least one clock signal; The power saving state further includes: reducing the power consumption of the current balancing circuit or stopping the operation of the current balancing circuit.

14. The pulse width modulation control circuit according to claim 4, wherein: Leave the transition mode and enter the main loop mode according to any of the following situations: After a preset transition delay time; or When it is determined that the N current sensing circuits and the current balancing circuit have entered a ready-to-operate state.

15. The pulse width modulation control circuit according to claim 8, wherein: The light-load loop control circuit further comprises a light-load trigger circuit; wherein the synthesized current signal comprises a first synthesized current signal; in the light-load mode, the current synthesizing circuit generates the first synthesized current signal in the digital domain based on a second clock signal and also according to at least one of the N fixed on-times, and the light-load trigger circuit generates the corresponding trigger signal in the digital domain based on the second clock signal according to the digital output voltage related signal and the first synthesized current signal; The at least one clock signal includes the second clock signal.

16. The pulse width modulation control circuit according to claim 15, wherein: The frequency of the second clock signal is lower than the frequency of the first clock signal, so that the power consumption of the pulse width modulation control circuit is reduced in the power saving state.

17. The pulse width modulation control circuit according to claim 8, wherein: The synthesized current signal also includes a second synthesized current signal; in the transition mode, the current synthesis circuit generates the second synthesized current signal in the digital domain based on the first clock signal, and in the transition mode, the main loop control circuit generates the N trigger signals based on the first clock signal and according to the digital output voltage related signal and the second synthesized current signal replacing the digital summed current related signal.

18. The pulse width modulation control circuit according to claim 17, wherein: The second composite current signal is updated based on the period of the first clock signal to simulate the corresponding N phase currents in real time or simulate the sum of the N current sensing signals in real time.

19. The pulse width modulation control circuit according to claim 17, wherein: N is an integer greater than or equal to 2, the second composite current signal includes corresponding N sub-composite current signals, wherein the main loop control circuit includes a second current balancing circuit, the second current balancing circuit operates in the digital domain, and is used to generate corresponding N current balancing signals in the digital domain in the transition mode according to the difference between the summed average value of the second composite current signal and the N sub-composite current signals, wherein the N current balancing signals are used to adjust the corresponding N fixed conduction times to achieve current balance between the corresponding N phase currents.

20. The pulse width modulation control circuit according to claim 15, wherein: The first composite current signal is updated based on the period of the second clock signal to simulate the average value of the corresponding phase current.

21. The pulse width modulation control circuit according to claim 1, wherein: The power saving state also includes: reducing the power consumption of a main trigger circuit of the main loop control circuit or stopping the operation of the main trigger circuit.

22. A pulse width modulation control circuit for controlling a power conversion circuit, the power conversion circuit comprising N power stage circuits, wherein N is an integer greater than or equal to 1, the pulse width modulation control circuit comprising: A loop control circuit; a first analog-to-digital converter, configured to convert an output voltage-related signal related to an output voltage into a digital output voltage-related signal in a digital domain; a second analog-to-digital converter, configured to convert a summed current-related signal into a digital summed current-related signal in a digital domain, wherein the summed current-related signal is a sum of the N current sensing signals; and N on-time generating circuits, for timing corresponding N fixed on-times in an analog domain according to the triggering of corresponding N trigger signals, and generating corresponding N pulse width modulation signals, thereby reducing the frequency of at least one clock signal in the pulse width modulation control circuit; The loop control circuit includes N current sensing circuits and a digital trigger circuit, wherein the N current sensing circuits are used to sense the N phase currents of the corresponding N power stage circuits to generate the corresponding N current sensing signals, and the loop control circuit generates the corresponding N pulse width modulation signals according to the corresponding N current sensing signals to respectively control the duty cycle of the N power stage circuits; the digital trigger circuit generates the N trigger signals according to the digital output voltage related signal and the digital summed current related signal based on a first clock signal in the digital domain; The at least one clock signal includes the first clock signal.

23. The pulse width modulation control circuit as claimed in claim 22, wherein: The end time of the pulse width modulation signal is not synchronized by the first clock signal.

24. The pulse width modulation control circuit as claimed in claim 22, wherein: The N current sensing circuits are used to sense the corresponding N phase currents in an analog domain and generate the corresponding N current sensing signals, thereby reducing the frequency of the at least one clock signal.

25. The pulse width modulation control circuit as claimed in claim 22, wherein: N is an integer greater than or equal to 2, wherein the loop control circuit further includes: A current balancing circuit operates in an analog domain, wherein the current balancing circuit is used to generate corresponding N current balancing signals according to the difference between the average value of the summed current related signal and the N current sensing signals, wherein the N current balancing signals are used to adjust the corresponding N fixed conduction times to achieve current balance between the corresponding N phase currents, thereby reducing the frequency of the at least one clock signal.

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