Switching circuit, attenuation circuit, receiver, base station and mobile device

Abstract

The invention provides a switching circuit, an attenuation circuit, a receiver, a base station and a mobile device. The switching circuit includes: a first node for coupling to a first conductive path; and a second node for coupling to a second conductive path. Further, the switching circuit includes a first stack and a second stack of transistors arranged between the first node and the second node. The first transistor in the first stack and the first transistor in the second stack are cross-coupled with the second transistor in the second stack and the second transistor in the first stack, respectively. The first transistors in the first stack and the second stack are coupled to a first node. The third transistor in the first stack and the third transistor in the second stack are cross-coupled with the fourth transistor in the second stack and the fourth transistor in the first stack, respectively. The fourth transistors in the first stack and the second stack are coupled to a second node.

Description

Technical Field

[0001] The present disclosure relates to transistor-based switches. In particular, examples of the present disclosure relate to switching circuits, attenuation circuits, receivers, base stations, and mobile devices. Background Art

[0002] In modern high-speed and Multi-Gigabit wireless communication systems and applications (e.g., 5G or 6G), there is an increasing interest and need for integrated circuits that operate at high frequencies and are capable of uniformly controlling signal strength and phase to achieve an automatic gain control function.

[0003] For example, due to high-power blocking or overload conditions in congested areas, the signal swings received by a 5G base station can significantly exceed the supply voltage and ground voltage. Such conditions may occur several times during the product life cycle. The radio frequency (RF) transceiver of the base station must tolerate those transient events with unknown durations (only probabilistic) without damage.

[0004] It is desirable to integrate a gain control circuit (e.g., a digital step attenuator (DSA) with power handling capabilities) with all RF blocks into a single transceiver chip. For a DSA, low power consumption is a goal because the system consists of many transmit / receive chains (including automatic gain control of transmitter and receiver systems) integrated with corresponding antenna elements.

[0005] When the overvoltage and undervoltage tolerances significantly exceed the technical limits of the safe operating region of the device, it becomes very challenging to design an RF transceiver with an embedded DSA in state-of-the-art technologies. Since the transistor gate oxide scaling decreases as the semiconductor technology node advances, the device breakdown voltage of the semiconductor chip and the consequent overvoltage tolerance of the RF I / O pads are becoming increasingly problematic. Devices in modern semiconductor technology nodes are very sensitive to voltage stress (typically <1V), and the impact is that if the device is exposed to excessive overvoltage / undervoltage, there are serious reliability issues. This results in performance degradation over the life cycle, or in the worst case, early field failures and returns.

[0006] Therefore, there may be a need to overcome the above limitations. Brief Description of the Drawings

[0007] Some examples of the apparatus and / or method will be described hereinafter only by way of example and with reference to the drawings, wherein:

[0008] Figure 1 A first example of a switching circuit is shown;

[0009] Figure 2 A second example of a switching circuit is shown;

[0010] Figure 3 Shows a third example of a switching circuit;

[0011] Figure 4 Shows a first exemplary control circuit;

[0012] Figure 5 Shows a second exemplary control circuit;

[0013] Figure 6 Shows a first exemplary receiver having an attenuation circuit;

[0014] Figure 7 Shows a second exemplary receiver having an attenuation circuit;

[0015] Figure 8 Shows a comparison of the linearity for different attenuation circuits;

[0016] Figure 9 Shows an example of a base station; and

[0017] Figure 10 Shows an example of a mobile device. Detailed Description

[0018] Some examples will now be described in more detail with reference to the accompanying drawings. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of the features as well as equivalents and alternatives of the features. In addition, the terms used herein to describe particular examples should not limit other possible examples.

[0019] Throughout the description of the drawings, like or similar reference numerals refer to like or similar elements and / or features, which may be the same or implemented in a modified form while providing the same or similar functions. For clarity, the thickness of lines, layers, and / or regions in the figures may also be exaggerated.

[0020] When using "or" to combine two elements A and B, this should be understood to disclose all possible combinations (i.e., only A, only B, and A and B), unless otherwise explicitly defined in a separate case. As an alternative wording for the same combination, "at least one of A and B" or "A and / or B" may be used. This also applies to combinations of more than two elements.

[0021] If the singular forms (e.g., "a", "an", and "the") are used and the use of only a single element is not explicitly or implicitly defined as mandatory, additional examples may also use several elements to achieve the same function. If a function is described below as being implemented using multiple elements, additional examples may use a single element or a single processing entity to achieve the same function. It should also be understood that the terms "include", "including", "comprise", and / or "comprising", when used, describe the presence of a specified feature, integer, step, operation, process, element, component, and / or group thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components, and / or group thereof.

[0022] Figure 1 An exemplary switch circuit 100 is shown. The switch circuit 100 includes: a first node 110 for coupling to a first conductive path; and a second node 120 for coupling to a second conductive path. For example, the first conductive path and the second conductive path may be signal paths (lines, traces) of a differential circuit (e.g., an attenuator (e.g., DSA)).

[0023] The switch circuit 100 includes a first stack 130 of transistors, which is arranged between the first node 110 and the second node 120. Additionally, the switch circuit 100 includes a second stack 140 of transistors, which is arranged between the first node 110 and the second node 120. That is, the first node 110 is arranged above the first stack 130 and the second stack 140, while the second node 120 is arranged below the first stack 130 and the second stack 140. The first stack 130 includes four transistors 131, 132, 133, and 134, which are vertically stacked on top of each other. The second stack 140 includes four transistors 141, 142, 143, and 144, which are vertically stacked on top of each other. The first stack 130 is arranged to the left of the second stack 140. In other words, the first stack 130 and the second stack 140 are arranged to be offset from each other in the lateral direction.

[0024] In Figure 1In the example, transistors 131, 132, 143, and 144 are p-type transistors (examples of transistors of the first conduction type), while transistors 141, 142, 133, and 134 are n-type transistors (examples of transistors of the second conduction type). However, it should be noted that the present disclosure is not limited thereto. In other examples, transistors 131, 132, 143, and 144 may be n-type transistors, while transistors 141, 142, 133, and 134 may be p-type transistors. Generally, transistors 131, 132, 143, and 144 are of the first conduction type, while transistors 141, 142, 133, and 134 are of the second conduction type different from the first conduction type.

[0025] The drain (terminal) of transistor 131 (which may be referred to as "the first transistor in the first stack" in the present disclosure) is coupled to the first node 110. The source (terminal) of transistor 132 (which may be referred to as "the second transistor in the first stack" in the present disclosure) is coupled to the source (terminal) of transistor 133 (which may be referred to as "the third transistor in the first stack" in the present disclosure). The drain (terminal) of transistor 134 (which may be referred to as "the fourth transistor in the first stack" in the present disclosure) is coupled to the second node 120.

[0026] Similarly, the drain (terminal) of transistor 141 (which may be referred to as "the first transistor in the second stack" in the present disclosure) is coupled to the first node 110. The source (terminal) of transistor 142 (which may be referred to as "the second transistor in the second stack" in the present disclosure) is coupled to the source (terminal) of transistor 143 (which may be referred to as "the third transistor in the second stack" in the present disclosure). The drain (terminal) of transistor 144 (which may be referred to as "the fourth transistor in the second stack" in the present disclosure) is coupled to the second node 120.

[0027] The source (terminal) of transistor 131 is coupled to the drain (terminal) of transistor 142. The source (terminal) of transistor 141 is coupled to the drain (terminal) of transistor 132. Thus, the first conductive trace (path) 101 coupling the source of transistor 131 and the drain of transistor 142 intersects with the second conductive trace (path) 102 coupling the source of transistor 141 and the drain of transistor 132. That is, the first transistor in the first stack 130 is cross-coupled with the second transistor in the second stack 140, and the first transistor in the second stack 140 is cross-coupled with the second transistor in the first stack 130. In other words, the first stack 130 and the second stack 140 are cross-coupled via the coupling between the source of transistor 131 and the drain of transistor 142 and the coupling between the source of transistor 141 and the drain of transistor 132.

[0028] The source (terminal) of transistor 134 is coupled to the drain (terminal) of transistor 143. The source (terminal) of transistor 144 is coupled to the drain (terminal) of transistor 133. Thus, the third conductive trace 103 that couples the source of transistor 134 and the drain of transistor 143 intersects with the fourth conductive trace 104 that couples the source of transistor 144 and the drain of transistor 133. That is, the third transistor in the first stack 130 is cross-coupled with the fourth transistor in the second stack 140, and the third transistor in the second stack 140 is cross-coupled with the fourth transistor in the first stack 130. In other words, the first stack 130 and the second stack 140 are cross-coupled via the coupling between the source of transistor 134 and the drain of transistor 143 and the coupling between the source of transistor 144 and the drain of transistor 133.

[0029] The switch circuit 100 is suitable for high-voltage applications that exceed the maximum tolerable input voltage of individual transistor devices. Modern semiconductor technology nodes (e.g., nodes using all-gate surround field-effect transistors (GAAFETs) with nanosheets (also known as RibbonFET transistors) or complementary field-effect transistors (CFETs) with nanosheets) are accompanied by low breakdown voltages (e.g., below 3V) and low supply voltages (e.g., 1.2V). As Figure 1 shown, the stacked transistors allow for providing transistor-based switches that exceed the voltage limits of individual transistors. In other words, the maximum tolerable voltage is increased by stacking transistors (e.g., thin-oxide transistors) in series to achieve the desired power handling capabilities. V EoS_max is the maximum tolerable (allowed) voltage per transistor and depends on the semiconductor technology node. For example, for a node using RibbonFET transistors, V EoS_max <0.9V, such that the four stacked transistors in each of stacks 130 and 140 allow a voltage limit of 4x V EoS_max = 3.6V, or equivalently, allow +18dBm on a 100Ω balanced front-end input impedance. The above numbers are merely illustrative examples and do not limit the proposed architecture. As Figure 1 shown, the cross-coupled stacks of p-type and n-type transistors allow for maintaining a very high level of symmetry and linearity since the parallel paths are balanced and symmetric.

[0030] The equivalent total on-resistance R ON of the switch circuit 100 is given by the parallel combination of two series on-resistances of the p / n-type transistors forming the first stack 130 and the second stack 140. The configuration is fully symmetric (the two paths between nodes 110 and 120 are identical) to achieve the highest linearity.

[0031] As indicated above, the switching circuit 100 can be implemented with modern semiconductor technology nodes. For example, the transistors of the first stack 130 and the second stack 140 can be GAAFETs with nanosheets (e.g., RibbonFET transistors) or CFETs with nanosheets. For example, RibbonFET process technology offers the advantages of no bulk silicon (and associated wells) and substrate, enabling significant reduction of non-linearity caused by threshold voltage shift due to transistor bulk silicon modulation, reducing area (compact layout), avoiding latch-up risk, and reducing parasitic devices. However, the present disclosure is not limited thereto. Generally, the proposed switching circuit architecture can be used with any semiconductor technology node.

[0032] The corresponding voltage clamps 151, 152, 153, and 154 are coupled between the sources of transistors 131 and 142, the drains of transistors 132 and 142, the drains of transistors 133 and 143, and the sources of transistors 134 and 144. At Figure 1In the example, the corresponding voltage clamps 151, 152, 153, and 154 are formed by a corresponding set of two back-to-back diodes. However, the present disclosure is not limited thereto. In an alternative example, the corresponding voltage clamps 151, 152, 153, and 154 may be formed by corresponding semiconductor switches (e.g., formed by one or more n-type transistors and / or p-type transistors). In yet another example, the corresponding voltage clamps 151, 152, 153, and 154 may be formed by corresponding transmission gates (e.g., having parallel p-type and n-type transistors). The transistors of the corresponding transmission gates may be of the same type as the transistors coupled therebetween by the corresponding transmission gates (e.g., p-type or n-type) to track process and temperature variations. For example, the gates of the transistors of the corresponding transmission gates may be configured to receive the same signal as the gates of the transistors coupled therebetween by the corresponding transmission gates (e.g., the gate of the transistor forming the transmission gate between the sources of transistors 131 and 141 may be configured to receive the same signal as the gates of transistors 131 and 141 to control the conduction state of the transmission gate). In the case of overvoltage or undervoltage, the electrical stress is attenuated by the charge distribution in the switching circuit 100 and is controlled via the voltage clamps 151, 152, 153, and 154. The voltage clamps 151, 152, 153, and 154 equalize the source or drain voltages of the transistors coupled therebetween by the corresponding voltage clamps (e.g., voltage clamp 151 equalizes the source voltages of transistors 131 and 141), especially during the off state of the transistors and (therefore) the switching circuit 100. The voltage clamps 151, 152, 153, and 154 allow the drain-gate-source voltages of the transistors in the first stack 130 and the second stack 140 to be maintained with a safe operating range by acting as fast passive clamps without an additional penalty in terms of current consumption (especially during the off state of the transistors and (therefore) the switching circuit 100). This also holds true when a high-frequency RF signal is applied to the first node 110 and the second node 120.

[0033] The switching circuit 100 further includes a third node 160 configured to receive a DC reference voltage (common-mode voltage) V cm . The third node is resistively coupled between the sources of transistors 132 and 133 and between the sources of transistors 142 and 143. Assuming that the supply voltages of the switching circuit 100 are a first supply voltage V DD and a second supply voltage V SS , where V SS < V DD , then the DC reference voltage may be V cm = 1 / 2V DD。The third node 160 and its coupling to the first stack 130 and the second stack 140 are arranged on the symmetry line 105 of the switching circuit 100. The first stack 130 and the second stack 130 are symmetric with respect to the symmetry line. The DC reference voltage V cm allows for the balanced switching circuit 100.

[0034] The switching circuit 100 includes a control circuit 170 for controlling the respective conduction states of the transistors forming the first stack 130 and the second stack 140. Specifically, the control circuit 170 is configured to supply respective control signals to the respective gates (terminals) of the transistors in the first stack 130 and the second stack 140 to control the on and off states of the transistors. In Figure 1 the example, respective sub - circuits 171,..., 178 for controlling the on and off states of the respective transistors are shown. The sub - circuits 171,..., 178 form the control circuit 170.

[0035] Respective resistors are coupled between the respective gates of the transistors in the first stack 130 and the second stack 140 and the control circuit 170. Specifically, the respective resistors are coupled between the respective gates of the transistors in the first stack 130 and the second stack 140 and the respective sub - circuits 171,..., 178. The resistors allow for increasing the bandwidth of the switching circuit 100 by neutralizing device parasitic capacitances (e.g., gate - source and gate - drain parasitic capacitances). The resistors are optional and can be omitted in alternative examples (e.g., when chip area is limited).

[0036] By controlling the respective conduction states of the transistors forming the first stack 130 and the second stack 140, the first node 110 and the second node 120 can be coupled and decoupled in a controlled manner. For example, to electrically couple the first node 110 and the second node 120, the control circuit 170 can be configured to adjust the respective signal levels of the respective control signals to control the transistors in the first stack 130 and the second stack 140 to be in the on state. For example, the transistors in the first stack 130 and the second stack 140 can be controlled via the respective control signals to be in the strong depletion mode. The signal levels of the control signals for the p - type transistors 131, 132, 143, and 144 can be set, for example, to V SS to turn on these transistors and drive them into the strong depletion mode. Similarly, the signal levels of the control signals for the n - type transistors 141, 142, 133, and 134 can be set, for example, to V DD to turn on these transistors and drive them into the strong depletion mode.

[0037] For example, to electrically decouple the first node 110 and the second node 120, the control circuit 170 may be configured to: adjust the respective signal levels of the respective control signals to control the transistors in the first stack 130 and the second stack 140 to be in an off state. For example, the transistors in the first stack 130 and the second stack 140 may be controlled via the respective control signals to be in a strong enhancement mode or a strong accumulation mode to avoid unwanted self-turn-on of the transistors due to voltage swings (e.g., RF voltage swings) received at the first node 110 and the second node 120. When the transistors in the first stack 130 and the second stack 140 and (therefore) the switching circuit 100 are in an off state, the gate capacitances of the transistors are evenly divided (i.e., C gs = C gd = C g / 2). This allows the voltage difference between the first node 110 and the second node 120 to be evenly divided across the stacked transistors. The signal levels of the control signals for the p-type transistors 131, 132, 143, and 144 may be set, for example, to V DD to turn off these transistors and drive them into a strong enhancement mode (or a strong accumulation mode). Similarly, the signal levels of the control signals for the n-type transistors 141, 142, 133, and 134 may be set, for example, to V SS to turn off these transistors and drive them into a strong enhancement mode (or a strong accumulation mode).

[0038] The bias control of the transistors in the first stack 130 and the second stack 140 may be static (i.e., no current is required). In other words, setting and maintaining the static points of the transistors in the first stack 130 and the second stack 140 may not require current consumption.

[0039] Figure 2 Another switching circuit 200 based on the switching circuit 100 described above is shown. Compared with the switching circuit 100, respective capacitors are additionally coupled between the respective gates and respective sources of the transistors in the first stack 130 and the second stack 140. Similarly, respective capacitors are additionally coupled between the respective gates and respective drains of the transistors in the first stack 130 and the second stack 140. For example, capacitor 181 is coupled between the gate and the drain of transistor 131, and capacitor 182 is coupled between the gate and the source of transistor 131.

[0040] Compared with the switching circuit 100, the additional capacitors improve the balance of the switching circuit 200.

[0041] At Figure 1 and Figure 2In the example, each of the first stack 130 and the second stack 140 includes four transistors. However, it should be noted that the present disclosure is not limited thereto. Each of the first stack 130 and the second stack 140 may optionally include additional transistors. For example, N additional p-type transistors serially coupled to N additional n-type transistors may be serially coupled between transistors 132 and 133 in the first stack 130, and N additional n-type transistors serially coupled to N additional p-type transistors may be serially coupled between transistors 142 and 143 in the second stack 140 (where N is an integer). Additionally or alternatively, M additional p-type transistors may be serially coupled between the first node 110 and transistor 131 in the first stack 130, M additional n-type transistors may be serially coupled between the second node 120 and transistor 134 in the first stack 130, M additional n-type transistors may be serially coupled between the first node 110 and transistor 141 in the second stack 140, and M additional p-type transistors may be serially coupled between the second node 120 and transistor 144 in the second stack 140 (where M is an integer). Further, the switching circuit may include several other pairs of cross-couplings between optional additional transistors in the first stack 130 and the second stack 140 (i.e., 2, 4, 6, 8, etc. additional cross-couplings).

[0042] The switching circuits 100 and 200 described above are mainly designed for use in differential circuits. However, the proposed architecture is not limited to differential implementations. The proposed architecture can equally be used for single-ended implementations. An exemplary switching circuit 300 that can be used in a single-ended circuit is shown in Figure 3 .

[0043] The switching circuit 300 includes a first node 310 that is adapted to be coupled to a conductive path. For example, the conductive path may be a signal path (line, trace) of a single-ended circuit (e.g., an attenuator (e.g., DSA)).

[0044] In addition, the switching circuit 300 includes a second node 320 that is adapted to be coupled to ground or a supply voltage (e.g., V SS ). Additionally, the switching circuit 300 includes a third node 390 that is adapted to be coupled to ground or a supply voltage.

[0045] The switching circuit 300 includes transistors of a first stack 330, arranged between a first node 310 and a second node 320. Additionally, the switching circuit 300 includes transistors of a second stack 340, arranged between the first node 310 and a third node 390. That is, the first node 310 is arranged above the first stack 330 and the second stack 340, while each of the second node 320 and the third node 390 is arranged below the first stack 330 and the second stack 340. The first stack 330 includes two transistors 331 and 332, which are vertically stacked on top of each other. The second stack 340 includes two transistors 341 and 342, which are vertically stacked on top of each other. The first stack 330 is arranged to the left of the second stack 340. In other words, the first stack 330 and the second stack 340 are arranged to be offset from each other in the lateral direction.

[0046] In Figure 3 the example, transistors 331 and 332 are p-type transistors (examples of transistors of a first conduction type), while transistors 341 and 342 are n-type transistors (examples of transistors of a second conduction type). However, it should be noted that the present disclosure is not limited thereto. In other examples, transistors 331 and 332 may be n-type transistors, and transistors 341 and 342 may be p-type transistors. Generally, transistors 331 and 332 are of a first conduction type, while transistors 341 and 342 are of a second conduction type different from the first conduction type.

[0047] The drain (terminal) of transistor 331 (which may be referred to as "the first transistor in the first stack" in the present disclosure) is coupled to the first node 310. The source (terminal) of transistor 332 (which may be referred to as "the second transistor in the first stack" in the present disclosure) is coupled to the second node 320.

[0048] Similarly, the drain (terminal) of transistor 341 (which may be referred to as "the first transistor in the second stack" in the present disclosure) is coupled to the first node 310. The source (terminal) of transistor 342 (which may be referred to as "the second transistor in the second stack" in the present disclosure) is coupled to the third node 390.

[0049] The source (terminal) of transistor 331 is coupled to the drain (terminal) of transistor 342. The source (terminal) of transistor 341 is coupled to the drain (terminal) of transistor 332. Thus, the first conductive trace (path) 301 that couples the source of transistor 331 and the drain of transistor 342 intersects with the second conductive trace (path) 302 that couples the source of transistor 341 and the drain of transistor 332. That is, the first transistor in the first stack 330 is cross-coupled with the second transistor in the second stack 340, and the first transistor in the second stack 340 is cross-coupled with the second transistor in the first stack 330. In other words, the first stack 330 and the second stack 340 are cross-coupled via the coupling between the source of transistor 331 and the drain of transistor 342 and the coupling between the source of transistor 341 and the drain of transistor 332.

[0050] Like switch circuits 100 and 200, switch circuit 300 is also suitable for high-voltage applications that exceed the maximum tolerable input voltage of individual transistor devices. As Figure 3 shown, the stacked transistors can provide transistor-based switches that exceed the voltage limits of individual transistors, which makes switch circuit 300 particularly suitable for modern semiconductor technology nodes with low breakdown voltages and low supply voltages. For example, for the maximum tolerable (permissible) voltage V EoS_max per transistor, two stacked transistors in each of stacks 330 and 340 allow a voltage limit of 2x V EoS_max . As Figure 3 shown, the cross-coupled stacks of p-type and n-type transistors allow maintaining a very high level of symmetry and linearity because the parallel paths are balanced and symmetric.

[0051] As indicated above, switch circuit 100 can be implemented in modern semiconductor technology nodes. For example, the transistors in the first stack 330 and the second stack 340 can be GAAFETs with nanosheets (e.g., RibbonFET transistors) or CFETs with nanosheets. However, the present disclosure is not limited thereto. In general, the proposed switch circuit architecture can be used with any semiconductor technology node.

[0052] The equivalent total on-resistance R ON of switch circuit 300 is given by the parallel of two series on-resistances of the p / n-type transistors forming the first stack 330 and the second stack 340. The configuration is fully symmetric (the path from the first node 310 to the second node 320 is substantially equivalent to the path from the first node 310 to the third node 390) to achieve the highest linearity.

[0053] The corresponding voltage clamps 351 and 352 are coupled between the sources of transistors 331 and 342 and the drains of transistors 332 and 342. In Figure 3 the example of, the corresponding voltage clamps 351 and 352 are formed by corresponding semiconductor switches. However, the present disclosure is not limited thereto. In an alternative example, the corresponding voltage clamps 351 and 352 may be formed by a corresponding set of two back-to-back diodes or corresponding transmission gates similar to the transmission gates described above with respect to the switch circuit 100. The transistors of the corresponding transmission gates may be of the same type as the transistors between which the corresponding transmission gates are coupled (e.g., p-type or n-type) to track process and temperature variations. For example, the gates of the transistors of the corresponding transmission gates may be configured to receive the same signal as the gates of the transistors between which the corresponding transmission gates are coupled (e.g., the gates of the transistors forming the transmission gate between the sources of transistors 331 and 341 may be configured to receive the same signal as the gates of transistors 331 and 341 for controlling the conduction state of the transmission gate). In the case of overvoltage or undervoltage, the electrical stress is attenuated by the charge distribution in the switch circuit 300 and is controlled via the voltage clamps 351 and 352. The voltage clamps 351 and 352 equalize the source or drain voltages of the transistors between which the corresponding voltage clamps are coupled. The voltage clamps 351 and 352 allow the drain-gate-source voltages of the transistors of the first stack 130 and the second stack 140 to be maintained with a safe operating range by acting as fast passive clamps without an additional penalty in terms of current consumption.

[0054] The switch circuit 300 further includes a fourth node 360 configured to receive a DC reference voltage (common-mode voltage) V cm . The fourth node 360 is resistively coupled between the source of transistor 332 and the second node 120 and between the source of transistor 342 and the third node 390. Assuming that the supply voltages of the switch circuit 300 are a first supply voltage V DD and a second supply voltage V SS , where V SS < V DD , then the DC reference voltage may be V cm = 1 / 2V DD . The DC reference voltage V cm allows the switch circuit 300 to be balanced.

[0055] Although not explicitly shown in Figure 3 , corresponding capacitors may additionally be coupled between the corresponding gates and corresponding sources of the transistors in the first stack 330 and the second stack 340. Similarly, corresponding capacitors may additionally be coupled between the corresponding gates and corresponding drains of the transistors in the first stack 330 and the second stack 340. The additional capacitors allow the balance of the switch circuit 300 to be further improved.

[0056] The switching circuit 300 includes a control circuit 370 configured to control the respective conduction states of the transistors forming the first stack 330 and the second stack 340. Specifically, the control circuit 370 is configured to supply respective control signals to the respective gates (terminals) of the transistors in the first stack 330 and the second stack 340 to control the on and off states of the transistors. In Figure 3 the example, respective sub-circuits 371, ..., 374 for controlling the on and off states of the respective transistors are shown. The sub-circuits 371, ..., 374 form the control circuit 170.

[0057] Respective resistors are coupled between the respective gates of the transistors in the first stack 330 and the second stack 340 and the control circuit 370. Specifically, the respective resistors are coupled between the respective gates of the transistors in the first stack 330 and the second stack 340 and the respective sub-circuits 371, ..., 374. The resistors allow the bandwidth of the switching circuit 300 to be increased by neutralizing device parasitic capacitances (e.g., gate-source and gate-drain parasitic capacitances). The resistors are optional and may be omitted in alternative examples (e.g., when chip area is limited).

[0058] By controlling the respective conduction states of the transistors forming the first stack 330 and the second stack 340, the first node 310 can be coupled to and decoupled from the second node 320 and the third node 390 in a controlled manner. For example, to electrically couple the first node 310 to the second node 320 and the third node 390, the control circuit 370 can be configured to adjust the respective signal levels of the respective control signals to control the transistors in the first stack 330 and the second stack 340 to be in an on state. For example, the transistors in the first stack 330 and the second stack 340 can be controlled to be in a strong depletion mode via the respective control signals. The signal level of the control signal for the p-type transistors 331 and 332 can be set, for example, to V SS to turn on these transistors and drive them into the strong depletion mode. Similarly, the signal level of the control signal for the n-type transistors 341 and 342 can be set, for example, to V DD to turn on these transistors and drive them into the strong depletion mode.

[0059] For example, to electrically decouple the first node 310 from the second node 320 and the third node 390, the control circuit 370 can be configured to: adjust the respective signal levels of the respective control signals to control the transistors in the first stack 330 and the second stack 340 to be in an off state. For example, the transistors in the first stack 330 and the second stack 340 can be controlled via the respective control signals to be in a strong enhancement mode or a strong accumulation mode to avoid self-turn-on of unwanted transistors. The signal levels of the control signals for the p-type transistors 331 and 332 can be set, for example, to V DD , to turn off these transistors and drive them into a strong enhancement mode (or a strong accumulation mode). Similarly, the signal levels of the control signals for the n-type transistors 341 and 142 can be set, for example, to V SS , to turn off these transistors and drive them into a strong enhancement mode (or a strong accumulation mode).

[0060] The bias control of the transistors in the first stack 330 and the second stack 340 can be static (i.e., no current is required). In other words, setting and maintaining the static points of the transistors in the first stack 130 and the second stack 140 can be achieved without current consumption.

[0061] In the Figure 3 example, each of the first stack 330 and the second stack 340 includes two transistors. However, it should be noted that the present disclosure is not limited thereto. Each of the first stack 130 and the second stack 140 can optionally include additional transistors. L additional p-type transistors can be serially coupled between the first node 310 and the transistor 331 in the first stack 330, L additional p-type transistors can be serially coupled between the second node 320 and the transistor 332 in the first stack 330, L additional n-type transistors can be serially coupled between the first node 310 and the transistor 341 in the second stack 340, and L additional n-type transistors can be serially coupled between the third node 390 and the transistor 342 in the second stack 340 (where L is an integer).

[0062] The general function of the control circuit has been explained above with reference to Figure 1 and Figure 3 . The following describes two more detailed examples of the control circuit for the transistors in the first stack and the second stack with reference to Figure 4 and Figure 5 . It should be noted that the examples of Figure 4 and Figure 5 are illustrative examples, and the present disclosure is not limited thereto.

[0063] Figure 4 FIG. shows an exemplary control circuit 400. The control circuit 400 can be used in any of the switching circuits 100, 200, and 300 described above.Figure 4 Also shown is the first node 110 / 310 of the switch circuit together with the first stack 130 / 330 described above (only half of the transistor stack 130 is depicted in Figure 4 ), and the second transistor stack 140 / 340 (only half of the transistor stack 140 is depicted in Figure 4 ). The lower portions of the transistors are coupled to the second and third nodes as shown, or are coupled to the second node via additional transistors of the opposite conduction type as shown in Figure 3 and Figure 1 and Figure 2 .

[0064] The control circuit 400 includes two voltage buffers (e.g., amplifiers) 410 and 420, which are coupled to the respective gates (terminals) of the n-type transistors 141 / 341 and 142 / 342 in the second stack 140 / 340. In addition, the control circuit 400 includes two inverting voltage buffers (e.g., inverting amplifiers) 430 and 440, which are coupled to the respective gates (terminals) of the p-type transistors 131 / 331 and 132 / 332 in the first stack 130 / 330.

[0065] The voltage buffers 410 and 420 and the inverting voltage buffers 430 and 440 are configured to: receive the switch control signal 401 and, based on the switch control signal 401, generate respective control signals for the respective transistors. Specifically, the inverting voltage buffers 430 and 440 generate control signals for the transistors 131 / 331 and 132 / 332 by inverting the switch control signal 401. The voltage buffers 410 and 420 output the buffered switch control signal 401 as the control signals for the transistors 141 / 341 and 142 / 342.

[0066] The voltage buffers 410 and 420 and the inverting voltage buffers 430 and 440 receive a first supply voltage V DD and a second supply voltage V SS . The voltage buffers 410 and 420 and the inverting voltage buffers 430 and 440 generate respective control signals having a voltage (signal) level between the voltage level of the first supply voltage V DD and the voltage (signal) level of the second supply voltage V SS . For example, the voltage level of the control signals for the p-type transistors 131 / 331 and 132 / 332 can be V SS , and the voltage level of the control signals for the n-type transistors 141 / 341 and 142 / 342 can be V DD to turn on these transistors. Similarly, the voltage level of the control signals for the p-type transistors 131 / 331 and 132 / 332 can be V DD, and the voltage levels of the control signals for the n-type transistors 141 / 341 and 142 / 342 can be V SS , to turn off these transistors.

[0067] Note that, in an alternative example, the two voltage buffers 410 and 420 can be coupled to the gates of the p-type transistors 131 / 331 and 132 / 332 in the first stack 130 / 330, and the two inverted voltage buffers 430 and 440 can be coupled to the gates of the n-type transistors 141 / 341 and 142 / 342 in the second stack 140 / 340.

[0068] In the case where the control circuit 400 is used for the switch circuits 100 and 200 described above and shown in Figure 1 and Figure 2 , the control circuit 400 includes: additional voltage buffers coupled to the gates of the transistors 133 and 134; and additional inverted voltage buffers coupled to the gates of the transistors 143 and 144.

[0069] More generally, the control circuit 400 includes a plurality of voltage buffers, the plurality of voltage buffers (all) coupled to the respective gates of the transistors of either the first conduction type or the second conduction type in the first stack and the second stack. Additionally, the control circuit 400 includes a plurality of inverted voltage buffers, the plurality of inverted voltage buffers (all) coupled to the respective gates of the other of the transistors of the first conduction type and the second conduction type. The plurality of voltage buffers and the plurality of inverted voltage buffers are configured to: receive a switch control signal and, based on the switch control signal, generate a respective control signal for a respective transistor. As indicated in Figure 4 , the plurality of voltage buffers and the plurality of inverted voltage buffers can be configured to: receive a first supply voltage and a second supply voltage and generate a respective control signal having a voltage level between the voltage level of the first supply voltage and the voltage level of the second supply voltage.

[0070] The control circuit 400 allows for direct gate drive via a level-shifting signal. When using the switch circuit in an attenuation circuit (which makes the trade-off between the on-resistance R ON and the off-capacitance C OFF more difficult), omitting additional resistors between the transistor gates and the (inverted) voltage buffers allows for saving chip area at the cost of reduced overall linearity. The control circuit 400 for the proposed high-voltage switch is a static bias control circuit. The switch circuit with the control circuit can be used for each parallel shunt path of an attenuation circuit (e.g., DSA) because it allows for almost zero current consumption (equivalently only gate leakage) for different switch states (e.g., on and off).

[0071] Figure 5 An alternative control circuit 500 is shown. The control circuit 500 can be used for any one of the switching circuits 100, 200, and 300 described above. For reasons of simplicity, Figure 5 the control circuit 500 shown is only for the first transistors in the first stack and the first transistors in the second stack. Thus, in Figure 5 only the first transistors in the first stack and the first transistors in the second stack are shown. The control circuit 500 can include similar elements and functions for other transistors in the respective stacks.

[0072] The control circuit 500 includes a first n-type transistor 510. The source (terminal) of the first transistor 510 is coupled to a third node 160 / fourth node 360 that provides a DC reference voltage. Additionally, the control circuit 500 includes a second n-type transistor 520. The drain (terminal) of the second n-type transistor 520 is coupled to the gate of the transistor 131 / 331 in the first stack. The gate (terminal) of the second n-type transistor 520 is coupled to the drain (terminal) of the first n-type transistor 510.

[0073] Additionally, the control circuit 500 includes a first inverting voltage buffer (e.g., an amplifier) 530, which is configured to receive a first switch control signal 501 at its input (node). The output (node) of the first inverting voltage buffer 530 is coupled to the gate (terminal) of the first n-type transistor 510. The input of the first inverting voltage buffer 530 is also coupled to the source (terminal) of the second n-type transistor 520.

[0074] The control circuit 500 further includes a first p-type transistor 540. The source (terminal) of the first transistor 540 is coupled to a third node 160 / fourth node 360 that provides a DC reference voltage. Additionally, the control circuit 500 includes a second p-type transistor 550. The drain (terminal) of the second p-type transistor 550 is coupled to the gate of the transistor 141 / 341 in the second stack. The gate (terminal) of the second p-type transistor 550 is coupled to the drain (terminal) of the first p-type transistor 540.

[0075] Additionally, the control circuit 500 includes a second inverting voltage buffer (e.g., an amplifier) 560, which is configured to receive a second switch control signal 502 at its input (node). The output (node) of the second inverting voltage buffer 560 is coupled to the gate (terminal) of the first p-type transistor 540. The input of the second inverting voltage buffer 560 is also coupled to the source (terminal) of the second p-type transistor 550.

[0076] The first switch control signal 501 and the second switch control signal 502 are inverted relative to each other.

[0077] The inverting voltage buffers 530 and 560 receive a first supply voltage V DD and a second supply voltage V SS .

[0078] The output signals at the drains of the transistors 520 and 550 are control signals for the transistors 131 / 331 and 141 / 341 in the first stack and the second stack.

[0079] Compared with the control circuit 400, the control circuit 500 avoids using a level shifter with a full (rail-to-rail) output voltage swing V DD -V SS . Instead, the control signals are generated with respect to a common-mode reference voltage provided by the third node 160 / fourth node 360.

[0080] Compared with the control circuit 400, the control circuit 500 allows for reduced chip area consumption, complexity, and parasitics.

[0081] In the Figure 5 example, the transistors 510 and 520 are n-type transistors. However, it should be noted that the present disclosure is not limited thereto. Generally, the conduction type of the transistors 510 and 520 depends on the conduction type of the corresponding transistors in the first stack to which the transistor 520 is coupled. In other words, if the transistors 131 / 331 in the first stack (or any other transistors in the first stack to which the transistor 520 is coupled) are of the first conduction type, then the transistors 510 and 520 are of the second conduction type, and vice versa. Similarly, the conduction type of the transistors 540 and 550 depends on the conduction type of the corresponding transistors in the second stack to which the transistor 550 is coupled. In other words, if the transistors 141 / 341 in the second stack (or any other transistors in the second stack to which the transistor 550 is coupled) are of the second conduction type, then the transistors 540 and 550 are of the first conduction type, and vice versa.

[0082] As indicated above, the switching circuit according to the proposed technique can be used in an attenuation circuit (e.g., DSA). Two exemplary receivers having an attenuation circuit using the switching circuit according to the proposed technique will be described below with reference to Figure 6 and Figure 7 . It should be noted that although the switching circuit according to the proposed technique is described with reference to an attenuation circuit, the switching circuit according to the proposed technique can equally be used for other applications.

[0083] Figure 6 Receiver 600 is shown. The receiver includes an attenuation circuit 610.

[0084] The attenuation circuit 610 includes a first input node 611 and a second input node 612, each of which is configured to receive a respective input signal of a first input signal and a second input signal forming a differential input signal pair. For example, the first input node 611 may receive the first input signal of the differential input signal pair, and the second input node 612 may receive the second input signal of the differential input signal pair. The first input signal and the second input signal received by the input nodes 611 and 612 may be, for example, RF signals. For example, the RF signal may be an RF reception signal provided by an antenna element.

[0085] Additionally, the attenuation circuit 610 includes a first output node 613 and a second output node 614, each of which is configured to output a respective output signal of a first output signal and a second output signal forming a differential output signal pair. For example, the first output node 613 may output the first output signal of the differential output signal pair, and the second output node 614 may output the second output signal of the differential output signal pair.

[0086] A first signal path 615 is coupled between the first input node 611 and the first output node 613. Similarly, a second signal path 616 is coupled between the second input node 612 and the second output node 614.

[0087] The first signal path 615 includes two resistor elements 618-1 and 618-2, which are coupled between the first input node 611 and the first output node 613. However, it should be noted that the present disclosure is not limited thereto. Generally, any number F≥2 of resistor elements may be coupled between the first input node 611 and the first output node 613 (F is an integer). In other words, the first signal path 615 includes a first plurality of resistor elements.

[0088] The second signal path 616 includes two resistor elements 619-1 and 619-2, which are coupled in series between the second input node 612 and the second output node 614. However, it should be noted that the present disclosure is not limited thereto. Generally, any number G≥2 of resistor elements may be coupled between the second input node 612 and the second output node 614 (G is an integer that may be equal to or different from F). In other words, the second signal path 616 includes a second plurality of resistor elements.

[0089] At Figure 6In the example, each of the resistor elements 618-1 and 618-2 and the resistor elements 619-1 and 619-2 is a single resistor. In other examples, the resistor elements 618-1 and 618-2 and the resistor elements 619-1 and 619-2 may include respective multiple resistors coupled in parallel. According to the example, the first multiple resistor elements and the second multiple resistor elements may be formed to be the same as each other. In other examples, the first multiple resistor elements and the second multiple resistor elements may be formed to be different from each other. For example, at least a part of the first multiple resistor elements and / or the second multiple resistor elements may be a single resistor respectively. In other examples, at least a part of the first multiple resistor elements and / or the second multiple resistor elements may include respective multiple resistors coupled in parallel. The resistance of each of the first multiple resistor elements may be the same as or different from each other. Similarly, the resistance of each of the second multiple resistor elements may be the same as or different from each other.

[0090] The attenuation circuit 610 additionally includes a shunt path 617, which is coupled between the first signal path 615 and the second signal path 616. The shunt path 617 may be coupled to the first signal path 615 between any two (directly successive) resistor elements of the first multiple resistor elements. Similarly, the shunt path 617 may be coupled to the second signal path 616 between any two (directly successive) resistor elements of the second multiple resistor elements.

[0091] The shunt path 617 includes a switching circuit 605 according to the present disclosure to selectively couple (shunt) the first signal path 615 and the second signal path 616. Since the receiver 600 is a differential receiver, the switching circuit 605 may be, for example, one of the switching circuits 100 and 200 described above.

[0092] In the case where the switching circuit 605 does not couple the first signal path 615 and the second signal path 616, the first input signal and the second input signal in the differential input signal pair are not attenuated by the attenuation circuit 610. This state of the attenuation circuit 610 may be understood as a reference state or a through state. In the case where the switching circuit 605 couples the first signal path 615 and the second signal path 616, the first input signal and the second input signal in the differential input signal pair are attenuated by the attenuation circuit 610. This state of the attenuation circuit 610 may be understood as an attenuation state. The attenuation circuit 100 can thus achieve selective signal attenuation.

[0093] The switch circuit 605 in the shunt path 617 is configured to selectively couple the first signal path 615 and the second signal path 616 based on at least one switch control signal. The at least one switch control signal is generated by the attenuation control circuit 630 of the receiver 600 to control the coupling of the first signal path 615 and the second signal path 616 through the switch circuit 605 in the shunt path 617. For example, the attenuation control circuit 630 may be configured to control the coupling of the first signal path 615 and the second signal path 616 through the switch circuit 605 in the shunt path 617 based on the target attenuation degrees of the first input signal and the second input signal. The target attenuation degree is the desired attenuation degree of the attenuation circuit 610 for the first input signal and the second input signal. For example, the control circuit 630 may determine the target attenuation degree based on the signal power of the first input signal and the second input signal to the attenuation circuit 610 (e.g., indicated by the signal envelopes of the first input signal and the second input signal). For example, if the switch circuit 605 uses the control circuit 400 described above, the attenuation control circuit 630 may supply a single switch control signal to the switch circuit 605. On the other hand, if the switch circuit 605 uses the control circuit 500 described above, the attenuation control circuit 630 may supply two switch control signals that are in phase opposition with respect to each other to the switch circuit 605.

[0094] Optionally, the shunt path 617 may include more than one switch circuit 605 according to the present disclosure. Thus, the attenuation control circuit 630 may generate at least one corresponding switch control signal for each switch circuit of the shunt path.

[0095] Similarly, the attenuation circuit 610 may include more than one shunt path, and the more than one shunt path includes at least one corresponding switch circuit according to the present disclosure to selectively couple the first signal path 615 and the second signal path 616. The multiple shunt paths may be coupled to the first signal path 615 between different pairs of resistance elements of the first plurality of resistance elements. Similarly, the multiple shunt paths may be coupled to the second signal path 616 between different pairs of resistance elements of the second plurality of resistance elements. For example, the attenuation circuit according to the present disclosure may include two, three, four or more shunt paths for selectively coupling the first signal path 615 and the second signal path 616 at different intermediate nodes. Due to the linearity of the circuit arrangement, the cascading (superposition) of multiple parallel shunt paths allows the expansion of the attenuation range of the attenuation circuit. For example, the total attenuation of the attenuation circuit according to the present disclosure may be given by the sum of the attenuations of each parallel shunt path.

[0096] The attenuation control circuit 630 may generate at least one corresponding switch control signal for each switch circuit of each shunt path.

[0097] By selectively coupling and decoupling the first signal path 615 and the second signal path 616 via a switching circuit in one or more shunt paths, the attenuation of the attenuation circuit 610 can be varied in predetermined steps. Thus, the attenuation circuit according to the present disclosure can be understood as a DSA.

[0098] A load 620 is coupled to the output nodes 613 and 614 of the attenuation circuit 610 for further processing of the differential output signal pair. The load 620 can be, for example, one or more input buffers of an analog-to-digital converter (ADC).

[0099] Figure 7 A single-ended receiver 700 is shown. The receiver 700 includes an attenuation circuit 710.

[0100] The attenuation circuit 710 includes an input node 711 and an output node 712. A signal path 713 is coupled between the input node 711 and the output node 712. The input node 711 is configured to receive an input signal. The output node is configured to output an output signal. The input signal received by the input node 611 can be, for example, an RF signal. For example, the RF signal can be an RF received signal provided by an antenna element.

[0101] The signal path 713 includes two resistor elements 716-1 and 716-2, which are coupled in series between the input node 711 and the output node 712. However, it should be noted that the present disclosure is not limited thereto. Generally, any number H≥2 of resistor elements can be coupled between the input node 711 and the output node 712 (H is an integer). In other words, the signal path 713 includes a plurality of resistor elements.

[0102] The attenuation circuit 710 further includes a shunt path 714, which is coupled between the signal path 713 and the node 715. The node 715 is either grounded or provides a supply voltage (e.g., V SS ). The shunt path 714 can be coupled to the signal path 713 between any two (directly successive) resistor elements of the plurality of resistor elements.

[0103] The shunt path 714 includes a switching circuit 705 according to the present disclosure to selectively couple (shunt) the signal path 713 and the node 715 and (therefore) the ground voltage or the supply voltage. Since the receiver 700 is a single-ended receiver, the switching circuit 705 can be, for example, the switching circuit 300 described above.

[0104] In the case where the switching circuit 705 does not couple the signal path 713 to ground or the supply voltage, the input signal is not attenuated by the attenuation circuit 710. This state of the attenuation circuit 710 can be understood as the reference state or the pass state. In the case where the switching circuit 705 couples the signal path 713 to ground or the supply voltage, the input signal is attenuated by the attenuation circuit 710. This state of the attenuation circuit 710 can be understood as the attenuation state. Therefore, the attenuation circuit 700 can achieve selective signal attenuation.

[0105] The switching circuit 705 in the shunt path 714 is configured to selectively couple the signal path 713 to ground or the supply voltage based on at least one switching control signal. The at least one switching control signal is generated by the attenuation control circuit 730 of the receiver 700 to control the coupling of the signal path 713 to ground or the supply voltage through the switching circuit 705 in the shunt path 714. For example, the attenuation control circuit 730 can be configured to control the coupling of the signal path 713 to ground or the supply voltage through the switching circuit 705 in the shunt path 714 based on the target attenuation degree of the input signal. The target attenuation degree is the desired attenuation degree of the input signal by the attenuation circuit 710. For example, the control circuit 730 can determine the target attenuation degree based on the signal power of the input signal (e.g., indicated by the signal envelope of the input signal). For example, if the switching circuit 705 uses the control circuit 400 described above, the attenuation control circuit 730 can supply a single switching control signal to the switching circuit 705. On the other hand, if the switching circuit 705 uses the control circuit 500 described above, the attenuation control circuit 730 can supply two switching control signals that are inverted with respect to each other to the switching circuit 705.

[0106] Optionally, the shunt path 714 can include more than one switching circuit 705 according to the present disclosure. Therefore, the attenuation control circuit 730 can generate at least one corresponding switching control signal for each switching circuit of the shunt path 714.

[0107] Similarly, the attenuation circuit 710 can include more than one shunt path, and the more than one shunt path includes at least one corresponding switching circuit according to the present disclosure to selectively couple the signal path 713 to ground or the supply voltage. The multiple shunt paths can be coupled to the signal path 713 between different pairs of resistance elements of multiple resistance elements. For example, the attenuation circuit according to the present disclosure can include two, three, four or more shunt paths for selectively coupling the signal path 713 to ground or the supply voltage at different intermediate nodes. Due to the linearity of the circuit arrangement, the cascading (superposition) of multiple parallel shunt paths allows the expansion of the attenuation range of the attenuation circuit. For example, the total attenuation of the attenuation circuit according to the present disclosure can be given by the sum of the attenuations of each parallel shunt path.

[0108] The attenuation control circuit 730 can generate at least one corresponding switch control signal for each switch circuit of each shunt path.

[0109] By selectively coupling and decoupling the signal path 713 to ground or the supply voltage via the switch circuits in one or more shunt paths, the attenuation of the attenuation circuit 710 can be varied in predefined steps. Thus, the attenuation circuit according to the present disclosure can be understood as a DSA.

[0110] The load 720 is coupled to the output node 712 of the attenuation circuit 710 for further processing of the output signal. The load 620 can be, for example, one or more input buffers of an ADC.

[0111] Figure 8 A diagram 800 is shown that highlights an exemplary comparison regarding the linearity of different attenuation circuits. The linearity is measured for a two-tone test. The abscissa of the diagram 800 represents the input power (i.e., the power allocated per tone). The ordinate represents the power of the various signal components output by the respective attenuation circuit.

[0112] As a reference, the curve 810 shows the power of the fundamental frequency tone output by the attenuation circuit. The curve 820 shows an ideal path regarding third-order intermodulation distortion (IMD3) with a constant slope.

[0113] The curve 830 shows the IMD3 in the output of a conventional attenuation circuit. The curve 840 shows the IMD3 in the output of the attenuation circuit according to the present disclosure.

[0114] As can be seen from the curves 830 and 840, the linearity of the attenuation circuit according to the present disclosure is significantly improved (e.g., by more than 30 dB) due to the switch circuits according to the proposed technique. This allows for a significant expansion of the range and the maximum (tolerable) input power of the attenuation circuit. For example, the range and the maximum (tolerable) input power of the attenuation circuit can be expanded far beyond the limitations imposed by modern semiconductor technology nodes (e.g., RibbonFET process technology).

[0115] In Figure 9 is shown an example of the implementation of a switch circuit using one or more aspects of the architecture described above in conjunction with Figures 1 to 7 or one or more examples described above in conjunction with Figures 1 to 7 described. Figure 9 An example of a radio base station 900 (e.g., for a femtocell, picocell, microcell, or macrocell) including the proposed receiver 910 is schematically shown.

[0116] Base station 900 includes at least one antenna element 930, and at least one antenna element 930 is coupled to a receiver 910. The receiver 910 can be coupled to the antenna element 930 via one or more intermediate elements (e.g., one or more of signal lines, filters, etc.).

[0117] The receiver 910 includes the proposed attenuation circuit. For example, the receiver 910 can be one of the receivers 600 and 700 described above. The receiver 910 can include various additional elements (e.g., one or more of a low noise amplifier (LNA), a filter, a downconverter (mixer), an electrostatic discharge (ESD) protection circuit, etc.).

[0118] Additionally, base station 900 includes a transmitter 920 configured to generate an RF transmission signal. The transmitter 920 can use the antenna element 930 of base station 900 or another antenna element (not shown) to radiate the RF transmission signal into the environment. For example, the transmitter 920 can be coupled to the antenna element 930 via one or more intermediate elements (e.g., a filter, an upconverter (mixer), or a power amplifier (PA)).

[0119] To this end, a base station with improved signal attenuation capabilities can be provided.

[0120] Base station 900 can include additional elements (e.g., an application processor, a baseband processor, a memory, a network controller, a user interface, a power management circuit, a satellite navigation receiver, a network interface controller, or a power splitter circuit).

[0121] In some aspects, the application processor can include one or more central processing unit (CPU) cores and one or more of the following: cache memory, a low dropout (LDO) voltage regulator, an interrupt controller, a serial interface (e.g., a serial peripheral interface (SPI), an inter-integrated circuit (I 2 C), or a general-purpose programmable serial interface module), a real-time clock (RTC), a timer-counter (including an interval timer and a watchdog timer), general-purpose input-output (IO), a memory card controller (e.g., a secure digital (SD) / multimedia card (MMC), etc.), a universal serial bus (USB) interface, a Mobile Industry Processor Interface Alliance (MIPI) interface, and a Joint Test Action Group (JTAG) test access port.

[0122] In some aspects, the baseband processor can be implemented, for example, as a soldered-in substrate including one or more integrated circuits, a single-package integrated circuit soldered to the main circuit board, or a multi-chip module including two or more integrated circuits.

[0123] In some aspects, the memory may include one or more of the following: volatile memory (including dynamic random access memory (DRAM) and / or synchronous DRAM (SDRAM)) and non-volatile memory (NVM) (including high-speed electrically erasable memory (commonly known as flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), and / or three-dimensional cross-point (3D XPoint) memory). The memory may be implemented as one or more of a soldered-in package integrated circuit, a socketed memory module, and a plug-in memory card.

[0124] In some aspects, the power management (integrated) circuit may include one or more of the following: a voltage regulator, a surge protector, a power alert detection circuit, and one or more backup power sources (e.g., a battery or a capacitor). The power alert detection circuit may detect one or more of a power-down (undervoltage) condition and a surge (overvoltage) condition.

[0125] In some aspects, the power pass-through circuit may provide power drawn from a network cable to provide both power and a data connection to a base station using a single cable.

[0126] In some aspects, the network controller may provide a connection to the network using a standard network interface protocol (e.g., Ethernet). The network connection may be provided using a physical connection, which is one of an electrical connection (commonly known as copper interconnect), an optical connection, or a wireless connection.

[0127] In some aspects, the satellite navigation receiver may include circuitry for receiving and decoding signals transmitted by one or more navigation satellite constellations (e.g., Global Positioning System (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo, and / or Beidou). The receiver may provide data to an application processor, which may include one or more of position data or time data. The application processor may use the time data to synchronize operations with other radio base stations.

[0128] In some aspects, the user interface may include one or more of the following: physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., a light-emitting diode (LED)), and a display screen.

[0129] In Figure 10 is shown an example of the implementation of a switching circuit using one or more aspects of the architecture described above in connection with Figures 1 to 7 described, or another example of the implementation of a switching circuit using one or more examples described above in connection with Figures 1 to 7 described. Figure 10An example of a mobile device 1000 (e.g., a mobile phone, smartphone, tablet computer, or laptop device) including the proposed receiver 1010 is schematically shown.

[0130] The mobile device 1000 includes at least one antenna element 1030, and the at least one antenna element 1030 is coupled to the receiver 1010. The receiver 1010 may be coupled to the antenna element 1030 via one or more intermediate elements (e.g., one or more of signal lines, filters, etc.).

[0131] The receiver 1010 includes the proposed attenuation circuit. For example, the receiver 1010 may be one of the receivers 600 and 700 described above. The receiver 1010 may include various additional elements (e.g., one or more of an LNA, filter, downconverter (mixer), ESD protection circuit, etc.).

[0132] Additionally, the mobile device 1000 includes a transmitter 1020 configured to generate an RF transmission signal. The transmitter 1020 may use the antenna element 1030 of the mobile device 1000 or another antenna element (not shown) to radiate the RF transmission signal into the environment. For example, the transmitter 1020 may be coupled to the antenna element 1030 via one or more intermediate elements (e.g., a filter, upconverter (mixer), or PA).

[0133] To this end, a mobile device with improved signal attenuation capabilities may be provided.

[0134] The mobile device 1000 may include additional elements (e.g., an application processor, baseband processor, memory, connection module, near field communication (NFC) controller, audio driver, camera driver, touch screen, display driver, sensors, removable memory, power management integrated circuit, or smart battery).

[0135] In some aspects, the application processor may include, for example, one or more CPU cores and one or more of the following: cache memory, LDO voltage regulator, interrupt controller, serial interface (e.g., SPI, I 2 C or general programmable serial interface module), RTC, timer - counter (including interval timer and watchdog timer), general purpose input - output (IO), memory card controller (e.g., SD / MMC, etc.), USB interface, MIPI interface, and JTAG test access port.

[0136] In some aspects, the baseband processor may be implemented, for example, as a soldered - in substrate including one or more integrated circuits, a single - package integrated circuit soldered to the main circuit board, and / or a multi - chip module including two or more integrated circuits.

[0137] A wireless communication circuit using a switching circuit or an attenuation circuit according to the proposed architecture or one or more of the examples described above can be configured to operate according to one of the 3rd Generation Partnership Project (3GPP) standardized mobile communication networks or systems. The mobile or wireless communication system can correspond to, for example, 5th Generation New Radio (5G NR), Long Term Evolution (LTE), LTE-Advanced (LTE-A), High-Speed Packet Access (HSPA), Universal Mobile Telecommunications System (UMTS) or UMTS Terrestrial Radio Access Network (UTRAN), Evolved UTRAN (e-UTRAN), Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE) network or GSM / EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuit can be configured to operate according to a mobile communication network with different standards (e.g., Worldwide Interoperability for Microwave Access (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11, typically an Orthogonal Frequency Division Multiple Access (OFDMA) network, Time Division Multiple Access (TDMA) network, Code Division Multiple Access (CDMA) network, Wideband CDMA (WCDMA) network, Frequency Division Multiple Access (FDMA) network, Space Division Multiple Access (SDMA) network, etc.).

[0138] The examples described herein can be summarized as follows:

[0139] An example (e.g., Example 1) relates to a switching circuit, comprising: a first node for coupling to a first conductive path; a second node for coupling to a second conductive path; a first stack of transistors arranged between the first node and the second node; and a second stack of transistors arranged between the first node and the second node, wherein a first transistor in the first stack is cross-coupled with a second transistor in the second stack, wherein a first transistor in the second stack is cross-coupled with a second transistor in the first stack, the first transistors in the first stack and the second stack are coupled to the first node, wherein a third transistor in the first stack is cross-coupled with a fourth transistor in the second stack, wherein a third transistor in the second stack is cross-coupled with a fourth transistor in the first stack, the fourth transistors in the first stack and the second stack are coupled to the second node, wherein the second transistor in the first stack is coupled to the third transistor in the first stack, and wherein the second transistor in the second stack is coupled to the third transistor in the second stack.

[0140] Another example (e.g., Example 2) relates to a previous example (e.g., Example 1) or any other example, and further includes: the first and second transistors in the first stack and the third and fourth transistors in the second stack are of a first conduction type, wherein the first and second transistors in the second stack and the third and fourth transistors in the first stack are of a second conduction type.

[0141] Another example (e.g., Example 3) relates to a previous example (e.g., one of Examples 1 or 2) or any other example, and further includes: the drain of the first transistor in the first stack is coupled to the first node, wherein the source of the second transistor in the first stack is coupled to the source of the third transistor in the first stack, wherein the drain of the fourth transistor in the first stack is coupled to the second node, wherein the drain of the first transistor in the second stack is coupled to the first node, wherein the source of the second transistor in the second stack is coupled to the source of the third transistor in the second stack, wherein the drain of the fourth transistor in the second stack is coupled to the second node, wherein the source of the first transistor in the first stack is coupled to the drain of the second transistor in the second stack, wherein the source of the first transistor in the second stack is coupled to the drain of the second transistor in the first stack, wherein the source of the fourth transistor in the first stack is coupled to the drain of the third transistor in the second stack, and wherein the source of the fourth transistor in the second stack is coupled to the drain of the third transistor in the first stack.

[0142] Another example (e.g., Example 4) relates to a previous example (e.g., one of Examples 1 to 3) or any other example, and further includes: a first conductive trace coupling the first transistor in the first stack and the second transistor in the second stack crosses a second conductive trace coupling the first transistor in the second stack and the second transistor in the first stack.

[0143] Another example (e.g., Example 5) relates to a previous example (e.g., Example 4) or any other example, and further includes: a third conductive trace coupling the fourth transistor in the first stack and the third transistor in the second stack crosses a fourth conductive trace coupling the fourth transistor in the second stack and the third transistor in the first stack.

[0144] Another example (e.g., Example 6) relates to a previous example (e.g., one of Examples 1 to 5) or any other example, and further includes: the first stack and the second stack are arranged to be offset from each other in a lateral direction.

[0145] Another example (e.g., Example 7) relates to a previous example (e.g., one of Examples 1 to 6) or any other example, and further includes: a corresponding voltage clamp coupled between the source of the first transistor in the first stack and the second stack, the drain of the second transistor in the first stack and the second stack, the drain of the third transistor in the first stack and the second stack, and the source of the fourth transistor in the first stack and the second stack.

[0146] Another example (e.g., Example 8) relates to a previous example (e.g., one of Examples 1 to 7) or any other example, and further includes: a control circuit configured to supply corresponding control signals to the corresponding gates of the transistors in the first stack and the second stack to control the on and off states of the transistors.

[0147] Another example (e.g., Example 9) relates to a previous example (e.g., Example 8) or any other example, and further includes: in order to electrically couple the first node and the second node, the control circuit is configured to adjust the corresponding signal levels of the corresponding control signals to control the transistors in the first stack and the second stack to be in an on state.

[0148] Another example (e.g., Example 10) relates to a previous example (e.g., one of Examples 8 or 9) or any other example, and further includes: in order to electrically decouple the first node from the second node, the control circuit is configured to adjust the corresponding signal levels of the corresponding control signals to control the transistors in the first stack and the second stack to be in an off state.

[0149] Another example (e.g., Example 11) relates to a previous example (e.g., one of Examples 8 to 10) or any other example, and further includes: corresponding resistors coupled between the corresponding gates of the transistors in the first stack and the second stack and the control circuit.

[0150] Another example (e.g., Example 12) relates to a previous example (e.g., one of Examples 8 to 11) or any other example, and further includes: the control circuit includes: a plurality of voltage buffers coupled to the corresponding gates of either the first-conductivity-type transistors or the second-conductivity-type transistors in the first stack and the second stack; and a plurality of inverting voltage buffers coupled to the corresponding gates of the other of the first-conductivity-type transistors and the second-conductivity-type transistors, wherein the plurality of voltage buffers and the plurality of inverting voltage buffers are configured to receive a switch control signal and generate corresponding control signals for the corresponding transistors based on the switch control signal.

[0151] Another example (e.g., Example 13) relates to a previous example (e.g., Example 12) or any other example and further includes: the plurality of voltage buffers and the plurality of inverted voltage buffers are configured to: receive a first supply voltage and a second supply voltage; and generate corresponding control signals having voltage levels between the voltage level of the first supply voltage and the voltage level of the second supply voltage.

[0152] Another example (e.g., Example 14) relates to a previous example (e.g., one of Examples 8 to 11) or any other example and further includes: a third node configured to receive a DC reference voltage, wherein the third node is resistively coupled between a second transistor and a third transistor in the first stack and between a second transistor and a third transistor in the second stack, and wherein the control circuit includes: a first transistor of a second conductivity type, wherein the source of the first transistor is coupled to the third node; a second transistor of the second conductivity type, wherein the drain of the second transistor of the second conductivity type is coupled to the gate of the first transistor in the first stack, and wherein the gate of the second transistor of the second conductivity type is coupled to the drain of the first transistor of the second conductivity type; a first inverted voltage buffer configured to: receive a first switch control signal at its input, wherein the output of the first inverted voltage buffer is coupled to the gate of the first transistor of the second conductivity type, and wherein the input of the first inverted voltage buffer is coupled to the source of the second transistor of the second conductivity type; a first transistor of a first conductivity type, wherein the source of the first transistor of the first conductivity type is coupled to the third node; a second transistor of the first conductivity type, wherein the drain of the second transistor of the first conductivity type is coupled to the gate of the first transistor in the second stack, and wherein the gate of the second transistor of the first conductivity type is coupled to the drain of the first transistor of the first conductivity type; a second inverted voltage buffer configured to: receive a second switch control signal at its input, wherein the output of the second inverted voltage buffer is coupled to the gate of the first transistor of the first conductivity type, wherein the input of the second inverted voltage buffer is coupled to the source of the second transistor of the first conductivity type, and wherein the first switch control signal and the second switch control signal are inverted relative to each other.

[0153] Another example (e.g., Example 15) relates to a previous example (e.g., one of Examples 1 to 14) or any other example and further includes: corresponding capacitors coupled between corresponding gates and corresponding sources of the transistors in the first stack and the second stack.

[0154] Another example (e.g., Example 16) relates to a previous example (e.g., one of Examples 1 to 15) or any other example, and further includes: a corresponding capacitor coupled between a corresponding gate and a corresponding drain of transistors in the first stack and the second stack.

[0155] Another example (e.g., Example 17) relates to a previous example (e.g., one of Examples 1 to 14) or any other example, and further includes: a third node configured to receive a DC reference voltage, wherein the third node is resistively coupled between a second transistor and a third transistor in the first stack and between a second transistor and a third transistor in the second stack.

[0156] Another example (e.g., Example 18) relates to a previous example (e.g., one of Examples 1 to 17) or any other example, and further includes: the transistors in the first stack and the second stack are gate-all-around field-effect transistors (GAAFETs) with nanosheets or complementary field-effect transistors (CFETs) with nanosheets.

[0157] An example (e.g., Example 19) relates to an attenuation circuit, including: a first signal path coupled between a first input node and a first output node, wherein the first signal path includes a first plurality of resistive elements; a second signal path coupled between a second input node and a second output node, wherein the second signal path includes a second plurality of resistive elements, and wherein the first input node and the second input node are configured to: receive respective input signals of a first input signal and a second input signal forming a differential input signal pair; and at least one shunt path coupled between the first signal path and the second signal path, wherein the at least one shunt path includes at least one corresponding switch circuit as described in a previous example (e.g., one of Examples 1 to 18) or any other example to selectively couple the first signal path and the second signal path.

[0158] Another example (e.g., Example 20) relates to a previous example (e.g., Example 19) or any other example, and further includes: the at least one corresponding switch circuit in the at least one shunt path is configured to selectively couple the first signal path and the second signal path based on at least one corresponding switch control signal.

[0159] Example (e.g., Example 21) relates to a receiver, comprising: an attenuation circuit as described in a previous example (e.g., one of Examples 19 and 20) or any other example; a load coupled to a first output node and a second output node of the attenuation circuit; and a control circuit configured to: control coupling of the first signal path and the second signal path through at least one corresponding switching circuit in the at least one shunt path based on a target attenuation of the first input signal and the second input signal.

[0160] Another example (e.g., Example 22) relates to a previous example (e.g., Example 21) or any other example, further comprising: the first input signal and the second input signal are radio frequency signals.

[0161] Another example (e.g., Example 23) relates to a previous example (e.g., one of Examples 21 or 22) or any other example, further comprising: the load is one or more input buffers of an analog-to-digital converter.

[0162] Example (e.g., Example 24) relates to a switching circuit, comprising: a first node for coupling to a conductive path; a second node and a third node for coupling to ground or a supply voltage; a first stack of transistors arranged between the first node and the second node; and a second stack of transistors arranged between the first node and the third node, wherein a first transistor in the first stack is coupled to the first node, wherein a second transistor in the first stack is coupled to the second node, wherein a first transistor in the second stack is coupled to the first node, wherein a second transistor in the second stack is coupled to the third node, wherein the first transistor in the first stack and the second transistor in the second stack are cross-coupled, and wherein the first transistor in the second stack and the second transistor in the first stack are cross-coupled.

[0163] Another example (e.g., Example 25) relates to a previous example (e.g., Example 24) or any other example, further comprising: the first transistor and the second transistor in the first stack are of a first conduction type, wherein the first transistor and the second transistor in the second stack are of a second conduction type.

[0164] Another example (e.g., Example 26) relates to a previous example (e.g., one of Examples 24 or 25) or any other example, and further includes: the drain of the first transistor in the first stack is coupled to the first node, wherein the source of the second transistor in the first stack is coupled to the second node, wherein the drain of the first transistor in the second stack is coupled to the first node, wherein the source of the second transistor in the second stack is coupled to the third node, wherein the source of the first transistor in the first stack is coupled to the drain of the second transistor in the second stack, and wherein the source of the first transistor in the second stack is coupled to the drain of the second transistor in the first stack.

[0165] Another example (e.g., Example 27) relates to a previous example (e.g., one of Examples 24 to 26) or any other example, and further includes: a first conductive trace coupling the source of the first transistor in the first stack and the drain of the second transistor in the second stack intersects a second conductive trace coupling the source of the first transistor in the second stack and the drain of the second transistor in the first stack.

[0166] Another example (e.g., Example 28) relates to a previous example (e.g., one of Examples 24 to 27) or any other example, and further includes: the first stack and the second stack are arranged to be offset from each other in a lateral direction.

[0167] Another example (e.g., Example 29) relates to a previous example (e.g., one of Examples 24 to 28) or any other example, and further includes: corresponding voltage clamps are coupled between the sources of the first transistors in the first stack and the second stack and the drains of the second transistors in the first stack and the second stack.

[0168] Another example (e.g., Example 30) relates to a previous example (e.g., one of Examples 24 to 29) or any other example, and further includes: a control circuit configured to supply corresponding control signals to the respective gates of the transistors in the first stack and the second stack to control the on and off states of the transistors.

[0169] Another example (e.g., Example 31) relates to a previous example (e.g., Example 30) or any other example, and further includes: to electrically couple the first node to the second node and the third node, the control circuit is configured to adjust the respective signal levels of the corresponding control signals to control the transistors in the first stack and the second stack to be in an on state.

[0170] Another example (e.g., Example 32) relates to a previous example (e.g., one of Examples 30 or 31) or any other example, and further includes: to electrically decouple the first node from the second node and the third node, the control circuit is configured to: adjust the respective signal levels of the respective control signals to control the transistors in the first stack and the second stack to be in an off state.

[0171] Another example (e.g., Example 33) relates to a previous example (e.g., one of Examples 30 to 32) or any other example, and further includes: respective resistors are coupled between the respective gates of the transistors in the first stack and the second stack and the control circuit.

[0172] Another example (e.g., Example 34) relates to a previous example (e.g., one of Examples 30 to 33) or any other example, and further includes: the control circuit includes: a plurality of voltage buffers coupled to the respective gates of either the transistors in the first stack or the transistors in the second stack; and a plurality of inverting voltage buffers coupled to the respective gates of the other of the transistors in the first stack and the second stack, wherein the plurality of voltage buffers and the plurality of inverting voltage buffers are configured to: receive a switch control signal and, based on the switch control signal, generate respective control signals for the respective transistors.

[0173] Another example (e.g., Example 35) relates to a previous example (e.g., Example 34) or any other example, and further includes: the plurality of voltage buffers and the plurality of inverting voltage buffers are configured to: receive a first supply voltage and a second supply voltage; and generate respective control signals having voltage levels between the voltage level of the first supply voltage and the voltage level of the second supply voltage, wherein the second node and the third node are coupled to the second supply voltage.

[0174] Another example (e.g., Example 36) relates to a previous example (e.g., one of Examples 30 to 33) or any other example, and further includes: a fourth node configured to receive a DC reference voltage, wherein the fourth node is resistively coupled between the second transistor in the first stack and the second node and between the second transistor in the second stack and the third node, and wherein the control circuit includes: a first transistor of a second conduction type, wherein the source of the first transistor is coupled to the fourth node; a second transistor of a second conduction type, wherein the drain of the second transistor of the second conduction type is coupled to the gate of the first transistor in the first stack, and wherein the gate of the second transistor of the second conduction type is coupled to the drain of the first transistor of the second conduction type; a first inverting voltage buffer configured to: receive a first switch control signal at its input, wherein the output of the first inverting voltage buffer is coupled to the gate of the first transistor of the second conduction type, and wherein the input of the first inverting voltage buffer is coupled to the source of the second transistor of the second conduction type; a first transistor of a first conduction type, wherein the source of the first transistor of the first conduction type is coupled to the fourth node; a second transistor of a first conduction type, wherein the drain of the second transistor of the first conduction type is coupled to the gate of the first transistor in the second stack, and wherein the gate of the second transistor of the first conduction type is coupled to the drain of the first transistor of the first conduction type; a second inverting voltage buffer configured to: receive a second switch control signal at its input, wherein the output of the second inverting voltage buffer is coupled to the gate of the first transistor of the first conduction type, wherein the input of the second inverting voltage buffer is coupled to the source of the second transistor of the first conduction type, and wherein the first switch control signal and the second switch control signal are inverted relative to each other.

[0175] Another example (e.g., Example 37) relates to a previous example (e.g., one of Examples 26 to 36) or any other example, and further includes: corresponding capacitors coupled between the corresponding gates and corresponding sources of the transistors in the first stack and the second stack.

[0176] Another example (e.g., Example 38) relates to a previous example (e.g., one of Examples 26 to 37) or any other example, and further includes: corresponding capacitors coupled between the corresponding gates and corresponding drains of the transistors in the first stack and the second stack.

[0177] Another example (e.g., Example 39) relates to a previous example (e.g., one of Examples 26 to 38) or any other example, and further includes: a fourth node configured to receive a DC reference voltage, wherein the fourth node is resistively coupled between the second transistor in the first stack and the second node and between the second transistor in the second stack and the third node.

[0178] Another example (e.g., Example 40) relates to a previous example (e.g., one of Examples 26 to 39) or any other example, and further includes: the transistors in the first stack and the second stack are all-gate-all-around field-effect transistors (GAAFETs) with nanosheets or complementary field-effect transistors (CFETs) with nanosheets.

[0179] An example (e.g., Example 41) relates to an attenuation circuit, including: a signal path coupled between an input node and an output node, wherein the signal path includes a first plurality of resistive elements, and wherein the input node is configured to receive an input signal; and at least one shunt path coupled between the signal path and ground or a supply voltage, wherein the at least one shunt path includes at least one corresponding switch circuit as described in any one of Examples 26 to 40 to selectively couple the signal path to ground or the supply voltage.

[0180] Another example (e.g., Example 42) relates to a previous example (e.g., Example 41) or any other example, and further includes: the at least one corresponding switch circuit in the at least one shunt path is configured to selectively couple the signal path to ground or the supply voltage based on at least one corresponding switch control signal.

[0181] An example (e.g., Example 43) relates to a receiver, including: an attenuation circuit as described in a previous example (e.g., one of Examples 41 and 42) or any other example; a load coupled to the output node of the attenuation circuit; and a control circuit configured to control coupling of the signal path to ground or the supply voltage through the at least one corresponding switch circuit in the at least one shunt path based on a target attenuation degree of the input signal.

[0182] Another example (e.g., Example 44) relates to a previous example (e.g., Example 43) or any other example, and further includes: the input signal is a radio frequency signal.

[0183] Another example (e.g., Example 45) relates to a previous example (e.g., one of Examples 43 or 44) or any other example, and further includes: the load is one or more input buffers of an analog-to-digital converter.

[0184] Example (e.g., Example 46) relates to a base station, comprising: a receiver as described in the previous example (e.g., one of Examples 21 to 23 or 43 to 45); and a transmitter configured to generate a radio frequency transmission signal.

[0185] Another example (e.g., Example 47) relates to the previous example (e.g., Example 46) or any other example, further comprising: at least one antenna element coupled to at least one of the receiver and the transmitter.

[0186] Example (e.g., Example 48) relates to a mobile device, comprising: a receiver as described in the previous example (e.g., one of Examples 21 to 23 or 43 to 45); and a transmitter configured to generate a radio frequency transmission signal.

[0187] Another example (e.g., Example 49) relates to the previous example (e.g., Example 48) or any other example, further comprising: at least one antenna element coupled to at least one of the receiver and the transmitter.

[0188] Aspects and features described in relation to specific examples in the previous examples may also be combined with one or more in other examples to replace the same or similar features in that other example, or additionally introduce these features into that other example.

[0189] It should also be understood that the disclosure of a number of steps, processes, operations or functions in the specification or claims should not be construed as implying that these operations necessarily depend on the described order, unless explicitly stated in individual cases or necessary for technical reasons. Therefore, the previous description does not limit the execution of a number of steps or functions to a specific order. Additionally, in other examples, a single step, function, process or operation may include and / or be decomposed into a number of sub-steps, sub-functions, sub-processes or sub-operations.

[0190] If some aspects related to a device or system have been described, these aspects should also be understood as a description of the corresponding method. For example, the blocks, device or functional aspects of a device or system may correspond to the features (e.g., method steps) of the corresponding method. Therefore, aspects related to the method described should also be understood as a description of the nature or functional features of the corresponding blocks, corresponding elements, corresponding devices or corresponding systems.

[0191] The appended claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. It should also be noted that although in the claims, dependent claims refer to specific combinations with one or more other claims, other examples may also include combinations of the subject matter of such dependent claims with any other dependent or independent claim. Such combinations are expressly presented herein, unless in an individual case it is stated that a specific combination is not intended. Further, the features of a claim should also be included in any other independent claim, even if that claim is not directly defined as being dependent on that other independent claim.

Claims

1. A switching circuit, comprising: a first node for coupling to a first conductive path; a second node for coupling to a second conductive path; a first stack of transistors arranged between the first node and the second node; and a second stack of transistors arranged between the first node and the second node, wherein a first transistor in the first stack is cross-coupled with a second transistor in the second stack, wherein a first transistor in the second stack is cross-coupled with a second transistor in the first stack, and the first transistors in the first stack and the second stack are coupled to the first node, wherein a third transistor in the first stack is cross-coupled with a fourth transistor in the second stack, wherein a third transistor in the second stack is cross-coupled with a fourth transistor in the first stack, and the fourth transistors in the first stack and the second stack are coupled to the second node, wherein the second transistor in the first stack is coupled to the third transistor in the first stack, and wherein the second transistor in the second stack is coupled to the third transistor in the second stack.

2. The switching circuit according to claim 1, wherein: The first transistor and the second transistor in the first stack and the third transistor and the fourth transistor in the second stack are of a first conductivity type, and The first transistor and the second transistor in the second stack and the third transistor and the fourth transistor in the first stack are of the second conductivity type.

3. The switching circuit according to claim 1 or 2, wherein: a drain of a first transistor in the first stack coupled to the first node, wherein a source of the second transistor in the first stack is coupled to a source of the third transistor in the first stack, wherein a drain of a fourth transistor in the first stack is coupled to the second node, wherein a drain of a first transistor in the second stack is coupled to the first node, wherein a source of the second transistor in the second stack is coupled to a source of the third transistor in the second stack, wherein a drain of a fourth transistor in the second stack is coupled to the second node, wherein a source of a first transistor in the first stack is coupled to a drain of a second transistor in the second stack, wherein a source of a first transistor in the second stack is coupled to a drain of a second transistor in the first stack, wherein a source of the fourth transistor in the first stack is coupled to a drain of the third transistor in the second stack, and The source of the fourth transistor in the second stack is coupled to the drain of the third transistor in the first stack.

4. The switching circuit according to claim 1 or 2, wherein: A first conductive trace coupling a first transistor in the first stack and a second transistor in the second stack crosses a second conductive trace coupling a first transistor in the second stack and a second transistor in the first stack.

5. The switch circuit according to claim 4, wherein: A third conductive trace coupling a fourth transistor in the first stack and a third transistor in the second stack crosses a fourth conductive trace coupling a fourth transistor in the second stack and a third transistor in the first stack.

6. The switching circuit according to claim 1 or 2, wherein: The first stack and the second stack are arranged offset from each other in a lateral direction.

7. The switching circuit according to claim 1 or 2, wherein: Respective voltage clamps are coupled between sources of first transistors in the first and second stacks, drains of second transistors in the first and second stacks, drains of third transistors in the first and second stacks, and sources of fourth transistors in the first and second stacks.

8. The switch circuit according to claim 1 or 2, further comprising: The control circuit is configured to supply corresponding control signals to corresponding gates of transistors in the first stack and the second stack to control the on and off states of these transistors.

9. The switch circuit according to claim 8, wherein: In order to electrically couple the first node and the second node, the control circuit is configured to: The corresponding signal levels of the corresponding control signals are adjusted to control the transistors in the first stack and the second stack to be in a conducting state.

10. The switch circuit according to claim 8, wherein: In order to electrically decouple the first node from the second node, the control circuit is configured to: The corresponding signal level of the corresponding control signal is adjusted to control the transistors in the first stack and the second stack to be in an off state.

11. The switch circuit according to claim 8, wherein: Respective resistors are coupled between respective gates of transistors in the first stack and the second stack and the control circuit.

12. The switch circuit according to claim 8, wherein: The control circuit comprises: a plurality of voltage buffers coupled to respective gates of transistors of the first conductivity type or transistors of the second conductivity type in the first stack and the second stack; and a plurality of inverting voltage buffers coupled to respective gates of the other of the transistors of the first conductivity type and the second conductivity type, The plurality of voltage buffers and the plurality of inverting voltage buffers are configured to receive a switch control signal and generate corresponding control signals for corresponding transistors based on the switch control signal.

13. The switch circuit according to claim 12, wherein: The plurality of voltage buffers and the plurality of inverting voltage buffers are configured as: receiving a first supply voltage and a second supply voltage; and A corresponding control signal having a voltage level between the voltage level of the first supply voltage and the voltage level of the second supply voltage is generated.

14. The switch circuit according to claim 8, further comprising: a third node configured to receive a DC reference voltage, wherein the third node is resistively coupled between a second transistor in the first stack and a third transistor in the first stack and between a second transistor in the second stack and a third transistor in the second stack, and wherein the control circuit comprises: a first transistor of the second conductivity type, wherein a source of the first transistor is coupled to the third node; a second transistor of a second conductivity type, wherein a drain of the second transistor of the second conductivity type is coupled to a gate of a first transistor in the first stack, and wherein a gate of the second transistor of the second conductivity type is coupled to a drain of the first transistor of the second conductivity type; a first inverting voltage buffer configured to: receive a first switch control signal at an input thereof, wherein an output of the first inverting voltage buffer is coupled to a gate of a first transistor of a second conductivity type, and wherein an input of the first inverting voltage buffer is coupled to a source of a second transistor of a second conductivity type; a first transistor of a first conductivity type, wherein a source of the first transistor of the first conductivity type is coupled to the third node; a second transistor of a first conductivity type, wherein a drain of the second transistor of the first conductivity type is coupled to a gate of a first transistor in the second stack, and wherein a gate of the second transistor of the first conductivity type is coupled to a drain of the first transistor of the first conductivity type; A second inverting voltage buffer is configured to: receive a second switch control signal at its input, wherein the output of the second inverting voltage buffer is coupled to the gate of the first transistor of the first conductivity type, wherein the input of the second inverting voltage buffer is coupled to the source of the second transistor of the first conductivity type, and wherein the first switch control signal and the second switch control signal are inverted relative to each other.

15. The switch circuit according to claim 1 or 2, wherein: Respective capacitors are coupled between respective gates and respective sources of transistors in the first stack and the second stack.

16. The switch circuit according to claim 1 or 2, wherein: Respective capacitors are coupled between respective gates and respective drains of transistors in the first stack and the second stack.

17. The switch circuit according to claim 1 or 2, further comprising: The third node is configured to: receive a DC reference voltage, The third node is resistively coupled between the second transistor in the first stack and the third transistor in the first stack and between the second transistor in the second stack and the third transistor in the second stack.

18. The switch circuit according to claim 1 or 2, wherein: The transistors in the first stack and the second stack are gate-all-around field effect transistors (GAAFETs) with nanosheets or complementary field effect transistors (CFETs) with nanosheets.

19. An attenuation circuit, comprising: a first signal path coupled between the first input node and the first output node, wherein the first signal path includes a first plurality of resistive elements; a second signal path coupled between the second input node and the second output node, wherein the second signal path includes a second plurality of resistive elements, and wherein the first input node and the second input node are configured to: receive respective ones of a first input signal and a second input signal forming a differential input signal pair; and At least one shunt path is coupled between the first signal path and the second signal path, wherein the at least one shunt path includes at least one corresponding switch circuit as described in claim 1 or 2 to selectively couple the first signal path and the second signal path.

20. The attenuation circuit of claim 19, wherein: The at least one corresponding switch circuit in the at least one shunt path is configured as: The first signal path and the second signal path are selectively coupled based on at least one corresponding switch control signal.

21. A receiver, comprising: The attenuation circuit as claimed in claim 19; a load coupled to the first output node and the second output of the attenuation circuit; and The control circuit is configured as follows: Based on target attenuation levels of the first input signal and the second input signal, coupling of the first signal path and the second signal path is controlled by the at least one corresponding switch circuit in the at least one shunt path.

22. The receiver of claim 21, wherein: The first input signal and the second input signal are radio frequency signals.

23. The receiver of claim 21, wherein: The load is one or more input buffers of an analog-to-digital converter.

24. A base station, comprising: The receiver as claimed in claim 21; and The transmitter is configured to generate a radio frequency transmission signal.

25. A mobile device, comprising: The receiver as claimed in claim 21; and The transmitter is configured to generate a radio frequency transmission signal.

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