Signal transmission circuit for performing high-speed operation and method thereof

Abstract

The invention relates to a signal transmission circuit for performing high-speed operation and a method thereof. A signal transmission circuit includes: a first latch driving circuit configured to latch a first alignment signal based on a first divided clock signal and a second divided clock signal, and to drive a first transmission signal; and a second latch driving circuit configured to latch the second alignment signal based on the second divided clock signal and the first inverted divided clock signal, and to drive the transfer signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0167542, filed on November 28, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] Some embodiments of the present disclosure relate to a signal transmission circuit that performs high - speed operations. Background art

[0004] Recently, electronic devices advantageously include low - power characteristics and high - speed operation characteristics. For low - power characteristics, the electronic device performs internal operations at a low operating voltage, and for high - speed operation characteristics, the electronic device drives and transmits signals at a high voltage level when transmitting signals. Summary of the invention

[0005] According to an embodiment of the present disclosure, a signal transmission circuit may include: a first latch driving circuit configured to latch a first alignment signal based on a first divided - clock signal and a second divided - clock signal, and drive a first transmission signal; and a second latch driving circuit configured to latch a second alignment signal based on the second divided - clock signal and a first inverted divided - clock signal, and drive a transmission signal.

[0006] According to an embodiment of the present disclosure, a signal transmission circuit may include: a latch signal generation circuit configured to latch an alignment signal based on a first divided - clock signal and a second divided - clock signal, and generate a latch signal and an inverted latch signal, the latch signal and the inverted latch signal being driven to a voltage level higher than the voltage level of the alignment signal; a pre - charge signal generation circuit configured to generate a pre - charge signal and an inverted pre - charge signal based on the latch signal, the inverted latch signal, and the second divided - clock signal; a pull - down signal generation circuit configured to generate a pull - down driving signal based on the latch signal; a pull - up signal generation circuit configured to generate a pull - up driving signal based on the inverted latch signal; and a driving circuit configured to drive a transmission signal to a voltage level higher than the voltage level of the alignment signal based on the pull - up driving signal and the pull - down driving signal.

[0007] A method includes: latching a first alignment signal based on a first divided - clock signal and a second divided - clock signal to drive a transmission signal and generate a latch signal and an inverted latch signal; generating a pre - charge signal based on the latch signal, the inverted latch signal, and the second divided - clock signal; and driving the latch signal and the inverted latch signal in response to the pre - charge signal to perform a pre - charge operation to stop driving the transmission signal. Brief description of the drawings

[0008] Figure 1It is a block diagram showing a signal transmission circuit according to an embodiment of the present disclosure.

[0009] Figure 2 It is shown Figure 1 A block diagram showing an embodiment of a first latch driving circuit of the signal transmission circuit shown.

[0010] Figure 3 It is shown Figure 2 A block diagram showing an embodiment of a first drive control circuit of the first latch driving circuit shown.

[0011] Figure 4 It is shown Figure 3 A circuit diagram showing embodiments of a latch signal generation circuit, a pull - down signal generation circuit, and a pull - up signal generation circuit shown.

[0012] Figure 5 It is according to Figure 3 A circuit diagram showing an embodiment of a pre - charge signal generation circuit shown.

[0013] Figure 6 It is shown Figure 2 A block diagram showing an embodiment of a first drive circuit of the first latch driving circuit shown.

[0014] Figure 7 A timing diagram showing the operation timing of the first latch driving circuit according to an embodiment.

[0015] Figure 8 It is shown Figure 1 A block diagram showing an embodiment of a second latch driving circuit in the signal transmission circuit shown.

[0016] Figure 9 It is shown Figure 1 A block diagram showing an embodiment of a third latch driving circuit of the signal transmission circuit shown.

[0017] Figure 10 It is shown Figure 1 A block diagram showing an embodiment of a fourth latch driving circuit of the signal transmission circuit shown. Detailed implementation mode

[0018] In the following description of the embodiments, when a parameter is referred to as "predetermined", the value of the parameter can be determined in advance when the parameter is used in a process or an algorithm. The value of the parameter can be set at the start of the process or algorithm, or can be set during the execution of the process or algorithm.

[0019] Although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another and are not intended to imply the order or quantity of the elements. Thus, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0020] When an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there may be an intermediate element. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0021] Logic "high" level and logic "low" level can be used to describe the logic levels of electrical signals. A signal at logic "high" level is different from a signal at logic "low" level. For example, when a signal at a first voltage corresponds to a signal at logic "high" level, a signal at a second voltage corresponds to a signal at logic "low" level. In an embodiment, the logic "high" level can be set to a voltage level higher than the voltage level of the logic "low" level. According to an embodiment, the logic levels of signals can be set differently or oppositely. For example, a certain signal that is at logic "high" level in one embodiment can be set to logic "low" level in another embodiment.

[0022] The term "logic bit group" can include a combination of the logic levels of the bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit group of the signal can be set differently. For example, when the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logic bit group of the signal can be set to a first logic bit group, and when the logic level of each of the two bits included in the signal is "logic low level and logic high level", the logic bit group of the signal can be set to a second logic bit group.

[0023] Various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. The description of the embodiments is for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0024] For a synchronous electronic device that operates synchronously with a clock signal, a divided clock signal generated by dividing the clock signal is used for fast signal input and output. By driving and transmitting signals at a high voltage level when inputting and outputting signals based on the divided clock signal, the synchronous electronic device can have improved high-speed operation characteristics.

[0025] Figure 1 is a block diagram showing a signal transmission circuit 10 according to an embodiment of the present disclosure.

[0026] As Figure 1 shown, the signal transmission circuit 10 includes a first latch driving circuit (LAT DRV(1)) 101, a second latch driving circuit (LAT DRV(2)) 103, a third latch driving circuit (LAT DRV(3)) 105, and a fourth latch driving circuit (LAT DRV(4)) 107.

[0027] The first latch driving circuit 101 latches a first alignment signal DATA_I based on a first divided clock signal ICLK and a second divided clock signal QCLK to drive a transmission signal D_SER. Each of the first divided clock signal ICLK and the second divided clock signal QCLK may be generated by dividing a clock signal (not shown) received, for example, from an external source by an electronic device (not shown) including the signal transmission circuit 10. Each of the first divided clock signal ICLK and the second divided clock signal QCLK may be generated as a divided-by-two clock signal. The phase of the second divided clock signal QCLK lags behind the phase of the first divided clock signal ICLK by 90°. The present disclosure is not limited to this example. The divided-by-two signal may refer to a signal having a period twice that of the clock period. The first alignment signal DATA_I may include a signal aligned and synchronized with the first divided clock signal ICLK. The first alignment signal DATA_I is generated by being latched synchronously with the first divided clock signal ICLK, but the present disclosure is not limited to this example.

[0028] The first latch driving circuit 101 latches the first alignment signal DATA_I synchronously with the first divided clock signal ICLK, and drives the transmission signal D_SER based on the result of latching the first alignment signal DATA_I. In this example, the first latch driving circuit 101 latches the first alignment signal DATA_I at a voltage level higher than the voltage level of the first alignment signal DATA_I, and drives the transmission signal D_SER to a voltage level higher than the voltage level of the first alignment signal DATA_I. In this example, the first latch driving circuit 101 pre-charges the transmission signal D_SER synchronously with the second divided clock signal QCLK. As described above, the first latch driving circuit 101 drives the transmission signal D_SER synchronously with the first divided clock signal ICLK, and pre-charges the transmission signal D_SER synchronously with the second divided clock signal QCLK. Therefore, the first latch driving circuit 101 drives the transmission signal D_SER within a unit interval according to the first divided clock signal ICLK and the second divided clock signal QCLK. In this example, the unit interval may be set to 1 / 4 period of each of the first divided clock signal ICLK and the second divided clock signal QCLK, or 1 / 2 period of each of the clock signals, but the present disclosure is not limited to this example.

[0029] The second latch driving circuit 103 latches the second alignment signal DATA_Q based on the second divided clock signal QCLK and the first inverted divided clock signal ICLKB to drive the transmission signal D_SER. The first inverted divided clock signal ICLKB is generated by inverting the first divided clock signal ICLK. The second alignment signal DATA_Q may be a signal aligned and synchronized with the second divided clock signal QCLK. The second alignment signal DATA_Q is generated by being latched synchronously with the second divided clock signal QCLK, but the present disclosure is not limited to this example. The second latch driving circuit 103 latches the second alignment signal DATA_Q synchronously with the second divided clock signal QCLK, and drives the transmission signal D_SER based on the result of latching the second alignment signal DATA_Q. In this example, the second latch driving circuit 103 latches the second alignment signal DATA_Q at a voltage level higher than the voltage level of the second alignment signal DATA_Q, and drives the transmission signal D_SER to a voltage level higher than the voltage level of the second alignment signal DATA_Q. In this example, the second latch driving circuit 103 pre-charges the transmission signal D_SER synchronously with the first inverted divided clock signal ICLKB. As described above, the second latch driving circuit 103 drives the transmission signal D_SER synchronously with the second divided clock signal QCLK, and pre-charges the transmission signal D_SER synchronously with the first inverted divided clock signal ICLKB. Therefore, the second latch driving circuit 103 drives the transmission signal D_SER within a unit interval according to the second divided clock signal QCLK and the first inverted divided clock signal ICLKB.

[0030] The third latch driving circuit 105 latches the third alignment signal DATA_IB based on the first inverted divided clock signal ICLKB and the second inverted divided clock signal QCLKB to drive the transmission signal D_SER. The second inverted divided clock signal QCLKB is generated by inverting the second divided clock signal QCLK. The third alignment signal DATA_IB may be a signal aligned and synchronized with the first inverted divided clock signal ICLKB. The third alignment signal DATA_IB is generated by being latched synchronously with the first inverted divided clock signal ICLKB, but the present disclosure is not limited to this example. The third latch driving circuit 105 latches the third alignment signal DATA_IB synchronously with the first inverted divided clock signal ICLKB, and drives the transmission signal D_SER based on the result of latching the third alignment signal DATA_IB. In this example, the third latch driving circuit 105 latches the third alignment signal DATA_IB at a voltage level higher than the voltage level of the third alignment signal DATA_IB, and drives the transmission signal D_SER to a voltage level higher than the voltage level of the third alignment signal DATA_IB. In this example, the third latch driving circuit 105 pre-charges the transmission signal D_SER synchronously with the second inverted divided clock signal QCLKB. As described above, the third latch driving circuit 105 drives the transmission signal D_SER synchronously with the first inverted divided clock signal ICLKB, and pre-charges the transmission signal D_SER synchronously with the second inverted divided clock signal QCLKB. Therefore, the third latch driving circuit 105 drives the transmission signal D_SER within a unit interval according to the first inverted divided clock signal ICLKB and the second inverted divided clock signal QCLKB.

[0031] The fourth latch driving circuit 107 latches the fourth alignment signal DATA_QB based on the second inverted divided clock signal QCLKB and the first divided clock signal ICLK to drive the transmission signal D_SER. The fourth alignment signal DATA_QB is generated by being latched synchronously with the second inverted divided clock signal QCLKB, but the present disclosure is not limited to this example. The fourth latch driving circuit 107 latches the fourth alignment signal DATA_QB synchronously with the second inverted divided clock signal QCLKB, and drives the transmission signal D_SER based on the result of latching the fourth alignment signal DATA_QB. In this example, the fourth latch driving circuit 107 latches the fourth alignment signal DATA_QB at a voltage level higher than the voltage level of the fourth alignment signal DATA_QB, and drives the transmission signal D_SER to a voltage level higher than the voltage level of the fourth alignment signal DATA_QB. In this example, the fourth latch driving circuit 107 pre-charges the transmission signal D_SER synchronously with the first divided clock signal ICLK. As described above, the fourth latch driving circuit 107 drives the transmission signal D_SER synchronously with the second inverted divided clock signal QCLKB, and pre-charges the transmission signal D_SER synchronously with the first divided clock signal ICLK. Therefore, the fourth latch driving circuit 107 drives the transmission signal D_SER within a unit interval according to the second inverted divided clock signal QCLKB and the first divided clock signal ICLK.

[0032] Figure 2 is a diagram showing Figure 1 an embodiment of the first latch driving circuit 101 shown.

[0033] As Figure 2 shown, the first latch driving circuit 101A includes a first drive control circuit (DRV CTR(1)) 111 and a first drive circuit (DRV(1)) 113.

[0034] The first drive control circuit 111 generates a first pull-up drive signal PU1 and a first pull-down drive signal PD1 based on a first divided clock signal ICLK, a second divided clock signal QCLK, and a first alignment signal DATA_I. The first drive control circuit 111 latches the first alignment signal DATA_I synchronously with the first divided clock signal ICLK to generate the first pull-up drive signal PU1 and the first pull-down drive signal PD1. The first drive control circuit 111 generates the first pull-up drive signal PU1 and the first pull-down drive signal PD1 that are selectively activated according to the logic level of the first alignment signal DATA_I. As an example, the first drive control circuit 111 generates, synchronously with the first divided clock signal ICLK, the first pull-up drive signal PU1 that is activated and the first pull-down drive signal PD1 that is deactivated when the first alignment signal DATA_I is at a logic "high" level. As another example, the first drive control circuit 111 generates, synchronously with the first divided clock signal ICLK, the first pull-up drive signal PU1 that is deactivated and the first pull-down drive signal PD1 that is activated when the first alignment signal DATA_I is at a logic "low" level.

[0035] The first drive circuit 113 is electrically connected to the first drive control circuit 111 and receives the first pull-up drive signal PU1 and the first pull-down drive signal PD1 from the first drive control circuit 111. The first drive circuit 113 drives the transmission signal D_SER based on or in response to the first pull-up drive signal PU1 and the first pull-down drive signal PD1. The first drive circuit 113 controls the driving of the transmission signal D_SER according to which one of the first pull-up drive signal PU1 and the first pull-down drive signal PD1 is activated. As an example, when the first alignment signal DATA_I is at a logic "high" level and the activated first pull-up drive signal PU1 and the deactivated first pull-down drive signal PD1 are generated, the first drive circuit 113 drives the transmission signal D_SER to a voltage level higher than the voltage level of the first alignment signal DATA_I (e.g., the power supply voltage VDD). As another example, when the first alignment signal DATA_I is at a logic "low" level and the deactivated first pull-up drive signal PU1 and the activated first pull-down drive signal PD1 are generated, the first drive circuit 113 can drive the transmission signal D_SER to the ground voltage.

[0036] Figure 3 is a diagram showing Figure 2 an embodiment of the first drive control circuit 111 shown.

[0037] As Figure 3As shown, the first drive control circuit 111A includes a latch signal generation circuit (LAT GEN) 121, a precharge signal generation circuit (PCG GEN) 123, a pull-down signal generation circuit (PD GEN) 125, and a pull-up signal generation circuit (PU GEN) 127.

[0038] The latch signal generation circuit 121 latches the first alignment signal DATA_I based on the first divided clock signal ICLK and the second divided clock signal QCLK, and generates a latch signal LAT and an inverted latch signal LATB. As an example, when latching the first alignment signal DATA_I with a logic "high" level based on the first divided clock ICLK and the second divided clock signal QCLK, the latch signal generation circuit 121 generates a latch signal LAT driven to a voltage level higher than the voltage level of the first alignment signal DATA_I and an inverted latch signal LATB driven to the ground voltage. As another example, when latching the first alignment signal DATA_I with a logic "low" level based on the first divided clock signal ICLK and the second divided clock signal QCLK, the latch signal generation circuit 121 generates a latch signal LAT driven to the ground voltage and an inverted latch signal LATB driven to a voltage level higher than the voltage level of the first alignment signal DATA_I. The voltage levels of each of the latch signal LAT and the inverted latch signal LATB generated according to the first alignment signal DATA_I latched in the latch signal generation circuit 121 can be set differently according to embodiments.

[0039] The precharge signal generation circuit 123 is electrically connected to the latch signal generation circuit 121, and receives the latch signal LAT and the inverted latch signal LATB from the latch signal generation circuit 121. The precharge signal generation circuit 123 generates a precharge signal PCG and an inverted precharge signal PCGB based on the second divided clock signal QCLK, the latch signal LAT, and the inverted latch signal LATB. In a state where the logic level of the latch signal LAT is inverted with respect to the logic level of the inverted latch signal LATB, the precharge signal generation circuit 123 generates a precharge signal PCG and an inverted precharge signal PCGB that are both activated for the precharge operation in synchronization with the second divided clock signal QCLK. The state where the latch signal LAT and the inverted latch signal LATB have inverted logic levels can indicate the state where the latch signal generation circuit 121 latches the first alignment signal DATA_I in synchronization with the first divided clock signal ICLK. In addition, the precharge signal PCG and the inverted precharge signal PCGB are activated at logic levels that are inverted with respect to each other. In other words, the logic level of the precharge signal PCG is inverted with respect to the logic level of the inverted precharge signal PCGB, and the logic levels at which the precharge signal PCG and the inverted precharge signal PCGB are activated can be set in various ways according to embodiments.

[0040] The pull - down signal generation circuit 125 is electrically connected to the latch signal generation circuit 121 to receive the latch signal LAT from the latch signal generation circuit 121. The pull - down signal generation circuit 125 generates a first pull - down drive signal PD1 based on the latch signal LAT. The pull - down signal generation circuit 125 may be implemented as inverting the latch signal LAT to generate the first pull - down drive signal PD1, but the present disclosure is not limited to this example. As an example, when the first alignment signal DATA_I is at a logic "low" level and the latch signal LAT is generated at a logic "low" level, the pull - down signal generation circuit 125 generates the first pull - down drive signal PD1 that is activated at a logic "high" level.

[0041] The pull - up signal generation circuit 127 is electrically connected to the latch signal generation circuit 121 and receives the inverted latch signal LATB from the latch signal generation circuit 121. The pull - up signal generation circuit 127 generates a first pull - up drive signal PU1 based on the inverted latch signal LATB. The pull - up signal generation circuit 127 buffers the inverted latch signal LATB to generate the first pull - up drive signal PU1, but the present disclosure is not limited to this example. As an example, when the first alignment signal DATA_I is at a logic "high" level and the inverted latch signal LATB is generated at a logic "low" level, the pull - up signal generation circuit 127 generates the first pull - up drive signal PU1 that is activated at a logic "low" level.

[0042] Figure 4 is a diagram showing Figure 3 an embodiment of the illustrated latch signal generation circuit 121, pull - down signal generation circuit 125, and pull - up signal generation circuit 127.

[0043] The latch signal generation circuit 121A latches the first alignment signal DATA_I based on the first divided clock signal ICLK and the second divided clock signal QCLK, and generates a latch signal LAT and an inverted latch signal LATB. As an example, when the second divided clock signal QCLK is at a logic "low" level, in the case where the first divided clock signal ICLK transitions from a logic "low" level to a logic "high" level (hereinafter referred to as "rising edge"), the latch signal generation circuit 121A synchronously latches the first alignment signal DATA_I at a logic "high" level to generate a latch signal LAT driven to the power supply voltage VDD and an inverted latch signal LATB driven to the ground voltage. As another example, when the second divided clock signal QCLK is at a logic "low" level, the latch signal generation circuit 121A synchronously latches the first alignment signal DATA_I at a logic "low" level with the rising edge of the first divided clock signal ICLK to generate a latch signal LAT driven to the ground voltage and an inverted latch signal LATB driven to the power supply voltage VDD. The latch signal generation circuit 121A includes PMOS transistors 121_1 and 121_2 that are turned on based on the precharge signal PCG and PMOS transistors 121_3 and 121_4 that are turned on based on the inverted precharge signal PCGB. When the precharge operation is not performed, the PMOS transistors 121_1 and 121_2 are turned on to drive the latch signal LAT and the inverted latch signal LATB to the power supply voltage VDD. The PMOS transistors 121_3 and 121_4 drive the latch signal LAT and the inverted latch signal LATB to the power supply voltage VDD during the precharge operation. The PMOS transistors 121_1 and 121_2 can be implemented to have a weaker driving force than the PMOS transistors 121_3 and 121_4, so that the latch signal generation circuit 121 latches the first alignment signal DATA_I based on the first divided clock signal ICLK and the second divided clock signal QCLK to drive the latch signal LAT and the inverted latch signal LATB to different voltage levels when the precharge operation is not performed.

[0044] The pull - down signal generation circuit 125A inversely buffers the latch signal LAT to generate a first pull - down drive signal PD1. When the first alignment signal DATA_I is at a logic "low" level and the latch signal LAT is generated at a logic "low" level, the pull - down signal generation circuit 125A generates a first pull - down drive signal PD1 that is activated at a logic "high" level.

[0045] The pull-up signal generation circuit 127A buffers the inverted latch signal LATB to generate a first pull-up drive signal PU1. When the first alignment signal DATA_I is at a logic "high" level and the inverted latch signal LATB is generated at a logic "low" level, the pull-up signal generation circuit 127A generates the first pull-up drive signal PU1 that is activated at a logic "low" level.

[0046] Figure 5 is according to Figure 3 The circuit diagram of an embodiment of the precharge signal generation circuit 123 shown.

[0047] As Figure 5 shown, the precharge signal generation circuit 123A includes a NAND gate 131, a clock signal buffer circuit 132, a PMOS transistor 133, NMOS transistors 135 and 137, and an inverter 139. The NAND gate 131 receives the latch signal LAT and the inverted latch signal LATB and performs a logic "NAND" operation to generate a composite latch signal LAT_S. When both the latch signal LAT and the inverted latch signal LATB are driven to the power supply voltage VDD during the precharge operation, the NAND gate 131 generates the composite latch signal LAT_S that is activated at a logic "low" level. In a state where the latch signal LAT and the inverted latch signal LATB are driven at different voltage levels, the NAND gate 131 generates the composite latch signal LAT_S that is deactivated at a logic "high" level. The clock signal buffer circuit 132 buffers the second divided clock signal QCLK to generate a buffered clock signal BCLK. The PMOS transistor 133 conducts based on the composite latch signal LAT_S. When both the latch signal LAT and the inverted latch signal LATB are driven to the power supply voltage VDD and the composite latch signal LAT_S is activated at a logic "low" level, the PMOS transistor 133 conducts to drive the inverted precharge signal PCGB to the power supply voltage VDD. The NMOS transistor 135 conducts based on the buffered clock signal BCLK. The NMOS transistor 135 conducts in synchronization with the rising edge of the second divided clock signal QCLK. The NMOS transistor 137 conducts based on the composite latch signal LAT_S. When the latch signal LAT and the inverted latch signal LATB are driven to different voltage levels and the composite latch signal LAT_S is deactivated at a logic "high" level, the NMOS transistor 137 conducts. When the NMOS transistors 135 and 137 conduct, the inverted precharge signal PCGB is driven to the ground voltage. The inverter 139 inverts and buffers the inverted precharge signal PCGB to generate the precharge signal PCG.

[0048] The precharge signal generation circuit 123A generates an inverted precharge signal PCGB and inverts and buffers the inverted precharge signal PCGB to generate a precharge signal PCG that is activated at a logic "high" level. The inverted precharge signal PCGB is driven to the ground voltage by NMOS transistors 135 and 137 that are turned on in synchronization with the rising edge of the second divided clock signal QCLK, and is activated at a logic "low" level when the logic level of the latch signal LAT is inverted or opposite to the logic level of the inverted latch signal LATB. During the precharge operation, the precharge signal generation circuit 123A generates an inverted precharge signal PCGB and inverts and buffers the inverted precharge signal PCGB to generate a precharge signal PCG that is deactivated at a logic "low" level. The inverted precharge signal PCGB is driven to the power supply voltage VDD by a PMOS transistor 133 that is turned on by receiving a combined latch signal LAT_S that is activated at a logic "low" level when both the latch signal LAT and the inverted latch signal LATB are driven to the power supply voltage VDD.

[0049] Figure 6 is a diagram showing Figure 2 an embodiment of the first drive circuit 113 shown.

[0050] As Figure 6 shown, the first drive circuit 113 includes a PMOS transistor 141 and an NMOS transistor 143. The PMOS transistor 141 is turned on based on a first pull-up drive signal PU1. The PMOS transistor 141 receives the first pull-up drive signal PU1 that is activated at a logic "low" level when the inverted latch signal LATB is generated at a logic "low" level while the first alignment signal DATA_I is at a logic "high". When receiving the first pull-up drive signal PU1 that is activated at a logic "low" level, the PMOS transistor 141 is turned on to drive the transmission signal D_SER to the power supply voltage VDD. The NMOS transistor 143 is turned on based on a first pull-down drive signal PD1. The NMOS transistor 143 receives the first pull-down drive signal PD1 that is activated at a logic "high" level when the latch signal LAT is generated at a logic "low" level while the first alignment signal DATA_I is at a logic "low". When receiving the first pull-down drive signal PD1 that is activated at a logic "high" level, the NMOS transistor 143 is turned on to drive the transmission signal D_SER to the ground voltage.

[0051] Figure 7 is a timing diagram showing the operation timing of the first latch drive circuit 101A according to Figure 2 the embodiment in.

[0052] As Figure 4 and Figure 7As shown, the latch signal generation circuit 121A latches the first alignment signal DATA_I at the logic "high" level in synchronization with the rising edge of the first divided clock signal ICLK at 701, to generate a latch signal LAT driven to the power supply voltage VDD and an inverted latch signal LATB driven to the ground voltage. When the latch signal LAT is generated at the logic "high" level, the pull-down signal generation circuit 125A generates a first pull-down drive signal PD1 deactivated at the logic "low" level, and when the inverted latch signal LATB is generated at the logic "low" level, the pull-down signal generation circuit 125A generates a first pull-up drive signal PU1 activated at the logic "low" level.

[0053] As Figure 6 and Figure 7 shown, at 703, the first drive circuit 113A receives the first pull-down drive signal PD1 deactivated at the logic "low" level and the first pull-up drive signal PU1 activated at the logic "low" level, to drive the transmission signal D_SER to the power supply voltage VDD.

[0054] As Figure 5 and Figure 7 shown, at 705, in a state where the latch signal LAT is generated at the logic "high" level and the inverted latch signal LATB is generated at the logic "low" level, the precharge signal generation circuit 123A generates an inverted precharge signal PCGB activated at the logic "low" level and a precharge signal PCG activated at the logic "high" level in synchronization with the rising edge of the second divided signal QCLK.

[0055] As Figure 4 and Figure 7 shown, at 707, when receiving the inverted precharge signal PCGB activated at the logic "low" level and the precharge signal PCG activated at the logic "high" level, the latch signal generation circuit 121A drives both the latch signal LAT and the inverted latch signal LATB to the power supply voltage VDD for precharging operation. When the latch signal LAT is driven to the power supply voltage VDD, the latch signal generation circuit 121A generates a first pull-down drive signal PD1 driven to the logic "low" level, and when the inverted latch signal LATB is driven to the power supply voltage VDD, the latch signal generation circuit 121A generates a first pull-up drive signal PU1 driven to the logic "low" level.

[0056] As Figure 6 and Figure 7 shown, at 709, the first drive circuit 113A receives the first pull-down drive signal PD1 deactivated at the logic "low" level and the first pull-up drive signal PU1 deactivated at the logic "high" level to perform a precharging operation to stop driving the transmission signal D_SER.

[0057] As described above, the first latch driving circuit 101A latches the first alignment signal DATA_I aligned with the first divided clock signal ICLK at the power supply voltage VDD, and drives and transmits the first alignment signal DATA_I as a serial transmission signal D_SER, thereby improving the high-speed operation characteristics. In addition, the first latch driving circuit 101A can latch the first alignment signal DATA_I (at the power supply voltage VDD) at a voltage level higher than the voltage level of the first alignment signal DATA_I, and can drive the transmission signal D_SER to the power supply voltage VDD. Therefore, when latching the first alignment signal DATA_I at 0V to 800mV to generate a transmission signal D_SER of 0V to 1.2V, no separate level shifter is required, thereby reducing the layout area.

[0058] Figure 8 is a diagram showing Figure 1 an embodiment of the second latch driving circuit 103 shown.

[0059] As Figure 8 shown, the second latch driving circuit 103A includes a second driving control circuit (DRV CTR(2)) 151 and a second driving circuit (DRV(2)) 153.

[0060] The second driving control circuit 151 generates a second pull-up driving signal PU2 and a second pull-down driving signal PD2 based on the second divided clock signal QCLK, the first inverted divided clock signal ICLKB, and the second alignment signal DATA_Q. The second driving control circuit 151 latches the second alignment signal DATA_Q synchronously with the second divided clock signal QCLK to generate the second pull-up driving signal PU2 and the second pull-down driving signal PD2. The second driving control circuit 151 generates the second pull-up driving signal PU2 and the second pull-down driving signal PD2 that are selectively activated according to the logic level of the second alignment signal DATA_Q. As an example, the second driving control circuit 151 generates, synchronously with the second divided clock signal QCLK, a second pull-up driving signal PU2 that is activated when the second alignment signal DATA_Q is at a logic "high" level and a second pull-down driving signal PD2 that is deactivated. As another example, the second driving control circuit 151 generates, synchronously with the second divided clock signal QCLK, a second pull-up driving signal PU2 that is deactivated when the second alignment signal DATA_Q is at a logic "low" level and a second pull-down driving signal PD2 that is activated.

[0061] The second driving circuit 153 is electrically connected to the second driving control circuit 151, and receives a second pull-up driving signal PU2 and a second pull-down driving signal PD2 from the second driving control circuit 151. The second driving circuit 153 drives the transmission signal D_SER based on the second pull-up driving signal PU2 and the second pull-down driving signal PD2. The second driving circuit 153 controls the driving of the transmission signal D_SER according to which one of the second pull-up driving signal PU2 and the second pull-down driving signal PD2 is activated. As an example, when the second alignment signal DATA_Q is at a logic "high" level and an activated second pull-up driving signal PU2 and a deactivated second pull-down driving signal PD2 are generated, the second driving circuit 153 drives the transmission signal D_SER to the power supply voltage VDD. As another example, when the second alignment signal DATA_Q is at a logic "low" level and a deactivated second pull-up driving signal PU2 and an activated second pull-down driving signal PD2 are generated, the second driving circuit 153 drives the transmission signal D_SER to the ground voltage.

[0062] As described above, the second latch driving circuit 103A latches the second alignment signal DATA_Q synchronized with the second divided clock signal QCLK at the power supply voltage VDD, and drives and transmits the second alignment signal DATA_Q as a serial transmission signal D_SER, thereby improving the high-speed operation characteristics. In addition, the second latch driving circuit 103A can latch the second alignment signal DATA_Q (at the power supply voltage VDD) at a voltage level higher than the voltage level of the second alignment signal DATA_Q, and can drive the transmission signal D_SER to the power supply voltage VDD. Therefore, when latching the second alignment signal DATA_Q to generate the transmission signal D_SER, a separate level shifter is not required, thereby reducing the layout area.

[0063] Figure 9 is a diagram showing Figure 1 a block diagram of an embodiment of the third latch driving circuit 105 shown.

[0064] As Figure 9 shown, the third latch driving circuit 105A includes a third driving control circuit (DRV CTR(3)) 161 and a third driving circuit (DRV(3)) 163.

[0065] The third driving control circuit 161 generates a third pull-up driving signal PU3 and a third pull-down driving signal PD3 based on a first inverted divided clock signal ICLKB, a second inverted divided clock signal QCLKB, and a third alignment signal DATA_IB. The third driving control circuit 161 latches the third alignment signal DATA_IB synchronously with the first inverted divided clock signal ICLKB to generate the third pull-up driving signal PU3 and the third pull-down driving signal PD3. The third driving control circuit 161 generates the third pull-up driving signal PU3 and the third pull-down driving signal PD3 that are selectively activated according to the logic level of the third alignment signal DATA_IB. As an example, the third driving control circuit 161 generates, synchronously with the first inverted divided clock signal ICLKB, the third pull-up driving signal PU3 that is activated and the third pull-down driving signal PD3 that is deactivated when the third alignment signal DATA_IB is at a logic "high" level. As another example, the third driving control circuit 161 generates, synchronously with the first inverted divided clock signal ICLKB, the third pull-up driving signal PU3 that is deactivated and the third pull-down driving signal PD3 that is activated when the third alignment signal DATA_IB is at a logic "low" level.

[0066] The third driving circuit 163 is electrically connected to the third driving control circuit 161 and receives the third pull-up driving signal PU3 and the third pull-down driving signal PD3 from the third driving control circuit 161. The third driving circuit 163 drives a transmission signal D_SER based on the third pull-up driving signal PU3 and the third pull-down driving signal PD3. The third driving circuit 163 controls the driving of the transmission signal D_SER according to which one of the third pull-up driving signal PU3 and the third pull-down driving signal PD3 is activated. As an example, when the third alignment signal DATA_IB is at a logic "high" level and the activated third pull-up driving signal PU3 and the deactivated third pull-down driving signal PD3 are generated, the third driving circuit 163 drives the transmission signal D_SER to a power supply voltage VDD. As another example, when the third alignment signal DATA_IB is at a logic "low" level and the deactivated third pull-up driving signal PU3 and the activated third pull-down driving signal PD3 are generated, the third driving circuit 163 drives the transmission signal D_SER to a ground voltage.

[0067] As described above, the third latch driving circuit 105A latches the third alignment signal DATA_IB synchronized with the first inverted divided clock signal ICLKB at the power supply voltage VDD, and drives and transmits the latched third alignment signal DATA_IB as a serial transmission signal D_SER, thereby improving the high-speed operation characteristics. In addition, the third latch driving circuit 105A can latch the third alignment signal DATA_IB (at the power supply voltage VDD) at a voltage level higher than the voltage level of the third alignment signal DATA_IB, and can drive the transmission signal D_SER to the power supply voltage VDD. Therefore, when latching the third alignment signal DATA_IB to generate the transmission signal D_SER, a separate level shifter is not required, thereby reducing the layout area.

[0068] Figure 10 is a diagram showing Figure 1 an embodiment of the fourth latch driving circuit 107 shown.

[0069] As Figure 10 shown, the fourth latch driving circuit 107A includes a fourth driving control circuit (DRV CTR(4)) 171 and a fourth driving circuit (DRV(4)) 173.

[0070] The fourth driving control circuit 171 generates a fourth pull-up driving signal PU4 and a fourth pull-down driving signal PD4 based on the second inverted divided clock signal QCLKB, the first divided clock signal ICLK, and the fourth alignment signal DATA_QB. The fourth driving control circuit 171 latches the fourth alignment signal DATA_QB synchronously with the second inverted divided clock signal QCLKB to generate the fourth pull-up driving signal PU4 and the fourth pull-down driving signal PD4. The fourth driving control circuit 171 generates the fourth pull-up driving signal PU4 and the fourth pull-down driving signal PD4 that are selectively activated according to the logic level of the fourth alignment signal DATA_QB. As an example, the fourth driving control circuit 171 generates, synchronously with the second inverted divided clock signal QCLKB, a fourth pull-up driving signal PU4 that is activated when the fourth alignment signal DATA_QB is at a logic "high" level and a fourth pull-down driving signal PD4 that is deactivated. As another example, the fourth driving control circuit 171 generates, synchronously with the second inverted divided clock signal QCLKB, a fourth pull-up driving signal PU4 that is deactivated when the fourth alignment signal DATA_QB is at a logic "low" level and a fourth pull-down driving signal PD4 that is activated.

[0071] The fourth driving circuit 173 is electrically connected to the fourth driving control circuit 171 and receives a fourth pull-up driving signal PU4 and a fourth pull-down driving signal PD4 from the fourth driving control circuit 171. The fourth driving circuit 173 drives the transmission signal D_SER based on the fourth pull-up driving signal PU4 and the fourth pull-down driving signal PD4. The fourth driving circuit 173 controls the driving of the transmission signal D_SER according to which one of the fourth pull-up driving signal PU4 and the fourth pull-down driving signal PD4 is activated. As an example, when the fourth alignment signal DATA_QB is at a logic "high" level and an activated fourth pull-up driving signal PU4 and a deactivated fourth pull-down driving signal PD4 are generated, the fourth driving circuit 173 drives the transmission signal D_SER to the power supply voltage VDD. As another example, when the fourth alignment signal DATA_QB is at a logic "low" level and a deactivated fourth pull-up driving signal PU4 and an activated pull-down driving signal PD4 are generated, the fourth driving circuit 173 drives the transmission signal D_SER to the ground voltage.

[0072] As described above, the fourth latch driving circuit 107A latches the fourth alignment signal DATA_QB synchronized with the second inverted divided clock signal QCLKB at the power supply voltage VDD, and drives and transmits the latched fourth alignment signal DATA_QB as a serial transmission signal D_SER, thereby improving the high-speed operation characteristics. In addition, the fourth latch driving circuit 107A can latch the fourth alignment signal DATA_QB (at the power supply voltage VDD) at a voltage level higher than the voltage level of the fourth alignment signal DATA_QB, and can drive the transmission signal D_SER to the power supply voltage VDD. Therefore, when latching the fourth alignment signal DATA_QB to generate the transmission signal D_SER, a separate level shifter is not required, thereby reducing the layout area.

[0073] The concept is disclosed in combination with the various embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but rather from an illustrative perspective. The scope of the present disclosure is not limited to the above description, and all distinguishing features within the equivalent scope should be construed as being included in the present disclosure.

Claims

1. A signal transmission circuit, comprising: A first latch driving circuit, which: latches the first alignment signal based on the first frequency-divided clock signal and the second frequency-divided clock signal, and drives the transmission signal; and The second latch driving circuit latches a second alignment signal based on the second frequency-divided clock signal and the first inverted frequency-divided clock signal, and drives the transmission signal.

2. The signal transmission circuit according to claim 1, wherein: The first latch driving circuit receives the second frequency-divided clock signal, and a phase of the second frequency-divided clock signal lags behind a phase of the first frequency-divided clock signal by 90°.

3. The signal transmission circuit according to claim 1, wherein: The first latch driving circuit receives the first alignment signal, which is synchronously aligned with the first frequency-divided clock signal.

4. The signal transmission circuit according to claim 1, wherein: The first latch driving circuit latches the first alignment signal in synchronization with the first frequency-divided clock signal, and drives the transmission signal based on a result of latching the first alignment signal.

5. The signal transmission circuit according to claim 1, wherein: The first latch driving circuit precharges the transmission signal in synchronization with the second frequency-divided clock signal.

6. The signal transmission circuit according to claim 1, wherein: The first latch driving circuit latches the first alignment signal at a voltage level higher than a voltage level of the first alignment signal in synchronization with the first frequency-divided clock signal, and drives the transmission signal to a voltage level higher than the voltage level of the first alignment signal based on a result of latching the first alignment signal.

7. The signal transmission circuit according to claim 1, wherein: The first latch driving circuit comprises: a driving control circuit, which: latches the first alignment signal synchronously with the first frequency-divided clock signal to generate a first pull-up driving signal and a first pull-down driving signal; and A driving circuit drives the transmission signal based on the first pull-up driving signal and the first pull-down driving signal.

8. The signal transmission circuit according to claim 7, wherein: The driving control circuit generates the first pull-up driving signal and the first pull-down driving signal which are selectively activated according to a logic level of the first alignment signal.

9. The signal transmission circuit according to claim 7, wherein: The driving circuit: driving the transmission signal to a power supply voltage according to the first pull-up driving signal activated when the first alignment signal is at a first logic level, and The transmission signal is driven to a ground voltage according to the first pull-down driving signal activated when the first alignment signal is at a second logic level.

10. The signal transmission circuit according to claim 7, wherein: The drive control circuit comprises: a latch signal generating circuit, which: latches the first alignment signal based on the first frequency-divided clock signal and the second frequency-divided clock signal, and generates a latch signal and an inverted latch signal; A precharge signal generating circuit, which generates a precharge signal and an inverted precharge signal based on the latch signal, the inverted latch signal and the second frequency-divided clock signal; a pull-down signal generating circuit, which: generates the first pull-down driving signal based on the latch signal; and A pull-up signal generating circuit generates the first pull-up driving signal based on the inverted latch signal.

11. The signal transmission circuit according to claim 10, wherein: The latch signal generating circuit generates the latch signal and the inverted latch signal in synchronization with the first frequency-divided clock signal, and logic levels of the latch signal and the inverted latch signal depend on the first alignment signal.

12. The signal transmission circuit according to claim 10, wherein: The pre-charge signal generating circuit generates the pre-charge signal and the inverted pre-charge signal synchronously with the second divided clock signal when the logic level of the latch signal is inverted relative to the logic level of the inverted latch signal, and both the pre-charge signal and the inverted pre-charge signal are activated for pre-charge operation.

13. The signal transmission circuit according to claim 1, wherein: The second latch driving circuit receives the first inverted frequency-divided clock signal generated by inverting the first frequency-divided clock signal.

14. The signal transmission circuit according to claim 1, wherein: The second latch driving circuit receives the second alignment signal aligned in synchronization with the second frequency-divided clock signal.

15. The signal transmission circuit according to claim 1, wherein: The second latch driving circuit: latching the second alignment signal in synchronization with the second frequency-divided clock signal, and driving the transmission signal based on a result of latching the second alignment signal, and The transmission signal is precharged in synchronization with the first inverted frequency-divided clock signal.

16. The signal transmission circuit according to claim 1, wherein: The second latch driving circuit: latches the second alignment signal at a voltage level higher than the voltage level of the second alignment signal in synchronization with the second divided clock signal; and drives the transmission signal to a voltage level higher than the voltage level of the second alignment signal based on the result of latching the second alignment signal.

17. The signal transmission circuit according to claim 1, wherein: The second latch driving circuit comprises: a driving control circuit that: latches the second alignment signal in synchronization with the second frequency-divided clock signal to generate a second pull-up driving signal and a second pull-down driving signal; and A driving circuit drives the transmission signal based on the second pull-up driving signal and the second pull-down driving signal.

18. A signal transmission circuit, comprising: a latch signal generating circuit that: latches the alignment signal based on the first frequency-divided clock signal and the second frequency-divided clock signal, and generates a latch signal and an inverted latch signal, the latch signal and the inverted latch signal being driven to a voltage level higher than a voltage level of the alignment signal; A precharge signal generating circuit, which: generates a precharge signal and an inverted precharge signal based on the latch signal, the inverted latch signal and the second frequency-divided clock signal; A pull-down signal generating circuit, which: generates a pull-down driving signal based on the latch signal; a pull-up signal generating circuit, which: generates a pull-up driving signal based on the inverted latch signal; and A driving circuit drives a transmission signal to a voltage level higher than a voltage level of the alignment signal based on the pull-up driving signal and the pull-down driving signal.

19. The signal transmission circuit according to claim 18, wherein: The latch signal generating circuit generates the latch signal and the inverted latch signal in synchronization with the first frequency-divided clock signal, and logic levels of the latch signal and the inverted latch signal depend on the alignment signal.

20. The signal transmission circuit according to claim 18, wherein: The pre-charge signal generating circuit generates the pre-charge signal and the inverted pre-charge signal synchronously with the second divided clock signal when the logic level of the latch signal is inverted relative to the logic level of the inverted latch signal, and both the pre-charge signal and the inverted pre-charge signal are activated for pre-charge operation.

21. A method comprising: latching the first alignment signal based on the first frequency-divided clock signal and the second frequency-divided clock signal to drive the transmission signal and generate a latch signal and an inverted latch signal; generating a precharge signal based on the latch signal, the inverted latch signal and the second frequency-divided clock signal; as well as The latch signal is driven in response to the precharge signal, the inverted latch signal is driven to perform a precharge operation to stop driving the transmission signal.

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