Output port circuit, integrated chip and electronic equipment
By introducing a specific transistor structure into the output port circuit, the reverse leakage problem of conventional integrated circuit output ports when the power supply is not powered on is solved, and the stability and security of the output port are achieved.
Patent Information
- Application Number
- CN202311603457.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-28
- Publication Date
- 2025-05-30
AI Technical Summary
The output port of a conventional integrated circuit is prone to reverse leakage when the power supply voltage is not powered on.
By introducing three devices, a second switching transistor, a second control transistor and a third control transistor into the output port circuit, it is ensured that when the output port is powered on and the power supply voltage is not powered on, the output port cannot drain the power supply voltage or floor through these transistors.
It effectively avoids the problem of reverse leakage and ensures the stability and safety of the output port under different power supply states.
Smart Images
Figure CN120074502A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to an output port circuit, an integrated chip, and an electronic device. Background Art
[0002] The output port circuit of a conventional integrated circuit is as Figure 1 shown. Din is an input signal, and Enable is an enable control signal. When Enable = 1, the output port Out is in a high-impedance state; when Enable is 0, the output ends of the NOR and NAND are equal to the inversion of the input signal Din.
[0003] In some application environments, the output port Out powers on prior to the power supply voltage VDD. Since the doping type of the drain end of the first PMOS transistor P1 is P-type and the doping type of the substrate end is N-type, there is a parasitic diode between the drain end and the substrate end of the first PMOS transistor P1. The P end of this parasitic diode is connected to the drain end of the first PMOS transistor P1, and the N end of the diode is connected to the substrate end of the first PMOS transistor P1. The output end Out will sink current to the power supply voltage VDD through the parasitic diode from the drain end to the substrate end of the first PMOS transistor P1, that is, reverse leakage occurs.
[0004] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background technology of this invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of the present invention is to provide an output port circuit, an integrated chip, and an electronic device to solve the problem of output port leakage.
[0006] To solve the above technical problems, the present invention provides an output port circuit, including: an inverter, a NAND gate, a first control transistor, a second control transistor, a third control transistor, and a second switch transistor;
[0007] Providing an enable control signal and an input signal, the input end of the inverter is connected to the enable control signal, the output end of the inverter is connected to the first input end of the NAND gate, the output end of the inverter is also connected to the gates of the second switch transistor and the second control transistor, the input signal is connected to the second input end of the NAND gate, the output end of the NAND gate is connected to the gate of the first control transistor, and the second pole of the first control transistor is connected to the output port;
[0008] The second poles of the second control transistor and the second switching transistor are interconnected and connected to the gate of the third control transistor. The first pole of the second switching transistor is grounded. The first pole of the second control transistor is connected to a first node, which is also connected to the first pole of the third control transistor. The second pole of the third control transistor is connected to a power supply voltage.
[0009] Preferably, it further includes a NOR gate and a first switching transistor. The first input terminal and the second input terminal of the NOR gate are respectively connected to the enable control signal and the input signal. The output terminal of the NOR gate is interconnected with the gate of the first switching transistor. The first pole of the first switching transistor is grounded, and the second pole is connected to the output port.
[0010] Preferably, the first switching transistor is an NMOS transistor.
[0011] Preferably, the first control transistor is a PMOS transistor.
[0012] Preferably, the polarities of the second switching transistor and the second control transistor are opposite.
[0013] Preferably, the second switching transistor is an NMOS transistor and the second control transistor is a PMOS transistor.
[0014] Preferably, the third control transistor has the same polarity as the first control transistor.
[0015] Preferably, the third control transistor is a PMOS transistor.
[0016] The present invention also provides an integrated chip that employs the output port circuit as described above.
[0017] The present invention also provides an electronic device that employs the output port circuit as described above.
[0018] In the output port circuit provided by the present invention, by providing three devices, namely a second switching transistor, a second control transistor, and a third control transistor, when the output port is powered on and the power supply voltage is not powered on, the output port cannot leak electricity to the power supply voltage through the first control transistor and the third control transistor, nor can it leak electricity to the ground through the second switching transistor. Therefore, there is no leakage path, thus being able to solve the problem of reverse leakage.
[0019] The integrated chip and the electronic device provided by the present invention belong to the same inventive concept as the output port circuit provided by the present invention. Therefore, the integrated chip and the electronic device provided by the present invention at least have all the advantages of the output port circuit provided by the present invention, which will not be elaborated herein. The second poles of the second control transistor and the second switching transistor are interconnected and connected to the gate of the third control transistor. The first pole of the second switching transistor is grounded. The first pole of the second control transistor is connected to the first node, and the first node is also connected to the first pole of the third control transistor. The second pole of the third control transistor is connected to the power supply voltage. Further, when the output port is powered on and the power supply voltage is not powered on, the output port cannot leak electricity to the power supply voltage through the first control transistor and the third control transistor, nor can it leak electricity to the ground through the second switching transistor. Therefore, there is no leakage path, thus solving the problem of reverse leakage. Description of the Drawings
[0020] Figure 1 is a circuit diagram of the output port circuit of a conventional integrated circuit;
[0021] Figure 2 is a circuit diagram of the output port circuit provided by an embodiment of the present invention. Detailed Embodiments
[0022] The following further elaborates on the output port circuit, integrated chip, and electronic device proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used between different drawings to represent the same part or parts with the same function, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0023] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.
[0024] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0025] The inventors' research found that for a conventional output port circuit as Figure 1 shown, when the output port Out is powered on first and the power supply voltage VDD is not powered on, reverse conduction, that is, reverse leakage, will occur.
[0026] Among them, the working logic of the output port Out of the integrated circuit as Figure 1 shown is roughly as follows: when the enable input signal Enable = 1, the output terminal of the NOR gate (i.e., the gate voltage of the first NMOS transistor N1) is 0, the first NMOS transistor N1 is cut off, the output terminal of the NAND gate (the gate voltage of the first PMOS transistor P1) is the power supply voltage VDD, and the first PMOS transistor P1 is also cut off, and the output port Out is in a high-impedance state; when Enable = 0, the output terminals of the NOR gate and the NAND gate (i.e., the gates of the first PMOS transistor P1 and the first NMOS transistor N1) are equal to the inverted input signal Din. If the input signal Din = 1, the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are both 0, the first NMOS transistor N1 is cut off, the first PMOS transistor P1 is conducting, and the output port Out outputs the power supply voltage VDD. If the input signal Din = 0, the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are both 1, the first NMOS transistor N1 is conducting, the first PMOS transistor P1 is cut off, and the output port Out outputs 0.
[0027] Based on this, the core idea of the present invention is that by setting three devices, namely the second switching transistor N2, the second control transistor P2, and the third control transistor P3, when the output port Out is powered on and the power supply voltage VDD is not powered on, the output port Out cannot leak current to the power supply voltage VDD through the first control transistor P1 and the third control transistor P3, nor can it leak current to the ground Gnd through the second switching transistor N2. Therefore, there is no leakage path, and thus the problem of reverse leakage can be solved.
[0028] Specifically, please refer to Figure 2 , which is a schematic diagram of an embodiment of the present invention. As Figure 2 shown, an output port circuit includes: an inverter INV, a NAND gate NAND, a first control transistor P1, a second control transistor P2, a third control transistor P3, and a second switching transistor N2.
[0029] An enable control signal Enable and an input signal Din are provided. The input terminal of the inverter INV is connected to the enable control signal Enable. The output terminal of the inverter INV is connected to the first input terminal of the NAND gate NAND. The output terminal of the inverter INV is also connected to the gates of the second switching transistor N2 and the second control transistor P2. The input signal Din is connected to the second input terminal of the NAND gate NAND. The output terminal of the NAND gate NAND is connected to the gate of the first control transistor P1. The second pole of the first control transistor P1 is connected to the output port Out.
[0030] The second poles of the second control transistor P2 and the second switching transistor N2 are interconnected and connected to the gate of the third control transistor P3. The first pole of the second switching transistor N2 is grounded. The first pole of the second control transistor P2 is connected to the first node NetA. The first node NetA is also connected to the first pole of the third control transistor P3. The second pole of the third control transistor P3 is connected to the power supply voltage VDD.
[0031] When the output port Out is first powered up to a high level and the power supply voltage VDD is not powered up, for the first control transistor P1 connected to the output port Out, there is a parasitic diode between the drain and the substrate end of the first control transistor P1. The P electrode and the N electrode of the parasitic diode are connected to the output port Out and the substrate end respectively, or connected to the first node NetA. At this time, the parasitic diode conducts forward and charges the first node NetA until the voltage of the first node NetA is V Out -V dio ,V dio is the forward conduction voltage drop of the parasitic diode.
[0032] Since the power supply voltage VDD is not powered up temporarily, the voltage at the output terminal of the inverter INV (i.e., the second control transistor P2 and the second switching transistor N2) is 0. The second control transistor P2 conducts, and the second switching transistor N2 cuts off. At this time, the voltage at the output terminal of the inverter formed by the interconnected drains of the second control transistor P2 and the second switching transistor N2 (i.e., the gate voltage of the third control transistor P3) is equal to the voltage of the NetA node, that is, equal to V Out -V dio, so the voltages of the gate, the first pole, and the substrate end of the third control transistor P3 are the same, all being V Out -V dio , the second pole of the third control transistor P3 is connected to the power supply voltage VDD, and the voltage here is equal to 0. The second pole of the third control transistor P3 is equal to 0. Therefore, the third control transistor P3 is turned off, and the output port Out cannot leak electricity to the power supply voltage VDD through the path composed of the first control transistor P1 and the third control transistor P3 when powered on. Additionally, since the power supply voltage VDD is not powered on, the gate voltage of the first switching transistor N1 is equal to 0, and the first switching transistor N1 is turned off. There is also no leakage path between the output port Out and the ground Gnd. In summary, when the output port Out is powered on and the power supply voltage VDD is not powered on, the output port Out cannot leak electricity to the power supply voltage VDD through the first control transistor P1 and the third control transistor P3, nor can it leak electricity to the ground Gnd through the second switching transistor N2. Therefore, there is no leakage channel, avoiding the occurrence of reverse leakage problems.
[0033] Specifically, it further includes a NOR gate NOR and a first switching transistor N1. The first input terminal and the second input terminal of the NOR gate NOR are respectively connected to the enable control signal Enable and the input signal Din. The output terminal of the NOR gate NOR is interconnected with the gate of the first switching transistor N1. The first pole of the first switching transistor N1 is grounded, and the second pole is connected to the output port Out.
[0034] When the enable control signal Enable = 1, the output terminal of the NOR gate NOR (i.e., the gate voltage of the first switching transistor N1) is 0, the output terminal of the inverter INV is 0, the first switching transistor N1 is turned off, the output terminal of the NAND gate NAND (the gate voltage of the first control transistor P1) is the power supply voltage VDD, the first control transistor P1 is turned off, the second switching transistor N2 is turned off, and the output port Out is in a high-impedance state.
[0035] When the enable control signal Enable = 0, the output terminal of the inverter INV is 1, the gate voltage of the second switching transistor N2 is at a high level. At this time, the second switching transistor N2 is turned on, the second control transistor P2 is turned off, the third control transistor P3 is turned on, and the voltage of the first node NetA is equal to the power supply voltage VDD.
[0036] At this time, if the input signal Din = 1, both the NAND gate NAND and the NOR gate NOR output 0, that is, the gate voltages of the first control transistor P1 and the first switching transistor N1 are both equal to 0. Therefore, the first control transistor P1 is turned on and the first switching transistor N1 is turned off, and the output port Out outputs a high level.
[0037] In summary, when VDD is in the powered-on state, the circuit proposed by the present invention has the same logical function as Figure 1 the conventional circuit shown.
[0038] In all embodiments of the present application, the transistors used can be thin film transistors, field effect transistors, or other devices with the same characteristics. According to their functions in the circuit, the transistors used in the embodiments of the present application are mainly CMOS transistors (Complementary Metal Oxide Semiconductor). Since the source and drain of a CMOS transistor are symmetric, the source and drain can be interchanged. In the embodiments of the present application, to distinguish the other two poles of the transistor except the gate, the source of the transistor can be referred to as the first pole, and the drain of the transistor can be referred to as the second pole.
[0039] Specifically, the drain of the first control transistor P1 is connected to the output port Out. The drains of the second control transistor P2 and the second switching transistor N2 are interconnected and connected to the gate of the third control transistor P3. The source of the second switching transistor N2 is grounded. The source of the second control transistor P2 is connected to the first node NetA. The first node NetA is also connected to the source of the third control transistor P3. The drain of the third control transistor P3 is connected to the power supply voltage VDD.
[0040] In one embodiment, the first switching transistor N1 is an NMOS transistor. The first control transistor P1 is a PMOS transistor. The polarities of the second switching transistor N2 and the second control transistor P2 are opposite. The second switching transistor N2 is an NMOS transistor, and the second control transistor P2 is a PMOS transistor. The third control transistor P3 has the same polarity as the first control transistor N1. The third control transistor P3 is a PMOS transistor.
[0041] It can be understood that the first control transistor P1, the first switching transistor N1, the second control transistor P2, the second switching transistor N2, and the third control transistor P3 are all MOS transistors. Therefore, the substrate terminals of the above-mentioned transistors are all connected to the source in common.
[0042] Based on the same technical concept, the present application also provides an integrated chip that uses the above output port circuit. Since the integrated chip includes an output port, a second control transistor, a third control transistor, and a second switching transistor, it can avoid the occurrence of reverse leakage caused by the output port being powered on first while ensuring the normal operation of the output port.
[0043] Based on the same inventive concept, the present application also provides an electronic device that employs the above-described output port circuit. The electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, headphones, a removable storage device, a wearable device, a vehicle, a household appliance, and / or a medical device.
[0044] In summary, in the output port circuit, integrated chip, and electronic device provided by the embodiments of the present invention, since the power supply voltage VDD has not been powered on yet, the voltage at the output terminal of the inverter INV (i.e., the second control transistor P2 and the second switching transistor N2) is 0. The second control transistor P2 is turned on, and the second switching transistor N2 is turned off. At this time, the voltage at the output terminal of the inverter formed by interconnecting the drains of the second control transistor P2 and the second switching transistor N2 (i.e., the gate voltage of the third control transistor P3) is equal to the voltage of the NetA node, which is equal to V Out -V dio , so the voltages at the gate, first pole, and substrate end of the third control transistor P3 are the same and are all V Out -V dio . The second pole of the third control transistor P3 is connected to the power supply voltage VDD, and the voltage there is equal to 0. The second pole of the third control transistor P3 is equal to 0, so the third control transistor P3 is turned off. When the output port Out is powered on, it cannot leak current to the power supply voltage VDD through the path formed by the first control transistor P1 and the third control transistor P3. Additionally, since the power supply voltage VDD has not been powered on, the gate voltage of the first switching transistor N1 is equal to 0, and the first switching transistor N1 is turned off. There is also no leakage path between the output port Out and the ground Gnd. By setting the three devices of the second switching transistor, the second control transistor, and the third control transistor, when the output port Out is powered on and the power supply voltage VDD has not been powered on, the output port Out cannot leak current to the power supply voltage VDD through the first control transistor P1 and the third control transistor P3, nor can it leak current to the ground Gnd through the second switching transistor N2. Therefore, there is no leakage path, and the problem of reverse leakage can be solved.
[0045] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. An output port circuit, characterized in that, it includes: an inverter, a NAND gate, a first control transistor, a second control transistor, a third control transistor, and a second switching transistor; An enable control signal and an input signal are provided. The input end of the inverter is connected to the enable control signal, the output end of the inverter is connected to the first input end of the NAND gate, the output end of the inverter is also connected to the gates of the second switching transistor and the second control transistor, the input signal is connected to the second input end of the NAND gate, the output end of the NAND gate is connected to the gate of the first control transistor, and the second pole of the first control transistor is connected to the output port; The second poles of the second control transistor and the second switching transistor are interconnected and connected to the gate of the third control transistor. The first pole of the second switching transistor is grounded. The first pole of the second control transistor is connected to a first node, and the first node is also connected to the first pole of the third control transistor. The second pole of the third control transistor is connected to the power supply voltage.
2. The output port circuit according to claim 1, characterized in that, it further includes a NOR gate and a first switching transistor. The first input end and the second input end of the NOR gate are respectively connected to the enable control signal and the input signal. The output end of the NOR gate is interconnected with the gate of the first switching transistor. The first pole of the first switching transistor is grounded, and the second pole is connected to the output port.
3. The output port circuit according to claim 2, characterized in that, the first switching transistor is an NMOS transistor.
4. The output port circuit according to claim 2, characterized in that, the first control transistor is a PMOS transistor.
5. The output port circuit according to claim 1, characterized in that, the second switching transistor and the second control transistor have opposite polarities.
6. The output port circuit according to claim 5, characterized in that, the second switching transistor is an NMOS transistor, and the second control transistor is a PMOS transistor.
7. The output port circuit according to claim 1, characterized in that, the third control transistor has the same polarity as the first control transistor.
8. The output port circuit according to claim 7, characterized in that, the third control transistor is a PMOS transistor.
9. An integrated chip, characterized in that, it adopts the output port circuit according to any one of claims 1-8.
10. An electronic device, characterized in that, it adopts the output port circuit according to any one of claims 1-8.