CDAC self-calibration method based on noise shaping successive approximation analog-to-digital converter

Abstract

The invention discloses a CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter, which multiplexes a capacitor and a redundant capacitor of a capacitor array low section, a noise shaping filter circuit, a comparator and an SAR logic circuit as a Z-ADC with an ideal weight coefficient, and quantizes the voltage variation generated by a capacitor to be calibrated. In order to improve the calibration precision, the same capacitor to be calibrated is subjected to multiple times of setting and quantization, which is equivalent to oversampling, and the noise shaping technology is combined, so that the quantization noise in the bandwidth is greatly inhibited, and the calibration precision is ensured. After the capacitance calibration of the current bit is completed, the current bit is included in the Z-ADC as the highest bit, and calibration to the high bit is carried out in sequence until the highest bit is reached.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converters, and particularly relates to a CDAC self-calibration method based on a noise-shaping successive approximation analog-to-digital converter. Background Art

[0002] An analog-to-digital converter (ADC) can convert analog signals in the environment into digital signals for signal processing by a processor, and is an indispensable module in fields such as communication, Internet of Things, and biomedicine. Among many ADC architectures, the successive approximation register (SAR) ADC has the characteristic of low power consumption due to its highly digital structure and is widely used in medium-low speed (1 kHz to 100 MHz) and medium-precision (8 to 12 bits) scenarios. However, the successive approximation ADC is limited by quantization noise and capacitance mismatch errors of the capacitive digital-to-analog converter (CDAC), making it difficult to develop towards high precision. In order to maintain its low-power characteristic and achieve high precision (greater than 14 bits), the noise-shaping (NS) successive approximation ADC combines delta-sigma modulation and oversampling techniques to effectively suppress quantization noise within the bandwidth. Therefore, how to calibrate the capacitance mismatch error of the CDAC has become the next challenge to be solved.

[0003] The capacitance mismatch error of the CDAC refers to the deviation between the actual value and the designed value of the capacitance in the chip, and this deviation comes from the chip manufacturing process. The mismatch error will change the proportional relationship of the weight coefficients between the high-order capacitance and the low-order capacitance, thereby generating non-linearity and hindering the development of the ADC towards high precision.

[0004] Existing CDAC calibration techniques can generally be divided into two categories: The first category is the split ADC technique (such as [Wang Mingyue. Research and Implementation of Calibration Algorithms for High-Precision Successive Approximation Analog-to-Digital Converters [D]. Xi'an: Xidian University, 2023]), which is applied to front-end or back-end calibration with a fast convergence speed. However, it requires splitting an ADC design into two sub-ADCs, greatly increasing the power consumption and area of the circuit. The second category is the self-calibration technique (such as the Chinese patent application with the publication number CN117879603A), which is mainly applied to the calibration scenario of high-precision SAR ADCs, and uses its smaller quantization noise to calibrate the actual weight coefficients successively from the lower bits to the higher bits. However, the CDAC of a high-precision noise shaping successive approximation ADC is usually around 10 bits, and the remaining quantization noise after 10 conversions is still relatively large. Therefore, when simply applying the self-calibration technique from SAR ADCs to the calibration process of noise shaping successive approximation ADCs, it cannot support high-precision design goals. Summary of the Invention

[0005] In view of the above, the present invention provides a CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter, which can realize the calibration of CDAC weight coefficients and improve the linearity of the noise shaping successive approximation ADC.

[0006] A CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter includes the following steps:

[0007] (1) Initially, select the lowest i - 1 capacitors C 1 , C 2 , …, C i-1 from the capacitor array and regard them as a CDAC with ideal weight coefficients, denoted as the calibration CDAC, where C i-1 is the redundant capacitor, and the rest are bit capacitors, i - 1 < N, and N is the bit number of the noise shaping successive approximation analog-to-digital converter;

[0008] (2) Combine the calibration CDAC, the noise shaping filter circuit, the comparator, and the SAR logic circuit to form an ideal noise shaping successive approximation analog-to-digital converter, denoted as Z-ADC, for calibrating the capacitor C i (capacitor to be calibrated);

[0009] (3) Switch the lower plate of C i to a high potential, and use Z-ADC to calibrate it to obtain the weight coefficient calibration matrix D i of C i,set1 ;

[0010] (4) Switch the lower plate of C i to a ground potential, and use Z-ADC to calibrate it to obtain C iWeight coefficient calibration matrix D i,set0 ;

[0011] (5) Average the result of D i,set1 - D i,set0 after digital filtering to obtain the true weight coefficient w i of C i , thus completing the calibration of capacitor C i ;

[0012] (6) Let i = i + 1 and determine whether i > N holds: If it holds, use the weight coefficient matrix W corresponding to the Z-ADC as the final weight coefficient matrix, complete the calibration, and exit the calibration mode; if it does not hold, incorporate C i into the calibration CDAC, incorporate w i into the weight coefficient matrix W, and return to step (3) to start the calibration of the next bit.

[0013] Further, the noise shaping successive approximation analog-to-digital converter includes a capacitor array, a noise shaping filter circuit, a comparator, an SAR logic circuit, a calibration control circuit, and a digital filtering weight calculation circuit. This analog-to-digital converter has two working modes, namely, a calibration mode and a conversion mode. In the calibration mode, the ADC performs calibration work, and in the conversion mode, the ADC performs normal analog-to-digital conversion work.

[0014] Further, the specific implementation of step (3) is as follows: First, switch the lower plate of C i to 1, i.e., high potential, so that a voltage change amount +V i representing the weight coefficient of C i appears on the upper plates of the entire capacitor array. Use the Z-ADC to quantize +V i into a digital code; repeat the above process K times, and store the digital codes obtained in these K cycles in the calibration control circuit as a matrix DOUT i,set1 of size K×(i - 1), where K is a natural number greater than 1; then obtain the weight coefficient calibration matrix D i of C i,set1 = DOUT i,set1 × W, W = [w i-1 , w i-2 , …, w 1 T , that is, obtain the weight coefficients of C i when the lower plate is set to 1 K times.

[0015] Further, the specific implementation of step (4) is as follows: First, switch the lower plate of C i to 0, i.e., ground potential, so that a voltage change amount representing C i ​Voltage change amount -V of the weight coefficient i , use the Z-ADC to quantize -V i into a digital code; repeat the above process K times, and store the digital codes obtained in these K cycles in a calibration control circuit as a matrix DOUT of size K×(i - 1) i,set0 , where K is a natural number greater than 1; then obtain the weight coefficient calibration matrix D of C i through matrix multiplication operation i,set0 = DOUT i,set0 ×W, W = [w i-1 , w i-2 , …, w 1 T , that is, obtain the weight coefficients of C i in the case where the lower plates of K times are set to 0.

[0016] Furthermore, the CDAC self-calibration method multiplexes the noise shaping filter circuit in the noise shaping successive approximation analog-to-digital converter to suppress the quantization noise in the calibration mode.

[0017] Furthermore, the upper plate of the calibration CDAC is connected to the input end of the comparator through the noise shaping filter circuit. The comparison result output by the comparator controls the potential connection of the lower plate of the calibration CDAC through the SAR logic circuit. At the same time, the SAR logic circuit inputs the conversion result into the digital filter weight calculation circuit, calculates the weight coefficient of the capacitor to be calibrated and incorporates this capacitor into the calibration CDAC, and then calibrates successively to the higher bits.

[0018] Furthermore, the sum of the weight coefficients of the calibration CDAC is greater than the weight coefficient of the capacitor to be calibrated.

[0019] Furthermore, the CDAC self-calibration method multiplexes the noise shaping filter circuit, the comparator and the SAR logic circuit to form a noise shaping successive approximation analog-to-digital converter for calibration, namely Z-ADC, without adding additional circuits.

[0020] The CDAC self-calibration method of the present invention multiplexes the capacitors in the lower segment of the capacitor array and the redundant capacitors, the noise shaping filter circuit, the comparator and the SAR logic circuit as the Z-ADC with ideal weight coefficients to quantize the voltage change amount generated by the capacitor to be calibrated. To improve the calibration accuracy, the present invention performs multiple setting and quantization on the same capacitor to be calibrated, which is equivalent to oversampling. Combining with the noise shaping technology, the quantization noise within the bandwidth is greatly suppressed, ensuring the accuracy of calibration. After completing the calibration of the capacitor at the current bit, the present invention incorporates it into the Z-ADC as the highest bit and calibrates successively to the higher bits until the highest bit.

[0021] ​After calibration, the present invention can obtain the true weights of the capacitor array in the noise-shaping successive approximation ADC, improve linearity, and serve high-precision designs. Compared with traditional SAR ADC-based self-calibration techniques, the present invention uses oversampling and noise-shaping techniques through the multiplexed Z-ADC to more effectively suppress quantization noise within the bandwidth in the calibration mode, improving calibration accuracy and being more suitable for the case of fewer CDAC bits. In the calibration mode, the capacitor array, noise-shaping filter circuit, comparator, and SAR logic circuit can all be multiplexed without adding additional circuits to the ADC. Therefore, the present invention can ensure calibration performance while saving chip area and cost, improving the accuracy of the ADC. Description of the Drawings

[0022] Figure 1 It is a structural block diagram of the noise-shaping successive approximation analog-to-digital converter of the present invention.

[0023] Figure 2 It is a schematic flow chart of the CDAC self-calibration method of the present invention.

[0024] Figure 3 It is a schematic diagram of CDAC self-calibration based on a 10-bit noise-shaping successive approximation analog-to-digital converter in an embodiment of the present invention.

[0025] Figure 4 It is a schematic diagram of the dynamic performance of the ADC before calibration in an embodiment of the present invention.

[0026] Figure 5 It is a schematic diagram of the dynamic performance of the ADC after calibration in an embodiment of the present invention. Detailed Embodiments

[0027] To describe the present invention more specifically, the technical solutions of the present invention will be described in detail below in conjunction with the drawings and specific embodiments.

[0028] The CDAC self-calibration method of the present invention is based on as Figure 1The shown noise shaping successive approximation type analog-to-digital converter includes a CDAC, a noise shaping filter circuit, a comparator, a successive approximation logic circuit, a calibration control circuit, and a digital filter weight calculation circuit. This analog-to-digital converter performs calibration work in the calibration mode and normal ADC conversion work in the conversion mode; the upper plate of the CDAC is connected to the input end of the comparator through the noise shaping filter circuit, and the lower plate is connected to the successive approximation logic circuits of each bit; redundant capacitors need to be added to the CDAC, and the bit capacitors and redundant capacitors together are N bits; in the calibration mode, the low-segment bit capacitors and redundant capacitors, a total of i - 1 bits (i - 1 < N), are multiplexed and regarded as a CDAC with ideal weight coefficients, and it is ensured that the sum of the weight coefficients of this ideal CDAC is greater than the weight of the capacitor to be calibrated. In the calibration mode, the present invention multiplexes the noise shaping filter circuit, the comparator, and the successive approximation logic circuit to form a Z-ADC for calibration without additional addition. The conversion result is input to the digital filter weight calculation circuit to calculate the weight coefficient of the capacitor to be calibrated, and this bit capacitor is incorporated into the ideal noise shaping successive approximation type analog-to-digital converter, and calibration is performed sequentially from the low bit to the high bit. The specific process of the CDAC self-calibration method of the present invention is as follows:

[0029] S1: The initially calibrated CDAC selects C 1 , C 2 , …, C i-1 These i - 1 capacitors of the lowest bits, where C i-1 is a redundant capacitor, and its weight coefficient is equal to C i-2 ; these i - 1 bit capacitors, the noise shaping filter circuit, the comparator, and the successive approximation logic are combined to form an ideal noise shaping successive approximation type analog-to-digital converter, denoted as Z-ADC, for calibrating the capacitor to be calibrated C i ;

[0030] S2.1: Switch the lower plate of C i to "1" (i.e., high potential), so that a voltage change amount +V i representing the weight coefficient of C i appears on the upper plate of the entire CDAC.

[0031] S3.1: Use the Z-ADC to quantize +V i into a digital code.

[0032] S4.1: Repeat steps S2.1 to S3.1 a total of K times, store the digital codes obtained in these K cycles in a calibration digital circuit as a K×(i - 1) matrix DOUT i,set1 , the weight coefficient matrix corresponding to the Z-ADC is defined as W = [w i-1 , w i-2 , …, w 1 T , perform matrix multiplication operation to obtain C i ​Coefficient calibration matrix D of i,set1 =DOUT i,set1 ×W, thus obtaining C i The weight coefficients with the K lower plates of

[0033] S2.2: Switch the lower plates of C i to "0" (i.e., ground potential), causing the upper plates of the entire CDAC to exhibit a voltage change -V i representing the weight coefficients of i .

[0034] S3.2: Use the Z-ADC to quantize -V i into a digital code

[0035] S4.2: Repeat steps S2.2 to S3.2 a total of K times, and store the digital codes obtained in these K cycles in a calibration digital circuit as a K×(i - 1) matrix DOUT i,set0 , and the weight coefficient matrix corresponding to the Z-ADC is defined as W = [w i-1 , w i-2 , …, w 1 T , perform matrix multiplication operation to obtain the coefficient calibration matrix D of C i =DOUT i,set0 ×W, thus obtaining the weight coefficients of the K lower plates of C i,set0 being set to "0". i

[0036] S5: Execute D i,set1 -D i,set0 , perform digital filtering on the differences of these K weight coefficients and then average them to obtain the true weight w i of C i , thereby completing the calibration of the currently to-be-calibrated capacitor C i ; in this way, the method of "first set to 1, then set to 0, and then take the difference" eliminates the influence of the comparator offset voltage on the calibration accuracy

[0037] S6: Let i = i + 1, and then determine whether i > N holds: If so, take W as the final weight coefficient matrix, complete the calibration, and exit the calibration mode; if not, incorporate C i into the Z-ADC as its most significant bit, and incorporate w i into the matrix W, thereby forming a new calibration circuit, and return to step S2.1 to start the calibration of the next bit

[0038] Embodiment

[0039] Apply the present invention to an ADC scenario such as Figure 3 ​​As shown, it includes 5 modules: a CDAC with N = 10 bits (including 9 binary capacitors and 1 redundant capacitor, divided into 2 segments and connected with a bridge capacitor C b ), a noise shaping filter circuit, a comparator, a successive approximation logic circuit, and a digital filter weight calculation output circuit. In the conversion mode, the ADC performs normal conversion operations on the input signal V INPUT . After each quantization, the remaining margin voltage V RES on the upper plate is given to the noise shaping filter circuit for operations such as integration and summation, and then output to the comparator for comparison to obtain the digital code of this bit. The digital code controls the successive approximation logic circuit to switch the lower plate of the corresponding capacitor of the CDAC, thereby generating a new V RES , starting a new cycle; after 10 conversions are completed, the 10-bit digital code is output as D[10:1] through the digital filter weight calculation output circuit.

[0040] In the calibration mode, the ADC no longer samples the V INPUT signal, but executes the process shown in Figure 2 , and the specific process includes:

[0041] Step 1: Since the capacitance weight coefficients of the lower segment have less influence on the overall linearity of the ADC and can be considered to have ideal weight coefficients, in this embodiment, the initial CDAC for calibration selects the 4 lowest-bit capacitors C 1 , C 2 , C 3 , C 4 , where C 4 is the redundant capacitor and its weight coefficient is equal to C 3 . These 4-bit capacitors, the noise shaping filter circuit, the comparator, and the successive approximation logic circuit are combined to form an ideal noise shaping successive approximation analog-to-digital converter, denoted as Z-ADC, for calibrating the capacitor C 5 to be calibrated. At this time, i = 5.

[0042] Step 2.1: Switch the lower plate of C i to "1" (i.e., V REF ), so that a voltage change amount +V i representing the weight coefficient of C i appears on the upper plate of the CDAC.

[0043] Step 2.2: Use the Z-ADC to quantize +V i into a digital code.

[0044] Step 2.3: Repeat steps 2.1 to 2.2 a total of K = 512 times, and store the digital codes obtained in these 512 cycles in a calibration digital circuit as a K×(i - 1) matrix DOUT i,set1, the weight coefficient matrix corresponding to the Z-ADC is defined as W = [w i-1 , w i-2 , …, w 1 T , perform matrix multiplication to obtain the coefficient calibration matrix D i of C i,set1 = DOUT i,set1 × W, that is, obtain the weight coefficients of the K lower plates of C i set to "1".

[0045] Step 3.1: Switch the lower plate of C i to "0" (i.e., GND), so that a voltage change amount -V i representing the weight coefficient of C i appears on the upper plate of the CDAC.

[0046] Step 3.2: Use the Z-ADC to quantize -V i into a digital code.

[0047] Step 3.3: Repeat steps 3.1 to 3.2 a total of K = 512 times, and store the digital codes obtained in these 512 cycles in a calibration digital circuit as a K×(i - 1) matrix DOUT i,set0 , the weight coefficient matrix corresponding to the Z-ADC is defined as W = [w i-1 , w i-2 , …, w 1 T , perform matrix multiplication to obtain the coefficient calibration matrix D i of C i,set0 = DOUT i,set0 × W, that is, obtain the weight coefficients of the K lower plates of C i set to "0".

[0048] Step 4: Execute D i,set1 - D i,set0 , perform digital filtering on the difference of these K weight coefficients and then average to obtain the true weight w i of C i , thereby completing the calibration of the currently to-be-calibrated capacitor C i ; in this way, the method of "first set to 1, then set to 0, and then take the difference" eliminates the influence of the offset voltage of the comparator on the calibration accuracy.

[0049] Step 5: Let i = i + 1, and then judge whether i > N holds: if so, take W as the final weight coefficient matrix, complete the calibration, and exit the calibration mode; if not, incorporate C i into the Z-ADC as its highest bit, and incorporate w i into the matrix W, thereby forming a new calibration circuit, and return to step 2.1 to start the calibration of the next capacitor C i+1 ​​Calibration of the weight coefficient.

[0050] Figure 4 and Figure 5 The comparison results of the dynamic performance of the ADC in this embodiment before and after calibration are given. Under the condition that the relative capacitance mismatch error is 0.1%, the Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC before calibration is 64.21 dB. As Figure 4 shown, its Total Harmonic Distortion (THD) dominates and affects the accuracy. Figure 5 The following are the dynamic performance results after adopting the CDAC self-calibration technology of the present invention. Its SNDR is 85.40 dB, achieving a 14-bit accuracy, and the THD drops to -99.20 dB. It can be seen that in the calibration mode, the noise shaping technology effectively suppresses the in-band quantization noise and meets the accuracy requirements of calibration. In addition, the CDAC self-calibration method of the present invention greatly reuses the existing circuits of the ADC, without adding additional circuits, saving area and circuit overhead while ensuring performance.

[0051] The above description of the embodiments is to enable those of ordinary skill in the art to understand and apply the present invention. Obviously, those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative efforts. Therefore, the present invention is not limited to the above embodiments, and all improvements and modifications made by those skilled in the art based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A CDAC self-calibration method based on a noise shaping successive approximation analog-to-digital converter, comprising the following steps: (1) Initially select the lowest i-1 capacitors C1, C2, ..., C from the capacitor array. i-1 is regarded as a CDAC with an ideal weight coefficient, denoted as the calibration CDAC, where C i-1 is a redundant capacitor, and the rest are bit capacitors, i-1<N, N is the number of bits of the noise shaping successive approximation analog-to-digital converter; (2) The calibration CDAC, noise shaping filter circuit, comparator and SAR logic circuit form an ideal noise shaping successive approximation analog-to-digital converter, denoted as Z-ADC, which is used to calibrate the capacitor C in the capacitor array. i ; (3) Switch C i The lower plate of the capacitor is at high potential, and the Z-ADC is used to calibrate it to obtain C i The weight coefficient calibration matrix D i,set1 ; (4) Switch C i The lower plate of the capacitor is at ground potential, and the Z-ADC is used to calibrate it to obtain C i The weight coefficient calibration matrix D i,set0 ; (5) D i,set1 -D i,set0 The result is digitally filtered and averaged to obtain C i The real weight coefficient w i , thus completing the capacitor C i Calibration of (6) Let i = i + 1, and determine whether i > N. If so, the weight coefficient matrix W corresponding to Z-ADC is used as the final weight coefficient matrix, the calibration is completed, and the calibration mode is exited. If not, C i Incorporate into the calibration CDAC, w i The weight coefficient matrix W is incorporated and the process returns to step (3) to start the next calibration.

2. The CDAC self-calibration method according to claim 1, characterized in that: The noise shaping successive approximation analog-to-digital converter includes a capacitor array, a noise shaping filter circuit, a comparator, a SAR logic circuit, a calibration control circuit and a digital filter weight calculation circuit. The analog-to-digital converter has two working modes, namely a calibration mode and a conversion mode. In the calibration mode, the ADC performs calibration work, and in the conversion mode, the ADC performs normal analog-to-digital conversion work.

3. The CDAC self-calibration method according to claim 2, characterized in that: The specific implementation method of step (3) is: first switch C i The lower plate of the capacitor is 1, i.e., high potential, so that the upper plate of the entire capacitor array appears to represent C i Voltage change of weight coefficient +V i , use Z-ADC to convert +V i Quantize into digital code; repeat the above process for K times, and store the digital code obtained in these K cycles into a K×(i-1) size matrix DOUT in the calibration control circuit i,set1 , K is a natural number greater than 1; Then we get C by matrix multiplication. i The weight coefficient calibration matrix D i,set1 =DOUT i,set1 ×W,W=[w i-1 ,w i-2 ,…,w1] T , that is, C i The weight coefficient when the Kth lower plate is set to 1.

4. The CDAC self-calibration method according to claim 2, characterized in that: The specific implementation method of step (4) is: first switch C i The lower plate of the capacitor is at 0, i.e., ground potential, so that the upper plate of the entire capacitor array appears to represent C i Voltage change of weight coefficient -V i , use Z-ADC to convert -V i Quantize into digital code; repeat the above process for K times, and store the digital code obtained in these K cycles into a K×(i-1) size matrix DOUT in the calibration control circuit i,set0 , K is a natural number greater than 1; Then we get C by matrix multiplication. i The weight coefficient calibration matrix D i,set0 =DOUT i,set0 ×W,W=[w i-1 ,w i-2 ,…,w1] T , that is, C i The weight coefficient when the lower plate is set to 0 for the Kth time.

5. The CDAC self-calibration method according to claim 2, characterized in that: The CDAC self-calibration method reuses the noise shaping filter circuit in the noise shaping successive approximation analog-to-digital converter to suppress the quantization noise in the calibration mode.

6. The CDAC self-calibration method according to claim 2, characterized in that: The upper plate of the calibration CDAC is connected to the input end of the comparator through a noise shaping filter circuit. The comparison result output by the comparator controls the potential connection of the lower plate of the calibration CDAC through a SAR logic circuit. At the same time, the SAR logic circuit inputs the conversion result into a digital filter weight calculation circuit, calculates the weight coefficient of the capacitor to be calibrated and incorporates the capacitor into the calibration CDAC, and then calibrates in sequence towards the higher position.

7. The CDAC self-calibration method according to claim 6, characterized in that: The sum of the weight coefficients for calibrating CDAC is greater than the weight coefficient of the capacitance to be calibrated.

8. The CDAC self-calibration method according to claim 2, characterized in that: The CDAC self-calibration method reuses a noise shaping filter circuit, a comparator and a SAR logic circuit to form a noise shaping successive approximation analog-to-digital converter (Z-ADC) for calibration without adding additional circuits.

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