High-impedance-state sampling circuit, control method and multiplexing analog-to-digital converter
By using a high-resistance sampling circuit in a multiplexed analog-to-digital converter to precharge the sampling capacitor, the problem of increasing power consumption and excessive establishment time in traditional solutions is solved, and fast and low-power sampling voltage establishment is achieved.
Patent Information
- Application Number
- CN202510156059.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2025-05-30
AI Technical Summary
When sampling between channels, traditional multiplexed successive approximation register analog-to-digital converters (SAR ADCs) need to be pre-charged through broadband drive amplifiers and RC filters, resulting in increased power consumption and excessive establishment time, which affects the actual application effect.
The high-resistance sampling circuit is adopted to pre-charge the sampling capacitor to ensure that the voltage is quickly established to the current channel voltage value, avoid the use of broadband drive amplifiers, and reduce circuit power consumption.
It realizes the rapid establishment of the voltage of the sampling capacitor in a multiplexed analog-to-digital converter, reduces power consumption, shortens the establishment time, and improves the practical application effect.
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Figure CN120074524A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and particularly to a high-impedance state sampling circuit, a control method, and a multiplexing analog-to-digital converter. Background Art
[0002] Multiplexing successive approximation register type analog-to-digital converters (SAR ADCs) have size and power limitations, which typically depend on the design choices of each channel's analog signal chain. Multiplexing applications have some common requirements. There are many channels to be monitored, and the ADC sorts through all channels, but the voltages of each channel are different. Therefore, when the ADC finishes converting the previous channel, the sampling capacitor needs to be charged to the current voltage value of the next channel so that the voltage value on the sampling capacitor can be accurately established to the new voltage in a short time. To achieve this purpose, in order to solve this problem, some solutions add a broadband drive amplifier and an RC filter before the sampling capacitor. However, the broadband drive amplifier often brings greater power consumption, and the power consumption after passing through the broadband drive amplifier will increase significantly. This brings problems in terms of size. At the same time, using this front-end sampling circuit without a pre-charge mode will result in too long a settling time and the voltage on the sampling switch cannot be established in time. These two problems will lead to poor performance of traditional solutions in practical applications. Summary of the Invention
[0003] In view of the above-mentioned disadvantages of the prior art, this application provides a high-impedance state sampling circuit, a control method, and a multiplexing analog-to-digital converter to solve at least one defect in the prior art.
[0004] To achieve the above and other purposes, this application provides a high-impedance state sampling circuit, and the sampling circuit includes: a high input impedance circuit, and the high input impedance circuit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, and a second capacitor;
[0005] One end of the first switch is connected to a first input signal, the other end of the first switch is connected to the first plate of the first capacitor, the second plate of the first capacitor is connected to one end of the second switch, and the other end of the second switch is connected to the input channel selection module of the ADC; the first capacitor and the first switch are connected to form a first electrical node, one end of the third switch is connected to a first charging voltage, and the other end of the third switch is connected to the first electrical node;
[0006] One end of the fourth switch is connected to the second input signal, the other end of the fourth switch is connected to the first plate of the second capacitor, the second plate of the second capacitor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the input channel selection module of the ADC; the second capacitor and the fourth switch are connected to form a second electrical node, and one end plate of the sixth switch is connected to the second charging voltage, and the other end of the sixth switch is connected to the second electrical node.
[0007] In an embodiment of the present invention, the closing and opening of the first switch and the fourth switch are controlled by a first control signal, the closing and opening of the second switch and the fifth switch are controlled by a second control signal, the third switch and the sixth switch are controlled by a third control signal, the second control signal is consistent with the third control signal, and the third control signal is enabled earlier than the first control signal.
[0008] In an embodiment of the present invention, the first control signal is enabled after the third control signal is turned off.
[0009] In an embodiment of the present invention, the sampling circuit further includes: a first resistor and a second resistor, one end of the first resistor is connected to the first switch, and the other end of the first resistor is connected to the first input signal; one end of the second resistor is connected to the fourth switch, and the other end of the second resistor is connected to the second input signal.
[0010] To achieve the above and other purposes, the present application provides a control method for a high-impedance state sampling circuit, and the control method includes:
[0011] Enable the second switch, the third switch, the fifth switch, and the sixth switch, disconnect the first switch and the fourth switch, and charge the first capacitor and the second capacitor;
[0012] After the charging is completed, disconnect the third switch and the sixth switch, enable the first switch and the fourth switch, and the circuit enters the sampling stage.
[0013] In an embodiment of the present invention, when the voltage of the first capacitor is the first charging voltage and the voltage of the second capacitor is the second charging voltage, the charging is completed.
[0014] To achieve the above and other purposes, the present application provides a multiplexing analog-to-digital converter, including the high-impedance state sampling circuit described above.
[0015] Advantages of the present application:
[0016] A high-impedance state sampling circuit of the present application includes: one end of a first switch is connected to a first input signal, the other end of the first switch is connected to a first electrode plate of a first capacitor, a second electrode plate of the first capacitor is connected to one end of a second switch, and the other end of the second switch is connected to an input channel selection module of an ADC; the first capacitor and the first switch are connected to form a first electrical node, one end of a third switch is connected to a first charging voltage, and the other end of the third switch is connected to the first electrical node; one end of a fourth switch is connected to a second input signal, the other end of the fourth switch is connected to a first electrode plate of a second capacitor, a second electrode plate of the second capacitor is connected to one end of a fifth switch, and the other end of the fifth switch is connected to the input channel selection module of the ADC; the second capacitor and the fourth switch are connected to form a second electrical node, one end of a sixth switch is connected to a second charging voltage, and the other end of the sixth switch is connected to the second electrical node. By pre-charging the capacitor, the present invention ensures that the voltage on the sampling capacitor can be quickly established to the voltage value of the current channel each time, and at the same time, the use of a broadband drive amplifier can be avoided through pre-charging, reducing the power consumption of the circuit.
[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:
[0019] Figure 1 is a schematic block diagram of the principle of an ADC drive interface circuit;
[0020] Figure 2 is Figure 1 the equivalent circuit diagram of;
[0021] Figure 3 is Figure 2 the timing diagram of the switch in;
[0022] Figure 4 is the circuit diagram of the high-impedance state sampling circuit in an embodiment of the present application;
[0023] Figure 5 is Figure 4 the equivalent circuit diagram of;
[0024] Figure 6 is Figure 5 the timing diagram of the switch in;
[0025] Figure 7It is a graph of the establishment duration of the voltage on the sampling capacitor. Detailed implementation mode
[0026] The following uses specific specific examples to illustrate the implementation modes of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0027] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be an arbitrary change, and the component layout type may also be more complex.
[0028] Although terms such as "first", "second", "A", and "B" can be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, without departing from the scope of the following technology, the first element can be called the second element, and similarly, the second element can be called the first element. The term "and / or" includes combinations of multiple related items or any item among multiple related items.
[0029] As used herein, unless the context indicates otherwise, the singular form is also intended to include the plural form. It will be understood that the term "comprising" means the presence of the described features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.
[0030] Before the detailed description, it is intended to clarify that the division of components in this specification is only based on the main functions of each component. That is, two or more of the following-described components can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main functions of the components, each of the following-described components can also perform some or all of the functions of other components, and some of the main functions of each component can be specifically performed by other components.
[0031] Multiplexed successive approximation register type analog-to-digital converters (SAR ADCs) applications have size and power limitations, which typically depend on the design choices of each channel's analog signal chain. Multiplexed applications have some common requirements. There are many channels that need to be monitored. The ADC sorts through all the channels, but the voltages of each channel are different. Therefore, when the ADC finishes converting the previous channel, the sampling capacitor needs to be charged to the current voltage value of the next channel so that the voltage value on the sampling capacitor can be accurately established to the new voltage in a short time. To solve this problem, as Figure 1 shown, a broadband driver amplifier and an RC filter are added before the sampling capacitor. However, broadband driver amplifiers tend to bring greater power consumption, and the power consumption after passing through the broadband driver amplifier will increase significantly. This brings problems in terms of size. At the same time, using this front-end sampling circuit will result in too long a settling time and the voltage on the sampling switch cannot be established in a timely manner. These two problems will affect the effectiveness of traditional solutions in practical applications.
[0032] Figure 1 The circuit shown in Figure 2 can be equivalent to the circuit shown in Figure 2 which consists of a broadband driver amplifier and several resistors and capacitors. Figure 3 The corresponding switch timing is as shown in
[0033] where Ph1_slew is turned on first to control the output current of the amplifier and the time constant of the filter. When Ph1_slew is turned off, Ph1 and Ph1_d are still conducting and the capacitor is charged to the common-mode level. When Ph1 and Ph1_d are turned off, then Ph2 and Ph2_d are turned on and the circuit enters the sampling mode. Figure 1 Regarding the problems existing in the circuit shown in Figure 4 , Figure 4 This application provides a high-impedance sampling circuit applied to a multiplexed analog-to-digital converter. Please refer to Figure 5 which is a block diagram of a high-impedance sampling circuit according to an embodiment of this application. Specifically, as shown in
[0034] One end of the first switch S1 is connected to the first input signal VIN. The other end of the first switch S1 is connected to the first plate of the first capacitor C3. The second plate of the first capacitor C3 is connected to one end of the second switch S2. The other end of the second switch S2 is connected to the input channel selection module of the ADC. The first capacitor C1 and the first switch S1 are connected to form a first electrical node. One end of the third switch S3 is connected to the first charging voltage. The other end of the third switch S3 is connected to the first electrical node.
[0035] One end of the fourth switch S4 is connected to the second input signal VIP. The other end of the fourth switch S4 is connected to the first plate of the second capacitor C2. The second plate of the second capacitor C2 is connected to one end of the fifth switch S5. The other end of the fifth switch S5 is connected to the input channel selection module of the ADC. The second capacitor C4 and the fourth switch S4 are connected to form a second electrical node. One end of the sixth switch S6 is connected to the second charging voltage. The other end of the sixth switch S6 is connected to the second electrical node.
[0036] Please refer to Figure 5 , the closing and opening of the first switch S1 and the fourth switch S4 are controlled by the first control signal Ph1. The closing and opening of the second switch S2 and the fifth switch S5 are controlled by the second control signal Ph2_d. The third switch S3 and the sixth switch S6 are controlled by the third control signal Ph2. The second control signal Ph2_d is consistent with the third control signal Ph2. The third control signal Ph2 is enabled earlier than the first control signal Ph1.
[0037] The switch timing of the high-impedance sampling circuit is as Figure 6 shown. After each conversion is completed, the third control signal Ph2 and the second control signal Ph2_d will be immediately turned on to charge the sampling capacitor. After the charging is completed, the third control signal Ph2 is turned off. At this time, the first control signal Ph1 is turned on, and the circuit enters the sampling stage. After such a capacitor is pre-charged, it can quickly establish the voltage value of the currently selected channel.
[0038] In one embodiment, the first control signal Ph1 is enabled after the third control signal Ph2 is turned off.
[0039] In one embodiment, the sampling circuit further includes: a first resistor R1 and a second resistor R2. One end of the first resistor R2 is connected to the first switch S1. The other end of the first resistor R2 is connected to the first input signal VIN. One end of the second resistor R2 is connected to the fourth switch S4. The other end of the second resistor R2 is connected to the second input signal VIP.
[0040] Please refer to Figure 7 , Figure 7 For using Figure 2 and Figure 4The comparison diagram of the voltage establishment duration on the sampling capacitor of the front-end sampling circuit shown. As Figure 7 shown, using Figure 2 the circuit shown will result in too long an establishment time and the voltage on the sampling capacitor cannot be established in time, while using Figure 4 the circuit shown, the voltage establishment time on the sampling capacitor is shorter.
[0041] Through the above method, a broadband drive amplifier is reduced in the entire circuit, and the RC network does not need to be added either. The power consumption brought by a broadband drive amplifier is saved, solving the problem of increased power consumption existing in the circuit as Figure 1 shown.
[0042] This application provides a control method for a high-impedance state sampling circuit. The control method includes:
[0043] Enable the second switch S2, the third switch S3, the fifth switch S5, and the sixth switch S6, disconnect the first switch S1 and the fourth switch S4, and charge the first capacitor C3 and the second capacitor C4;
[0044] After the charging is completed, disconnect the third switch S3 and the sixth switch S6, enable the first switch S1 and the fourth switch S4, and the circuit enters the sampling stage.
[0045] In an embodiment, when the voltage of the first capacitor C3 is the first charging voltage and the voltage of the second capacitor C4 is the second charging voltage, the charging is completed.
[0046] This application provides a multiplexing analog-to-digital converter including the high-impedance state sampling circuit described above.
[0047] It should be noted that a large number of technical features are recorded in the specification of this application, distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are listed, the specification will be too long. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed. Features C and D are equivalent technical means that play the same role and only one of them can be used technically and they cannot be used simultaneously. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been recorded.
[0048] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means performing the act according to at least that element, including two cases: performing the act only according to that element and performing the act according to that element and other elements. Expressions such as multiple, many times, various, etc. include 2, 2 times, 2 kinds, and more than 2, more than 2 times, more than 2 kinds.
[0049] The term "coupled to" and its derivatives may be used herein. "Coupling" may mean that two or more elements are in direct physical or electrical contact. However, "coupling" may also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.
[0050] This specification includes combinations of various embodiments described herein. Separate references to embodiments (e.g., "an embodiment" or "some embodiments" or "preferred embodiments") are not necessarily to the same embodiment; however, unless indicated as being mutually exclusive or clearly understood by those skilled in the art as being mutually exclusive, these embodiments are not mutually exclusive. It should be noted that the word "or" is used in a non-exclusive sense in this specification unless the context clearly dictates otherwise or requires otherwise.
[0051] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present application should still be covered by the claims of the present application.
Claims
1. A high impedance sampling circuit, characterized in that: The sampling circuit comprises: a high input impedance circuit, wherein the high input impedance circuit comprises: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, and a second capacitor; One end of the first switch is connected to the first input signal, the other end of the first switch is connected to the first plate of the first capacitor, the second plate of the first capacitor is connected to one end of the second switch, and the other end of the second switch is connected to the input channel selection module of the ADC; the first capacitor is connected to the first switch to form a first electrical node, one end of the third switch is connected to the first charging voltage, and the other end of the third switch is connected to the first electrical node; One end of the fourth switch is connected to the second input signal, the other end of the fourth switch is connected to the first plate of the second capacitor, the second plate of the second capacitor is connected to one end of the fifth switch, and the other end of the fifth switch is connected to the input channel selection module of the ADC; the second capacitor is connected to the fourth switch to form a second electrical node, one end of the sixth switch is connected to the second charging voltage, and the other end of the sixth switch is connected to the second electrical node.
2. The high-impedance sampling circuit according to claim 1, characterized in that: The closing and opening of the first switch and the fourth switch are controlled by a first control signal, the closing and opening of the second switch and the fifth switch are controlled by a second control signal, the third switch and the sixth switch are controlled by a third control signal, the second control signal is consistent with the third control signal, and the third control signal is enabled earlier than the first control signal.
3. The high-impedance sampling circuit according to claim 2, characterized in that: The first control signal is enabled after the third control signal is turned off.
4. The high-impedance sampling circuit according to claim 1, characterized in that: The sampling circuit also includes: a first resistor and a second resistor, one end of the first resistor is connected to the first switch, and the other end of the first resistor is connected to the first input signal; one end of the second resistor is connected to the fourth switch, and the other end of the second resistor is connected to the second input signal.
5. A control method for a high impedance sampling circuit as claimed in any one of claims 1 to 4, characterized in that: The control method comprises: Enable the second switch, the third switch, the fifth switch, and the sixth switch, disconnect the first switch and the fourth switch, and charge the first capacitor and the second capacitor; After charging is completed, the third switch and the sixth switch are disconnected, the first switch and the fourth switch are enabled, and the circuit enters a sampling phase.
6. The control method according to claim 5, characterized in that: When the voltage of the first capacitor is the first charging voltage and the voltage of the second capacitor is the second charging voltage, the charging is completed.
7. A multiplexed analog-to-digital converter, characterized in that: It comprises the high-impedance sampling circuit as described in any one of claims 1 to 5.