On-chip pseudo-resistor calibration circuit based on a ΔΣ modulator

Abstract

This application relates to an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator. The circuit is based on the ΔΣ modulator technology, which has the characteristics of simple implementation method, relatively accurate resistance value of the switched-capacitor resistor, and large resistance value of the pseudo-resistor, and realizes a continuously adjustable large resistor with an on-chip resistance ranging from G ohm to T ohm. Based on the characteristics of large loop gain, high accuracy, and small hardware overhead of the ΔΣ modulator, the resistance value of the pseudo-resistor is accurately calibrated to the resistance value of the switched-capacitor resistor, and its resistance value is amplified. Compared with traditional pseudo-resistors, this circuit realizes accurate controllability of the resistance value, and improves the robustness, temperature characteristics, and linearity of the resistor. Compared with switched-capacitor resistors, this circuit realizes resistance values above the T ohm level. Compared with the existing pseudo-resistor calibration circuit technologies, this circuit can achieve a wider resistance adjustment range, less hardware and power consumption overhead.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator. Background Art

[0002] Giga-ohm level large resistors have important applications in many fields. In weak current detection, a transimpedance amplifier requires a resistor in the range of Giga-ohm to Tera-ohm to amplify the input picoampere current to an appropriate voltage range for subsequent analog-to-digital converter design; in the design of a current digital-to-analog converter, a low-pass filter composed of Giga-ohm level resistors is used in the bias circuit to effectively filter out the thermal noise generated by the bias circuit; in a capacitive coupling amplifier, a Tera-ohm level resistor is required to bias the amplifier, and the resistance value of this resistor also determines the high-pass corner frequency of the amplifier; in some low-frequency integrator applications that require a few Hz or even a few hundred mHz, Giga-ohm to Tera-ohm level resistors can greatly reduce the use of on-chip capacitors. If off-chip Giga-ohm level large resistors are used for design, the leakage of ESD in the IO will cause the equivalent resistance value to decrease, and using a specific IO design will also increase the design difficulty of the overall circuit. Integrating Giga-ohm level large resistors directly on-chip can effectively avoid this problem.

[0003] Currently, the commonly used on-chip implementation methods for Giga-ohm to Tera-ohm level resistors are divided into three types, namely: 1) pseudo-resistors, 2) switched-capacitor resistors, and 3) duty-cycle resistors. The advantage of pseudo-resistors is that they have a small area, a compact layout, a simple implementation method, and can achieve a large resistance value. The disadvantages are that the resistance value fluctuates greatly with process and temperature changes, the resistance linearity is poor, and the resistance value is difficult to adjust. A switched-capacitor resistor consists of a sampling capacitor and a sampling switch. Its advantage is that the resistance value can be accurately adjusted by the clock frequency, and the temperature and voltage coefficients of the capacitor are small, so that the resistance value fluctuates little with process and temperature changes. The disadvantage is that it is easily affected by parasitic capacitance, and the maximum achievable resistance value is often less than 100 Giga-ohms. A duty-cycle resistor can achieve precise control of the resistance value by adjusting the conduction time of the resistor. The advantage is that the resistance linearity is good, and the disadvantage is that the maximum achievable resistance value is limited (<100 Giga-ohms), and the change in process temperature will affect the duty cycle.

[0004] Existing on-chip large resistors are difficult to achieve a controllable Tera-ohm level resistor, and have problems of poor temperature characteristics and poor consistency. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator. This circuit improves the technology for implementing Tera-ohm level resistors on-chip, realizes an adjustable large resistor in the range of Giga-ohm to Tera-ohm, and greatly reduces the resistance value fluctuation caused by process and temperature changes.

[0006] An on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator, the on-chip pseudo-resistor calibration circuit comprising:

[0007] A direction comparator for determining a conversion control signal according to the magnitude relationship between an input voltage and a common-mode voltage.

[0008] A conversion switch for outputting a first voltage and a second voltage according to the input voltage, the common-mode voltage, and the conversion control signal, and respectively transmitting them to a reference input terminal and a calibration input terminal of a pseudo-resistor calibration module based on a ΔΣ modulator.

[0009] A pseudo-resistor calibration module based on a ΔΣ modulator for converting the first voltage into a reference current using a switched-capacitor reference resistor, converting the second voltage into a calibration current using a calibration pseudo-resistor, integrating, quantifying, digitally-to-analog converting, and low-pass filtering the difference between the reference current and the calibration current to obtain a filtered voltage, feeding back the filtered voltage to the calibration pseudo-resistor, and transmitting the filtered voltage to a control voltage replication circuit.

[0010] A control voltage replication circuit for replicating the difference between the filtered voltage and the common-mode voltage to a replication pseudo-resistor.

[0011] A replication pseudo-resistor for regulating its resistance value according to the replicated voltage, the common-mode voltage, and the input voltage, and calibrating its resistance value to several times the resistance value of the switched-capacitor reference resistor.

[0012] In one embodiment, the pseudo-resistor calibration module based on a ΔΣ modulator comprises: a switched-capacitor reference resistor, a calibration pseudo-resistor, an integrator, a quantizer, a digital-to-analog conversion module, and a low-pass filter.

[0013] A switched-capacitor reference resistor for converting the first voltage into a reference current using a series-connected switched-capacitor unit, and transmitting the reference current to the integrator.

[0014] A calibration pseudo-resistor for converting the second voltage into a calibration current using a parallel-connected calibration pseudo-resistor unit, and transmitting the calibration current to the integrator.

[0015] An integrator for integrating the difference between the reference current and the calibration current to obtain an analog voltage.

[0016] A quantizer for comparing the magnitude of the analog voltage and the common-mode voltage, converting the comparison result into a digital code, and obtaining a digital output voltage.

[0017] A digital-to-analog conversion module for converting the digital output voltage into an analog output voltage.

[0018] A low-pass filter for low-pass filtering the analog output voltage to obtain a filtered voltage.

[0019] In one embodiment, the switched-capacitor reference resistor includes M series-connected switched-capacitor resistors, and the resistance value of the switched-capacitor resistor is adjusted by the clock frequency. The resistance value of the switched-capacitor reference resistor is:

[0020]

[0021] Wherein, is the resistance value of the switched-capacitor reference resistor, is the clock frequency, is the sampling capacitor, and M is the number of series-connected switched-capacitor units.

[0022] In one embodiment, the calibration pseudo-resistor is composed of N parallel-connected calibration pseudo-resistor units.

[0023] The calibration pseudo-resistor unit includes two series-connected P-type transistors; the drains of the two P-type transistors are connected, the sources of the two P-type transistors are respectively configured as the input and output of the calibration pseudo-resistor unit, and the gates of the two transistors are connected and connected to the output of the low-pass filter; the body terminals of the two P-type transistors are connected to the drains or respectively connected to their respective sources; the aspect ratios and layout connection methods of the P-type transistors in the N calibration pseudo-resistor units are exactly the same.

[0024] The resistance value of the calibration pseudo-resistor unit is:

[0025]

[0026] Wherein, is the resistance value of the calibration pseudo-resistor unit; is the resistance value of the switched-capacitor reference resistor is the clock frequency, is the sampling capacitor, M is the number of series-connected switched-capacitor units, and N is the number of parallel-connected calibration pseudo-resistor units.

[0027] In one embodiment, the integrator is a passive or active integrator.

[0028] In one embodiment, the quantizer uses a dynamic comparator or a static comparator to compare the analog voltage and the common-mode voltage.

[0029] In one embodiment, the conversion switch is further configured to, if the input voltage is greater than the common-mode voltage, the first voltage is the input voltage, and the second voltage is the difference between twice the common-mode voltage and the input voltage.

[0030] If the input voltage is less than the common-mode voltage, the first voltage is the difference between twice the common-mode voltage and the input voltage, and the second voltage is the input voltage.

[0031] If the input voltage is equal to the common-mode voltage, both the first voltage and the second voltage are common-mode voltages.

[0032] Transmit the first voltage to the reference input terminal of the pseudo-resistor calibration module based on the ΔΣ modulator, and transmit the second voltage to the calibration input terminal of the pseudo-resistor calibration module based on the ΔΣ modulator.

[0033] In one embodiment, the replica pseudo-resistor includes: a floating voltage source and a replica pseudo-resistor unit composed of two P-type transistors; the resistance value of the replica pseudo-resistor is controlled by the floating voltage source.

[0034] The floating voltage source includes a unity-gain amplifier and a bootstrap capacitor;

[0035] The output of the unity-gain amplifier drives the lower plate of the bootstrap capacitor. The input terminal of the unity-gain amplifier is the input terminal of the floating voltage source, and the upper plate of the bootstrap capacitor is connected to the output terminal of the floating voltage source.

[0036] The voltage stored in the bootstrap capacitor is used to control the on-resistance of the P-type transistors in the replica pseudo-resistor unit.

[0037] In one embodiment, the aspect ratios and connection manners of the P-type transistors in the replica pseudo-resistor unit are the same as those of the calibration pseudo-resistor units in the calibration pseudo-resistor.

[0038] In one embodiment, the control voltage replication circuit includes: a sampling capacitor and a sampling switch.

[0039] At the sampling moment, sample the voltage difference between the sampled filtered voltage and the common-mode voltage (VCM), and store the voltage difference on the sampling resistor.

[0040] At the transmission moment, transmit the voltage difference on the sampling resistor to the replica pseudo-resistor through the sampling switch.

[0041] The above-mentioned on-chip pseudo-resistor calibration circuit based on the ΔΣ modulator realizes a continuously adjustable large resistor in the range of G ohms to T ohms on-chip based on the characteristics of simple implementation method, relatively accurate resistance value of switched-capacitor resistors, and large resistance value of pseudo-resistors in the ΔΣ modulator technology. Based on the characteristics of large loop gain, high precision, and small hardware overhead of the ΔΣ modulator, the resistance value of the pseudo-resistor is accurately calibrated to the resistance value of the switched-capacitor resistor, and its resistance value is amplified. Compared with traditional pseudo-resistors, this circuit realizes precise control of the resistance value, improves the robustness, temperature characteristics, and linearity of the resistor; compared with switched-capacitor resistors, this circuit realizes resistance values above the T ohm level; compared with the existing pseudo-resistor calibration circuit technologies, this circuit can achieve a wider resistance adjustment range, less hardware and power consumption overhead. Brief Description of the Drawings

[0042] Figure 1 It is a block diagram of an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator in one embodiment;

[0043] Figure 2 It is a schematic diagram of a reference pseudo-resistor calibration loop implemented based on ΔΣ modulator technology in another embodiment;

[0044] Figure 3 It is a schematic diagram of a replicated pseudo-resistor in another embodiment;

[0045] Figure 4 It is a schematic diagram of a direction comparator and a switch in another embodiment;

[0046] Figure 5 It is a graph of the measured resistance value versus the clock frequency in another embodiment;

[0047] Figure 6 It is a graph of the measured resistance value versus the temperature in another embodiment, where (a) is the graph of the measured resistance value versus the temperature under the first resistor value configuration, (b) is the graph of the measured resistance value versus the temperature under the second resistor value configuration, (c) is the graph of the measured resistance value versus the temperature under the third resistor value configuration, and (d) is the graph of the measured resistance value versus the temperature under the fourth resistor value configuration;

[0048] Figure 7 It is a multi-chip test result diagram in another embodiment, where (a) is the first multi-chip test result diagram, (b) is the second multi-chip test result diagram, (c) is the third multi-chip test result diagram, and (d) is the fourth multi-chip test result diagram;

[0049] Figure 8 It is a graph of the measured amplitude versus the total harmonic distortion in another embodiment. Detailed implementation manners

[0050] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] In one embodiment, as Figure 1 shown, an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator is provided. The on-chip pseudo-resistor calibration circuit includes: a direction comparator 10, a switch 20, a pseudo-resistor calibration module 30 based on a ΔΣ modulator, a control voltage replication circuit 40, and a replicated pseudo-resistor 50.

[0052] The direction comparator 10 is configured to determine a conversion control signal according to the magnitude relationship between the input voltage and the common-mode voltage.

[0053] Specifically, the input signal of the direction comparator 10 is the input voltage (VIN). By comparing the magnitude relationship between the input voltage and the common-mode voltage, a corresponding control signal (DIR) is input.

[0054] The direction comparator 10 controls the switching switch according to the magnitude relationship between the input voltage and the common-mode voltage, and outputs a corresponding control signal (DIR) to the switched-capacitor reference resistor and the calibration pseudo-resistor of the pseudo-resistor calibration module based on the ΔΣ modulator.

[0055] The switching switch 20 is used to output a first voltage and a second voltage according to the input voltage, the common-mode voltage, and the conversion control signal, and transmit them to the reference input terminal and the calibration input terminal of the pseudo-resistor calibration module 30 based on the ΔΣ modulator respectively.

[0056] Specifically, the input signals of the switching switch 20 are the input voltage VIN and the output of the direction comparator (DIR), and the output first voltage VA and second voltage VB are determined by the DIR signal.

[0057] The pseudo-resistor calibration module 30 based on the ΔΣ modulator is used to convert the first voltage into a reference current by using the switched-capacitor reference resistor, convert the second voltage into a calibration current by using the calibration pseudo-resistor, integrate, quantize, perform digital-to-analog conversion, and low-pass filter the difference between the reference current and the calibration current to obtain a filtered voltage, feedback the filtered voltage to the calibration pseudo-resistor, and transmit the filtered voltage to the control voltage replication circuit 40.

[0058] The switched-capacitor reference resistor will be driven by a clock, and its resistance value can be controlled by the clock frequency. Charge is injected into the integrator through this switched-capacitor reference resistor; the quantizer quantizes the output result of the integrator and drives the digital-to-analog converter; the low-pass filter filters the output of the digital-to-analog converter, inputs the filtered voltage to the gate of the calibration pseudo-resistor composed of P-type transistors to control the on-resistance of the P-type transistors, and the charge on the integrator can flow out through the calibration pseudo-resistor; by controlling the voltage replication circuit, the difference between the output voltage of the integrator and the common-mode voltage is replicated into the replication pseudo-resistor composed of P-type transistors to regulate the resistance value of the replication pseudo-resistor.

[0059] The control voltage replication circuit 40 is used to replicate the difference between the filtered voltage and the common-mode voltage to the replication pseudo-resistor 50.

[0060] The replication pseudo-resistor 50 is used to regulate its resistance value according to the replicated voltage, the common-mode voltage, and the input voltage, and calibrate its resistance value to several times the resistance value of the switched-capacitor reference resistor.

[0061] In the above-mentioned on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator, the circuit is based on the ΔΣ modulator technology, with a simple implementation method, relatively accurate resistance values of switched-capacitor resistors, and large resistance values of pseudo-resistors, achieving a continuously adjustable large resistor on the chip in the order of G ohms to T ohms; based on the characteristics of large loop gain, high precision, and small hardware overhead of the ΔΣ modulator, the resistance value of the pseudo-resistor is accurately calibrated to the resistance value of the switched-capacitor resistor, and its resistance value is amplified. Compared with traditional pseudo-resistors, this circuit realizes precise control of the resistance value, improving the robustness, temperature characteristics, and linearity of the resistor; compared with switched-capacitor resistors, this circuit realizes resistance values above the order of T ohms; compared with the existing pseudo-resistor calibration circuit technologies, this circuit can achieve a wider resistance adjustment range, less hardware and power consumption overhead.

[0062] In one embodiment, the pseudo-resistor calibration module 30 based on a ΔΣ modulator includes: a switched-capacitor reference resistor, a calibration pseudo-resistor, an integrator, a quantizer, a digital-to-analog conversion module, and a low-pass filter.

[0063] The switched-capacitor reference resistor is used to convert the first voltage into a reference current by using a series-connected switched-capacitor unit and transmit the reference current to the integrator.

[0064] The calibration pseudo-resistor is used to convert the second voltage into a calibration current by using a parallel-connected calibration pseudo-resistor unit and transmit the calibration circuit to the integrator.

[0065] The integrator is used to integrate the difference between the reference current and the calibration current to obtain an analog voltage.

[0066] Specifically, the input of the integrator is connected to voltage VX, and the output of the integrator is connected to the quantizer. The input currents of the integrator are I IN and I OUT , the integration capacitor in the integrator is C INT , and the output result V(t) of the integrator is the sum of the integration result of the difference between I IN and I OUT on the capacitor at a given time and the integration result V(t - T CLK ) at the previous moment. It can be expressed by the following formula:

[0067]

[0068] Among them, is the derivative of the adopted frequency.

[0069] The quantizer is used to compare the magnitudes of the analog voltage and the common-mode voltage, convert the comparison result into a digital code, and obtain a digital output voltage.

[0070] Specifically, the input signal of the quantizer is the output analog voltage of the integrator. By comparing its magnitude with the common-mode voltage, the comparison result is converted into a digital code for output. The comparator circuit inside the quantizer can use a dynamic comparator or a static comparator.

[0071] A digital-to-analog conversion module for converting the digital output voltage into an analog output voltage.

[0072] Specifically, the input signal of the digital-to-analog conversion module is the output digital code of the quantizer, and the output signal is the corresponding analog voltage.

[0073] A low-pass filter for performing low-pass filtering on the analog output voltage to obtain a filtered voltage.

[0074] Specifically, the input signal of the low-pass filter is the output analog voltage of the digital-to-analog converter, and the output signal is the filtered voltage.

[0075] In one embodiment, the switched-capacitor reference resistor includes: M series-connected switched-capacitor resistors. The resistance value of the switched-capacitor resistor is adjusted by the clock frequency. The resistance value of the switched-capacitor reference resistor is:

[0076]

[0077] Wherein, is the resistance value of the switched-capacitor reference resistor, is the clock frequency, is the sampling capacitor, and M is the number of series-connected switched-capacitor units.

[0078] Specifically, the switched-capacitor reference resistor (R REF ) formed by M switched-capacitor resistors. The resistance value of R REF can be adjusted by the clock frequency, and the resistance value is jointly determined by the clock frequency, the sampling capacitor ( ) and the number of series-connected switched-capacitors (M).

[0079] The sampling capacitor ( ) can be composed of a fixed-capacitance capacitor or a variable-capacitance capacitor. The number of series-connected switched-capacitors (M) can be configured by a digital code, and the values of and M can be configured according to the usage scenario.

[0080] Such as Figure 1 shown, one end of the switched-capacitor reference resistor is connected to voltage VA, and the other end is connected to voltage VX. The current flowing through the resistor is the input current (I IN ), and the current direction is from VA to VX.

[0081] In one embodiment, the calibration dummy resistor consists of N calibration dummy resistor units ( )(Connected in parallel; the calibration pseudo-resistance unit includes two P-type transistors connected in series; the drains of the two P-type transistors are connected, the sources of the two P-type transistors are respectively configured as the input and output of the calibration pseudo-resistance unit, and the gates of the two transistors are connected and connected to the output of the low-pass filter; the body terminals (the body terminal is the substrate of the P-type transistor) of the two P-type transistors are connected to the drains or respectively connected to their respective sources; the aspect ratios and layout connection methods of the P-type transistors in the N calibration pseudo-resistance units are exactly the same; the resistance value of the calibration pseudo-resistance unit is:

[0082]

[0083] Wherein, is the resistance value of the calibration pseudo-resistance unit; is the resistance value of the switched-capacitor reference resistor is the clock frequency, is the sampling capacitor, M is the number of series-connected switched-capacitor units, and N is the number of parallel-connected calibration pseudo-resistance units.

[0084] Specifically, the calibration pseudo-resistance composed of N calibration pseudo-resistance units ( ) connected in parallel finally realizes that the equivalent resistance (R CAL / N) of the N parallel-connected calibration pseudo-resistance units is equal to the reference resistance value (R REF ). Then the resistance value of a single calibration pseudo-resistance unit is NR REF , achieving an amplification of the resistance value.

[0085] The inputs, outputs, and gates of the N parallel-connected calibration pseudo-resistance units are respectively connected to form a calibration pseudo-resistance. The input terminal is connected to the voltage VX, the output terminal is connected to the voltage V B , and the current flowing through the calibration pseudo-resistance is the output current (I OUT ), and the current direction is from VX to VB. The average value of the voltage VB and the voltage VA is the common-mode voltage (VCM) of the circuit operation.

[0086] The two P-type transistors inside the calibration pseudo-resistance unit are connected in series, and the calibration pseudo-resistance units are connected in parallel. All the calibration pseudo-resistance units are connected to the output point of the low-pass filter.

[0087] In one embodiment, the integrator is a passive or active integrator.

[0088] In one embodiment, the quantizer uses a dynamic comparator or a static comparator to compare the analog voltage and the common-mode voltage.

[0089] In one embodiment, the switching switch 20 is further configured to, if the input voltage is greater than the common-mode voltage, the first voltage is the input voltage, and the second voltage is the difference between twice the common-mode voltage and the input voltage.

[0090] If the input voltage is less than the common-mode voltage, the first voltage is the difference between twice the common-mode voltage and the input voltage, and the second voltage is the input voltage.

[0091] If the input voltage is equal to the common-mode voltage, both the first voltage and the second voltage are the common-mode voltage.

[0092] Transmit the first voltage to the reference input terminal of the pseudo-resistor calibration module 30 based on the ΔΣ modulator, and transmit the second voltage to the calibration input terminal of the pseudo-resistor calibration module 30 based on the ΔΣ modulator.

[0093] In one embodiment, the replica pseudo-resistor 50 includes: a floating voltage source and a replica pseudo-resistor 50 unit composed of two P-type transistors; the resistance value of the replica pseudo-resistor 50 is controlled by the floating voltage source.

[0094] The floating voltage source includes a unity-gain amplifier and a bootstrap capacitor;

[0095] The output of the unity-gain amplifier drives the lower plate of the bootstrap capacitor, the input terminal of the unity-gain amplifier is the input terminal of the floating voltage source, and the upper plate of the bootstrap capacitor is connected to the output terminal of the floating voltage source.

[0096] The voltage stored in the bootstrap capacitor is used to control the on-resistance of the P-type transistors in the replica pseudo-resistor 50 unit.

[0097] Specifically, inside the replica pseudo-resistor, there is a replica pseudo-resistor unit composed of two P-type transistors and a floating voltage source. The aspect ratio of the P-type transistors in the replica pseudo-resistor unit is the same as that of the transistors in the calibration pseudo-resistor unit. The connection method is that the drains are connected and connected to the input of the floating voltage source, the sources of the two transistors respectively form the input and output of the replica pseudo-resistor, the gates are connected and connected to the output of the floating voltage source, and the connection of the body terminals needs to be consistent with the calibration pseudo-resistor unit. One end of the replica pseudo-resistor is connected to the common-mode voltage (VCM), and the other end is the input voltage (VIN).

[0098] The resistance value of the replica pseudo-resistor is controlled by the floating voltage source. The floating voltage source is composed of a unity-gain amplifier with a high input impedance cascaded with a bootstrap capacitor (C H ), and the output of the unity-gain amplifier is connected to the lower plate of the bootstrap capacitor (C H ). The input of the unity-gain amplifier is the input of the floating voltage source, and the upper plate of the bootstrap capacitor is the output of the floating voltage source.

[0099] In one embodiment, the aspect ratio and connection method of the P-type transistors in the replica pseudo-resistor 50 unit are the same as those of the calibration pseudo-resistor unit in the calibration pseudo-resistor.

[0100] In one embodiment, the control voltage replication circuit 40 includes: a sampling capacitor and a sampling switch.

[0101] At the sampling moment, the voltage difference between the sampled filtered voltage and the common-mode voltage (VCM) is stored on the sampling resistor.

[0102] At the transmission moment, the voltage difference on the sampling resistor is transmitted to the replica dummy resistor 50 through the sampling switch.

[0103] Specifically, the input signal of the control voltage replication circuit is the difference between the output analog voltage of the low-pass filter and the common-mode voltage. During the sampling period, this difference voltage is stored in the sampling capacitor, and during the transmission period, this difference voltage is transmitted to the capacitor (C H ) in the floating voltage source of the replica dummy resistor formed by P-type transistors.

[0104] In one embodiment, the schematic diagram of the reference dummy resistor calibration loop implemented based on delta-sigma (ΔΣ) modulator technology is as Figure 2 shown. Its principle is that the switched-capacitor reference resistor 1 is formed by connecting M switched-capacitor units 11 in series. The equivalent resistance value of the switched-capacitor unit 11 can be precisely controlled by the clock frequency. One end of the switched-capacitor reference resistor 1 is connected to one end of the calibration dummy resistor 2 formed by P-type transistors and is commonly connected to the input VX of the integrator. The integration voltage result on the integrator 3 is the difference between the injected charge of the switched-capacitor reference resistor 1 and the outflow charge of the calibration dummy resistor 2 formed by P-type transistors. The quantizer 4 quantizes the output result of the integrator 3 and drives the digital-to-analog converter 5, and the low-pass filter 6 filters the output of the digital-to-analog converter 5, outputs the filtered voltage 61 after removing high-frequency noise, and uses this voltage signal to control the on-resistance of the calibration dummy resistor 2 formed by P-type transistors. The above-mentioned switched-capacitor reference resistor 1, the calibration dummy resistor 2 formed by P-type transistors, the integrator 3, the quantizer 4, the digital-to-analog converter 5, and the low-pass filter 6 together constitute the ΔΣ modulator. The above-mentioned ΔΣ modulator has a large loop gain and a negative feedback response, making the charge flowing into the integrator 3 through the switched-capacitor reference resistor 1 equal to the charge flowing out of the integrator 3 through the calibration dummy resistor 2 formed by P-type transistors, and also making the VX voltage equal to the common-mode voltage VCM.

[0105] The input voltages of the above-mentioned reference pseudo-resistance calibration loop are VA and VB respectively. VA is the input voltage at one end of the above-mentioned switched-capacitor reference resistor 1, and VB is the input voltage at one end of the calibration pseudo-resistor 2 composed of the above-mentioned P-type transistors. The average value of VA and VB is equal to the common-mode voltage VCM, so that the switched-capacitor reference resistor 1 and the calibration pseudo-resistor 2 composed of P-type transistors have the same voltage drop, and the amount of charge flowing through them is equal, so that the resistance value of the switched-capacitor reference resistor 1 is equal to the resistance value of the calibration pseudo-resistor 2 composed of P-type transistors, realizing the calibration and control of the pseudo-resistance value calibration.

[0106] The resistance value ( ) of the switched-capacitor reference resistor 1 composed of M switched-capacitor units 11 connected in series can be adjusted by the clock frequency. The resistance value is determined by the clock frequency ( ), the sampling capacitor ( ) and the number of switched-capacitor units connected in series (M) together.

[0107] The calibration pseudo-resistor 2 composed of P-type transistors. The calibration pseudo-resistor is composed of N calibration pseudo-resistor units ( ) 21 connected in parallel. Each calibration pseudo-resistor unit 21 contains two P-type transistors connected in series. The connection method is that the drains of the transistors are connected, and the sources of the two transistors respectively form the input and output of the pseudo-resistor unit, and the gates are connected and connected to the output of the low-pass filter. The body terminals can be selected to be connected to the drains or connected to their respective sources respectively. The aspect ratios of the P-type transistors and the layout connection methods in the above-mentioned N calibration pseudo-resistor units 21 are exactly the same. The resistance value of the calibration pseudo-resistor 2 composed of the above-mentioned P-type transistors is , then the resistance value of a single calibration pseudo-resistor unit 21 can be calculated as follows:

[0108]

[0109] The calibration pseudo-resistor 2 composed of P-type transistors. The resistance value can be adjusted by the clock frequency ( ). The number of switched-capacitor units 11 connected in series M and the number of calibration pseudo-resistor units 21 connected in parallel N form a resistance amplification factor, realizing the amplification of the pseudo-resistance value to NM times the resistance value of the switched-capacitor unit.

[0110] The current flowing into the switched-capacitor reference resistor 1 can be calculated as:

[0111]

[0112] The current flowing out of the calibration pseudo-resistor 2 composed of P-type transistors can be calculated as:

[0113]

[0114] The input signal of integrator 3 is current I IN and I OUT The difference between and I. Integrator 3 can be composed of a passive or active integrator. The integration capacitor in the integrator is denoted as C INT The output result of the integrator is and The integral result of the difference between on the capacitor at a given time and the previous integral result The sum of can be calculated as:

[0115]

[0116] Quantizer 4, whose input signal is the output analog voltage of integrator 3. By comparing its magnitude with the common-mode voltage, the comparison result is converted into a digital code for output. The comparator circuit inside the quantizer can use a dynamic comparator or a static comparator. The above-mentioned digital-to-analog converter 5, whose input signal is the output digital code of quantizer 4, and the output signal is the corresponding analog voltage. The above-mentioned low-pass filter 6, whose input signal is the output analog voltage of the digital-to-analog converter 5, and the output signal is the filtered voltage 61, uses this filtered voltage to control the resistance value of the calibration pseudo-resistor 2 composed of P-type transistors.

[0117] As Figure 3 shown, the replicated pseudo-resistor 50 composed of P-type transistors, whose resistance value is controlled by a floating voltage source. The floating voltage source is composed of a high-input-impedance unity-gain amplifier 72 cascaded with a bootstrap capacitor 73. The output of the above-mentioned unity-gain amplifier 72 drives the lower plate of the bootstrap capacitor 73. The input of the unity-gain amplifier 72 is the input of the floating voltage source, and the upper plate of the bootstrap capacitor 73 is the output of the floating voltage source. The voltage stored in the bootstrap capacitor controls the on-resistance of the P-type transistor in the replicated pseudo-resistor unit 71. The aspect ratio and connection method of the P-type transistors in the replicated pseudo-resistor unit 71 are the same as those of the calibration pseudo-resistor unit, minimizing the systematic mismatch between transistors. The replicated pseudo-resistor 7 composed of P-type transistors, one end of its resistance needs to be connected to the common-mode voltage (VCM), and the other end is the input voltage (VIN).

[0118] As Figure 4 shown, the control voltage replication circuit 40 is composed of a sampling capacitor and a sampling switch. At the sampling moment, the voltage difference between the sampled filtered voltage 61 and the common-mode voltage (VCM) is sampled, and this difference voltage is stored in the sampling capacitor ; at the transmission moment, the voltage on the sampling capacitor is transmitted to the bootstrap capacitor 73.

[0119] The direction comparator 10 has an input signal as the input voltage VIN. By comparing the magnitude relationship between the input voltage VIN and the common-mode voltage VCM, it outputs a corresponding control signal (DIR) to control the output voltages VA and VB of the switching converter 20. When VIN is greater than VCM, VA is equal to VIN and VB is equal to 2*VCM - VIN. When VIN is less than VCM, VA is equal to 2*VCM - VIN and VB is equal to VIN. When VIN is equal to VCM, both VA and VB are VCM.

[0120] Figure 5 It shows the relationship between the clock frequency obtained by testing and the resistance value of the replicated pseudo-resistor, achieving a wide-range on-chip adjustable large resistor from 2.5 T ohms to 1.6 G ohms. Figure 6 (a) to (d) in it show the resistance value versus temperature curves obtained by testing under four resistor value configurations. Between -40°C and 60°C, the maximum fluctuation of the resistance value is 20%, which is more than two orders of magnitude higher than that of the traditional pseudo-resistor. In the case of high temperature, the configuration of large resistance values will increase the leakage current and reduce the resistance value. Figure 7 (a) to (d) in it show the four test results of 24 chip samples. The maximum resistance value change rate (three times the variance ratio to the mean) is 25%. Figure 8 It shows the relationship between the total harmonic distortion (THD) and the input voltage amplitude under different input voltage amplitudes. This calibration scheme achieves a large input range of 3.93 Vpp.

[0121] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0122] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator, characterized in that The upper pseudo-resistance calibration circuit includes: A direction comparator for determining a conversion control signal according to the magnitude relationship between an input voltage and a common-mode voltage; A conversion switch for outputting a first voltage and a second voltage according to the input voltage, the common-mode voltage, and the conversion control signal, and respectively transmitting them to the reference input terminal and the calibration input terminal of a pseudo-resistance calibration module based on a ΔΣ modulator; A pseudo-resistance calibration module based on a ΔΣ modulator for converting the first voltage into a reference current by using a switched-capacitor reference resistor, converting the second voltage into a calibration current by using a calibration pseudo-resistor, integrating, quantifying, performing digital-to-analog conversion, and low-pass filtering the difference between the reference current and the calibration current to obtain a filtered voltage, feeding back the filtered voltage to the calibration pseudo-resistor, and transmitting the filtered voltage to a control voltage copying circuit; A control voltage copying circuit for copying the difference between the filtered voltage and the common-mode voltage to a copying pseudo-resistor; A copying pseudo-resistor for adjusting its resistance value according to the copied voltage, the common-mode voltage, and the input voltage, and calibrating its resistance value to several times the resistance value of the switched-capacitor reference resistor; Wherein, the conversion switch is further configured such that if the input voltage is greater than the common-mode voltage, the first voltage is the input voltage, and the second voltage is the difference between twice the common-mode voltage and the input voltage; If the input voltage is less than the common-mode voltage, the first voltage is the difference between twice the common-mode voltage and the input voltage, and the second voltage is the input voltage; If the input voltage is equal to the common-mode voltage, both the first voltage and the second voltage are the common-mode voltage; Transmitting the first voltage to the reference input terminal of the pseudo-resistance calibration module based on a ΔΣ modulator, and transmitting the second voltage to the calibration input terminal of the pseudo-resistance calibration module based on a ΔΣ modulator.

2. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 1, wherein The pseudo-resistance calibration module based on a ΔΣ modulator includes: a switched-capacitor reference resistor, a calibration pseudo-resistor, an integrator, a quantizer, a digital-to-analog conversion module, and a low-pass filter; The switched-capacitor reference resistor is configured to convert the first voltage into a reference current by using a series of switched-capacitor units, and transmit the reference current to the integrator; The calibration pseudo-resistor is configured to convert the second voltage into a calibration current by using a parallel of calibration pseudo-resistor units, and transmit the calibration current to the integrator; The integrator is configured to integrate the difference between the reference current and the calibration current to obtain an analog voltage; The quantizer is configured to compare the magnitude of the analog voltage and the common-mode voltage, convert the comparison result into a digital code, and obtain a digital output voltage; The digital-to-analog conversion module is configured to convert the digital output voltage into an analog output voltage; The low-pass filter is configured to perform low-pass filtering on the analog output voltage to obtain a filtered voltage.

3. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 2, wherein The switched-capacitor reference resistor includes: M series-connected switched-capacitor resistors, the resistance value of the switched-capacitor resistor is adjusted by a clock frequency, and the resistance value of the switched-capacitor reference resistor is: ； Among them, is the resistance value of the switched-capacitor reference resistor, is the clock frequency, is the sampling capacitor, and M is the number of cascaded switched-capacitor units.

4. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 2, wherein The calibration pseudo-resistor is composed of N parallel-connected calibration pseudo-resistor units; The calibration pseudo-resistance unit includes two P-type transistors connected in series; the drains of the two P-type transistors are connected, the sources of the two P-type transistors are respectively configured as the input and output of the calibration pseudo-resistance unit, and the gates of the two transistors are connected and connected to the output of the low-pass filter; The body terminals of the two P-type transistors are connected to the drains or respectively connected to their respective sources; The aspect ratios and layout connection methods of the P-type transistors in the N calibration pseudo-resistance units are exactly the same; The resistance value of the calibration pseudo-resistance unit is: ； wherein, is for calibrating the resistance value of the pseudo-resistance unit; is the resistance value of the switched-capacitor reference resistor, is the clock frequency, is the sampling capacitor, M is the number of series-connected switched-capacitor units, and N is the number of parallel-connected calibration pseudo-resistance units.

5. The on-chip pseudo-resistance calibration circuit based on a ΔΣ modulator according to claim 2, wherein The integrator is a passive or active integrator.

6. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 2, wherein The quantizer uses a dynamic comparator or a static comparator to compare the analog voltage and the common-mode voltage.

7. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 1, characterized in that, The replicated pseudo-resistance includes: a floating voltage source and a replicated pseudo-resistance unit composed of two P-type transistors; the resistance value of the replicated pseudo-resistance is controlled by the floating voltage source; The floating voltage source includes a unity-gain amplifier and a bootstrap capacitor; The output of the unity-gain amplifier drives the lower plate of the bootstrap capacitor, the input of the unity-gain amplifier is the input of the floating voltage source, and the upper plate of the bootstrap capacitor is connected to the output of the floating voltage source; The voltage stored in the bootstrap capacitor is used to control the on-resistance of the P-type transistors in the replicated pseudo-resistance unit.

8. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 7, wherein The aspect ratios and connection methods of the P-type transistors in the replicated pseudo-resistance unit are the same as those of the calibration pseudo-resistance unit in the calibration pseudo-resistance.

9. The on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator according to claim 1, wherein The control voltage copying circuit includes: a sampling capacitor and a sampling switch; At the sampling moment, sample the voltage difference between the filtered voltage and the common-mode voltage (VCM), and store the voltage difference on the sampling resistor; At the transmission moment, transmit the voltage difference on the sampling resistor to the replicated pseudo-resistance through the sampling switch.

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