Satellite-borne high-performance processing system

Abstract

The invention discloses a satellite-borne high-performance processing system which comprises a high-speed data SRIO + 10GE network switching module, a TTE network switching module, a high-speed data processing module, an intelligent module and a storage module. The high-speed data SRIO + 10GE network switching module is respectively connected with the high-speed data processing module, the intelligent module and the storage module, and is a center for carrying out high-speed data SRIO switching among the high-speed data processing module, the intelligent module and the storage module; the TTE network switching module is respectively connected with the high-speed data processing module, the intelligent module and the storage module, and is a time determination high-reliability data exchange center among the high-speed data processing module, the intelligent module and the storage module; and the high-speed data SRIO + 10GE network switching module is connected with the TTE network switching module so as to realize interaction of SRIO high-speed data and TTE time determination high-reliability data. The method solves the problems that an existing satellite information system is not high in processing capacity, not enough in data transmission bandwidth and low in processing real-time performance, and has remarkable advantages.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite information systems, and particularly to an on-board high-performance processing system. Background Art

[0002] The existing satellite information system consists of a management unit and several interface expansion units. The management unit controls each interface expansion unit through a serial RS422 interface and controls other system devices through a 1553B bus. The management unit is the control core of the satellite information system and is used to complete functions such as remote control data processing, telemetry data acquisition, telemetry data packaging, data operation, and system management. In the standard system configuration, the management unit includes eight different types of modules, which are: channel gateway module, measurement and control encryption module, command module, telemetry module, CPU module, power supply module, time base IO module, and data storage and multiplexing module. The interface expansion unit is an extension of the management unit's telemetry, remote control, power distribution, drive, etc. functions and is controlled by the management unit through a serial interface or a bus.

[0003] With the continuous progress of high-performance embedded system technology, the requirements for inter-chip and inter-board interconnection in terms of bandwidth, cost, flexibility, and reliability are increasing day by day. Traditional interconnection technologies, such as processor buses, PCI buses, and Ethernet, are difficult to meet these emerging requirements. The current satellite information system exposes several defects: the connection relationship is intricate, with a large number and variety of types, resulting in frequent low-level and repetitive work; the function density is low, the computing and processing capabilities are insufficient, the scalability is limited, and the upgrade ability is weak; the data utilization rate is relatively low, the autonomous management ability is insufficient, and the dependence on external control is relatively high; the link is long, the time delay is inconsistent, the bandwidth is uneven, the fault tolerance is poor, the fault is easy to spread, and there are barriers between protocols.

[0004] Therefore, in order to improve the information interaction capabilities within the satellite, between satellites, and between the satellite and the ground, it is very important to design an on-board high-performance processing system to overcome the above problems.

[0005] It can be understood that the above statements only provide background technology related to the present invention and do not necessarily constitute prior art. Summary of the Invention

[0006] The object of the present invention is to provide an on-board high-performance processing system to solve the problems of low processing capacity, insufficient data transmission bandwidth, and low processing real-time performance of the existing satellite information system.

[0007] To achieve the above object, the present invention provides a spaceborne high-performance processing system, comprising: a high-speed data SRIO + 10GE network switching module, a TTE network switching module, a high-speed data processing module, an intelligent module, and a storage module; the high-speed data SRIO + 10GE network switching module is respectively connected to the high-speed data processing module, the intelligent module, and the storage module, and is the center for high-speed data SRIO exchange among the high-speed data processing module, the intelligent module, and the storage module; the TTE network switching module is respectively connected to the high-speed data processing module, the intelligent module, and the storage module, and is the center for time-deterministic and highly reliable data exchange among the high-speed data processing module, the intelligent module, and the storage module; the high-speed data SRIO + 10GE network switching module is connected to the TTE network switching module to achieve the interaction of SRIO high-speed data and TTE time-deterministic and highly reliable data.

[0008] Optionally, the spaceborne high-performance processing system further includes a power supply module, which is respectively connected to the high-speed data SRIO + 10GE network switching module, the TTE network switching module, the high-speed data processing module, the intelligent module, and the storage module to provide power.

[0009] Optionally, the high-speed data SRIO + 10GE network switching module, the TTE network switching module, the high-speed data processing module, the intelligent module, the storage module, and the power supply module are all connected to the VPX backplane connector on the spaceborne high-performance processing system to achieve information transmission among the modules; and the high-speed data SRIO + 10GE network switching module, the TTE network switching module, the high-speed data processing module, the intelligent module, the storage module, and the power supply module are all connected to the front panel of the spaceborne high-performance processing system, enabling external products to communicate with each module through interfaces.

[0010] Optionally, the spaceborne high-performance processing system further includes a plurality of expansion modules, which are connected to the VPX backplane connector on the spaceborne high-performance processing system through standard interfaces to expand the functions of the spaceborne high-performance processing system.

[0011] Optionally, each module in the spaceborne high-performance processing system includes a primary module and a backup module to ensure that critical tasks can continue to run using the backup module when the primary module fails.

[0012] Optionally, the intelligent module includes: at least two AI processor chips, a first 10 Gigabit Ethernet chip, a network auto-identification chip, and a storage chip; the first AI processor chip serves as the module controller and realizes data interaction with the TTE terminal module through a PCIe interface; the second AI processor chip is an intelligent operation processor and is connected to the first 10 Gigabit Ethernet chip to realize high-speed image processing; the network auto-identification chip is respectively connected to the first AI processor chip and the second AI processor chip and is responsible for data transmission between the two processing chips.

[0013] Optionally, the intelligent module further includes a clock synchronization circuit, and this clock synchronization circuit provides a clock signal and a synchronization signal for the intelligent module.

[0014] Optionally, the high-speed data processing module includes: several groups of digital signal processors, a RapidIO switching chip, and a first FPGA chip; each group of the digital signal processors is connected to the RapidIO switching chip to realize the RapidIO data exchange function; the first FPGA chip is connected to the RapidIO switching chip to realize the processing of RapidIO data.

[0015] Optionally, the storage module includes: a multi-core processor, which serves as the management center and realizes the construction and management of a data directory; a PCIe switching chip, which is connected to the multi-core processor to realize data exchange and transmission; a second FPGA chip, which serves as a coprocessor and is connected to the PCIe switching chip to provide a high-speed physical link and realize high-speed data transmission and instruction exchange.

[0016] Optionally, the high-speed data SRIO + 10GE network switching module includes: a high-performance processor chip, which serves as the main processor and has 1 SRIO interface, 2 PCIe interfaces, and 2 1GE interfaces; a first SRIO chip, which is connected to the SRIO interface of the high-performance processor chip to realize high-speed data interaction of SRIO signals between the primary modules; a second SRIO chip, which is connected to the first SRIO chip to realize high-speed data interaction of SRIO signals between the backup modules; a TTE terminal module, which is connected to one of the PCIe interfaces of the high-performance processor chip to realize command interaction between the TTE bus interface and the outside; a second 10 Gigabit Ethernet chip, which is connected to the other PCIe interface of the high-performance processor chip; a routing chip, which is connected to the second 10 Gigabit Ethernet chip through an inter-board high-speed connector to lead out a 10GE network; wherein, for the 2 1GE interfaces of the high-performance processor chip, one is connected to the backplane VPX connector, and the other is expanded into 2 1GE interfaces through a selection switch, one is connected to the front panel for debugging, and the other is connected to the backplane VPX connector.

[0017] In summary, compared with the prior art, a spaceborne high-performance processing system provided by the present invention has at least the following beneficial effects:

[0018] (1) The high-performance processing system provided by the present invention has high floating-point processing ability while meeting the low-power consumption requirement, that is, it improves the computing power while reducing the power consumption, effectively improving the real-time processing ability of the satellite information processing system. In satellite image processing applications, it can realize real-time data acquisition and processing, realize applications such as on-board autonomous task decision-making and heuristic intelligent task reasoning, improve the overall service ability of satellite remote sensing, and can quickly respond to emergency situations;

[0019] (2) The high-performance processing system provided by the present invention has the ability to preprocess payload data, including filtering, recognition, and target extraction of payload images in multiple modes, and functions such as recognizing, screening, and rejecting real-time payload data in multiple modes according to time and position information;

[0020] (3) The high-performance processing system provided by the present invention is designed according to the SpaceVPX electronic system architecture, adopts standardized and generalized module design, and the single-board dual-machine redundancy mode. The relationship between modules is simple, and it supports module-based testing and production assurance, which is convenient for system integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is the overall block diagram of a spaceborne high-performance processing system provided by an embodiment of the present invention;

[0022] Figure 2 is the schematic diagram of the intelligent module of a spaceborne high-performance processing system provided by an embodiment of the present invention;

[0023] Figure 3 is the schematic diagram of the high-speed data processing module of a spaceborne high-performance processing system provided by an embodiment of the present invention;

[0024] Figure 4 is the schematic diagram of the large-capacity storage module of a spaceborne high-performance processing system provided by an embodiment of the present invention;

[0025] Figure 5 is the schematic diagram of the high-speed data exchange module of a spaceborne high-performance processing system provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The following further elaborates on the present invention by Figures 1 to 5 detailedly describing a preferred specific embodiment in conjunction with the attached

[0027] It should be noted that the accompanying drawings are in a very simplified form and use non-precise scales, solely for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention, rather than being used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have any substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.

[0028] It should be noted that in the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements expressly listed, but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0029] As Figure 1 shown, the present invention provides a spaceborne high-performance processing system, which is implemented using the SpaceVPX system architecture and includes: a high-speed data SRIO (Serial RapidIO) + 10GE (10 Gigabit Ethernet) network switching module, a TTE (Time-triggered Ethernet) network switching module, a high-speed data processing module, an intelligent module, a storage module, and a power module.

[0030] It can be understood that each of the above modules is connected to the VPX backplane connector on the spaceborne high-performance processing system to achieve information transmission between the modules; and each of the above modules is connected to the front panel of the spaceborne high-performance processing system, enabling external products to communicate with each module through the interface.

[0031] Among them, the power module is respectively connected to the other modules to provide power for the other modules; the high-speed data SRIO + 10GE network switching module is respectively connected to the high-speed data processing module, the intelligent module, and the storage module, and is the center for high-speed data SRIO exchange among these three modules and also the center for the entire system to exchange high-speed data with the outside; the TTE network switching module is respectively connected to the high-speed data processing module, the intelligent module, and the storage module, and is the center for time-determined high-reliability data exchange among these three modules and also the center for the entire system to exchange time-determined high-reliability data with the outside.

[0032] In addition, the high-speed data SRIO + 10GE network switching module is also connected to the TTE network switching module to achieve the interaction of SRIO high-speed data and TTE time-determined high-reliability data. Specifically, in this embodiment, the high-speed data SRIO + 10GE network switching module and the TTE network switching module are connected by a 1GE (1 Gigabit Ethernet) network interface.

[0033] Furthermore, a spaceborne high-performance processing system according to the present invention further includes several expansion modules capable of expanding the functions of the spaceborne high-performance processing system and adding different functions to the spaceborne high-performance processing system. The expansion module is connected to the VPX backplane connector on the spaceborne high-performance processing system through a standard interface, ensuring the compatibility between modules and the upgradability of the spaceborne high-performance processing system. For example, by adding a specific GPU module, the image data processing ability of the system can be improved to achieve a better processing effect. In addition, the addition of the expansion module not only enriches the application scenarios of the spaceborne high-performance processing system but also enables the spaceborne high-performance processing system to adapt to changing technical requirements and mission requirements.

[0034] Even further, in the present invention, each module in the spaceborne high-performance processing system includes a primary module and a backup module to prevent the primary module from failing. When the primary module fails, the backup module can be immediately used to replace the primary module to ensure that critical tasks can still continue to run when the primary module fails, thereby improving the stability and reliability of the entire system.

[0035] Furthermore, as Figure 2 shown, the intelligent module includes: at least two AI processor chips, a 10 Gigabit Ethernet chip, a network auto-identification chip, and a storage chip. In this embodiment, the AI processor chip uses the artificial intelligence processor chip Yulong810A, the 10 Gigabit Ethernet chip uses the Intel 82599 chip, the network auto-identification chip uses the RTL8367N-VB-CG chip, and the storage chip uses a DDR chip and a FLASH chip.

[0036] Further, the first AI processor chip 21 serves as a module controller and realizes data interaction with the TTE terminal module 23 in the form of a PCIe (Peripheral Component Interconnect Express) interface, realizes command interaction between the TTE bus interface and the outside, and realizes functions such as task allocation; the second AI processor chip 22 serves as an intelligent computing processor, which is connected to the first 10 Gigabit Ethernet chip 25 to realize intelligent computing, including floating-point operation, fixed-point operation, deep learning, neural network algorithms, and can expand the image interface to realize functions such as high-speed image processing; the network automatic identification chip is respectively connected to the first AI processor chip 21 and the second AI processor chip 22 and is responsible for data transmission between the two processing chips.

[0037] Further, the first module controller AI processor chip 21 integrates 1 PCIe interface, 1 1GE, and 1 serial RapidIO. The PCIe interface is used to integrate the daughter board of the TTE terminal module 23; the 1GE interface is connected to the network automatic identification chip 24; 1 bandwidth-configurable RapidIO interface (*1, *2, *4) is used to connect to the backplane VPX connector to interact with other modules for data. The second AI processor chip 22, in addition to providing functions related to intelligent computing, the internal RapidIO interface (*1, *2, *4) is also used to connect to the backplane VPX connector to interact with other modules for data; the 1GE interface is connected to the network automatic identification chip 24; the TTE bus interface is used to connect to the first 10 Gigabit Ethernet chip 25 to generate 2 external 10GE Ethernet interfaces. The RapidIO interface realizes high-speed data input / output with a transmission rate of up to 20 Gbps. The other two ports of the network automatic identification chip 24 connect 2 1GE interfaces to the front panel. Finally, the 2 1GE interfaces on the front panel and the 1GE interfaces of the two AI processor chips form an on-chip routing module, which can connect the front panel interfaces to the corresponding AI processor chips through program configuration to realize debugging of each AI processor chip, and at the same time, it can also realize data interaction between the first AI processor chip and the first AI processor chip.

[0038] Furthermore, in the present invention, each AI intelligent processor chip is composed of key components such as a main processor unit, an AI coprocessor unit, an image processing unit, an on-chip bus, a peripheral interface unit, and on-chip storage. The AI intelligent processor chip integrates a 4-core ARM Cortex-A9 processor with a peak computing power of up to 12 TOPS, a floating-point processing ability of 64 GFLOPS, and a power consumption ratio of 2. In addition, the AI intelligent processor chip adopts the FD-SOI (Fully Depleted Silicon on Insulator) manufacturing process. It can be understood that this manufacturing process has more precise control over the transistor channels, effectively reducing the parasitic capacitance effect, thereby improving the operating speed of the AI intelligent processor chip. Compared with traditional bulk silicon materials, the operating speed of SOI devices can be increased by 20% - 35%. At the same time, the latch-up effect is eliminated, the interference of substrate pulse current is suppressed, and the incidence of soft errors is significantly reduced; endowing the AI intelligent processor chip with the characteristics of high performance, high reliability, and low power consumption.

[0039] Furthermore, it should be noted that the intelligent module further includes a clock synchronization circuit, which can provide a clock signal and a synchronization signal for the intelligent module.

[0040] In addition, the main processor unit in the AI intelligent processor chip is equipped with rich storage and interface resources, facilitating the rapid and efficient development of AI software programs. The main processor unit supports multiple AI development frameworks, such as TensorFlow, Caffe, etc., and is compatible with software libraries such as OPENCL, OPENVX, OPENCV, etc., making AI development possible. At the same time, the main processor unit also supports real-time embedded operating systems such as eCOS, VxWorks, Linux, etc., and can easily implement the high-performance multi-core parallel processing design of an embedded real-time control system.

[0041] Furthermore, in this embodiment, as Figure 3 shown, the high-speed data processing module uses several groups of digital signal processors 32, and each group of the digital signal processors 32 contains 2 chips. Then, in the embodiment of the present invention, 4 high-performance 8-core floating-point digital signal processors (Digital Signal Processor, DSP), namely TMS320C6678, are used, and the total floating-point operation ability reaches 640G GFLOP@1.25GHz.

[0042] Furthermore, the four digital signal processors 32 are divided into two groups, with two in each group. The two digital signal processors 32 within the same group exchange data through a dedicated DSP Hyperlink interface. In addition, the four digital signal processors 32 can utilize a RapidIO switching chip 31 (CPS1848 chip) to achieve the RapidIO data exchange function. At the same time, the model of the first FPGA chip 33 is ZC7045, which is responsible for signal preprocessing of the payload data. The peripheral memory of the first FPGA chip 33 includes a DDRIII memory chip and a FLASH memory chip. Among them, the DDRIII memory chip is used for the high-speed cache of the FPGA chip; the FLASH memory chip includes: a parallel interface NOR FLASH memory chip and an SPI interface NOR FLASH memory chip. The parallel interface NOR FLASH memory chip is used to store the key data during the data processing of the first FPGA chip 33 to ensure its non-volatility; the SPI interface NOR FLASH is used to store the specific program codes of the processor and the first FPGA chip 33.

[0043] In addition, it should be noted that the digital signal processor 32 communicates with the first FPGA chip 33 through multiple interconnection networks such as I2C, EMIF, and SRIO.

[0044] Specifically, in this embodiment, a digital signal processing system is composed of a digital signal processor 32 (TMS320C6678) and storage chips (DDR3, FLASH), and various high-speed communication interfaces are externally expanded according to application requirements. This digital signal processing system is the integrated image processing unit in the module. Among them, each digital signal processor is externally connected to 4 memory chips, with a single-chip storage capacity of 512MB and a total capacity of 2GB. The reference voltage and termination power supply of the DDR3 storage chip adopt LTC3618. One RGMII is led out from the interface of the digital signal processor 32, and a 10 / 100M adaptive PHY and transformer are externally expanded, and one interface for system debugging is led out. In addition, in this embodiment, the 4 digital signal processors 32 in the present invention are divided into 2 groups. Two digital signal processors in each group perform high-speed communication through a 4Lane HyperLink interface, and the two digital signal processors 32 can implement an SRIO circuit design with an interconnection interface with a maximum line rate of 50G. In addition, in the present invention, the SRIO of each digital signal processor 32 is connected to the GTX (Gigabit Transceiver) of the first FPGA chip 33 to achieve 4x SRIO, and the maximum bandwidth can reach 40Gbps. Each signal requires an AC coupling capacitor, and the capacitor is located close to the receiving end. Each digital signal processor 32 has two SPI (Serial Peripheral Interface) chip select signals and can be connected to two SPI peripherals. In this system, the CS0 (Chip Select0) signal line of the SPI of each digital signal processor 32 is externally connected to a 32MB Flash storage chip for power-on program loading.

[0045] Further, when configuring the FLASH memory chip, the commonly used methods are the SPI FLASH loading method and the BPI FLASH loading method. Among them, the SPI FLASH loading method has the advantages of low price, simple design, and small board area, while the BPI FLASH loading method has the characteristics of large capacity and fast loading speed. In the present invention, since the PCIE interface has requirements for the loading time of the on-board high-performance processing system, once the loading time is too long, it may cause the main control board to fail to recognize when powered on. Therefore, the parallel loading method, that is, the BPI FLASH loading method, is adopted when configuring the FLASH memory chip in the present invention. Further, to meet the storage and calculation requirements of the first FPGA chip 33 during data processing, it is also necessary to expand a memory through the MCB (Memory Controller Block) in the first FPGA chip 33. In the embodiment of the present invention, a 2GB DDR3 memory is selected to meet the requirements of data caching for each communication interface.

[0046] Further, as Figure 4 shown, the storage module uses 1 ARM architecture multi-core processor 41 of model HI3559 as the management center to realize the construction and management of the data directory, and realizes the external interaction function through the gigabit network; uses 1 second FPGA chip 42 as a coprocessor to provide a high-speed physical link to ensure that the theoretical maximum bandwidth of data input is 50 Gbps, and ensures that the theoretical bandwidth is greater than 48 Gbps after deducting the 64 / 66 coding overhead, providing a high-speed serial interconnection for continuous acquisition and recording of data; uses 1 PCIe switch chip 43 of model PEX8749 to access the high-speed PCIe3.0 NVMe1.2 protocol solid-state disk storage. Among them, the maximum number of such solid-state disk storages supported is 6, and the storage capacity can be expanded up to 12 TB at most.

[0047] Among them, the second FPGA chip 42 and the PCIe switch chip 43 are connected through a high-speed interface (such as PCIe, AXI, etc.) to realize high-speed data transmission and instruction exchange; the multi-core processor 41 and the PCIe switch chip 43 are also connected through a high-speed interface to realize data exchange and transmission.

[0048] It should be noted that the large-capacity storage module provides an expansion interface externally. Its front panel provides 1 communication serial port, 1 1000M-Base-T network interface, and 1 FPGA debugging interface; its back VPX connector interface provides 4 x4 RapidIO interfaces, 2 TTE network interfaces, 1 RS422 interface, 1 PPS interface, and 1 I2C interface.

[0049] Specifically, in the embodiments of the present invention, if the large-capacity storage module wants to achieve a capture and recording speed greater than 5 GBps, then the data flow capacity of each link needs to be considered in the design, which specifically includes the following aspects:

[0050] 1) Acquisition data input capacity

[0051] The acquisition data is 2-way 4x high-speed serial. At this time, the high-speed serial data enters the large-capacity storage module through the high-speed physical link provided by the FPGA chip. The design rate of 2-way 4x high-speed serial is up to 6.25 Gbps at most, and the theoretical maximum bandwidth of external data input is 50 Gbps. After deducting the 64 / 66 coding overhead, the theoretical bandwidth is greater than 48 Gbps. Thus, high-speed serial interconnection is provided for continuous capture and recording requirements, meeting the external interface interconnection requirements greater than 40 Gbps (5 GBps).

[0052] 2) FPGA chip cache processing capacity

[0053] The recording function is mainly completed by the second FPGA chip 42. The second FPGA chip 42 uses XC7VX690T and can provide an interface capacity not less than DDR3 1800. The theoretical total bandwidth of the 64-bit interface of DDR3 1800 is 14.4 GBps, and its actual efficiency can reach about 11.52 GBps at about 80%. However, since the recording process requires simultaneous read and write operations for DDR3 1800, the total bandwidth is only half of the unidirectional bandwidth, which is 5.76 GBps, greater than 5 GBps.

[0054] 3) PCIE SSD's own read and write speed

[0055] The measured stable read and write speed of a single-way PCIE SSD is greater than 1300 MBps, and the maximum of 4-way can provide an access bandwidth greater than 5 GB / s. It meets the requirement of 5 GB / s.

[0056] Furthermore, in this embodiment, the functional design of the ARM architecture multi-core processor HI3559 chip is as follows:

[0057] 1) The multi-core processor 41 is connected to the OBC (On-Board Computer) through the LPC (Low-Pin-Count) bus and shares the 256 MB NORFLASH storage chip externally attached to the OBC with the second FPGA chip 42.

[0058] 2) Configure 1-way x2 PCIE interface to be interconnected with the PCIE switch chip 43 to implement PPC network data exchange and store the data into the SSD solid-state disk under the PCIE switch chip 43.

[0059] Further, the design of the PCIe switch chip 43 is as follows:

[0060] 1) The PCIE switch chip 43 is designed with 6 PCIE X2 buses respectively connected to 6 SSD solid-state drives, and 2 PCIE X8 buses are designed to connect to the second FPGA chip 42. One PCIE X2 bus is output to the multi-core processor HI3559, and 2 PCIE X8 buses are output to the VPX connector P2 port, which is used for data exchange between the FPGA, PPC and SSD solid-state drives to achieve the solid-state storage function, and can also achieve board-level cascading for expansion.

[0061] 2) The OBC outputs a single-ended control signal to the PCIe switch chip 43 to realize the reset control and status reading of the PEX8749.

[0062] Further, as Figure 5 shown, the high-speed data SRIO + 10GE network switching module includes: a high-performance processor chip 51, whose model is P5020; a first SRIO chip 52 and a second SRIO chip 53, both of whose models are CPS-1848; a second 10 Gigabit Ethernet chip 54, whose model is Intel 82599; a routing chip 55, whose model is CTC5160; a TTE terminal module; and a storage chip.

[0063] Specifically, the high-speed data SRIO + 10GE network switching module uses the high-performance processor chip 51 as the main processor. The high-performance processor chip 51 provides 1 SRIO interface, 2 PCIe interfaces and 2 1GE interfaces. One of the PCIe interfaces realizes data interaction with the TTE terminal module, realizes command interaction between the TTE bus interface and the outside, and realizes functions such as task allocation, etc.; the other PCIe interface is used to connect to the second 10 Gigabit Ethernet interface chip 54, and after passing through the 10 Gigabit Ethernet chip, 1 SFI signal is output, and it is connected to the switch daughter board through a high-speed board-to-board connector, and 6 10 Gigabit Ethernet SFI interfaces are led out by the routing chip 55 and connected to the SFP+ optical module to realize high-speed data connection; 1 SRIO interface is connected to the first SRIO chip 52 for high-speed data interaction with the SRIO signal on the VPX backplane; 2 1GE interfaces, one of which is directly connected to the backplane VPX connector, and the other is expanded into 2 1GE interfaces through the relay chip TS3L501ERUAR, one is connected to the front panel for debugging, and the other is connected to the backplane VPX connector. The storage chip is connected to the high-performance processor chip 51 to realize data storage.

[0064] It should be noted that the high-speed data exchange SRIO interface is equipped with a total of 20 channels, which are generated by two of the said SRIO chips, and each of the said SRIO interfaces can be configured with bandwidths of *1, *2, and *4 widths, and the highest bandwidth can be configured to 20 Gpbs, so as to achieve high-speed data interaction internally. Among them, the first SRIO chip 52 is used to communicate with the primary module, and the second SRIO chip 53 is connected to the first SRIO chip 52 and is used to communicate with the backup module.

[0065] Furthermore, in the high-speed data SRIO + 10GE network switching module, the external high-speed data interfaces are all implemented through 10GE Ethernet; the implementation of the 10GE Ethernet is to connect the PCIe interface of the high-performance processor chip 51 to the interface of the second 10 Gigabit Ethernet chip 54, and output 1 channel of 10GE Ethernet in the SFI form through this 10 Gigabit Ethernet chip 54, and connect it to the routing chip 55 of the routing daughter board through the high-speed inter-board connector. The 10GE network in the SFI form is led out by this routing chip 55 and finally connected to the SFP+ optical module on the panel.

[0066] Furthermore, in the high-speed data SRIO + 10GE network switching module, the TTE dual-redundancy network is mainly implemented by the TTE terminal and the relay chip TS3L501ERUAR. The TTE terminal is respectively connected to the first AI processor chip 21 and the second AI processor chip 22 through PCIe. The two 1GE networks output by the TTE terminal are divided into 4 1GE networks through the relay chip TS3L501ERUAR, and 2 of the 1GE networks are connected to the front panel through the RJ45 interface to achieve the external network port configuration, and the other 2 1GE networks are connected to the VPX connector to achieve the acquisition of telemetry information inside the receiving device and the control of remote control commands inside the device.

[0067] Further, the on-board high-performance processing system further includes Time-Triggered Ethernet (TTE). The Time-Triggered Ethernet is respectively connected to the first AI processor chip 21 and the second AI processor chip 22 through PCIe. Among them, the TTE adopts an existing TTE-MDI module. One PCIE signal goes to the TTE-MDI module, and the two TTE signals led out by the TTE-MDI module each pass through a Gigabit Ethernet LAN chip and are each divided into two paths. One path is connected to the front panel through RJ45, and the other path is connected to other modules through a VPX connector; the two 1GE networks are connected to the front panel through RJ45 interfaces to realize the external network port configuration. The two 1GE networks are connected to the VPX connector to receive the telemetry information collection inside the device and the remote control command control inside the device, realizing the real-time and reliable transmission of safety-critical data between modules.

[0068] In summary, the present invention provides an on-board high-performance processing system, which improves the computing power of the information processing system, shortens the algorithm calculation time of satellite application software, increases the data stream bandwidth, improves the real-time processing ability of the satellite information processing system, and solves the problems of low processing ability, insufficient data transmission bandwidth, and low processing real-time performance in the existing satellite information system. In addition, the present invention is based on high-performance artificial intelligence chips, digital signal processors, programmable logic devices, and high-speed large-capacity memories as hardware support. It receives payload source data through a high-speed data exchange module, preprocesses it through a high-speed data processing module, and uses artificial intelligence, deep learning, and computing technologies to realize applications such as satellite autonomous mission decision-making and heuristic intelligent mission reasoning.

[0069] Although the content of the present invention has been introduced in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A high-performance onboard processing system, characterized in that: include: High-speed data SRIO+10GE network switching module, TTE network switching module, high-speed data processing module, intelligent module and storage module; The high-speed data SRIO+10GE network switching module is connected to the high-speed data processing module, the intelligent module and the storage module respectively, and serves as a hub for high-speed data SRIO switching between the high-speed data processing module, the intelligent module and the storage module; The TTE network switching module is connected to the high-speed data processing module, the intelligent module and the storage module respectively, and serves as a hub for time-determined high-reliability data exchange between the high-speed data processing module, the intelligent module and the storage module; The high-speed data SRIO+10GE network switching module is connected to the TTE network switching module to achieve the interaction between SRIO high-speed data and TTE time-determined high-reliability data.

2. The onboard high performance processing system according to claim 1, characterized in that: The onboard high-performance processing system also includes a power supply module, which is respectively connected to the high-speed data SRIO+10GE network switching module, the TTE network switching module, the high-speed data processing module, the intelligent module and the storage module to provide power.

3. The onboard high performance processing system according to claim 2, characterized in that: The high-speed data SRIO+10GE network switching module, TTE network switching module, high-speed data processing module, intelligent module, storage module and power module are all connected to the VPX backplane connector on the onboard high-performance processing system to realize information transmission between the modules; The high-speed data SRIO+10GE network switching module, TTE network switching module, high-speed data processing module, intelligent module, storage module and power module are all connected to the front panel of the onboard high-performance processing system, so that external products can communicate with each module through the interface.

4. The onboard high performance processing system according to claim 3, characterized in that: The onboard high-performance processing system also includes a plurality of expansion modules, which are connected to the VPX backplane connector on the onboard high-performance processing system through a standard interface to expand the functions of the onboard high-performance processing system.

5. The onboard high performance processing system according to claim 4, characterized in that: Each module in the onboard high-performance processing system includes a primary module and a backup module to ensure that critical tasks can continue to run using the backup module when the primary module fails.

6. The onboard high performance processing system according to claim 1, characterized in that: The intelligent module includes: at least two AI processor chips, a first 10 Gigabit Ethernet chip, a network automatic identification chip, and a storage chip; The first AI processor chip is a module controller, which implements data interaction with the TTE terminal module through a PCIe interface; The second AI processor chip is an intelligent computing processor, which is connected to the first 10 Gigabit Ethernet chip to achieve high-speed image processing; The network automatic identification chip is connected to the first AI processor chip and the second AI processor chip respectively, and is responsible for data transmission between the two processing chips.

7. The onboard high performance processing system according to claim 6, characterized in that: The intelligent module also includes a clock synchronization circuit, and the clock synchronization circuit provides a clock signal and a synchronization signal for the intelligent module.

8. The onboard high performance processing system according to claim 1, characterized in that: The high-speed data processing module includes: a plurality of groups of digital signal processors, a RapidIO switching chip and a first FPGA chip; Each group of the digital signal processors is connected to the RapidIO switching chip to implement the RapidIO data exchange function; The first FPGA chip is connected to the RapidIO switch chip to implement the processing of RapidIO data.

9. The onboard high performance processing system according to claim 1, characterized in that: The storage module comprises: A multi-core processor, which is the management center and implements the construction and management of the data directory; A PCIe switching chip connected to the multi-core processor to achieve data exchange and transmission; The second FPGA chip, which is a coprocessor, is connected to the PCIe switching chip to provide a high-speed physical link to achieve high-speed data transmission and instruction exchange.

10. The onboard high performance processing system according to claim 1, characterized in that: The high-speed data SRIO+10GE network switching module includes: High-performance processor chip, which is the main processor, has 1 SRIO interface, 2 PCIe interfaces and 2 1GE interfaces; A first SRIO chip is connected to the SRIO interface of the high-performance processor chip to realize high-speed data interaction of SRIO signals between the primary and secondary modules; A second SRIO chip is connected to the first SRIO chip to realize high-speed data interaction of SRIO signals between backup modules; A TTE terminal module is connected to a PCIe interface of the high-performance processor chip to realize command interaction between the TTE bus interface and the outside; A second 10 Gigabit Ethernet chip is connected to another PCIe interface of the high-performance processor chip, A routing chip connected to the second 10 Gigabit Ethernet chip through an inter-board high-speed connector to bring out a 10GE network; Among them, the high-performance processor chip has two 1GE interfaces, one of which is connected to the backplane VPX connector, and the other is expanded into two 1GE interfaces through a selection switch, one of which is connected to the front panel for debugging, and the other is connected to the backplane VPX connector.

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