Miniaturized power packaging structure with low parasitic inductance

Abstract

The invention belongs to the technical field of electronics, and particularly relates to a low parasitic inductance and miniaturized power packaging structure which comprises a PCB intermediate layer, a power supply unit and a chip unit, the power supply unit and the chip unit are electrically connected with the PCB intermediate layer, and the PCB intermediate layer comprises a plurality of circuit layers; the power supply circuit is arranged in the multi-layer circuit layer, one end of the power supply circuit is electrically connected with the power supply unit, and the other end of the power supply circuit is electrically connected with the chip unit; and the control circuit is arranged in the multi-layer circuit layer, one end of the control circuit is electrically connected with the chip unit, and the other end of the control circuit is electrically connected with the control end. The packaging structure integrally forms a three-dimensional commutation loop and a compact layout, more power devices can be integrated in a limited space, and the power density can be greatly improved while the size is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and particularly relates to a low parasitic inductance and miniaturized power packaging structure. Background Art

[0002] With the rapid growth of the new energy vehicle market, the integrated design of the electric drive system has gradually become the mainstream, which not only helps to improve the space utilization efficiency of the whole vehicle, but also can reduce energy consumption and enhance the driving experience.

[0003] Therefore, the technological development of low parasitic inductance and miniaturized power modules is particularly important. The low parasitic inductance directly affects the performance of the motor controller and the conversion efficiency of AC and DC power. The lower the parasitic inductance, the higher the energy conversion efficiency, and at the same time, the smaller the electromagnetic interference.

[0004] Integrating more power devices in a limited space while maintaining or improving performance is a difficult problem in electric drive design. Miniaturizing the power module can not only significantly improve the power density. Traditional power modules adopt a planar structure, making it difficult to achieve miniaturization of the power module and improvement of the power density. Therefore, there is an urgent need for a low parasitic inductance and miniaturized power packaging structure to solve this problem. Summary of the Invention

[0005] The purpose of the present invention is to provide a low parasitic inductance and miniaturized power packaging structure to solve the above problems.

[0006] To achieve the above purpose, the present invention provides the following solutions:

[0007] A low parasitic inductance and miniaturized power packaging structure, comprising: a PCB intermediate layer, a power supply unit and a chip unit electrically connected to the PCB intermediate layer,

[0008] The PCB intermediate layer includes multiple circuit layers;

[0009] A power supply line, arranged in the multiple circuit layers, one end of the power supply line is used to connect to a power source, and the other end of the power supply line is electrically connected to the chip unit;

[0010] A control line, arranged in the multiple circuit layers, one end of the control line is electrically connected to the chip unit, and the other end of the control line is electrically connected to a control end.

[0011] Optionally, the power supply line includes a DC positive terminal port, a DC negative terminal port and an AC electrode port arranged on the circuit layer;

[0012] The DC positive terminal ports of two adjacent circuit layers are electrically connected;

[0013] The DC negative electrode ports of two adjacent circuit layers are electrically connected;

[0014] The AC electrode ports of two adjacent circuit layers are electrically connected;

[0015] A plurality of vias arranged in a matrix are provided in the middle of the circuit layer, and the vias of two adjacent circuit layers are electrically connected;

[0016] The DC positive electrode port, the DC negative electrode port and the AC electrode port are all electrically connected to the chip unit.

[0017] Optionally, a fourth switch terminal pad for electrically connecting to the chip unit is provided in the middle of the circuit layer at the top, and a first switch terminal pad for electrically connecting to the chip unit is provided in the middle of the circuit layer at the bottom. The first switch terminal pad is electrically connected to the fourth switch terminal pad through the via;

[0018] An AC electrode copper pour electrically connected to the AC electrode port is laid on the circuit layer in the middle, and the AC electrode copper pour is electrically connected to the via.

[0019] Optionally, a first control terminal pad is provided on the circuit layer at the bottom. The first control terminal pad is electrically connected to a first control port through a first control copper pour. The first control port and the first control copper pour are both laid in the corresponding circuit layer;

[0020] A DC positive electrode pad is provided on the circuit layer at the bottom. The DC positive electrode pad is electrically connected to the DC positive electrode port through a DC positive electrode copper pour;

[0021] The DC positive electrode copper pour is laid in the corresponding circuit layer.

[0022] Optionally, a second control terminal pad is provided on the circuit layer at the top. The second control terminal pad is electrically connected to a second control port through a second control copper pour. The second control port and the second control copper pour are both laid in the corresponding circuit layer;

[0023] A DC negative electrode pad is provided on the circuit layer at the top. The DC negative electrode pad is electrically connected to the DC negative electrode port through a DC negative electrode copper pour;

[0024] The DC negative electrode port is laid in the corresponding circuit layer.

[0025] Optionally, the chip unit includes a PCB upper layer component and a PCB lower layer component, and both the PCB upper layer component and the PCB lower layer component are electrically connected to the PCB middle layer.

[0026] Optionally, the upper-layer component of the PCB includes a lower-bridge-arm die, a DC negative electrode gasket, a second control terminal gasket, and a DC negative electrode substrate;

[0027] The lower-bridge-arm die, the DC negative electrode gasket, and the second control terminal gasket are located between the DC negative electrode substrate and the middle layer of the PCB; the DC negative electrode gasket and the second control terminal gasket are at the same horizontal height;

[0028] The DC negative electrode substrate is a three-layer structure. The lower layer of the DC negative electrode substrate is provided with a DC negative electrode layer, and a second control electrode layer is provided in the middle of the DC negative electrode layer; the middle layer of the DC negative electrode substrate is an insulating and heat-conducting material, and the upper and lower layers of the DC negative electrode substrate are both high-conductive materials;

[0029] The lower-bridge-arm die is provided with a second control terminal, a third switch terminal, and a fourth switch terminal;

[0030] The fourth switch terminal is electrically connected to the fourth switch terminal pad;

[0031] The third switch terminal is electrically connected to the DC negative electrode layer;

[0032] The second control terminal is electrically connected to the second control electrode layer;

[0033] The DC negative electrode gasket is electrically connected to the DC negative electrode pad and the DC negative electrode layer;

[0034] The second control terminal gasket is electrically connected to the second control terminal pad and the second control electrode layer.

[0035] Optionally, the lower-layer component of the PCB includes an upper-bridge-arm die, a DC positive electrode gasket, and a DC positive electrode substrate;

[0036] The upper-bridge-arm die and the DC positive electrode gasket are located between the middle layer of the PCB and the DC positive electrode substrate, and the upper-bridge-arm die and the DC positive electrode gasket are at the same height;

[0037] The DC positive electrode substrate is a three-layer structure. The upper layer of the DC positive electrode substrate is provided with a DC positive electrode layer, the middle layer of the DC positive electrode substrate is an insulating and heat-conducting material, and the upper and lower layers of the DC positive electrode substrate are both high-conductive materials;

[0038] The upper-bridge-arm die is provided with a first control terminal, a first switch terminal, and a second switch terminal;

[0039] The first control terminal is electrically connected to the first control terminal pad, the first switch terminal is electrically connected to the first switch terminal pad, and the second switch terminal is electrically connected to the DC positive electrode layer;

[0040] The DC positive electrode gasket is electrically connected to the DC positive electrode pad and the DC positive electrode layer.

[0041] Compared with the prior art, the present invention has the following advantages and technical effects:

[0042] During use, since the PCB intermediate layer gasket includes multiple circuit layers, the originally planar circuit structure can be stacked in the PCB intermediate layer gasket. By installing the chip unit and the power supply unit on the PCB intermediate layer gasket, power supply and operation of the chip unit are realized through the power supply line and the control line. The overall packaging structure forms a three-dimensional commutation circuit and a compact layout, which can integrate more power devices in a limited space, reduce the volume, and greatly improve the power density at the same time. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings:

[0044] Figure 1 It is an exploded view of the structure of the present invention;

[0045] Figure 2 It is a structure diagram of the lower surface of the PCB intermediate layer of the present invention;

[0046] Figure 3 It is a structure diagram of the upper surface of the PCB intermediate layer of the present invention;

[0047] Figure 4 It is a structure diagram of each circuit layer of the PCB intermediate layer of the present invention;

[0048] Figure 5 It is a structure diagram of the DC negative electrode substrate of the present invention;

[0049] Figure 6 It is a structure diagram of the DC positive electrode substrate of the present invention;

[0050] Among them, 1 is the middle layer of the PCB; 101 is the DC positive terminal port; 102 is the DC negative terminal port; 103 is the AC electrode port; 104 is the first control port; 105 is the second control port; 106 is the DC positive pad; 107 is the DC negative pad; 108 is the first control terminal pad; 109 is the second control terminal pad; 110 is the first switch terminal pad; 111 is the fourth switch terminal pad; 112 is the DC positive copper pour; 113 is the DC negative copper pour; 114 is the AC electrode copper pour; 115 is the first control copper pour; 116 is the second control copper pour; 2 is the DC positive substrate; 201 is the DC positive electrode layer; 3 is the DC negative substrate; 301 is the DC negative electrode layer; 302 is the second control electrode layer; 4 is the upper bridge arm die; 5 is the lower bridge arm die; 6 is the DC positive electrode gasket; 7 is the DC negative electrode gasket; 8 is the second control terminal gasket. Detailed implementation manners

[0051] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0053] Referring to Figures 1 to 6 , the present invention discloses a low parasitic inductance and miniaturized power packaging structure, including: a middle layer 1 of the PCB, a power supply unit and a chip unit electrically connected to the middle layer 1 of the PCB,

[0054] The middle layer 1 of the PCB includes multiple circuit layers;

[0055] A power supply line is arranged in the multiple circuit layers. One end of the power supply line is electrically connected to the power supply unit, and the other end of the power supply line is electrically connected to the chip unit;

[0056] A control line is arranged in the multiple circuit layers. One end of the control line is electrically connected to the chip unit, and the other end of the control line is electrically connected to the control terminal.

[0057] In use, since the middle layer 1 of the PCB includes multiple circuit layers, the originally planar circuit structure can be stacked in the middle layer 1 of the PCB. By installing the chip unit and the power supply unit on the middle layer 1 of the PCB, power supply and operation of the chip unit are achieved through power supply lines and control lines. This packaging structure generally forms a three-dimensional commutation circuit and a compact layout, enabling more power devices to be integrated in a limited space, reducing the volume while greatly improving the power density.

[0058] As an alternative implementation, the power supply line includes a DC positive terminal port 101, a DC negative terminal port 102, and an AC electrode port 103 provided on the circuit layer;

[0059] The DC positive terminal ports 101 of adjacent two circuit layers are electrically connected;

[0060] The DC negative terminal ports 102 of adjacent two circuit layers are electrically connected;

[0061] The AC electrode ports 103 of adjacent two circuit layers are electrically connected;

[0062] A number of vias arranged in a matrix are provided in the middle of the circuit layer, and the vias of adjacent two circuit layers are electrically connected;

[0063] The DC positive terminal port 101, the DC negative terminal port 102, and the AC electrode port 103 are all electrically connected to the chip unit.

[0064] As an alternative implementation, a fourth switch terminal pad 111 for electrically connecting to the chip unit is provided in the middle of the top circuit layer, and a first switch terminal pad 110 for electrically connecting to the chip unit is provided in the middle of the bottom circuit layer. The first switch terminal pad 110 and the fourth switch terminal pad 111 are electrically connected through vias;

[0065] An AC electrode copper pour 114 electrically connected to the AC electrode port 103 is laid on the middle circuit layer, and the AC electrode copper pour 114 is electrically connected to the via.

[0066] As an alternative implementation, a first control terminal pad 108 is provided on the bottom circuit layer. The first control terminal pad 108 is electrically connected to a first control port 104 through a first control copper pour 115. The first control port 104 and the first control copper pour 115 are both laid in the corresponding circuit layer;

[0067] A DC positive pad 106 is provided on the bottom circuit layer. The DC positive pad 106 is electrically connected to the DC positive terminal port 101 through a DC positive copper pour 112;

[0068] The DC positive copper pour 112 is laid in the corresponding circuit layer.

[0069] As an alternative embodiment, a second control terminal pad 109 is provided on the top circuit layer. The second control terminal pad 109 is electrically connected to a second control port 105 through a second control copper pour 116. Both the second control port 105 and the second control copper pour 116 are laid in the corresponding circuit layer.

[0070] A DC negative pad 107 is provided on the top circuit layer. The DC negative pad 107 is electrically connected to a DC negative terminal port 102 through a DC negative copper pour 113.

[0071] The DC negative terminal port 102 is laid in the corresponding circuit layer.

[0072] As an alternative embodiment, the chip unit includes an upper PCB component and a lower PCB component. Both the upper PCB component and the lower PCB component are electrically connected to the PCB intermediate layer 1.

[0073] As an alternative embodiment, the upper PCB component includes a lower bridge arm die 5, a DC negative electrode gasket 7, a second control terminal gasket 8, and a DC negative substrate 3.

[0074] The lower bridge arm die 5, the DC negative electrode gasket 7, and the second control terminal gasket 8 are located between the DC negative substrate 3 and the PCB intermediate layer 1. The DC negative electrode gasket 7 and the second control terminal gasket 8 are at the same horizontal height.

[0075] The DC negative substrate 3 has a three-layer structure. A DC negative electrode layer 301 is provided on the lower layer of the DC negative substrate 3, and a second control electrode layer 302 is provided in the middle of the DC negative electrode layer 301. The middle layer of the DC negative substrate 3 is an insulating and heat-conducting material, and both the upper and lower layers of the DC negative substrate 3 are high-conductive materials.

[0076] The lower bridge arm die 5 is provided with a second control terminal, a third switch terminal, and a fourth switch terminal.

[0077] The fourth switch terminal is electrically connected to a fourth switch terminal pad 111.

[0078] The third switch terminal is electrically connected to the DC negative electrode layer 301.

[0079] The second control terminal is electrically connected to the second control electrode layer 302.

[0080] The DC negative electrode gasket 7 is electrically connected to the DC negative pad 107 and the DC negative electrode layer 301.

[0081] The second control terminal gasket 8 is electrically connected to the second control terminal pad 109 and the second control electrode layer 302.

[0082] As an alternative embodiment, the lower PCB component includes an upper bridge arm die 4, a DC positive electrode gasket 6, and a DC positive substrate 2.

[0083] The upper-bridge-arm die 4 and the DC positive electrode gasket 6 are located between the PCB middle layer 1 and the DC positive substrate 2, and the upper-bridge-arm die 4 and the DC positive electrode gasket 6 are at the same height;

[0084] The DC positive substrate 2 is a three-layer structure. The upper layer of the DC positive substrate 2 is provided with a DC positive electrode layer 201, the middle layer of the DC positive substrate 2 is an insulating heat-conducting material, and both the upper and lower layers of the DC positive substrate 2 are high-conductive materials;

[0085] The upper-bridge-arm die 4 is provided with a first control terminal, a first switch terminal, and a second switch terminal;

[0086] The first control terminal is electrically connected to the first control terminal pad 108, the first switch terminal is electrically connected to the first switch terminal pad 110, and the second switch terminal is electrically connected to the DC positive electrode layer 201;

[0087] The DC positive electrode gasket 6 is electrically connected to the DC positive pad 106 and the DC positive electrode layer 201.

[0088] A low-parasitic-inductance and miniaturized power packaging structure of the present invention includes: a PCB middle layer 1, a PCB upper-layer component, and a PCB lower-layer component. By overlapping the PCB middle layer 1, the PCB upper-layer component, and the PCB lower-layer component vertically, a three-dimensional commutation loop and a compact layout are achieved;

[0089] The PCB middle layer 1 includes a DC positive terminal 101, a DC negative terminal 102, an AC electrode port 103, a first control port 104, a second control port 105, a DC positive pad 106, a DC negative pad 107, a first control terminal pad 108, a second control terminal pad 109, a first switch terminal pad 110, a fourth switch terminal pad 111, a DC positive copper pour 112, a DC negative copper pour 113, an AC electrode copper pour 114, a first control copper pour 115, and a second control copper pour 116.

[0090] Among them, the DC positive pad 106 is electrically connected to the DC positive terminal 101 through the DC positive copper pour 112;

[0091] The DC negative pad 107 is electrically connected to the DC negative terminal 102 through the DC negative copper pour 113;

[0092] The first switch terminal pad 110 and the fourth switch terminal pad 111 are electrically connected by vias and are electrically connected to the AC electrode port 103 via the AC electrode copper pour 114;

[0093] The first control terminal pad 108 is electrically connected to the first control port 104 via the first control copper pour 115;

[0094] The second control terminal pad 109 is electrically connected to the second control port 105 via the second control copper pour 116.

[0095] The upper-layer components of the PCB include: the lower-bridge arm die 5, the DC negative electrode gasket 7, the second control terminal gasket 8, and the DC negative electrode substrate 3. The lower layer of the DC negative electrode substrate 3 is provided with a DC negative electrode layer 301 and a second control electrode layer 302. The DC negative electrode substrate 3 is a three-layer structure, with an insulating heat-conducting material in the middle layer and highly conductive materials in the upper and lower layers.

[0096] Among them, the lower-bridge arm die 5, the DC negative electrode gasket 7, and the second control terminal gasket 8 are arranged between the DC negative electrode substrate 3 and the PCB middle layer 1. The lower-bridge arm die 5 is provided with a second control terminal, a third switch terminal, and a fourth switch terminal. The second control terminal is electrically connected to the second control electrode layer 302, the third switch terminal is electrically connected to the DC negative electrode layer 301, and the fourth switch terminal is electrically connected to the fourth switch terminal pad 111. The DC negative electrode gasket 7 is electrically connected to the DC negative electrode pad 107 and the DC negative electrode layer 301. The second control terminal gasket 8 is electrically connected to the second control terminal pad 109 and the second control electrode layer 302. The lower-bridge arm die 5, the DC negative electrode gasket 7, and the second control terminal gasket 8 are at the same height.

[0097] The lower-layer components of the PCB include: the upper-bridge arm die 4, the DC positive electrode gasket 6, and the DC positive electrode substrate 2. The upper layer of the DC positive electrode substrate 2 is provided with a DC positive electrode layer 201. The DC positive electrode substrate 2 is a three-layer structure, with an insulating heat-conducting material in the middle layer and highly conductive materials in the upper and lower layers. Among them, the upper-bridge arm die 4 and the DC positive electrode gasket 6 are arranged between the DC positive electrode substrate 2 and the PCB middle layer 1. The upper-bridge arm die 4 is provided with a first control terminal, a first switch terminal, and a second switch terminal. The first control terminal is electrically connected to the first control terminal pad 108, the first switch terminal is electrically connected to the first switch terminal pad 110, and the second switch terminal is electrically connected to the DC positive electrode layer 201. The DC positive electrode gasket 6 is electrically connected to the DC positive electrode pad 106 and the DC positive electrode layer 201. The upper-bridge arm die 4 and the DC positive electrode gasket 6 are at the same height.

[0098] The DC positive electrode gasket 6, the DC negative electrode gasket 7, and the second control terminal gasket 8 are all metal blocks, and their materials can be: copper, molybdenum, copper-molybdenum alloy, or other suitable metals. The DC positive electrode gasket 6 is electrically connected to the DC positive electrode pad 106 and the DC positive electrode layer 201.

[0099] In this embodiment, the DC negative copper pour 113, the second control copper pour 116, the DC negative pad 107, the fourth switch terminal pad 111, the second control terminal pad 109, and the second control port 105 are all located on the first circuit layer of the middle layer 1 of the PCB; the DC positive copper pour 112, the first control copper pour 115, the DC positive pad 106, the first switch terminal pad 110, the first control terminal pad 108, and the first control port 104 are all located on the fourth circuit layer of the middle layer 1 of the PCB; the AC electrode copper pour 114 is located on the second and third circuit layers of the middle layer 1 of the PCB; the DC positive terminal port 101, the DC negative terminal port 102, and the AC electrode port 103 are distributed among the four circuit layers of the middle layer 1 of the PCB.

[0100] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0101] The embodiments described above are only for describing the preferred embodiments of the present invention, and do not limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations and improvements made by those of ordinary skill in the art to the technical solutions of the present invention shall fall within the protection scope determined by the claims of the present invention.

Claims

1. A low parasitic inductance, miniaturized power packaging structure, comprising: A PCB middle layer (1) and a chip unit electrically connected to the PCB middle layer (1), characterized in that: The PCB middle layer (1) comprises multiple circuit layers; A power supply circuit is arranged in the multi-layer circuit layer, one end of the power supply circuit is used to be connected to a power source, and the other end of the power supply circuit is electrically connected to the chip unit; A control circuit is arranged in the multi-layer circuit layer, one end of the control circuit is electrically connected to the chip unit, and the other end of the control circuit is electrically connected to the control end.

2. A low parasitic inductance, miniaturized power packaging structure according to claim 1, characterized in that: The power supply circuit comprises a DC positive electrode port (101), a DC negative electrode port (102) and an AC electrode port (103) arranged on the circuit layer; The DC positive ports (101) of two adjacent circuit layers are electrically connected; The DC negative ports (102) of two adjacent circuit layers are electrically connected; The AC electrode ports (103) of two adjacent circuit layers are electrically connected; A plurality of vias arranged in a matrix are provided in the middle of the circuit layer, and the vias of two adjacent circuit layers are electrically connected; The DC positive electrode port (101), the DC negative electrode port (102) and the AC electrode port (103) are all electrically connected to the chip unit.

3. The low parasitic inductance, miniaturized power packaging structure according to claim 2, characterized in that: A fourth switch end pad (111) for electrically connecting to the chip unit is provided in the middle of the circuit layer at the top, and a first switch end pad (110) for electrically connecting to the chip unit is provided in the middle of the circuit layer at the bottom, wherein the first switch end pad (110) and the fourth switch end pad (111) are electrically connected via the via hole; An AC electrode copper plating (114) electrically connected to the AC electrode port (103) is laid on the circuit layer located in the middle, and the AC electrode copper plating (114) is electrically connected to the via hole.

4. The low parasitic inductance, miniaturized power packaging structure according to claim 3, characterized in that: A first control terminal pad (108) is provided on the circuit layer at the bottom, the first control terminal pad (108) is electrically connected to a first control port (104) via a first control copper plating (115), and the first control port (104) and the first control copper plating (115) are both laid in the corresponding circuit layer; A DC positive electrode pad (106) is provided on the circuit layer at the bottom, and the DC positive electrode pad (106) is electrically connected to the DC positive electrode port (101) via a DC positive electrode copper plating (112); The DC positive electrode copper plating (112) is laid in the corresponding circuit layer.

5. The low parasitic inductance, miniaturized power packaging structure according to claim 4, characterized in that: A second control terminal pad (109) is provided on the circuit layer at the top, the second control terminal pad (109) is electrically connected to a second control port (105) via a second control copper plating (116), and the second control port (105) and the second control copper plating (116) are both laid in the corresponding circuit layer; A DC negative electrode pad (107) is provided on the circuit layer at the top, and the DC negative electrode pad (107) is electrically connected to the DC negative electrode port (102) via a DC negative electrode copper plating (113); The DC negative electrode port (102) is laid in the corresponding circuit layer.

6. The low parasitic inductance, miniaturized power packaging structure according to claim 5, characterized in that: The chip unit comprises a PCB upper layer component and a PCB lower layer component, and both the PCB upper layer component and the PCB lower layer component are electrically connected to the PCB middle layer (1).

7. The low parasitic inductance, miniaturized power packaging structure according to claim 6, characterized in that: The PCB upper layer components include a lower bridge arm bare chip (5), a DC negative electrode pad (7), a second control end pad (8) and a DC negative electrode substrate (3); The lower bridge arm bare chip (5), the DC negative electrode gasket (7) and the second control end gasket (8) are located between the DC negative electrode substrate (3) and the PCB middle layer (1); the DC negative electrode gasket (7) and the second control end gasket (8) are located at the same level; The DC negative electrode substrate (3) has a three-layer structure, the lower layer of the DC negative electrode substrate (3) is provided with a DC negative electrode layer (301), and the middle part of the DC negative electrode layer (301) is provided with a second control electrode layer (302); the middle layer of the DC negative electrode substrate (3) is an insulating heat transfer material, and the upper and lower layers of the DC negative electrode substrate (3) are both highly conductive materials; The lower bridge arm bare chip (5) is provided with a second control terminal, a third switch terminal and a fourth switch terminal; The fourth switch terminal is electrically connected to the fourth switch terminal pad (111); The third switch end is electrically connected to the DC negative electrode layer (301); The second control terminal is electrically connected to the second control electrode layer (302); The DC negative electrode gasket (7) is electrically connected to the DC negative electrode pad (107) and the DC negative electrode layer (301); The second control-end pad (8) is electrically connected to the second control-end pad (109) and the second control electrode layer (302).

8. The low parasitic inductance, miniaturized power packaging structure according to claim 6, characterized in that: The PCB lower layer components include an upper bridge arm bare chip (4), a DC positive electrode gasket (6) and a DC positive electrode substrate (2); The upper bridge arm bare chip (4) and the DC positive electrode gasket (6) are located between the PCB middle layer (1) and the DC positive electrode substrate (2), and the upper bridge arm bare chip (4) and the DC positive electrode gasket (6) are located at the same height; The DC positive electrode substrate (2) has a three-layer structure, the upper layer of the DC positive electrode substrate (2) is provided with a DC positive electrode layer (201), the middle layer of the DC positive electrode substrate (2) is an insulating heat transfer material, and the upper and lower layers of the DC positive electrode substrate (2) are both highly conductive materials; The upper bridge arm bare chip (4) is provided with a first control end, a first switch end and a second switch end; The first control end is electrically connected to the first control end welding pad (108), the first switch end is electrically connected to the first switch end welding pad (110), and the second switch end is electrically connected to the DC positive electrode layer (201); The DC positive electrode gasket (6) is electrically connected to the DC positive electrode pad (106) and the DC positive electrode layer (201).

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