CrSi thin-film resistor preparation method and CrSi thin-film resistor

Abstract

The invention discloses a CrSi thin-film resistor preparation method and a CrSi thin-film resistor, and relates to the technical field of semiconductor manufacturing. The preparation method of the CrSi thin-film resistor comprises the following steps: providing a substrate, and depositing a first dielectric layer on the substrate; depositing a metal compound layer on the first dielectric layer, and etching the metal compound layer into a plurality of connection bonding pads; a CrSi thin film layer is deposited on the first dielectric layer and the connecting bonding pads, the two ends of the CrSi thin film layer are removed to expose the first dielectric layer below the CrSi thin film layer, and the remaining CrSi thin film layer covers the multiple connecting bonding pads; a second dielectric layer is deposited on the CrSi thin film layer and the first dielectric layer, a connecting hole and a groove are etched in the second dielectric layer, and the connecting hole is communicated with the connecting bonding pad; and filling a metal material in the connecting hole and the groove to form a metal wire. Through the technical means, the problem that the CrSi thin film layer is etched when the metal compound is etched in the prior art is avoided through the process link of depositing the metal compound firstly, and the yield and the success rate of the CrSi thin film resistor are improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor manufacturing, and particularly to a method for fabricating a CrSi thin film resistor and a CrSi thin film resistor. Background Art

[0002] As a high-performance thin film material, the CrSi thin film resistor has important application value in semiconductor devices due to its high resistivity, low temperature coefficient, and excellent long-term stability. It plays a key role in high-precision analog circuits, RF modules, sensors, and power management chips. For example, it is used in scenarios such as signal conditioning, circuit protection, and oscillator frequency control, directly affecting the accuracy and reliability of the device. Currently, the domestic semiconductor industry mainly focuses on the 8-inch wafer platform for the fabrication of CrSi thin film resistors, and the related processes have become relatively mature.

[0003] In the prior art, the traditional method for fabricating a CrSi thin film resistor is to form a CrSi thin film layer and a metal compound on a substrate by sputtering, etch the CrSi thin film layer and the metal compound into a resistor pattern by dry etching, deposit an isolation layer on the resistor layer, etch vias in the isolation layer, and deposit metal wires in the vias. However, in the traditional fabrication method, it is extremely difficult to control the stopping moment when etching the metal compound with the CrSi thin film layer as the barrier layer, it is not easy to control the thickness of the CrSi thin film layer, and even the CrSi thin film layer may be etched through, resulting in the scrapping of the CrSi thin film resistor, affecting the yield and success rate of the CrSi thin film resistor. Summary of the Invention

[0004] This application provides a method for fabricating a CrSi thin film resistor and a CrSi thin film resistor. By first depositing a metal compound on a substrate dielectric layer and then depositing a CrSi thin film layer, and finally forming metal wires, the stacked structure of the metal compound, CrSi thin film layer, and metal wires meets the structural requirements of the CrSi thin film resistor and does not affect the resistance performance. The process of first depositing the metal compound effectively avoids the problem of etching the CrSi thin film layer when etching the metal compound in the prior art, ensures the thickness of the CrSi thin film layer, and thus improves the yield and success rate of the CrSi thin film resistor.

[0005] In a first aspect, this application provides a method for fabricating a CrSi thin film resistor, including: Providing a substrate and depositing a first dielectric layer on the substrate; Depositing a metal compound layer on the first dielectric layer and etching the metal compound layer into a plurality of connection pads; Depositing a CrSi thin film layer on the first dielectric layer and the connection pads, removing both ends of the CrSi thin film layer to expose the underlying first dielectric layer, and the remaining CrSi thin film layer covers the plurality of connection pads; Deposit a second dielectric layer above the CrSi thin film layer and the first dielectric layer, and etch connection holes and trenches on the second dielectric layer, where the connection holes communicate with the connection pads; Fill the connection holes and the trenches with a metal material to form metal wires.

[0006] Optionally, deposit a metal compound layer on the first dielectric layer, including: Deposit titanium nitride on the first dielectric layer through physical vapor deposition to form a metal compound layer.

[0007] Optionally, etch the metal compound layer into a plurality of connection pads, including: Deposit a photoresist above the metal compound layer, and expose and develop the photoresist through a preset pad mask to expose the underlying metal compound layer; Remove the exposed metal compound layer through dry etching so that the remaining metal compound layer forms a plurality of connection pads.

[0008] Optionally, deposit a CrSi thin film layer on the first dielectric layer and the connection pads, including: Deposit CrSi on the first dielectric layer and the connection pads through chemical vapor deposition to form a CrSi thin film layer.

[0009] Optionally, after depositing the CrSi thin film layer, further include: Perform a high-temperature annealing treatment on the CrSi thin film layer.

[0010] Optionally, remove both ends of the CrSi thin film layer to expose the underlying first dielectric layer, including: Deposit a photoresist above the CrSi thin film layer, and expose and develop the photoresist through a preset thin film mask to expose both ends of the CrSi thin film layer; Remove the exposed both ends of the CrSi thin film layer through dry etching to expose the underlying first dielectric layer.

[0011] Optionally, deposit a second dielectric layer above the CrSi thin film layer and the first dielectric layer, including: Deposit a second dielectric layer above the CrSi thin film layer and the first dielectric layer through physical vapor deposition so that the second dielectric layer wraps the CrSi thin film layer.

[0012] Optionally, etch connection holes and trenches on the second dielectric layer, including: Etch connection holes and trenches on the second dielectric layer through anisotropic dry etching.

[0013] Optionally, a metal material is filled into the connection holes and the trenches to form metal wires, including: By physical vapor deposition process, copper material is filled into the connection holes and the trenches and a copper deposition layer is formed by deposition on the second dielectric layer; The copper deposition layer is polished to remove the copper deposition layer above the second dielectric layer, so that the copper material remaining in the connection holes and the trenches forms metal wires.

[0014] In a second aspect, the present application provides a CrSi thin film resistor prepared by using the CrSi thin film resistor preparation method as described in the first aspect.

[0015] In the present application, CrSi is deposited by chemical vapor deposition process to form a CrSi thin film layer with uniform thickness and composition distribution. By dry etching process, the metal compound layer and the CrSi thin film layer are etched, which can better control the appearance of the connection pads and the CrSi thin film layer. By advancing the preparation step of the connection pads to before the preparation step of the CrSi thin film layer, it is avoided that the CrSi thin film layer is thinned or etched through due to the inability to control the stop moment of etching when the metal compound layer is etched into the connection pads, ensuring the thickness of the CrSi thin film layer, thereby improving the yield and success rate of the CrSi thin film resistor. Moreover, the stacked structure of the metal compound, the CrSi thin film layer and the metal wires meets the structural requirements of the CrSi thin film resistor, while ensuring the performance of the CrSi thin film resistor, simplifying the preparation process flow and complexity of the CrSi thin film resistor, thereby improving the preparation efficiency of the CrSi thin film resistor. Description of the Drawings

[0016] Figure 1 is a flowchart of the CrSi thin film resistor preparation method provided by an embodiment of the present application; Figure 2 is a cross-sectional schematic diagram of the device structure during the preparation of the CrSi thin film resistor provided by an embodiment of the present application; In the figure, 11, substrate; 12, first dielectric layer; 13, metal compound layer; 14, photoresist; 15, connection pad; 16, CrSi thin film layer; 17, metal wire; 18, second dielectric layer; 19, trench; 20, connection hole. Detailed Embodiments

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following provides a more detailed description of specific embodiments of this application with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. Additionally, it should be noted that for ease of description, only parts related to this application rather than all content are shown in the drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.

[0018] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of this application can be implemented in an order different from those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / ", generally represents an "or" relationship between the associated objects before and after.

[0019] In a relatively common existing implementation, the traditional preparation method of CrSi thin-film resistors is to form a CrSi thin-film layer and a masking layer on a substrate by sputtering, etch the CrSi thin-film layer and the masking layer into a resistor pattern by dry etching, deposit an isolation layer on the resistor layer, etch through-holes in the isolation layer, and deposit metal wires in the through-holes. The traditional preparation method mainly focuses on the 8-inch wafer platform, and the related processes have been relatively mature. However, with the development of integrated circuits towards higher integration and larger wafer sizes (such as 12 inches), the traditional preparation method no longer meets the new requirements. The reason is that when the traditional preparation method is implemented on a 12-inch wafer, the difficulty of uniformly controlling the CrSi thin-film layer increases due to the increase in the wafer area, which easily leads to uneven distribution of resistance values and a decrease in the yield. In addition, when etching the masking layer in the traditional preparation method, it is extremely difficult to control the stopping moment with the CrSi thin-film layer as the barrier layer, and it is easy to etch through the CrSi thin-film layer, which also causes a decrease in the yield of CrSi thin-film resistors.

[0020] To solve the above problems, this embodiment provides a method for fabricating a CrSi thin film resistor and a CrSi thin film resistor. By first depositing a metal compound on a substrate dielectric layer and then depositing a CrSi thin film layer, and finally forming metal wires, the stacked structure of the metal compound, the CrSi thin film layer, and the metal wires meets the structural requirements of the CrSi thin film resistor and does not affect the resistance performance. The process of first depositing the metal compound effectively avoids the problem in the prior art that the CrSi thin film layer is etched during the etching of the metal compound, ensures the thickness of the CrSi thin film layer, and thus improves the yield and success rate of the CrSi thin film resistor. Then, a chemical vapor deposition process is used during the deposition of the CrSi thin film layer to ensure the uniformity of the thickness and composition of the CrSi thin film over a larger wafer area and improve the yield of the CrSi thin film resistor.

[0021] Figure 1 The flowchart of a method for fabricating a CrSi thin film resistor provided by an embodiment of the present application is given. As Figure 1 shown, the method for fabricating the CrSi thin film resistor includes: S110. Provide a substrate and deposit a first dielectric layer on the substrate.

[0022] For a wafer, the wafer is used as the substrate 11, and then an insulating material is deposited on the upper surface of the wafer to form the first dielectric layer 12. The first dielectric layer 12, as an insulating layer, can block the diffusion of the metal compound formed on its upper surface subsequently.

[0023] Optionally, an insulating material such as silicon nitride or silicon oxide can be deposited on the substrate 11 through a physical vapor deposition process to form the first dielectric layer 12.

[0024] For example, Figure 2 is a cross-sectional schematic diagram of the device structure during the fabrication of the CrSi thin film resistor provided by an embodiment of the present application. In the figure, (a)-(j) respectively represent the cross-sections of the device structure during the fabrication process, and arrows indicate the generation order of each device structure during the fabrication process. This embodiment will be described in combination with Figure 2 the cross-sectional schematic diagram of the device structure at a certain time duration. Depositing an insulating material on the substrate 11 to form the first dielectric layer 12, that is, forming Figure 2 the device structure shown in (a) in

[0025] S120. Deposit a metal compound layer on the first dielectric layer and etch the metal compound layer into a plurality of connection pads.

[0026] Deposit a metal compound on the upper surface of the first dielectric layer 12 to form a metal compound layer 13. Then, use dry etching to etch the metal compound layer 13 into a plurality of connection pads 15. The connection pads 15 can be used to connect the metal wire 17 and the CrSi thin film layer 16. The stacked structure of the connection pads 15, the CrSi thin film layer 16, and the metal wire 17 meets the structural requirements of the CrSi thin film resistor and does not affect its resistance performance.

[0027] It should be noted that in the traditional preparation process of the CrSi thin film resistor, the CrSi thin film layer 16 is first formed, and then the metal compound layer 13 is formed on the CrSi thin film layer 16. However, when etching the metal compound layer 13 into the connection pads 15, it is extremely difficult to stop using the CrSi thin film layer 16 as the barrier layer, and it is easy to etch through the CrSi thin film layer 16, resulting in device scrapping and seriously affecting the preparation success rate of the device. In this embodiment, the preparation step of the connection pads 15 is advanced before the preparation step of the CrSi thin film layer 16, so that when etching the metal compound layer 13 into the connection pads 15, only the first dielectric layer 12 exists below. The etching rate ratio between the first dielectric layer 12 and the metal compound layer 13 is quite different. When the first dielectric layer 12 is used as the barrier layer, the etching stop time can be effectively controlled, greatly simplifying the preparation difficulty of the connection pads 15. Moreover, in some traditional preparation processes of the CrSi thin film resistor, when preparing the connection pads 15, a through hole for filling the metal compound is etched on the dielectric layer, and the metal compound is deposited in the through hole to form the connection pads 15. However, in this preparation method, when filling the metal compound, the metal compound will also be deposited on the surface of the dielectric layer, and then the metal compound on the surface of the dielectric layer needs to be removed through an etching process such as mechanical grinding. In this embodiment, the metal compound layer 13 is first deposited on the first dielectric layer 12, and then the connection pads 15 are etched on the metal compound layer 13, omitting the process steps of filling and etching back, greatly simplifying the preparation process of the connection pads 15, thereby improving the preparation efficiency of the CrSi thin film resistor.

[0028] Optionally, titanium nitride can be deposited on the first dielectric layer 12 through a physical vapor deposition process to form the metal compound layer 13. For example, the ion plating process can be used to transfer titanium nitride to the surface of the substrate 11 and deposit it to form a thin film, which is the metal compound layer 13. The ion plating process can improve the bonding strength between titanium nitride and the substrate 11 through ion bombardment, so that the metal compound layer 13 strongly adheres to the substrate 11.

[0029] After the metal compound layer 13 is formed, photolithography and dry etching can be combined to etch the metal compound layer 13 into connection pads 15. The specific implementation process is as follows: A photoresist 14 is deposited above the metal compound layer 13, and the photoresist 14 is exposed and developed through a preset pad mask to expose the underlying metal compound layer 13; the exposed metal compound layer 13 is removed by dry etching so that the remaining metal compound layer 13 forms a plurality of connection pads 15. Among them, the pad mask is a mask containing the pattern of the connection pads 15. Exemplarily, a positive photoresist 14 is coated on the upper surface of the metal compound layer 13, and the exposure light source exposes the positive photoresist 14 through the pad mask, and the positive photoresist 14 in the exposed area not covered by the pad mask undergoes a chemical reaction. Then it is removed in the developer, leaving the photoresist 14 in the unexposed area, that is, the area covered by the pad mask. The remaining photoresist 14 is the pattern of the connection pads 15. After the photoresist 14 in the exposed area is removed, the underlying metal compound layer 13 is exposed, and the exposed metal compound layer 13 is etched away by a dry etching process to expose the underlying first dielectric layer 12. The metal compound layer 13 covered by the remaining photoresist 14 is retained to form connection pads 15 that meet the preset shape, and then the remaining photoresist 14 is washed away to complete the preparation of the connection pads 15.

[0030] Reference Figure 2 , deposit a metal compound layer 13 on the first dielectric layer 12, and the device is formed Figure 2 The structure shown in (b) in. After depositing a positive photoresist 14 on the metal compound layer 13, the positive photoresist 14 is exposed and developed based on a preset pad mask to form a photoresist 14 on the metal compound layer 13 that is the same as the pattern of the connection pads 15, and the device is formed Figure 2 The structure shown in (c) in. Then, the area not covered by the photoresist 14 is etched by a dry etching process to remove the corresponding area of the metal compound layer 13 and expose the underlying first dielectric layer 12. After washing the remaining photoresist 14, the unetched metal compound layer 13 forms connection pads 15, and the device is formed Figure 2 The structure shown in (d) in.

[0031] S130. Deposit a CrSi thin film layer on the first dielectric layer and the connection pads, remove both ends of the CrSi thin film layer to expose the underlying first dielectric layer, and the remaining CrSi thin film layer covers a plurality of connection pads.

[0032] Exemplarily, when depositing a chromium silicide material on the upper surface of the wafer, the chromium silicide material will be deposited in the area of the first dielectric layer 12 not covered by the connection pads 15 and on top of the connection pads 15, thereby forming a CrSi thin film layer 16 on the first dielectric layer 12 and the connection pads 15.

[0033] Optionally, CrSi is deposited on the first dielectric layer 12 and the connection pad 15 through a chemical vapor deposition process to form a CrSi thin film layer 16. Exemplarily, a reaction gas containing Cr atoms and Si atoms undergoes a chemical reaction on the surfaces of the first dielectric layer 12 and the connection pad 15 to generate solid CrSi, and the solid CrSi is deposited to form the CrSi thin film layer 16. Compared with the physical vapor deposition process, the chemical vapor deposition process can grow a CrSi thin film layer 16 with a more uniform thickness and distribution. Therefore, even when preparing a CrSi thin film resistor on a 12-inch wafer, the thickness and composition uniformity of the CrSi thin film can be ensured, thereby improving the yield of the CrSi thin film resistor.

[0034] Reference Figure 2 , after depositing a chromized silicon material on the first dielectric layer 12 and the connection pad 15, a CrSi thin film layer 16 covering the first dielectric layer 12 and completely wrapping the connection pad 15 is formed, and the device is formed Figure 2 in the structure shown in (e) of

[0035] Optionally, after forming the CrSi thin film layer 16, a high-temperature annealing treatment is performed on the CrSi thin film layer 16. The high-temperature annealing treatment is a heat treatment process in which the material is exposed to a high temperature for a period of time and then slowly cooled. In this way, the compactness of the CrSi thin film is better, which is convenient for better preparing the CrSi thin film resistor.

[0036] After the high-temperature annealing treatment of the CrSi thin film layer 16, both ends of the CrSi thin film layer 16 can be removed by photolithography etching and dry etching processes to expose the underlying first dielectric layer 12, and the remaining CrSi thin film layer 16 can still completely wrap the connection pad 15. The specific implementation process is as follows: Deposit a photoresist 14 above the CrSi thin film layer 16, and expose and develop the photoresist 14 through a preset thin film mask to expose both ends of the CrSi thin film layer 16; Remove the exposed both ends of the CrSi thin film layer 16 by dry etching to expose the underlying first dielectric layer 12. Among them, the thin film mask is a mask containing a CrSi thin film pattern. Exemplarily, a positive photoresist 14 is coated on the upper surface of the CrSi thin film layer 16, and the exposure light source exposes the positive photoresist 14 through the CrSi thin film mask, and the positive photoresist 14 in the exposed area not covered by the CrSi thin film mask undergoes a chemical reaction. Then it is removed in the developer, leaving the photoresist 14 in the unexposed area, that is, the area covered by the pad mask, and the remaining photoresist 14 is the CrSi thin film pattern. After the photoresist 14 in the exposed area is removed, the underlying CrSi thin film layer 16 is exposed, and the exposed CrSi thin film layer 16 is etched away by dry etching process to expose the underlying first dielectric layer 12. The CrSi thin film layer 16 covered by the remaining photoresist 14 is retained to form a CrSi thin film layer 16 that meets the preset shape, and then the remaining photoresist 14 is washed away to complete the preparation of the CrSi thin film layer 16.

[0037] It should be noted that the CrSi thin film pattern is generally designed as a thin film pattern with a preset length, and the size of this thin film pattern can cover all connection pads 15 but will not cover the entire wafer. Therefore, the finally formed CrSi thin film layer 16 will cover all connection pads 15 but not cover the first dielectric layer 12 at both ends.

[0038] Reference Figure 2 , after depositing the positive photoresist 14 on the CrSi thin film layer 16, expose and develop the positive photoresist 14 based on the preset thin film mask to form a photoresist 14 on the metal compound layer 13 that is the same as the thin film mask pattern, and the device is formed Figure 2 in the structure shown in (f) of Figure 2 . Then, the area not covered by the photoresist 14 is etched by dry etching process to remove the corresponding area of the CrSi thin film layer 16, exposing the underlying first dielectric layer 12. After washing the remaining photoresist 14, a CrSi thin film layer 16 that wraps the connection pad 15 but is etched at both ends is exposed, and the device is formed

[0039] S140. Deposit a second dielectric layer above the CrSi thin film layer and the first dielectric layer, and etch connection holes and trenches on the second dielectric layer, and the connection holes communicate with the connection pads.

[0040] Exemplarily, when depositing an insulating material on the upper surface of the wafer, the insulating material is deposited in the area of the first dielectric layer 12 not covered by the CrSi thin film layer 16 and on top of the CrSi thin film layer 16, thereby forming a second dielectric layer 18 on the first dielectric layer 12 and the CrSi thin film layer 16.

[0041] Optionally, the second dielectric layer 18 is deposited on the CrSi thin film layer 16 and the first dielectric layer 12 through a physical vapor deposition process so that the second dielectric layer 18 wraps the CrSi thin film layer 16. For example, an ion plating process can be used to transfer the insulating material onto the surfaces of the CrSi thin film layer 16 and the first dielectric layer 12 and deposit to form the second dielectric layer 18.

[0042] Reference Figure 2 , after depositing the insulating material on the first dielectric layer 12 and the CrSi thin film layer 16, a second dielectric layer 18 that covers the first dielectric layer 12 and completely wraps the CrSi thin film layer 16 is formed, and the structure shown in (h) in the device formation Figure 2 is obtained.

[0043] After forming the second dielectric layer 18, connection holes 20 for connecting the connection pads 15 and trenches 19 for forming conductive paths are etched in the second dielectric layer 18. Optionally, the connection holes 20 and trenches 19 are etched on the second dielectric layer 18 through anisotropic dry etching. Among them, anisotropic dry etching means that the etching direction has obvious directivity, and the etching speed in the vertical direction is higher than that in the horizontal direction, thereby forming holes and grooves with a high aspect ratio. In this embodiment, by utilizing the etching characteristics of anisotropic dry etching, shallow but wide trenches 19 and deep but narrow connection holes 20 can be etched in the second dielectric layer 18 at one time, without preparing multiple masks and performing multiple etching processes, simplifying the preparation process of the connection holes 20 and trenches 19 and improving the preparation efficiency.

[0044] For example, a layer of positive photoresist 14 is coated on the upper surface of the second dielectric layer 18, and an exposure light source exposes the positive photoresist 14 through a trench 19 mask. The positive photoresist 14 in the exposed area not covered by the trench 19 mask undergoes a chemical reaction. Then it is removed in a developer, leaving the unexposed area, that is, the trench 19 mask, and the remaining photoresist 14 is the connection pad 15 pattern. After the photoresist 14 in the exposed area is removed, the underlying second dielectric layer 18 is exposed, and the exposed second dielectric layer 18 is etched through an anisotropic dry etching process, thereby forming trenches 19 and connection holes 20 on the second dielectric layer 18.

[0045] Reference Figure 2 , after anisotropic dry etching of the second dielectric layer 18, trenches 19 and connection holes 20 are formed on the second dielectric layer 18. The width of the trenches 19 is greater than that of the connection holes 20 but the depth is less than that of the connection holes 20, and the connection holes 20 are connected to the connection pads 15, and the device formationFigure 2 The structure shown in (i).

[0046] S150: Fill the connection holes and trenches with a metal material to form metal wires.

[0047] After forming connection holes 20 and trenches 19 in the second dielectric layer 18, copper material is filled into the connection holes 20 and trenches 19 to form copper wires, thereby forming a stacked structure of copper wires, CrSi thin film layer 16, and connection pads 15. Moreover, since the CrSi thin film layer 16 surrounds the connection between the copper wires and the connection pads 15, the contact area between the copper wires and the connection pads 15 is increased, thus improving the stability of the CrSi thin film resistance.

[0048] Optionally, through a physical vapor deposition process, copper material is filled into the connection holes 20 and trenches 19 and a copper deposition layer is deposited on the second dielectric layer 18; the copper deposition layer is polished to remove the copper deposition layer above the second dielectric layer 18, so that the copper material remaining in the connection holes 20 and trenches 19 forms metal wires 17. For example, copper material is deposited on the second dielectric layer 18 by using ion plating or sputtering process. The copper material will fill into the connection holes 20 and trenches 19, but will also be deposited on the upper surface of the second dielectric layer 18 to form a copper deposition layer. At this time, the copper deposition layer is polished by a mechanical polishing process to remove the copper material on the surface of the second dielectric layer 18 and expose the underlying second dielectric layer 18. Thus, the preparation process of the CrSi thin film resistor is completed.

[0049] Reference Figure 2 , after depositing a metal material on the second dielectric layer 18, the connection holes 20 and trenches 19 are filled with the metal material. Then, the metal material deposited on the upper surface of the second dielectric layer 18 is removed, and the metal material remaining in the connection holes 20 and trenches 19 forms metal wires 17, and the device is formed Figure 2 The structure shown in (j).

[0050] In summary, the method for preparing a CrSi thin film resistor provided by the embodiments of the present application deposits CrSi through a chemical vapor deposition process to form a CrSi thin film layer 16 with uniform thickness and composition distribution. By etching the metal compound layer 13 and the CrSi thin film layer 16 through a dry etching process, the appearance of the connection pad 15 and the CrSi thin film layer 16 can be better controlled. By advancing the preparation step of the connection pad 15 to before the preparation step of the CrSi thin film layer 16, it is possible to avoid thinning or etching through the CrSi thin film layer 16 when etching the metal compound layer 13 into the connection pad 15 due to the inability to control the stop moment of etching, ensuring the thickness of the CrSi thin film layer 16, thereby improving the yield and success rate of the CrSi thin film resistor. Moreover, the stacked structure of the metal compound, the CrSi thin film layer 16, and the metal wire 17 meets the structural requirements of the CrSi thin film resistor, simplifies the preparation process flow and complexity of the CrSi thin film resistor while ensuring the performance of the CrSi thin film resistor, thereby improving the preparation efficiency of the CrSi thin film resistor.

[0051] Based on the above embodiments, the embodiments of the present application further provide a CrSi thin film resistor, which is prepared by using the method for preparing a CrSi thin film resistor provided by the above embodiments. The structure of the CrSi thin film resistor can refer to Figure 2 the structure shown in (j) in [reference]. The structure of the CrSi thin film resistor is simpler than the traditional resistor structure, and the preparation process is also simpler and faster than the preparation process of the traditional resistor. It can shorten the R & D cycle and ensure the production yield and success rate, and has great advantages in the mass production of large-size wafers.

[0052] The above is only the preferred embodiment of the present application and the technical principles applied. The present application is not limited to the specific embodiments here. Various obvious changes, re-adjustments, and substitutions that can be made by those skilled in the art will not depart from the protection scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments. Without departing from the concept of the present application, it may include more other equivalent embodiments, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for preparing a CrSi thin film resistor, characterized in that: include: Providing a substrate, and depositing a first dielectric layer on the substrate; Depositing a metal compound layer on the first dielectric layer, and etching the metal compound layer into a plurality of connecting pads; Depositing a CrSi thin film layer on the first dielectric layer and the connecting pads, removing two ends of the CrSi thin film layer to expose the first dielectric layer underneath, and the remaining CrSi thin film layer covers the plurality of connecting pads; Depositing a second dielectric layer above the CrSi thin film layer and the first dielectric layer, etching connection holes and grooves on the second dielectric layer, wherein the connection holes are connected to the connection pads; Metal materials are filled into the connection holes and the grooves to form metal wires.

2. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: Depositing a metal compound layer on the first dielectric layer comprises: Titanium nitride is deposited on the first dielectric layer by a physical vapor deposition process to form a metal compound layer.

3. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: The metal compound layer is etched into a plurality of connection pads, comprising: Depositing a photoresist on the metal compound layer, and exposing and developing the photoresist through a preset pad mask to expose the metal compound layer underneath; The exposed metal compound layer is removed by dry etching, so that the remaining metal compound layer forms a plurality of connection pads.

4. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: Depositing a CrSi thin film layer on the first dielectric layer and the connecting pad comprises: CrSi is deposited on the first dielectric layer and the connecting pad by a chemical vapor deposition process to form a CrSi thin film layer.

5. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: After depositing the CrSi thin film layer, the method further comprises: The CrSi thin film layer is subjected to high temperature annealing treatment.

6. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: Removing both ends of the CrSi thin film layer to expose the first dielectric layer thereunder, comprising: Depositing a photoresist on the CrSi thin film layer, and exposing and developing the photoresist through a preset thin film mask to expose two ends of the CrSi thin film layer; The exposed ends of the CrSi thin film layer are removed by dry etching to expose the first dielectric layer underneath.

7. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: Depositing a second dielectric layer on the CrSi thin film layer and the first dielectric layer comprises: A second dielectric layer is deposited on the CrSi thin film layer and the first dielectric layer by a physical vapor deposition process, so that the second dielectric layer wraps the CrSi thin film layer.

8. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: Etching connection holes and grooves on the second dielectric layer, comprising: Connecting holes and trenches are etched on the second dielectric layer by anisotropic dry etching.

9. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: Filling the connection hole and the groove with metal material to form a metal wire, comprising: Filling the connection hole and the groove with copper material and depositing the copper material on the second dielectric layer to form a copper deposition layer through a physical vapor deposition process; The copper deposition layer is polished to remove the copper deposition layer above the second dielectric layer, so that the copper material remaining in the connecting hole and the trench forms a metal wire.

10. A CrSi thin film resistor, characterized in that: The CrSi thin film resistor is prepared using the preparation method of the CrSi thin film resistor as described in any one of claims 1 to 9.

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