Capacitor and DRAM device including same

Abstract

The invention discloses a capacitor and a DRAM device. The capacitor comprises a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconia layer, a hafnium oxide layer, and a second zirconia layer stacked in sequence; the upper electrode is located on the dielectric layer structure, and the hafnium oxide layer is provided with a tetragonal crystal phase or an orthorhombic crystal phase.

Description

[0001] This application is a divisional application of the invention patent application "Capacitor and DRAM Device Including the Capacitor" with the application date of June 17, 2021 and the application number of 202110670117.0. Technical Field

[0002] The embodiments relate to a capacitor and a dynamic random access memory (DRAM) device including the capacitor. Background Art

[0003] In a DRAM device, a unit memory cell may include a transistor and a capacitor, and the capacitor may have a high capacitance. Summary of the Invention

[0004] The embodiments may be implemented by providing a capacitor including: a lower electrode; a dielectric layer structure located on the lower electrode, the dielectric layer structure including a first zirconia layer, a hafnium oxide layer, and a second zirconia layer sequentially stacked; and an upper electrode located on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal phase or an orthorhombic phase.

[0005] The embodiments may be implemented by providing a capacitor including: a lower electrode; a dielectric layer structure located on the lower electrode, the dielectric layer structure including a first zirconia layer, a hafnium oxide layer, and a second zirconia layer sequentially stacked; and an upper electrode located on the dielectric layer structure, wherein the dielectric layer structure has a thickness of about 20 Å to about 60 Å, and the first zirconia layer, the hafnium oxide layer, and the second zirconia layer are all crystalline.

[0006] The embodiments may be implemented by providing a dynamic random access memory device (DRAM) including: a substrate; a unit transistor located on the substrate, the unit transistor including a gate structure, a first impurity region, and a second impurity region; a bit line structure electrically connected to the first impurity region; and a capacitor located on the bit line structure, the capacitor electrically connected to the second impurity region, wherein the capacitor includes: a lower electrode; a dielectric layer structure located on the lower electrode, the dielectric layer structure including a first zirconia layer, a hafnium oxide layer, and a second zirconia layer sequentially stacked; and an upper electrode located on the dielectric layer structure, wherein the dielectric layer structure has a thickness of about 20 Å to about 60 Å, and wherein the hafnium oxide layer has a tetragonal phase or an orthorhombic phase. Description of the Drawings

[0007] Features will be apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the drawings, in which: Figures 1 to 3 is a cross-sectional view of a capacitor according to an exemplary embodiment; Figure 4 is a cross-sectional view of a capacitor according to an exemplary embodiment; Figure 5 is a graph showing the capacitance according to the applied voltage of a capacitor; Figure 6 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment; Figure 7 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment; Figure 8 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment; Figure 9 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment; Figure 10 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment; Figure 11 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment; Figures 12 to 14 is a cross-sectional view of each stage in a method of manufacturing a capacitor according to an exemplary embodiment; and Figure 15 is a cross-sectional view of a DRAM device having a capacitor according to an exemplary embodiment. DETAILED DESCRIPTION

[0008] Figures 1 to 3 is a cross-sectional view of a capacitor according to an exemplary embodiment. Figure 4 is a cross-sectional view of a capacitor according to an exemplary embodiment.

[0009] Figures 1 to 3 The capacitor shown in includes a lower electrode having a column shape. Figure 4 The capacitor shown in includes a lower electrode having a cylindrical (e.g., hollow cylindrical) shape.

[0010] Figure 1 is a vertical cross-sectional view of the capacitor. Figure 2 is along Figure 1 a horizontal cross-sectional view taken along line I-I'. Figure 3 is Figure 1 an enlarged cross-sectional view of part A of

[0011] Referring to Figures 1 to 4 , the capacitor 180 may include a stacked lower electrode 110, a dielectric layer structure 140, and an upper electrode 150.

[0012] In an embodiment, the capacitor 180 may be located on a lower structure 102 on a substrate 100. In an embodiment, the lower structure 102 may include transistors, contact plugs, wires, interlayer insulating layers, and the like.

[0013] Each of the lower electrode 110 and the upper electrode 150 may include a metal, a metal nitride, or a conductive oxide. In an embodiment, each of the lower electrode 110 and the upper electrode 150 may independently include, for example, titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), tungsten, tungsten nitride, Nb, NbN, indium tin oxide (ITO), Ta-doped SnO 2 , Nb-doped SnO 2 , Sb-doped SnO 2 , V-doped SnO 2 and the like. In an embodiment, the material of the lower electrode 110 may be the same as the material of the upper electrode 150. In an embodiment, the material of the lower electrode 110 and the material of the upper electrode 150 may be different from each other. As used herein, the term "or" is not an exclusive term. For example, "A or B" will include A, B, or both A and B.

[0014] The lower electrode 110 may have various three-dimensional structures.

[0015] In an embodiment, the lower electrode 110 may have a three-dimensional structure such as a cylindrical shape or a columnar shape. As Figures 1 to 3 shown, the lower electrode 110 may have a columnar shape. As Figure 4 shown, the lower electrode 110 may have a cylindrical (e.g., hollow cylindrical) shape.

[0016] In an embodiment, the lower electrode 110 may have a two-dimensional shape such as a plate shape. In this case, the capacitor may have a shape similar to the enlarged view Figure 3 shown. The capacitance of the capacitor 180 may be determined by the surface area of the lower electrode 110, and the lower electrode 110 may have various modified structures for increasing the capacitance.

[0017] The dielectric layer structure 140 may be located between the lower electrode 110 and the upper electrode 150. The dielectric layer structure 140 may contact (e.g., directly contact) the surface of the lower electrode 110 to cover the surface of the lower electrode 110. The dielectric layer structure 140 may be conformally formed on the surface of the lower electrode 110. When the lower electrode 110 has a two-dimensional shape such as a plate shape, the dielectric layer structure 140 may be located on the upper surface of the lower electrode 110 to have a two-dimensional shape. When the lower electrode 110 has a columnar shape or a cylindrical shape, the dielectric layer structure 140 may be formed along the surface of the lower electrode 110 to have a three-dimensional shape.

[0018] For the capacitor 180 with high capacitance, the dielectric layer structure 140 may be designed to have a high dielectric constant. In an embodiment, the dielectric layer structure 140 may have an equivalent oxide layer thickness of about 5 Å or less (e.g., about 3.7 Å or less).

[0019] The dielectric layer structure 140 may include a plurality of stacked dielectric layers. In an embodiment, the dielectric layer structure 140 may have a thickness of about 20 Å to about 60 Å. Keeping the thickness of the dielectric layer structure 140 at about 20 Å or greater may help prevent an increase in leakage current in the capacitor. Keeping the thickness of the dielectric layer structure 140 at about 60 Å or less may help ensure that the capacitor has a high target capacitance. In an embodiment, the dielectric layer structure 140 having a thickness of about 20 Å to about 60 Å may be suitable for a capacitor in a highly integrated semiconductor device. Hereinafter, the thickness of a layer represents the thickness of the layer in the vertical direction (e.g., the thickness in the outward direction) from the surface of the structure underlying the layer.

[0020] The dielectric layer structure 140 may include a main dielectric layer and a sub-dielectric layer. The main dielectric layer may be a ferroelectric material having ferroelectric properties or antiferroelectric properties according to an electric field. The dielectric constant of the ferroelectric material may increase greatly within a switching voltage range, which is a voltage range in which the ferroelectric properties can be converted to antiferroelectric properties or the antiferroelectric properties can be converted to ferroelectric properties. In this case, when the switching voltage range matches the operating voltage range of the capacitor or the switching voltage range is within the operating voltage range of the capacitor, the dielectric constant of the dielectric layer structure may increase greatly. Therefore, the capacitor may have a high capacitance within the operating voltage range.

[0021] In a highly integrated semiconductor device (e.g., a DRAM device), the semiconductor device may have a low operating voltage range (e.g., an operating voltage range of about -1 V to about 1 V). In an embodiment, the highly integrated DRAM device may have a low operating voltage range of about -0.7 V to about 0.7 V. Therefore, the dielectric layer structure 140 of the capacitor 180 can be boosted to a high dielectric constant within the operating voltage range of about -1 V to about 1 V.

[0022] The dielectric layer structure 140 may include a sandwich structure or a layered structure having a hafnium oxide layer 122 and zirconium oxide layers 120 and 124 directly contacting the upper surface and the lower surface of the hafnium oxide layer 122, respectively. In an embodiment, the dielectric layer structure 140 may include a first stacked structure in which a first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124 are stacked in sequence. The first zirconium oxide layer 120, hafnium oxide layer 122, and second zirconium oxide layer 124 included in the first stacked structure may all be crystalline layers or crystalline state layers.

[0023] The main dielectric layer of the dielectric layer structure 140 may be the hafnium oxide layer 122. A (e.g., crystalline) hafnium oxide layer having a tetragonal phase or an orthorhombic phase may be a ferroelectric material having ferroelectric properties or antiferroelectric properties according to an electric field. A hafnium oxide layer having a tetragonal phase or an orthorhombic phase may have a high dielectric constant of 70 or greater.

[0024] In an embodiment, the dielectric constant of the dielectric layer structure 140 can be increased by using a hafnium oxide layer having ferroelectric properties. Accordingly, the capacitance of the capacitor can be increased by the hafnium oxide layer having ferroelectric properties. Thus, the hafnium oxide layer 122 included in the dielectric layer structure 140 can have a tetragonal phase or an orthorhombic phase.

[0025] A hafnium oxide layer having a monoclinic phase or an amorphous hafnium oxide layer does not have ferroelectric properties. In an embodiment, the hafnium oxide layer 122 included in the dielectric layer structure 140 may not have a monoclinic phase and may not be amorphous. The stacking structure of the dielectric layer structure 140 can be optimized such that the hafnium oxide layer 122 can have a stable tetragonal phase or a stable orthorhombic phase.

[0026] The coercive field of the hafnium oxide layer 122 having a tetragonal phase or an orthorhombic phase can be in the operating voltage range of about -1V to about 1V. When the hafnium oxide layer 122 having a tetragonal phase or an orthorhombic phase is used as the main dielectric layer of the dielectric layer structure 140, the capacitor 180 can have a high capacitance in the operating voltage range.

[0027] Hereinafter, the hafnium oxide layer 122 may represent a hafnium oxide layer having a tetragonal phase or an orthorhombic phase.

[0028] The hafnium oxide layer 122 can have a thickness of about 5 Å to about 18 Å. Maintaining the thickness of the hafnium oxide layer at about 5 Å or greater can help prevent leakage current from occurring in the capacitor. In addition, it is easier to form a hafnium oxide layer having a thickness of about 5 Å or greater. Maintaining the thickness of the hafnium oxide layer at about 18 Å or less can help ensure that the phase of the hafnium oxide layer is a tetragonal phase or an orthorhombic phase rather than a monoclinic phase.

[0029] The first zirconium oxide layer 120 and the second zirconium oxide layer 124 can have a small lattice mismatch with the hafnium oxide layer 122. In an embodiment, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can directly contact the upper surface and the lower surface (e.g., the inner surface and the outer surface) of the hafnium oxide layer 122, respectively. Accordingly, the stacking structure including the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer can have low residual stress.

[0030] If the hafnium oxide layer 122 directly contacts the lower electrode 110 and the upper electrode 150, the lattice mismatch between the hafnium oxide layer 122 and the lower electrode 110 and the lattice mismatch between the hafnium oxide layer 122 and the upper electrode 150 will be high. Accordingly, the residual stress of the hafnium oxide layer 122 will be very high. In an embodiment, the hafnium oxide layer may not directly contact the lower electrode 110 and the upper electrode 150.

[0031] After the dielectric layer included in the dielectric layer structure is crystallized, if the residual stress of the dielectric layer structure is high, the electric field for changing the polarization direction of the dielectric layer (e.g., hafnium oxide layer 122) will increase. Therefore, the coercive field of the dielectric layer will increase, and thus the electric field (E) required to have the same polarization (P) in the dielectric layer with high residual stress will increase.

[0032] P = χe * ε0 * E, χe = εr - 1 (P: polarization density, χe: electric susceptibility, ε0: vacuum permittivity, εr: relative permittivity) C = ε0 * εr * A / t (C: capacitance, A: capacitor area, t: dielectric material thickness) The electric field with the same polarization will increase, the electric susceptibility (χe) will decrease, and the relative permittivity will decrease.

[0033] If the residual stress of the dielectric layer structure is high, the relative permittivity of the dielectric layer structure will not increase in the low operating voltage range (e.g., about -1V to about 1V). In addition, the relative permittivity of the dielectric layer structure 140 will increase at operating voltages below -1V and above 1V. Therefore, in order to have a high capacitance in the low operating voltage range of about -1V to about 1V, the residual stress of the dielectric layer structure 140 can be low.

[0034] The first zirconium oxide layer 120 and the second zirconium oxide layer 124 can be crystalline. In an embodiment, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can have a stable tetragonal phase. In an embodiment, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 that are in direct contact with the hafnium oxide layer 122 can be crystalline. In an embodiment, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can induce crystallization of the hafnium oxide layer 122, such that the hafnium oxide layer 122 can have a stable tetragonal phase or orthorhombic phase during the process for forming the dielectric layer structure 140 and subsequent annealing processes.

[0035] In an embodiment, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can have the same thickness. In an embodiment, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can have different thicknesses.

[0036] Each of the first zirconia layer 120 and the second zirconia layer 124 can independently have a thickness of about 5 Å to about 30 Å. Maintaining the thickness of each of the first zirconia layer 120 and the second zirconia layer 124 at about 5 Å or greater can help ensure that the first zirconia layer 120 and the second zirconia layer 124 induce crystallization of the hafnium oxide layer 122, such that the hafnium oxide layer 122 can have a stable tetragonal phase or orthorhombic phase. Maintaining the thickness of each of the first zirconia layer 120 and the second zirconia layer 124 at about 30 Å or less can help ensure that the capacitor has a high target capacitance.

[0037] Figure 5 is a graph showing the capacitance according to the applied voltage of the capacitor.

[0038] As Figure 5 shown, the capacitance of the capacitor 180 in which the lower electrode 110, the dielectric layer structure 140, and the upper electrode 150 are stacked can have a hysteresis characteristic. The capacitance can be maximized in a voltage range of about -1 V to about 1 V.

[0039] In an embodiment, the dielectric layer structure can include a first stacked structure in which the first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer 124 are sequentially stacked, and the dielectric layer structure can further include at least one additional layer on or under the first stacked structure.

[0040] Except for the dielectric layer structure, each of the following embodiments is the same as the capacitor described with reference to Figures 1 to 4 described. Therefore, only the dielectric layer structure will be mainly described.

[0041] Figure 6 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment.

[0042] Referring to Figure 6 , the capacitor 180a can include a stack of a lower electrode 110 / dielectric layer structure 140a / upper electrode 150.

[0043] The dielectric layer structure 140a can include an interface layer 130 and a first stacked structure in which the first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer 124 are stacked. In an embodiment, the interface layer 130 can be additionally formed between the lower electrode 110 and the first zirconia layer 120.

[0044] As described above, the dielectric layer structure 140a can have a thickness of about 20 Å to about 60 Å.

[0045] The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 may independently have a thickness of about 5 Å to about 30 Å. The thickness of the interface layer 130 may be controlled such that the sum of the thickness of the interface layer 130 and the thickness of the first stacked structure in which the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124 are stacked may be equal to or less than 60 Å. In an embodiment, the thickness of the interface layer 130 may be less than the thickness of the first zirconium oxide layer 120.

[0046] The interface layer 130 may help prevent direct contact between the lower electrode 110 and the first zirconium oxide layer 120. The interface layer 130 may be a layer having a small lattice mismatch with the first zirconium oxide layer 120.

[0047] In an embodiment, the interface layer 130 may include a ZrNbO x layer or a TiNbO x layer. In an embodiment, the interface layer 130 may have a structure in which a TiNbO x layer and a ZrNbO x layer are stacked.

[0048] In an embodiment, the dielectric layer structure 140a may further include the interface layer 130 and may reduce the residual stress of the dielectric layer structure 140a. Accordingly, a capacitor including the dielectric layer structure 140a may have a high capacitance.

[0049] Figure 7 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment.

[0050] Referring to Figure 7 , the capacitor 180b may include a stack of a lower electrode 110 / dielectric layer structure 140b / upper electrode 150.

[0051] The dielectric layer structure 140b may include a first stacked structure 125, an insertion layer 132, and a third zirconium oxide layer 134. In an embodiment, the insertion layer 132 and the third zirconium oxide layer 134 may be further formed on the second zirconium oxide layer 124.

[0052] The dielectric layer structure 140b may have a thickness of about 20 Å to about 60 Å. The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 may independently have a thickness of about 5 Å to about 30 Å. The thickness of the insertion layer 132 and the thickness of the third zirconium oxide layer 134 may be separately controlled such that the sum of the thickness of the first stacked structure in which the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124 are stacked, the thickness of the insertion layer 132, and the thickness of the third zirconium oxide layer 134 may be equal to or less than 60 Å.

[0053] The insertion layer 132 may be located between the second zirconia layer 124 and the third zirconia layer 134. In an embodiment, the second zirconia layer 124 may be a crystalline layer, and the third zirconia layer 134 may be an amorphous layer. The insertion layer 132 may be an amorphous layer. In an embodiment, the insertion layer 132 may be amorphous, and the third zirconia layer 134 may be formed on the insertion layer 132 to be amorphous.

[0054] The insertion layer 132 may include a metal oxide. In an embodiment, the insertion layer 132 may include an oxide of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd. In an embodiment, the thickness of the insertion layer 132 may be less than the thickness of each of the second zirconia layer 124 and the third zirconia layer 134.

[0055] Compared with a crystalline zirconia layer, an amorphous zirconia layer may have excellent surface roughness. Therefore, in the capacitor 180b having the dielectric layer structure 140b according to the present embodiment, the concentration of the electric field caused by the poor surface roughness of the dielectric layer can be reduced. Therefore, the leakage current of the capacitor 180b can be reduced.

[0056] Figure 8 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment.

[0057] Referring to Figure 8 , the capacitor 180c may include a stack of a lower electrode 110 / a dielectric layer structure 140c / an upper electrode 150.

[0058] The dielectric layer structure 140c may include an interface layer 130, a first stack structure 125, an insertion layer 132, and a third zirconia layer 134. In an embodiment, the interface layer 130 may be located between the lower electrode 110 and the first zirconia layer 120. The insertion layer 132 and the third zirconia layer 134 may be further formed on the second zirconia layer 124.

[0059] The dielectric layer structure 140c may have a thickness of about 20 Å to about 60 Å. The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å. Each of the first zirconia layer 120 and the second zirconia layer 124 may independently have a thickness of about 5 Å to about 30 Å. The thickness of the interface layer 130, the thickness of the insertion layer 132, and the thickness of the third zirconia layer 134 may be respectively controlled such that the sum of the thickness of the interface layer 130, the thickness of the first stack structure in which the first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer 124 are stacked, the thickness of the insertion layer 132, and the thickness of the third zirconia layer 134 may be equal to or less than 60 Å.

[0060] The material of the interface layer 130 may be the same as that referred to inFigure 6 The materials of the interface layers shown are the same. The material of the insertion layer 132 can be the same as that of the insertion layer Figure 7 shown.

[0061] The dielectric layer structure 140c can have low residual stress. In an embodiment, a capacitor having the dielectric layer structure 140c can have a high capacitance and can reduce the leakage current of the capacitor.

[0062] Figure 9 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment.

[0063] Referring to Figure 9 , the capacitor 180d can include a stack of a lower electrode 110 / a dielectric layer structure 140d / an upper electrode 150.

[0064] The dielectric layer structure 140d can include an interface layer 130, a first insertion layer 132a, a first stacked structure 125, a second insertion layer 132b, and a third zirconia layer 134. In an embodiment, in the structure of the capacitor shown in Figure 8 , the capacitor can further include a first insertion layer 132a located between the interface layer 130 and the first stacked structure 125. The material of the first insertion layer 132a can be the same as that of the insertion layer Figure 7 shown. The first insertion layer 132a can prevent the material in the first stacked structure 125 from diffusing toward the lower electrode 110.

[0065] In an embodiment, the second insertion layer may not be formed.

[0066] Figure 10 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment.

[0067] Referring to Figure 10 , the capacitor 180e can include a stack of a lower electrode 110 / a dielectric layer structure 140e / an upper electrode 150.

[0068] The dielectric layer structure 140e can include a first insertion layer 132a, an interface layer 130, a first stacked structure 125, a second insertion layer 132b, and a third zirconia layer 134. In an embodiment, in the structure of the capacitor shown in Figure 8 , the capacitor can further include a first insertion layer 132a located between the lower electrode 110 and the interface layer 130. The material of the first insertion layer 132a can be the same as that of the insertion layer Figure 7 shown.

[0069] In an embodiment, the second insertion layer may not be formed.

[0070] In an embodiment, in Figure 10In the dielectric layer structure shown, the dielectric layer structure may further include an insertion layer located between the interface layer 130 and the first stacked structure 125. In an embodiment, a stacked structure including an insertion layer / interface layer / insertion layer may be located between the lower electrode 110 and the first stacked structure 125.

[0071] Figure 11 is an enlarged cross-sectional view of a capacitor according to an exemplary embodiment.

[0072] Referring to Figure 11 , the capacitor 180f may include a stack of a lower electrode 110 / dielectric layer structure 140f / an upper electrode 150.

[0073] The dielectric layer structure 140f may include a first insertion layer 132a, a first stacked structure 125, a second insertion layer 132b, and a third zirconia layer 134. In an embodiment, the dielectric layer structure 140f may not include an interface layer, but may further include Figure 10 the first insertion layer 132a located between the lower electrode 110 and the first stacked structure 125 in the dielectric layer structure shown in Figure 7 . The material of the first insertion layer 132a may be the same as the material of the insertion layer shown in reference to

[0074] Figures 12 to 14 is a cross-sectional view of each stage in a method of manufacturing a capacitor according to an exemplary embodiment.

[0075] Hereinafter, an example of a method of manufacturing a capacitor including a lower electrode having a column shape is described.

[0076] Referring to Figure 12 , a molding layer 104 may be formed on a substrate. A portion of the molding layer 104 may be etched to form holes. Holes may be formed at portions for forming the lower electrode.

[0077] In an embodiment, before forming the molding layer 104, a lower structure 102 may be further formed on the substrate 100. The lower structure 102 may include a lower circuit including transistors, contact plugs, and wires, and an interlayer insulating layer covering the lower circuit.

[0078] A lower electrode layer filling the holes may be formed on the molding layer 104. The lower electrode layer may be planarized until the upper surface of the molding layer 104 can be exposed to form the lower electrode 110 in the holes.

[0079] In an embodiment, the lower electrode layer may be deposited by a deposition process such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The planarization process may include a chemical mechanical polishing (CMP) process or an etch-back process.

[0080] In an embodiment, a lower electrode layer may be formed on the lower structure 102. The lower electrode layer may be patterned by a photolithography process to form the lower electrode 110. In this case, a molding layer may not be formed on the lower structure 102.

[0081] Referring to Figure 13 , the molding layer 104 may be removed. Accordingly, the surface of the lower electrode 110 having a column shape may be exposed.

[0082] A first zirconia layer 120 may be conformally formed on the surface of the lower electrode 110 and the surface of the lower structure 102 so that the first zirconia layer 120 has a uniform thickness. A hafnium oxide layer 122 may be formed on the first zirconia layer 120. A second zirconia layer 124 may be formed on the hafnium oxide layer 122. Accordingly, a first stacked structure in which the first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer 124 are stacked may be formed on the lower electrode 110 and the lower structure 102.

[0083] The hafnium oxide layer 122 may be formed to have a tetragonal phase or an orthorhombic phase. Each of the first zirconia layer 120 and the second zirconia layer 124 may be formed to have a crystalline phase. In an embodiment, each of the first zirconia layer 120 and the second zirconia layer 124 may have a tetragonal phase as a stable phase.

[0084] The dielectric layer structure 140 may have a thickness of about 20 Å to about 60 Å. Each of the first zirconia layer 120 and the second zirconia layer 124 may independently have a thickness of about 5 Å to about 30 Å. The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å.

[0085] In an embodiment, each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 may be formed by an atomic layer deposition (ALD) process. The deposition process of each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 may be performed at a relatively low temperature, for example, about 200 °C to about 450 °C. Performing the deposition process of each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 at a temperature of about 200 °C or higher may help ensure that each of the precursors can be thermally decomposed and these layers can be appropriately deposited. Performing the deposition process of each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 at a temperature of about 450 °C or lower may help ensure the stable growth of these layers. In an embodiment, the deposition process of each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 may be performed at a temperature of about 200 °C to about 320 °C.

[0086] In an embodiment, in the deposition process of each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124, the oxidant may include O 3 , H 2 O or O 2 .

[0087] In an embodiment, each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 may be formed in a batch-type deposition apparatus. In an embodiment, each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 may be formed in a single-wafer-type deposition apparatus.

[0088] In an embodiment, the deposition chamber for forming the first zirconia layer 120 and the second zirconia layer 124 may be different from the deposition chamber for forming the hafnium oxide layer 122. In an embodiment, the deposition chamber for forming the first zirconia layer 120 and the second zirconia layer 124 may be the same as the deposition chamber for forming the hafnium oxide layer 122.

[0089] In an embodiment, the hafnium oxide layer 122 may be formed between the first zirconia layer 120 and the second zirconia layer 124, and the first stacked structure including the stacked first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer may have low residual stress.

[0090] During the formation of the hafnium oxide layer 122 and the formation of the second zirconia layer 124 on the hafnium oxide layer 122, the hafnium oxide layer 122 may crystallize at a low temperature. Therefore, the hafnium oxide layer 122 may have a tetragonal phase or an orthorhombic phase. Additionally, the first zirconia layer 120 and the second zirconia layer 124 may also crystallize during the formation of the first zirconia layer 120 and the second zirconia layer 124 and the hafnium oxide layer 122. Therefore, the first zirconia layer 120 and the second zirconia layer 124 may have a stable tetragonal phase.

[0091] In an embodiment, before forming the first zirconia layer 120, an interface layer (refer to Figure 6 , 130) may be further formed on the surface of the lower electrode 110 and the surface of the lower structure 102 so that the interface layer has a uniform thickness. In an embodiment, the interface layer 130 may be formed by an atomic layer deposition process. The deposition process of the interface layer 130 may be performed at a low temperature of about 200°C to about 450°C. In an embodiment, the deposition process of the interface layer 130 may be performed at a temperature of about 200°C to about 320°C. In this case, a capacitor as shown in Figure 6 may be formed by a subsequent process.

[0092] In an embodiment, an insertion layer (refer toFigure 7 , 132) and a third zirconia layer (refer to Figure 7 , 134). The insertion layer 132 may include a metal oxide. In an embodiment, the insertion layer 132 may include an oxide of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd. In an embodiment, the insertion layer 132 may be formed to have a thickness smaller than the thickness of each of the second zirconia layer 124 and the third zirconia layer 134. In an embodiment, the insertion layer 132 and the third zirconia layer 134 may be formed by an atomic layer deposition process. The deposition process of the insertion layer 132 and the third zirconia layer 134 may be performed at a low temperature of about 200°C to about 450°C. In an embodiment, the deposition process of the insertion layer 132 and the third zirconia layer 134 may be performed at a temperature of about 200°C to about 320°C. In this case, a capacitor as shown in Figure 7 may be formed by a subsequent process.

[0093] In an embodiment, before forming the first zirconia layer 120, an interface layer (refer to Figure 8 , 130) may be further formed on the surface of the lower electrode 110 and the surface of the lower structure 102 so that the interface layer has a uniform thickness. An insertion layer (refer to Figure 8 , 132) and a third zirconia layer (refer to Figure 8 , 134) may be further formed on the second zirconia layer 124. In this case, a capacitor as shown in Figure 8 may be formed by a subsequent process.

[0094] One of the capacitors shown in Figures 9 to 11 may be formed by additionally performing a process of forming an interface layer and / or an insertion layer and a subsequent process.

[0095] Refer to Figure 14 , the upper electrode 150 may be formed on the second zirconia layer 124.

[0096] In an embodiment, the upper electrode 150 may be formed of the same material as the material of the lower electrode 110. In an embodiment, the upper electrode 150 may be formed of a material different from the material of the lower electrode 110.

[0097] In an embodiment, the upper electrode 150 may be formed by a deposition process such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process.

[0098] In an embodiment, after forming the upper electrode 150, an annealing process may be further performed. When the annealing process is performed, the first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer 124 included in the dielectric layer structure 140 may be crystallized additionally or further. In an embodiment, the annealing process may be performed at a temperature higher than the temperature of the deposition process for forming the dielectric layer structure 140.

[0099] As described above, the hafnium oxide layer 122 included in the dielectric layer structure 140 may have a tetragonal phase or an orthorhombic phase. The zirconia layers 120 and 124 may be formed on the upper surface and the lower surface (e.g., the inner surface and the outer surface) of the hafnium oxide layer 122, respectively, such that the residual stress of the dielectric layer structure 140 may be reduced. Accordingly, the dielectric layer structure 140 may have a low coercive field, and the capacitance of the capacitor may be greatly increased in a range of about -1V to about 1V, which is the operating voltage range of the capacitor including the dielectric layer structure 140.

[0100] Figure 15 is a cross-sectional view of a DRAM device having a capacitor according to an exemplary embodiment.

[0101] Although only a DRAM device is shown in Figure 15 the capacitor may be used in all memory devices that use a capacitor as a data storage unit.

[0102] Referring to Figure 15 , the DRAM device may include a cell transistor, a capacitor, and a bit line formed on a substrate. The DRAM device may include a unit cell including one cell transistor and one capacitor.

[0103] The substrate 200 may include an active region and a field region. The field region may be a region where an isolation layer 220 is formed in isolation trenches included in the substrate 200. The active region may be a region of the substrate other than the field region.

[0104] A gate trench 202 extending in a first direction parallel to the upper surface of the substrate 200 may be formed at an upper portion of the substrate 200. A gate structure 210 may be formed in the gate trench 202.

[0105] In an embodiment, the gate structure 210 may include a gate insulating layer 204, a gate electrode 206, and a capping insulating pattern 208. A plurality of gate structures 210 may be arranged in a second direction parallel to the upper surface of the substrate 200 and perpendicular to the first direction.

[0106] The gate insulating layer 204 may include silicon oxide. The gate electrode 206 may include a metal material or polysilicon. The capping insulating pattern 208 may include silicon nitride.

[0107] The impurity regions 230 serving as source / drain regions may be formed at the active regions of the substrate 100 located between the gate structures 210.

[0108] In an embodiment, the impurity region 230 may include a first impurity region 230a electrically connected to the bit line structure 260 and a second impurity region 230b electrically connected to the capacitor 180.

[0109] The pad insulating pattern 240, the first etch stop pattern 242, and the first conductive pattern 246 may be formed on the active region, the isolation layer 220, and the gate structure 210. The pad insulating pattern 240 may include an oxide such as silicon oxide, and the first etch stop pattern 242 may include a nitride such as silicon nitride. The first conductive pattern 246 may include polysilicon doped with impurities.

[0110] The recessed portion may pass through the stacked structure including the pad insulating pattern 240, the first etch stop pattern 242, and the first conductive pattern 246. The recessed portion may be provided at the portion of the substrate 100 located between the gate structures. The upper surface of the first impurity region 230a may be exposed through the bottom of the recessed portion.

[0111] The second conductive pattern 248 filling the recessed portion may be formed. The second conductive pattern 248 may include, for example, polysilicon doped with impurities. In an embodiment, the second conductive pattern 248 may contact the first impurity region 230a.

[0112] The third conductive pattern 250 may be stacked on the first conductive pattern 246 and the second conductive pattern 248. The third conductive pattern 250 may include, for example, polysilicon doped with impurities. Since the first to third conductive patterns 246, 248, and 250 include substantially the same material, the first to third conductive patterns 246, 248, and 250 may be combined into one pattern. The barrier metal pattern 252, the metal pattern 254, and the hard mask pattern 256 may be stacked on the third conductive pattern 250.

[0113] The stacked structure including the first conductive pattern 246, the second conductive pattern 248, the third conductive pattern 250, the barrier metal pattern 252, the metal pattern 254, and the hard mask pattern 256 may be used as the bit line structure 260.

[0114] In an embodiment, the second conductive pattern 248 may serve as a bit line contact, and the first conductive pattern 246, the third conductive pattern 250, the barrier metal pattern 252, and the metal pattern 254 may serve as bit lines. The bit line structure 260 may extend in the second direction. A plurality of bit line structures 260 may be arranged in the first direction.

[0115] In an embodiment, spacers may be formed on the sidewalls of the bit line structure 260.

[0116] In an embodiment, a first interlayer insulating layer may be formed in a portion between the fill bit line structures 260.

[0117] A contact plug 270 may be formed through the first interlayer insulating layer, the first etch stop pattern 242, and the pad insulating pattern 240. The contact plug 270 may contact the second impurity region 230b. The contact plug 270 may be located between the bit line structures 260.

[0118] A capacitor 180 may be formed on the contact plug 270.

[0119] The capacitor 180 may include a lower electrode 110, a dielectric layer structure 140, and an upper electrode 150. The dielectric layer structure 140 may include a stack of a first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer 124.

[0120] The capacitor 180 may have the same structure as that of the capacitor as shown with reference to Figure 1 In an embodiment, the capacitor may have the same structure as one of the capacitors shown with reference to Figures 6 to 8 A plate electrode 160 may be further formed on the upper electrode 150. The plate electrode 160 may include polysilicon doped with an impurity.

[0121] The DRAM device may operate in an operating voltage range of about -1V to about 1V. In the capacitor, the dielectric constant of the dielectric layer structure may be greatly increased in the operating voltage range of about -1V to about 1V, so that the capacitance of the capacitor may be greatly increased. The DRAM device may have excellent electrical characteristics.

[0122] By summary and review, when the DRAM device is highly integrated, it may be difficult for the capacitor included in the DRAM to have a high capacitance and a low leakage current.

[0123]

[0124] One or more embodiments may provide a capacitor having a high capacitance.

[0125] One or more embodiments may provide a DRAM device including a capacitor having a high capacitance.

[0126] In an exemplary embodiment, the dielectric layer structure included in the capacitor may have ferroelectric properties in an operating voltage range (e.g., an operating voltage range of about -1V to about 1V). The capacitor may have a high capacitance in the operating voltage range.

[0127] ​Example embodiments have been disclosed herein, and although specific terms are employed, they are used in a general and descriptive sense only and are not to be construed for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art from the present application, unless specifically stated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A capacitor, the capacitor comprises: a lower electrode; a dielectric layer structure located on the lower electrode; and an upper electrode located on the dielectric layer structure, wherein the dielectric layer structure comprises: an interface layer located on the lower electrode, the interface layer comprising zirconium niobium oxide (ZrNbO); a first layer located on the interface layer; and a second layer located on the first layer.

2. The capacitor according to claim 1, wherein, the first layer comprises zirconium or zirconium oxide.

3. The capacitor according to claim 2, wherein, the second layer comprises hafnium or hafnium oxide.

4. The capacitor according to claim 1, wherein, the dielectric layer structure further comprises a third layer located between the first layer and the interface layer, the third layer comprising Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd.

5. The capacitor according to claim 1, wherein, wherein, the dielectric layer structure further comprises a fourth layer, the fourth layer comprising zirconium or zirconium oxide.

6. The capacitor according to claim 5, wherein, the fourth layer is amorphous.

7. The capacitor according to claim 1, wherein, each of the lower electrode and the upper electrode comprises titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), tungsten, or tungsten nitride.

8. The capacitor according to claim 1, wherein, the lower electrode has a columnar shape.

9. The capacitor according to claim 1, wherein, the first layer has a thickness of about 5 Å to 30 Å.

10. The capacitor according to claim 1, wherein, the second layer has a thickness of about 5 Å to 18 Å.

11. The capacitor according to claim 1, wherein, the dielectric layer structure has a thickness of about 20 Å to 60 Å.

12. The capacitor according to claim 1, wherein, the first layer has an orthorhombic phase.

13. The capacitor according to claim 1, wherein, the second layer has a tetragonal phase or an orthorhombic phase.

14. A capacitor, the capacitor comprises: a lower electrode; a dielectric layer structure located on the lower electrode; and an upper electrode located on the dielectric layer structure, wherein the dielectric layer structure comprises: an interface layer contacting the lower electrode, the interface layer comprising a zirconium niobium oxide (ZrNbO) layer, a titanium niobium oxide (TiNbO) layer, or a stacked structure of a titanium niobium oxide (TiNbO) layer and a zirconium niobium oxide (ZrNbO) layer, a first zirconium oxide layer located on the interface layer; a hafnium oxide layer located on the first zirconium oxide layer; and an insertion layer located between the interface layer and the first zirconium oxide layer, and the insertion layer comprises at least one of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc or Gd.

15. The capacitor according to claim 14, wherein, the first zirconium oxide layer has a thickness of about 5 Å to 30 Å.

16. The capacitor according to claim 14, wherein, the hafnium oxide layer has a thickness of about 5 Å to 18 Å.

17. The capacitor according to claim 14, wherein, the dielectric layer structure further comprises a second zirconium oxide layer located on the hafnium oxide layer.

18. A memory device, the memory device comprises; a substrate; A unit transistor is located on a substrate. The unit transistor includes a gate structure, a first impurity region, and a second impurity region; A bit line structure is electrically connected to the first impurity region; and a capacitor is located on the bit line structure. The capacitor is electrically connected to the second impurity region, wherein the capacitor includes: a lower electrode; a dielectric layer located on the lower electrode. The dielectric layer includes a zirconium niobium oxide (ZrNbO) layer; an insertion layer located on the interface layer. The insertion layer includes Al; a first zirconia layer located on the interface layer; a hafnium oxide layer located on the first zirconia layer; and an upper electrode located on the hafnium oxide layer.

19. The memory device according to claim 18, wherein, the lower electrode has a column shape.

20. The memory device according to claim 18, wherein, the gate structure is located in a gate trench and includes a gate insulating layer, a gate electrode, and a capping insulating pattern.

Images