Capacitor and dram device including the same
By employing a dielectric layer structure design in DRAM devices, utilizing a stacked structure of zirconium oxide, hafnium oxide, and zirconium oxide layers, the challenges of high capacitance and low leakage current are solved, achieving high capacitance and excellent electrical characteristics within a low operating voltage range.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2021-06-17
- Publication Date
- 2026-06-12
AI Technical Summary
In DRAM devices, it is difficult to achieve both high capacitance and low leakage current of capacitors simultaneously, especially in highly integrated semiconductor devices. Existing technologies struggle to optimize the dielectric layer structure to meet the high capacitance requirements in low operating voltage ranges.
The dielectric layer structure consists of a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer stacked sequentially. The hafnium oxide layer has a tetragonal or orthorhombic crystal phase, and the thickness of the dielectric layer structure is controlled between 20 Å and 60 Å. The crystallinity of the layer and low residual stress are ensured by a low-temperature deposition process, thereby reducing leakage current.
Within an operating voltage range of approximately -1V to approximately 1V, the capacitance of the capacitor is significantly increased, leakage current is reduced, and the electrical characteristics of the DRAM device are improved.
Smart Images
Figure CN120076351B_ABST
Abstract
Description
[0001] This application is a divisional application of the invention patent application "Capacitor and DRAM device including capacitor" filed on June 17, 2021, with application number 202110670117.0. Technical Field
[0002] The embodiments relate to a capacitor and a dynamic random access memory (DRAM) device including the capacitor. Background Technology
[0003] In a DRAM device, a single memory cell may include a transistor and a capacitor, and the capacitor may have high capacitance. Summary of the Invention
[0004] An embodiment can be implemented by providing a capacitor, the capacitor comprising: a lower electrode; a dielectric layer structure located on the lower electrode, the dielectric layer structure comprising a first zirconium oxide layer, a hafnium oxide layer and a second zirconium oxide layer stacked sequentially; and an upper electrode located on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal or orthorhombic crystal phase.
[0005] An embodiment can be implemented by providing a capacitor comprising: a lower electrode; a dielectric layer structure located on the lower electrode, the dielectric layer structure comprising a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer stacked sequentially; and an upper electrode located on the dielectric layer structure, wherein the dielectric layer structure has a thickness of about 20 Å to about 60 Å, and the first zirconium oxide layer, the hafnium oxide layer, and the second zirconium oxide layer are all crystalline.
[0006] An embodiment can be implemented by providing a dynamic random access memory (DRAM) device, the DRAM device comprising: a substrate; a cell transistor located on the substrate, the cell transistor including a gate structure, a first impurity region, and a second impurity region; a bit line structure electrically connected to the first impurity region; and a capacitor located on the bit line structure, the capacitor being electrically connected to the second impurity region, wherein the capacitor includes: a lower electrode; a dielectric layer structure located on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode located on the dielectric layer structure, wherein the dielectric layer structure has a thickness of about 20 Å to about 60 Å, and wherein the hafnium oxide layer has a tetragonal or orthorhombic crystal phase. Attached Figure Description
[0007] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:
[0008] Figures 1 to 3 This is a cross-sectional view of a capacitor according to an example embodiment;
[0009] Figure 4 This is a cross-sectional view of a capacitor according to an example embodiment;
[0010] Figure 5 It is a graph showing the capacitance as a function of the applied voltage.
[0011] Figure 6 This is an enlarged cross-sectional view of a capacitor according to an example embodiment;
[0012] Figure 7 This is an enlarged cross-sectional view of a capacitor according to an example embodiment;
[0013] Figure 8 This is an enlarged cross-sectional view of a capacitor according to an example embodiment;
[0014] Figure 9 This is an enlarged cross-sectional view of a capacitor according to an example embodiment;
[0015] Figure 10 This is an enlarged cross-sectional view of a capacitor according to an example embodiment;
[0016] Figure 11 This is an enlarged cross-sectional view of a capacitor according to an example embodiment;
[0017] Figures 12 to 14 These are cross-sectional views of various stages in a method of manufacturing a capacitor according to an example embodiment; and
[0018] Figure 15 This is a cross-sectional view of a DRAM device having a capacitor according to an example embodiment. Detailed Implementation
[0019] Figures 1 to 3 This is a cross-sectional view of a capacitor according to an example embodiment. Figure 4 This is a cross-sectional view of a capacitor according to an example embodiment.
[0020] Figures 1 to 3 The capacitor shown includes a lower electrode with a columnar shape. Figure 4 The capacitor shown includes a lower electrode having a cylindrical (e.g., hollow cylindrical) shape.
[0021] Figure 1 This is a vertical sectional view of a capacitor. Figure 2 It is along Figure 1 A horizontal sectional view taken from line I-I'. Figure 3 yes Figure 1 An enlarged sectional view of part A.
[0022] Reference Figures 1 to 4 The capacitor 180 may include a stacked lower electrode 110, a dielectric layer structure 140, and an upper electrode 150.
[0023] In one embodiment, capacitor 180 may be located on lower structure 102 on substrate 100. In another embodiment, lower structure 102 may include transistors, contact plugs, wires, interlayer insulation layers, etc.
[0024] Each of the lower electrode 110 and the upper electrode 150 may comprise a metal, a metal nitride, or a conductive oxide. In embodiments, each of the lower electrode 110 and the upper electrode 150 may independently comprise, for example, titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), tungsten, tungsten nitride, Nb, NbN, indium tin oxide (ITO), Ta-doped SnO2, Nb-doped SnO2, Sb-doped SnO2, V-doped SnO2, etc. In embodiments, the material of the lower electrode 110 may be the same as the material of the upper electrode 150. In embodiments, the materials of the lower electrode 110 and the upper electrode 150 may be different from each other. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.
[0025] The lower electrode 110 can have various three-dimensional structures.
[0026] In embodiments, the lower electrode 110 may have a three-dimensional structure such as a cylindrical or columnar shape. Figures 1 to 3 As shown, the lower electrode 110 can have a cylindrical shape. Figure 4 As shown, the lower electrode 110 may have a cylindrical (e.g., hollow cylindrical) shape.
[0027] In an embodiment, the lower electrode 110 may have a two-dimensional shape, such as a plate shape. In this case, the capacitor may have a shape similar to... Figure 3 The enlarged view shown indicates the shape. The capacitance of capacitor 180 can be determined by the surface area of lower electrode 110, and lower electrode 110 can have various modified structures for increasing capacitance.
[0028] A dielectric layer structure 140 may be located between the lower electrode 110 and the upper electrode 150. The dielectric layer structure 140 may contact (e.g., directly contact) the surface of the lower electrode 110 to cover the surface of the lower electrode 110. The dielectric layer structure 140 may be conformally formed on the surface of the lower electrode 110. When the lower electrode 110 has a two-dimensional shape such as a plate, the dielectric layer structure 140 may be located on the upper surface of the lower electrode 110 to have a two-dimensional shape. When the lower electrode 110 has a pillar shape or a cylindrical shape, the dielectric layer structure 140 may be formed along the surface of the lower electrode 110 to have a three-dimensional shape.
[0029] For a capacitor 180 with high capacitance, the dielectric layer structure 140 can be designed to have a high dielectric constant. In an embodiment, the dielectric layer structure 140 may have an equivalent oxide layer thickness of about 5 Å or less (e.g., about 3.7 Å or less).
[0030] The dielectric layer structure 140 may include multiple stacked dielectric layers. In an embodiment, the dielectric layer structure 140 may have a thickness of about 20 Å to about 60 Å. Maintaining the thickness of the dielectric layer structure 140 at about 20 Å or greater can help prevent an increase in leakage current in the capacitor. Maintaining the thickness of the dielectric layer structure 140 at about 60 Å or less can help ensure that the capacitor has a high target capacitance. In an embodiment, the dielectric layer structure 140 having a thickness of about 20 Å to about 60 Å can be suitable for capacitors in highly integrated semiconductor devices. Hereinafter, the thickness of a layer refers to the thickness of the layer in the vertical direction (e.g., the thickness in the outward direction) from the surface of the structure beneath the layer.
[0031] The dielectric layer structure 140 may include a main dielectric layer and a sub-dielectric layer. The main dielectric layer may be a ferroelectric material that exhibits ferroelectric or antiferroelectric properties depending on the electric field. The dielectric constant of the ferroelectric material can be significantly increased within the switching voltage range, which is the voltage range from which ferroelectric properties can be converted to antiferroelectric properties or vice versa. In this case, when the switching voltage range matches or is within the operating voltage range of the capacitor, the dielectric constant of the dielectric layer structure can be significantly increased. Therefore, the capacitor can have high capacitance within the operating voltage range.
[0032] In highly integrated semiconductor devices (e.g., DRAM devices), the semiconductor devices can have a low operating voltage range (e.g., an operating voltage range of about -1V to about 1V). In an embodiment, a highly integrated DRAM device can have a low operating voltage range of about -0.7V to about 0.7V. Therefore, the dielectric layer structure 140 of the capacitor 180 can be boosted with a high dielectric constant within an operating voltage range of about -1V to about 1V.
[0033] The dielectric layer structure 140 may include a sandwich or layered structure having a hafnium oxide layer 122 and zirconium oxide layers 120 and 124 that are respectively in direct contact with the upper and lower surfaces of the hafnium oxide layer 122. In an embodiment, the dielectric layer structure 140 may include a first stacked structure in which the first zirconium oxide layer 120, the hafnium oxide layer 122, and the second zirconium oxide layer 124 are sequentially stacked. The first zirconium oxide layer 120, the hafnium oxide layer 122, and the second zirconium oxide layer 124 included in the first stacked structure may both be crystalline layers or crystalline layers.
[0034] The main dielectric layer of dielectric layer structure 140 may be a hafnium oxide layer 122. The hafnium oxide layer having a tetragonal or orthorhombic phase (e.g., crystalline) may be a ferroelectric material that has ferroelectric or antiferroelectric properties depending on the electric field. The hafnium oxide layer having a tetragonal or orthorhombic phase may have a high dielectric constant of 70 or greater.
[0035] In this embodiment, the dielectric constant of the dielectric layer structure 140 can be increased by using a hafnium oxide layer with ferroelectric properties. Therefore, the capacitance of the capacitor can be increased by using a hafnium oxide layer with ferroelectric properties. Thus, the hafnium oxide layer 122 included in the dielectric layer structure 140 can have a tetragonal or orthorhombic crystal phase.
[0036] Hafnium oxide layers with a monoclinic phase or amorphous hafnium oxide layers do not possess ferroelectric properties. In embodiments, the hafnium oxide layer 122 included in the dielectric layer structure 140 may not have a monoclinic phase and may not be amorphous. The stacking structure of the dielectric layer structure 140 can be optimized so that the hafnium oxide layer 122 can have a stable tetragonal phase or a stable orthorhombic phase.
[0037] The coercive field of the hafnium oxide layer 122 having a tetragonal or orthorhombic phase can be within an operating voltage range of about -1V to about 1V. When the hafnium oxide layer 122 having a tetragonal or orthorhombic phase is used as the main dielectric layer of the dielectric layer structure 140, the capacitor 180 can have high capacitance within the operating voltage range.
[0038] In the following text, hafnium oxide layer 122 may refer to a hafnium oxide layer having a tetragonal or orthorhombic phase.
[0039] The hafnium oxide layer 122 can have a thickness of about 5 Å to about 18 Å. Maintaining the thickness of the hafnium oxide layer at about 5 Å or more can help prevent leakage current in the capacitor. Furthermore, it is easier to form a hafnium oxide layer with a thickness of about 5 Å or more. Maintaining the thickness of the hafnium oxide layer at about 18 Å or less can help ensure that the phase of the hafnium oxide layer is a tetragonal or orthorhombic phase, rather than a monoclinic phase.
[0040] The first zirconia layer 120 and the second zirconia layer 124 can have a small lattice mismatch with the hafnium oxide layer 122. In an embodiment, the first zirconia layer 120 and the second zirconia layer 124 can directly contact the upper and lower surfaces (e.g., the inner and outer surfaces) of the hafnium oxide layer 122, respectively. Therefore, the stacked structure comprising the first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer can have low residual stress.
[0041] If the hafnium oxide layer 122 directly contacts the lower electrode 110 and the upper electrode 150, the lattice mismatch between the hafnium oxide layer 122 and the lower electrode 110, and between the hafnium oxide layer 122 and the upper electrode 150, will be high. Therefore, the residual stress in the hafnium oxide layer 122 will be very high. In an embodiment, the hafnium oxide layer may not directly contact the lower electrode 110 and the upper electrode 150.
[0042] If the residual stress of the dielectric layer structure is high after the dielectric layer is crystallized, the electric field required to change the polarization direction of the dielectric layer (e.g., hafnium oxide layer 122) will increase. Therefore, the coercive field of the dielectric layer will increase, which in turn will increase the electric field (E) required to have the same polarization (P) in a dielectric layer with high residual stress.
[0043] P = χe * ε0 * E, χe = εr - 1 (P: polarization density, χe: electric susceptibility, ε0: vacuum permittivity, εr: permittivity)
[0044] C = ε0 * εr * A / t (C: capacitance, A: capacitor area, t: dielectric material thickness)
[0045] An electric field with the same polarization will be increased, the polarizability (χe) will be decreased, and the dielectric constant will be decreased.
[0046] If the residual stress of the dielectric layer structure is high, the dielectric constant of the dielectric layer structure will not increase in the low operating voltage range (e.g., from about -1V to about 1V). Furthermore, the dielectric constant of the dielectric layer structure 140 increases at operating voltages below -1V and above 1V. Therefore, in order to have high capacitance in the low operating voltage range of about -1V to about 1V, the residual stress of the dielectric layer structure 140 can be low.
[0047] The first zirconia layer 120 and the second zirconia layer 124 may be crystalline. In an embodiment, the first zirconia layer 120 and the second zirconia layer 124 may have a stable tetragonal crystal phase. In an embodiment, the first zirconia layer 120 and the second zirconia layer 124 in direct contact with the hafnium oxide layer 122 may be crystalline. In an embodiment, the first zirconia layer 120 and the second zirconia layer 124 may induce the crystallization of the hafnium oxide layer 122, such that the hafnium oxide layer 122 may have a stable tetragonal or orthorhombic crystal phase during the process used to form the dielectric layer structure 140 and the subsequent annealing process.
[0048] In one embodiment, the first zirconia layer 120 and the second zirconia layer 124 may have the same thickness. In another embodiment, the first zirconia layer 120 and the second zirconia layer 124 may have different thicknesses.
[0049] Each of the first zirconia layer 120 and the second zirconia layer 124 can independently have a thickness of about 5 Å to about 30 Å. Maintaining the thickness of each of the first zirconia layer 120 and the second zirconia layer 124 at about 5 Å or greater helps ensure that the first zirconia layer 120 and the second zirconia layer 124 induce the crystallization of the hafnium oxide layer 122, so that the hafnium oxide layer 122 can have a stable tetragonal or orthorhombic phase. Maintaining the thickness of each of the first zirconia layer 120 and the second zirconia layer 124 at about 30 Å or less helps ensure that the capacitor has a high target capacitance.
[0050] Figure 5 It is a graph showing the capacitance as a function of the applied voltage.
[0051] like Figure 5 As shown, the capacitance of capacitor 180, in which a lower electrode 110, a dielectric layer structure 140, and an upper electrode 150 are stacked, can have hysteresis characteristics. The capacitance can be maximized over a voltage range of approximately -1V to approximately 1V.
[0052] In an embodiment, the dielectric layer structure may include a first stacked structure in which a first zirconium oxide layer 120, a hafnium oxide layer 122, and a second zirconium oxide layer 124 are sequentially stacked, and the dielectric layer structure may also include at least one additional layer on or under the first stacked structure.
[0053] In addition to the dielectric layer structure, each embodiment described below is consistent with the reference. Figures 1 to 4 The capacitors described are the same. Therefore, the main description focuses on the dielectric layer structure.
[0054] Figure 6 This is an enlarged cross-sectional view of a capacitor according to an example embodiment.
[0055] Reference Figure 6 The capacitor 180a may include a stack of a lower electrode 110, a dielectric layer structure 140a, and an upper electrode 150.
[0056] The dielectric layer structure 140a may include an interface layer 130 and a first stacked structure in which a first zirconium oxide layer 120, a hafnium oxide layer 122, and a second zirconium oxide layer 124 are stacked. In an embodiment, the interface layer 130 may be additionally formed between the lower electrode 110 and the first zirconium oxide layer 120.
[0057] As described above, the dielectric layer structure 140a can have a thickness of about 20 Å to about 60 Å.
[0058] The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 may independently have a thickness of about 5 Å to about 30 Å. The thickness of the interface layer 130 may be controlled such that the sum of the thickness of the interface layer 130 and the thickness of the first stacked structure in which the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124 are stacked may be equal to or less than 60 Å. In an embodiment, the thickness of the interface layer 130 may be less than the thickness of the first zirconium oxide layer 120.
[0059] The interface layer 130 can help prevent direct contact between the lower electrode 110 and the first zirconia layer 120. The interface layer 130 can be a layer with a small lattice mismatch with the first zirconia layer 120.
[0060] In this embodiment, the interface layer 130 may include ZrNbO x Layer or TiNbO x Layer. In an embodiment, interface layer 130 may have TiNbO stacked therein. x Layers and ZrNbO x Layered structure.
[0061] In an embodiment, the dielectric layer structure 140a may further include an interface layer 130, which can reduce the residual stress of the dielectric layer structure 140a. Therefore, the capacitor including the dielectric layer structure 140a can have high capacitance.
[0062] Figure 7 This is an enlarged cross-sectional view of a capacitor according to an example embodiment.
[0063] Reference Figure 7 The capacitor 180b may include a stack of a lower electrode 110, a dielectric layer structure 140b, and an upper electrode 150.
[0064] The dielectric layer structure 140b may include a first stack structure 125, an insertion layer 132, and a third zirconia layer 134. In an embodiment, the insertion layer 132 and the third zirconia layer 134 may be further formed on the second zirconia layer 124.
[0065] The dielectric layer structure 140b may have a thickness of about 20 Å to about 60 Å. The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 may independently have a thickness of about 5 Å to about 30 Å. The thickness of the insertion layer 132 and the thickness of the third zirconium oxide layer 134 may be controlled separately, such that the sum of the thickness of the first stacked structure wherein the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124, the thickness of the insertion layer 132, and the thickness of the third zirconium oxide layer 134 may be equal to or less than 60 Å.
[0066] The insertion layer 132 may be located between the second zirconia layer 124 and the third zirconia layer 134. In an embodiment, the second zirconia layer 124 may be a crystalline layer, and the third zirconia layer 134 may be an amorphous layer. The insertion layer 132 may also be an amorphous layer. In an embodiment, the insertion layer 132 may be amorphous, and the third zirconia layer 134 may be formed on the insertion layer 132 and may also be amorphous.
[0067] The insertion layer 132 may include a metal oxide. In an embodiment, the insertion layer 132 may include oxides of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd. In an embodiment, the thickness of the insertion layer 132 may be less than the thickness of each of the second zirconium oxide layer 124 and the third zirconium oxide layer 134.
[0068] Compared to crystalline zirconia layers, amorphous zirconia layers can possess superior surface roughness. Therefore, in the capacitor 180b having a dielectric layer structure 140b according to this embodiment, the concentration of the electric field caused by the poor surface roughness of the dielectric layer can be reduced. Consequently, the leakage current of the capacitor 180b can be reduced.
[0069] Figure 8 This is an enlarged cross-sectional view of a capacitor according to an example embodiment.
[0070] Reference Figure 8 The capacitor 180c may include a stack of a lower electrode 110, a dielectric layer structure 140c, and an upper electrode 150.
[0071] The dielectric layer structure 140c may include an interface layer 130, a first stack structure 125, an insertion layer 132, and a third zirconia layer 134. In one embodiment, the interface layer 130 may be located between the lower electrode 110 and the first zirconia layer 120. The insertion layer 132 and the third zirconia layer 134 may be further formed on the second zirconia layer 124.
[0072] The dielectric layer structure 140c can have a thickness of about 20 Å to about 60 Å. The hafnium oxide layer 122 can have a thickness of about 5 Å to about 18 Å. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can independently have a thickness of about 5 Å to about 30 Å. The thickness of the interface layer 130, the thickness of the insertion layer 132, and the thickness of the third zirconium oxide layer 134 can be controlled separately, such that the sum of the thickness of the interface layer 130, the thickness of the first stacked structure in which the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124 is stacked, the thickness of the insertion layer 132, and the thickness of the third zirconium oxide layer 134 can be equal to or less than 60 Å.
[0073] The material of interface layer 130 can be compared with the reference. Figure 6 The material of the interface layer shown is the same. The material of the insertion layer 132 can be the same as the reference layer. Figure 7 The materials of the inserted layers shown are the same.
[0074] The dielectric layer structure 140c can have low residual stress. In an embodiment, a capacitor having the dielectric layer structure 140c can have high capacitance and can reduce the leakage current of the capacitor.
[0075] Figure 9 This is an enlarged cross-sectional view of a capacitor according to an example embodiment.
[0076] Reference Figure 9 The capacitor 180d may include a stack of a lower electrode 110, a dielectric layer structure 140d, and an upper electrode 150.
[0077] The dielectric layer structure 140d may include an interface layer 130, a first insertion layer 132a, a first stacked structure 125, a second insertion layer 132b, and a third zirconium oxide layer 134. In an embodiment, in Figure 8 In the capacitor structure shown, the capacitor may further include a first insertion layer 132a located between the interface layer 130 and the first stacked structure 125. The material of the first insertion layer 132a may be the same as that of the referenced layer. Figure 7 The insert layers shown are made of the same material. The first insert layer 132a can prevent the material in the first stack structure 125 from diffusing toward the lower electrode 110.
[0078] In some implementations, a second insertion layer may not be formed.
[0079] Figure 10 This is an enlarged cross-sectional view of a capacitor according to an example embodiment.
[0080] Reference Figure 10 The capacitor 180e may include a stack of a lower electrode 110, a dielectric layer structure 140e, and an upper electrode 150.
[0081] The dielectric layer structure 140e may include a first insertion layer 132a, an interface layer 130, a first stacked structure 125, a second insertion layer 132b, and a third zirconium oxide layer 134. In an embodiment, in Figure 8 In the capacitor structure shown, the capacitor may further include a first insertion layer 132a located between the lower electrode 110 and the interface layer 130. The material of the first insertion layer 132a may be the same as that used in the reference... Figure 7 The materials of the inserted layers shown are the same.
[0082] In some implementations, a second insertion layer may not be formed.
[0083] In the implementation method, Figure 10In the dielectric layer structure shown, the dielectric layer structure may further include an insertion layer located between the interface layer 130 and the first stacked structure 125. In an embodiment, the stacked structure including the insertion layer / interface layer / insertion layer may be located between the lower electrode 110 and the first stacked structure 125.
[0084] Figure 11 This is an enlarged cross-sectional view of a capacitor according to an example embodiment.
[0085] Reference Figure 11 The capacitor 180f may include a stack of a lower electrode 110, a dielectric layer structure 140f, and an upper electrode 150.
[0086] The dielectric layer structure 140f may include a first insertion layer 132a, a first stacked structure 125, a second insertion layer 132b, and a third zirconium oxide layer 134. In some embodiments, the dielectric layer structure 140f may not include an interface layer, but may also include... Figure 10 The dielectric layer structure shown depicts a first insertion layer 132a located between the lower electrode 110 and the first stacked structure 125. The material of the first insertion layer 132a can be the same as that used in the reference... Figure 7 The insert layers shown are made of the same material. In some embodiments, a second insert layer may not be formed.
[0087] Figures 12 to 14 This is a cross-sectional view of each stage in a method of manufacturing a capacitor according to an example embodiment.
[0088] The following describes an example of a method for manufacturing a capacitor including a lower electrode with a columnar shape.
[0089] Reference Figure 12 A molding layer 104 can be formed on the substrate. A portion of the molding layer 104 can be etched to form a hole. A hole can be formed at the portion used to form the lower electrode.
[0090] In one embodiment, a lower structure 102 may be further formed on the substrate 100 prior to forming the molding layer 104. The lower structure 102 may include a lower circuit comprising transistors, contact plugs, and wires, and an interlayer insulating layer covering the lower circuit.
[0091] A lower electrode layer that fills the holes can be formed on the molding layer 104. The lower electrode layer can be planarized until the upper surface of the molding layer 104 can be exposed to form the lower electrode 110 in the holes.
[0092] In this implementation, the lower electrode layer can be deposited using deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Planarization processes may include chemical mechanical polishing (CMP) or etch-back processes.
[0093] In one embodiment, a lower electrode layer may be formed on the lower structure 102. The lower electrode layer may be patterned using a photolithography process to form the lower electrode 110. In this case, a molding layer may not be formed on the lower structure 102.
[0094] Reference Figure 13 The molding layer 104 can be removed. Therefore, the surface of the lower electrode 110, which has a column shape, can be exposed.
[0095] A first zirconia layer 120 can be conformally formed on the surface of the lower electrode 110 and the surface of the lower structure 102 to achieve a uniform thickness. A hafnium oxide layer 122 can be formed on the first zirconia layer 120. A second zirconia layer 124 can be formed on the hafnium oxide layer 122. Therefore, a first stacked structure in which the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 are stacked can be formed on the lower electrode 110 and the lower structure 102.
[0096] The hafnium oxide layer 122 can be formed having a tetragonal or orthorhombic crystal phase. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can be formed having a crystalline phase. In an embodiment, each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can have a tetragonal crystal phase as a stable phase.
[0097] The dielectric layer structure 140 may have a thickness of about 20 Å to about 60 Å. Each of the first zirconium oxide layer 120 and the second zirconium oxide layer 124 may independently have a thickness of about 5 Å to about 30 Å. The hafnium oxide layer 122 may have a thickness of about 5 Å to about 18 Å.
[0098] In an embodiment, each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 can be formed by an atomic layer deposition (ALD) process. The deposition process for each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 can be performed at a relatively low temperature, for example, from about 200°C to about 450°C. Performing the deposition process for each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 at a temperature of about 200°C or higher can help ensure that each of the precursors can be thermally decomposed and that these layers can be deposited appropriately. Performing the deposition process for each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 at a temperature of about 450°C or lower can help ensure that these layers grow stably. In an embodiment, the deposition process for each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 can be performed at a temperature of about 200°C to about 320°C.
[0099] In an embodiment, the oxidant may include O3, H2O or O2 in the deposition process of each of the first zirconium oxide layer 120, the hafnium oxide layer 122 and the second zirconium oxide layer 124.
[0100] In one embodiment, each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 can be formed in a batch deposition apparatus. In another embodiment, each of the first zirconia layer 120, the hafnium oxide layer 122, and the second zirconia layer 124 can be formed in a single wafer deposition apparatus.
[0101] In one embodiment, the deposition chambers for forming the first zirconia layer 120 and the second zirconia layer 124 may be different from the deposition chamber for forming the hafnium oxide layer 122. Alternatively, in another embodiment, the deposition chambers for forming the first zirconia layer 120 and the second zirconia layer 124 may be the same as the deposition chamber for forming the hafnium oxide layer 122.
[0102] In an embodiment, a hafnium oxide layer 122 may be formed between a first zirconia layer 120 and a second zirconia layer 124, and the first stacked structure comprising the stacked first zirconia layer 120 / hafnium oxide layer 122 / second zirconia layer may have low residual stress.
[0103] During the formation of the hafnium oxide layer 122 and the formation of the second zirconium oxide layer 124 on the hafnium oxide layer 122, the hafnium oxide layer 122 can crystallize at a low temperature. Therefore, the hafnium oxide layer 122 can have a tetragonal or orthorhombic crystal phase. Furthermore, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can also crystallize during the formation of the first zirconium oxide layer 120, the second zirconium oxide layer 124, and the hafnium oxide layer 122. Therefore, the first zirconium oxide layer 120 and the second zirconium oxide layer 124 can have a stable tetragonal crystal phase.
[0104] In this embodiment, before forming the first zirconium oxide layer 120, an interface layer may be further formed on the surface of the lower electrode 110 and the surface of the lower structure 102 (see reference). Figure 6 130) to make the interface layer have a uniform thickness. In an embodiment, the interface layer 130 can be formed by an atomic layer deposition process. The deposition process of the interface layer 130 can be performed at a low temperature of about 200°C to about 450°C. In an embodiment, the deposition process of the interface layer 130 can be performed at a temperature of about 200°C to about 320°C. In this case, subsequent processes can be used to form a layer with a uniform thickness. Figure 6 The capacitor shown.
[0105] In an embodiment, an insertion layer may be further formed on the second zirconium oxide layer 124 (see reference). Figure 7 ,132) and the third zirconium oxide layer (refer to Figure 7, 134). The insertion layer 132 may include a metal oxide. In an embodiment, the insertion layer 132 may include an oxide of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd. In an embodiment, the insertion layer 132 may be formed to have a thickness smaller than that of each of the second zirconia layer 124 and the third zirconia layer 134. In an embodiment, the insertion layer 132 and the third zirconia layer 134 may be formed by an atomic layer deposition process. The deposition process of the insertion layer 132 and the third zirconia layer 134 may be performed at a low temperature of about 200°C to about 450°C. In an embodiment, the deposition process of the insertion layer 132 and the third zirconia layer 134 may be performed at a temperature of about 200°C to about 320°C. In this case, subsequent processes may be used to form, such as Figure 7 The capacitor shown.
[0106] In this embodiment, before forming the first zirconium oxide layer 120, an interface layer may be further formed on the surface of the lower electrode 110 and the surface of the lower structure 102 (see reference). Figure 8 , 130), to make the interface layer have a uniform thickness. An insert layer can be further formed on the second zirconia layer 124 (see reference). Figure 8 ,132) and the third zirconium oxide layer (refer to Figure 8 In this case, it can be formed through subsequent processes such as 134). Figure 8 The capacitor shown.
[0107] It can be formed by performing additional processes to form the interface layer and / or the insertion layer, as well as subsequent processes. Figures 9 to 11 One of the capacitors shown.
[0108] Reference Figure 14 An upper electrode 150 can be formed on the second zirconium oxide layer 124.
[0109] In one embodiment, the upper electrode 150 may be formed of the same material as the lower electrode 110. In another embodiment, the upper electrode 150 may be formed of a different material than the lower electrode 110.
[0110] In one implementation, the upper electrode 150 can be formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).
[0111] In one embodiment, after the upper electrode 150 is formed, an annealing process may be further performed. During the annealing process, the first zirconium oxide layer 120 / hafnium oxide layer 122 / second zirconium oxide layer 124 included in the dielectric layer structure 140 may be additionally or further crystallized. In another embodiment, the annealing process may be performed at a temperature higher than the temperature of the deposition process used to form the dielectric layer structure 140.
[0112] As described above, the hafnium oxide layer 122 included in the dielectric layer structure 140 can have a tetragonal or orthorhombic crystal phase. Zirconia layers 120 and 124 can be formed on the upper and lower surfaces (e.g., the inner and outer surfaces) of the hafnium oxide layer 122, respectively, thereby reducing the residual stress in the dielectric layer structure 140. Therefore, the dielectric layer structure 140 can have a low coercive field, and the capacitance of the capacitor can be significantly increased in the range of about -1V to about 1V, which is the operating voltage range of the capacitor including the dielectric layer structure 140.
[0113] Figure 15 This is a cross-sectional view of a DRAM device with capacitors according to an example embodiment.
[0114] Despite Figure 15 Only DRAM devices are shown, but capacitors can be used in all memory devices that use capacitors as data storage units.
[0115] Reference Figure 15 A DRAM device may include cell transistors, capacitors, and bit lines formed on a substrate. A DRAM device may include a unit cell comprising one cell transistor and one capacitor.
[0116] The substrate 200 may include an active region and a field region. The field region may be the area in which an isolation layer 220 is formed in an isolation trench included in the substrate 200. The active region may be the region of the substrate other than the field region.
[0117] A gate trench 202 extending along a first direction parallel to the upper surface of the substrate 200 may be formed on the upper part of the substrate 200. A gate structure 210 may be formed in the gate trench 202.
[0118] In one embodiment, the gate structure 210 may include a gate insulating layer 204, a gate electrode 206, and a cap insulating pattern 208. Multiple gate structures 210 may be arranged in a second direction parallel to the upper surface of the substrate 200 and perpendicular to the first direction.
[0119] The gate insulating layer 204 may include silicon oxide. The gate electrode 206 may include a metallic material or polysilicon. The cap insulating pattern 208 may include silicon nitride.
[0120] Impurity regions 230, which serve as source / drain regions, can be formed in the active regions of the substrate 100 located between the gate structures 210.
[0121] In one embodiment, the impurity region 230 may include a first impurity region 230a electrically connected to the bit line structure 260 and a second impurity region 230b electrically connected to the capacitor 180.
[0122] A pad insulating pattern 240, a first etch stop pattern 242, and a first conductive pattern 246 may be formed on the active region, the isolation layer 220, and the gate structure 210. The pad insulating pattern 240 may include an oxide such as silicon oxide, and the first etch stop pattern 242 may include a nitride such as silicon nitride. The first conductive pattern 246 may include polysilicon doped with impurities.
[0123] The recessed portion can pass through the stacked structure including the pad insulating pattern 240, the first etch stop pattern 242, and the first conductive pattern 246. The recessed portion can be disposed in the portion of the substrate 100 located between the gate structures. The upper surface of the first impurity region 230a can be exposed through the bottom of the recessed portion.
[0124] A second conductive pattern 248 can be formed to fill the recessed portion. The second conductive pattern 248 may include, for example, polysilicon doped with impurities. In an embodiment, the second conductive pattern 248 may contact the first impurity region 230a.
[0125] The third conductive pattern 250 may be stacked on the first conductive pattern 246 and the second conductive pattern 248. The third conductive pattern 250 may include, for example, polysilicon doped with impurities. Since the first to third conductive patterns 246, 248 and 250 comprise substantially the same material, they may be merged into a single pattern. The barrier metal pattern 252, the metal pattern 254 and the hard mask pattern 256 may be stacked on the third conductive pattern 250.
[0126] The stacked structure including the first conductive pattern 246, the second conductive pattern 248, the third conductive pattern 250, the blocking metal pattern 252, the metal pattern 254 and the hard mask pattern 256 can be used as the bit line structure 260.
[0127] In one embodiment, the second conductive pattern 248 can be used as a bit line contact, and the first conductive pattern 246, the third conductive pattern 250, the blocking metal pattern 252, and the metal pattern 254 can be used as bit lines. The bit line structure 260 can extend along a second direction. A plurality of bit line structures 260 can be arranged along a first direction.
[0128] In one embodiment, spacers may be formed on the sidewall of the bit line structure 260.
[0129] In one embodiment, a first interlayer insulating layer may be formed to fill the portion between bit line structures 260.
[0130] A contact plug 270 can be formed through the first interlayer insulating layer, the first etch stop pattern 242, and the pad insulating pattern 240. The contact plug 270 can contact the second impurity region 230b. The contact plug 270 can be located between the bit line structures 260.
[0131] Capacitor 180 may be formed on contact plug 270.
[0132] The capacitor 180 may include a lower electrode 110, a dielectric layer structure 140, and an upper electrode 150. The dielectric layer structure 140 may include a stack of a first zirconium oxide layer 120, a hafnium oxide layer 122, and a second zirconium oxide layer 124.
[0133] Capacitor 180 may have the same characteristics as referenced. Figure 1 The capacitor shown has the same structure. In this embodiment, the capacitor may have the same structure as the reference capacitor. Figures 6 to 8 The capacitors shown have the same structure as one of them.
[0134] The plate electrode 160 may be further formed on the upper electrode 150. The plate electrode 160 may comprise polycrystalline silicon doped with impurities.
[0135] DRAM devices can operate within a voltage range of approximately -1V to approximately 1V. In capacitors, the dielectric constant of the dielectric layer structure can be significantly increased within this range, thus greatly increasing the capacitance. DRAM devices can therefore exhibit excellent electrical characteristics.
[0136] By summarizing and reviewing, it can be found that when DRAM devices are highly integrated, the capacitors included in the DRAM may have difficulty achieving high capacitance and low leakage current.
[0137] One or more embodiments may provide capacitors with high capacitance.
[0138] One or more embodiments may provide a DRAM device including a capacitor with high capacitance.
[0139] In an example embodiment, the dielectric layer structure included in the capacitor may have ferroelectric properties over an operating voltage range (e.g., an operating voltage range of about -1V to about 1V). The capacitor may have high capacitance over the operating voltage range.
[0140] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used in a general and descriptive sense only and will be interpreted as such, not for limiting purposes. In some instances, as will be apparent to those skilled in the art from the time of filing of this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.
Claims
1. A capacitor, the capacitor comprising: Lower electrode; The dielectric layer structure is located on the lower electrode; as well as The upper electrode is located on the dielectric layer structure. The dielectric layer structure includes: An interface layer, located on the lower electrode, includes zirconium oxide and niobium oxide. The first layer, comprising zirconium oxide, is located on the interface layer; and The second layer, located directly above the first layer, is composed of hafnium oxide. The second layer has a tetragonal or orthorhombic phase.
2. The capacitor according to claim 1, wherein, The dielectric layer structure also includes a third layer located between the first layer and the interface layer, which may contain Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd.
3. The capacitor according to claim 1, wherein, The dielectric layer structure also includes a fourth layer, which includes zirconium or zirconium oxide.
4. The capacitor according to claim 3, wherein, The fourth layer is amorphous.
5. The capacitor according to claim 1, wherein, Each of the lower and upper electrodes comprises titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, tungsten, or tungsten nitride.
6. The capacitor according to claim 1, wherein, The lower electrode has a cylindrical shape.
7. The capacitor according to claim 1, wherein, The first layer has a thickness of 5 Å to 30 Å.
8. The capacitor according to claim 1, wherein, The second layer has a thickness of 5 Å to 18 Å.
9. The capacitor according to claim 1, wherein, The dielectric layer structure has a thickness of 20 Å to 60 Å.
10. The capacitor according to claim 1, wherein, The first layer has an orthorhombic crystalline phase.
11. A capacitor, the capacitor comprising: Lower electrode; The dielectric layer structure is located on the lower electrode; as well as The upper electrode is located on the dielectric layer structure. The dielectric layer structure includes: The interface layer contacts the lower electrode and includes a zirconium niobium layer, a titanium niobium layer, or a stacked structure of titanium niobium layer and zirconium niobium layer. The first zirconium oxide layer is located on the interface layer; A hafnium oxide layer, directly situated on the first zirconium oxide layer, and having a tetragonal or orthorhombic phase; and An insertion layer is located between the interface layer and the first zirconia layer, and the insertion layer includes at least one of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc or Gd.
12. The capacitor according to claim 11, wherein, The first zirconium oxide layer has a thickness of 5 Å to 30 Å.
13. The capacitor according to claim 11, wherein, The hafnium oxide layer has a thickness of 5 Å to 18 Å.
14. The capacitor according to claim 11, wherein, The dielectric layer structure also includes a second zirconium oxide layer located on the hafnium oxide layer.
15. A memory device, the memory device comprising; Base; A unit transistor is located on a substrate and includes a gate structure, a first impurity region, and a second impurity region. Bitline structure, electrically connected to the first impurity region; as well as The capacitor, located on the bitline structure, is electrically connected to the second impurity region. Among them, capacitors include: Lower electrode; An interface layer, located on the lower electrode, includes a zirconium niobium oxide layer; An insertion layer, located on the interface layer, includes A1; The first zirconium oxide layer is located on the interface layer; A hafnium oxide layer, directly situated on the first zirconium oxide layer, and having a tetragonal or orthorhombic phase; and The upper electrode is located on the hafnium oxide layer.
16. The memory device according to claim 15, wherein, The lower electrode has a cylindrical shape.
17. The memory device according to claim 15, wherein, The gate structure is located in the gate trench and includes a gate insulating layer, a gate electrode, and a cap insulating pattern.