MOSFET Device and Its Fabrication Method

Abstract

The present application provides a MOSFET device and a method for manufacturing the same. The device includes at least one first region, which includes a first doped region, a second doped region, and a first body region. The first doped region is located on the side of the epitaxial layer away from the substrate. The second doped region surrounds the outer periphery of the first doped region. The first body region is located on the side of the second doped region close to the substrate. The first region is in contact with the source electrode of the MOSFET device. A plurality of second regions are distributed on the outer periphery of the first region. The second region includes an epitaxial region, a third doped region, and a second body region. The second body region surrounds the outer periphery of the epitaxial region. The third doped region is located on the side of the second body region away from the epitaxial region. Among them, the first body region is in contact with the second body region, the third doped region is in contact with the second doped region, and the second region is in contact with the gate structure of the MOSFET device, so as to solve the problems of large on-resistance and non-optimizable area of the MOSFET device in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, it relates to a MOSFET device and a method for manufacturing the same. Background Art

[0002] In the conventional hexagonal cell layout plane of a metal-oxide-semiconductor field-effect transistor (MOSFET), the cells are arranged in sequence and orderly. Among them, the cell includes a source region and a JFET region. The JFET region surrounds the outer periphery of the source region. Moreover, between any two adjacent cells, the source regions in the two cells are isolated by the JFET region. In this structure, the size of the cell has reached the limit of the current process capabilities. It is difficult to further reduce the size of the device cell and the size of the JFET region, resulting in the on-resistance of the device not being able to be further reduced, and it is difficult to optimize the area of the chip.

[0003] In the design of a MOSFET device, a thin layer of oxide is used as an insulating layer, which separates the gate from the core working area of the transistor. However, the gate oxide layer of a power MOSFET device is extremely fragile and is extremely vulnerable to electrostatic discharge (ESD). Once the ESD phenomenon occurs, it may cause the breakdown of the gate oxide layer, resulting in serious failures of the device. Even minor damage will also affect its performance and lifespan. Summary of the Invention

[0004] The main objective of this application is to provide a MOSFET device and a method for manufacturing the same, so as to solve the problems of large on-resistance and non-optimizable area of the MOSFET device in the prior art.

[0005] To achieve the above object, according to one aspect of the present application, a MOSFET device is provided, including a substrate, an epitaxial layer, a gate structure and a source. The epitaxial layer is located on one side of the substrate. The MOSFET device further includes: at least one first region located in the epitaxial layer, including a first doped region, a second doped region and a first body region. The first doped region is located on the side of the epitaxial layer away from the substrate. The second doped region surrounds the outer periphery of the first doped region. The first body region is located on the side of the second doped region close to the substrate. The first region is in contact with the source of the MOSFET device; a plurality of second regions located in the epitaxial layer and the plurality of second regions are distributed on the outer periphery of the first region. The second region includes an epitaxial region, a third doped region and a second body region. The epitaxial region is located on the side of the epitaxial layer away from the substrate. The second body region surrounds the outer periphery of the epitaxial region. The third doped region is located on the side of the second body region away from the epitaxial region and the third doped region is located on the side of the second body region away from the substrate. Wherein, the first body region is in contact with the second body region, the third doped region is in contact with the second doped region. Both the second doped region and the third doped region have a first doping type. The first doped region, the first body region and the second body region all have a second doping type. The second region is in contact with the gate structure of the MOSFET device.

[0006] Optionally, the first region has a first orthographic projection on a first surface, and the second region has a second orthographic projection on the first surface. The area of the first orthographic projection is greater than or equal to the area of the second orthographic projection. The first surface is the surface where the substrate contacts the epitaxial layer.

[0007] Optionally, there are multiple first regions, and there are two second regions between any two adjacent first regions in a first direction. Wherein, the first direction is the direction from the first region to the second region.

[0008] Optionally, it also includes at least one diode structure, which is located in at least one second region. In any direction parallel to the first surface, the epitaxial region has a portion located between the diode structure and the second body region. The diode structure includes a plurality of fourth doping regions stacked along the second direction, and any two adjacent fourth doping regions have different doping types. The fourth doping region with the smallest distance from the substrate in the second direction is the first target doping region, and the fourth doping region with the largest distance from the first target doping region is the second target doping region. The first target doping region and the epitaxial layer have different doping types. The number of the fourth doping regions is greater than or equal to 4 layers, and the first target doping region is in contact with the gate structure, and the second target doping region is in contact with the source. The second direction is perpendicular to the first surface, and the first surface is the surface of the substrate in contact with the epitaxial layer.

[0009] Optionally, the gate structure includes a sub-gate structure, which is in contact with the diode structure, and the sub-gate structure includes: a sub-gate oxide layer, which is at least respectively located on the side of the second body region facing away from the substrate, and the sub-gate oxide layer is respectively in contact with the second body region, the third doping region, the sub-epitaxial region and the first target doping region, wherein the portion of the epitaxial region located between the diode structure and the second body region is the sub-epitaxial region; a sub-gate, which is at least located on the side of the sub-gate oxide layer facing away from the substrate, and the sub-gate is also located on the side of the first target doping region facing away from the substrate, and the sub-gate is in contact with the first target doping region.

[0010] Optionally, the doping concentrations of the first target doping region and the second target doping region are respectively lower than the doping concentration of the adjacent fourth doping region.

[0011] Optionally, the second region having the diode structure is a target second region, and the target second region and the second region are spaced apart along the circumference of the first region.

[0012] Optionally, the first doping region and the first target doping region have the same doping concentration.

[0013] According to another aspect of the present application, a method for preparing a MOSFET device is provided, comprising: providing a substrate; forming an epitaxial layer on one side of the substrate; forming at least one first region and multiple second regions in the epitaxial layer, wherein the first region comprises a first doped region, a second doped region, and a first body region, the first doped region is located on a side of the epitaxial layer away from the substrate, the second doped region surrounds the periphery of the first doped region, the first body region is located on a side of the second doped region close to the substrate, the first region contacts the source of the MOSFET device, multiple second regions are distributed on the periphery of the first region, and the second region comprises an epitaxial region , a third doped region and a second body region, the epitaxial region is located on the side of the epitaxial layer away from the substrate, the second body region surrounds the periphery of the epitaxial region, the third doped region is located on the side of the second body region close to the epitaxial region, and the third doped region is located on the side of the second body region close to the substrate, wherein the first body region is in contact with the second body region, the third doped region is in contact with the second doped region, the second doped region and the third doped region respectively have a first doping type, the first doped region, the first body region and the second body region respectively have a second doping type, and the second region is in contact with the gate structure of the MOSFET device.

[0014] Optionally, the preparation method also includes forming at least one diode structure, and the steps of forming the diode structure include: performing multiple ion implantations in the epitaxial region to form multiple fourth doping regions stacked along the second direction, wherein, in any direction parallel to the first surface, the epitaxial region has a portion between the diode structure and the second body region, any two adjacent fourth doping regions have different doping types, the fourth doping region close to the substrate is a target doping region, the target doping region and the epitaxial layer have a different doping type, the number of film layers of the fourth doping region in the diode structure is greater than or equal to 4 layers, wherein the first surface is the surface of the substrate in contact with the epitaxial layer, and the second direction is perpendicular to the first surface.

[0015] Applying the technical solution of the present application, the above MOSFET device has a new cell layout. In the new cell, the source region includes both the first doped region, the second doped region and the first body region in the first region, and also includes the third doped region and the second body region in the second region. Here, the second region surrounds the outer periphery of the first region, and the epitaxial region in the second region is a JFET region. Moreover, the third doped region and the second body region are arranged around the periphery of the epitaxial region, that is, there are the third doped region and the second body region between two adjacent epitaxial regions. Therefore, in the new cell, the JFET region does not surround the outer periphery of the source region, but the source region surrounds the outer periphery of the JFET region, which improves the channel ratio of the device and further reduces the on-resistance of the device. And, in the above new cell layout, multiple second regions are arranged around the first region of the cell. The first region is in contact with the source, and the second region is in contact with the gate, such that there is no size limitation for the first doped region and the source contact hole in the second region. Using this layout structure can reduce the cell pitch, thereby achieving the reduction of the on-resistance and the shrinkage of the chip area. In addition, due to the presence of the third doped region between adjacent JFET regions, the third doped region and the second doped region are heavily doped regions in the cell, and the third doped region is in contact with the second doped region. Furthermore, the new cell increases the area of the heavily doped region in the device, and thus increases the stability of the channel current conduction of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments of the present application and the descriptions thereof are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0017] Figure 1 is a schematic cross-sectional structure diagram of a MOSFET device according to the prior art;

[0018] Figure 2 is a schematic top-view structure diagram of a MOSFET device according to the prior art;

[0019] Figure 3 is a schematic cross-sectional structure diagram of a MOSFET device according to an embodiment of the present application;

[0020] Figure 4 is a schematic top-view structure diagram of a MOSFET device according to an embodiment of the present application;

[0021] Figure 5 is a schematic cross-sectional structure diagram of another MOSFET device according to an embodiment of the present application;

[0022] Figure 6 is a schematic top-view structure diagram of another MOSFET device according to an embodiment of the present application;

[0023] Figure 7 It is a top view structural schematic diagram of another MOSFET device according to an embodiment of the present application;

[0024] Figure 8 It is a cross-sectional structural schematic diagram of another MOSFET device according to an embodiment of the present application;

[0025] Figure 9 It is a top view structural schematic diagram of another MOSFET device according to an embodiment of the present application;

[0026] Figure 10 It is a structure and circuit diagram of a PNPN diode according to an embodiment of the present application;

[0027] Figure 11 It is a flowchart of a preparation method of a MOSFET device according to an embodiment of the present application;

[0028] Figure 12 It is a basic structural schematic diagram obtained in each step in a preparation method of a MOSFET device according to an embodiment of the present application.

[0029] Among them, the above-mentioned drawings include the following reference numerals:

[0030] 10. Substrate; 11. Source region; 12. JFET region; 20. Epitaxial layer; 21. P-plus region; 22. N-plus region; 23. P-well region; 31. Gate structure; 310. Sub-gate structure; 311. Gate oxide layer; 3110. Sub-gate oxide layer; 312. Gate; 3120. Sub-gate; 313. Dielectric layer; 32. Source; 41. First region; 411. First doping region; 412. Second doping region; 413. First body region; 42. Second region; 421. Epitaxial region; 422. Third doping region; 423. Second body region; 50. Diode structure; 511. First target doping region; 512. Second target doping region; 61. Body region; 62. Second doping type injection region; 63. First doping type injection region. Detailed implementation manners

[0031] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanations of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of the present invention herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element or there can also be intervening elements. Also, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element or "connected" to the other element through a third element.

[0035] As introduced in the background art, in the prior art, the MOSFET device has a conventional hexagonal cell layout plane as Figure 1As shown, the cell includes a substrate 10 and an epitaxial layer 20 on one side of the substrate 10. The source region 11 and the JFET region 12 are alternately arranged in the epitaxial layer 20 along a third direction parallel to the surface where the substrate 10 contacts the epitaxial layer 20. The source region 11 includes a P-plus region 21, an N-plus region 22, and a P-well region 23. Among them, the P-plus region 21 is located in the epitaxial layer 20, the N-plus region 22 is located on the side of the P-plus region 21, and the P-well region 23 is located on the side of the N-plus region 22 close to the substrate 10 and on the side of the N-plus region 22 away from the P-plus region 21. The JFET region 12 is located on the side of the P-well region 23 away from the P-plus region 21. The MOSFET device further includes a gate structure 31 and a source 32. Among them, the gate structure 31 contacts the JFET region 12, the source region 11 contacts the source 32, the gate structure 31 includes a gate oxide layer 311 and a gate 312, and the gate oxide layer 311 is located on the side of the gate 312 close to the substrate 10. Figure 2 is Figure 1 a plan view of the structure shown at the surface of the epitaxial layer 20 away from the substrate 10, and Figure 1 is Figure 2 a cross-sectional view of the structure shown at aa′, as Figure 2 shown, the cells are arranged in sequence and orderly. Among them, the cell includes a source region 11 and a JFET region 12, and the JFET region 12 surrounds the outer periphery of the source region 11. Among them, the N-plus region 22 in the source region 11 surrounds the outer periphery of the P-plus region 21, and the P-well region 23 surrounds the outer periphery of the P-plus region 21. And, between any two adjacent cells, the source regions 11 in the two cells are completely isolated by the JFET region 12. In this structure, the size of the cell has reached the limit of the current process capabilities, and it is difficult to further reduce the sizes of the source region 11 and the JFET region 12 of the device, resulting in the on-resistance of the device not being able to be further reduced and the area of the chip being difficult to be optimized. To solve the above technical problems, embodiments of the present application provide a MOSFET device and a method for manufacturing the same.

[0036] Next, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention.

[0037] According to one aspect of the present application, a MOSFET device is provided, as Figure 3As shown, the MOSFET device includes a substrate 10, an epitaxial layer 20, a gate structure 31 and a source 32, the epitaxial layer 20 is located on one side of the substrate 10, and the MOSFET device further includes: at least one first region 41, located in the epitaxial layer 20, including a first doped region 411, a second doped region 412 and a first body region 413, the first doped region 411 is located on the side of the epitaxial layer 20 away from the substrate 10, the first body region 413 is located on the side of the second doped region 412 close to the substrate 10, and the first region 41 is in contact with the source 32 of the MOSFET device; a plurality of second regions 42, located in the epitaxial layer 20 and the plurality of second regions 42 are distributed on the periphery of the first region 41, and the second region 42 includes the epitaxial region 411. Region 421, a third doped region 422, and a second body region 423, the epitaxial region 421 is located on the side of the epitaxial layer 20 facing away from the substrate 10, the third doped region 422 is located on the side of the second body region 423 facing away from the epitaxial region 421, and the third doped region 422 is located on the side of the second body region 423 facing away from the substrate 10, wherein the first body region 413 is in contact with the second body region 423, the third doped region 422 is in contact with the second doped region 412, the second doped region 412 and the third doped region 422 both have the first doping type, the first doped region 411, the first body region 413, and the second body region 423 both have the second doping type, and the second region 42 is in contact with the gate structure 31 of the MOSFET device, wherein Figure 4 for Figure 3 The structure shown is a plan view of the surface of the epitaxial layer 20 facing away from the substrate 10, and Figure 3 for Figure 4 The cross-sectional view of the structure shown at bb′ is as follows: Figure 4 As shown, the second doping region 412 surrounds the outer periphery of the first doping region 411 , and the second body region 423 surrounds the outer periphery of the epitaxial region 421 .

[0038] A new cell layout is formed in the above MOSFET device, such as Figure 4As shown in the figure, the source region in the new cell includes both the first doped region 411, the second doped region 412, and the first body region in the first region, and also includes the third doped region 422 and the second body region 423 in the second region 42. Here, the second region 42 surrounds the outer periphery of the first region. The epitaxial region 421 in the second region 42 is a JFET region. Moreover, the third doped region 422 and the second body region 423 are disposed around the epitaxial region 421. That is, there are the third doped region 422 and the second body region 423 between two adjacent epitaxial regions 421. Therefore, in the new cell, the JFET region does not surround the outer periphery of the source region, but the source region surrounds the outer periphery of the JFET region. During the gate opening process, a carrier channel is formed in the source region as indicated by the current direction arrow, thereby increasing the channel ratio of the device and reducing the on-resistance of the device. And in the above new cell layout, multiple second regions 42 are arranged around the first region of the cell. The first region is in contact with the source, and the second region 42 is in contact with the gate, such that there is no size limitation for the first doped region and the source contact hole in the second region 42. Using this layout structure can reduce the cell pitch, thereby achieving a reduction in the on-resistance and a reduction in the chip area. In addition, since there is a third doped region between adjacent JFET regions, the third doped region and the second doped region are the plus regions in the cell, and the third doped region is in contact with the second doped region. Thus, the new cell increases the area of the plus region in the device, and further increases the stability of the channel current conduction of the device.

[0039] In the above embodiment, as Figure 5 shown, Figure 5 is Figure 4 a cross-sectional view of the structure shown at cc'. There are the third doped region 422 and the second body region 423 between two adjacent epitaxial regions 421. The third doped region 422 and the second body region 423 constitute the source region, and the epitaxial region 421 constitutes the JFET region. Compared with the conventional cell layout shown in Figure 2 where the entire JFET region 12 surrounds the source region 11, in the above new cell layout shown in Figure 4 not only multiple JFET regions are arranged around the source region, but also a source region is formed between the JFET regions, increasing the channel ratio of the device, and thus reducing the on-resistance of the device. In addition, Figure 5 the positional relationship of other structures shown in Figure 3 is the same as the positional relationship of the structure in

[0040] Figure 3 and Figure 5 shown, in the structure shown in

[0041] In some optional embodiments, the first region has a first orthographic projection on the first surface, the second region has a second orthographic projection on the first surface, the area of the first orthographic projection is greater than or equal to the area of the second orthographic projection, and the first surface is the surface where the substrate contacts the epitaxial layer.

[0042] Specifically, the second region includes a JEFT region, and the second region contacts the gate structure. The second orthographic projection of the second region is less than or equal to the first orthographic projection of the first region, which means that the second region has a smaller area, that is, the gate structure of the device has a smaller coverage area, reducing the gate capacitance. When the device performs a switching operation, the rising and falling speeds of the gate voltage are accelerated, thereby improving the switching speed of the MOSFET and reducing the switching loss. Moreover, since the second regions all have a smaller area, more cells can be integrated on the chip, thereby improving the utilization rate of the chip, saving the chip area, and possibly reducing the production cost and increasing the integration degree of the device.

[0043] In the above embodiments, the first orthographic projection can be a polygon such as a circle, a hexagon, a rectangle, a square, etc., and the present application does not make specific limitations.

[0044] In some optional embodiments, as Figure 6 shown, there are multiple first regions 41. There are two second regions 42 between any two adjacent first regions 41 in the first direction, where the first direction is the direction from the first region 41 to the second region 42. Additionally, Figure 6 the positional relationships of other structures shown in Figure 4 are the same as those of the structures in

[0045] Specifically, in the traditional MOSFET layout, the source region and the JFET region are arranged according to fixed design rules. There needs to be a sufficient distance between the source and the gate structure to ensure the stability of the device. At the same time, in order to form a reliable source contact, a plus injection region and contact holes of a larger size are required, which limits the further reduction of the cell size, and thus affects the on-resistance of the device and the chip area. In the new cell layout of the present application, six second regions surround the first region, that is, a new "1 + 6" cell layout is formed, such that the gate structure and the source are no longer restricted by the sizes of the plus injection region and the source contact holes, reducing the spacing between regions of each cell and decreasing the on-resistance.

[0046] Exemplarily, as Figure 4 shown, the first region has a first orthographic projection on the first surface, the second region 42 has a second orthographic projection on the first surface. The shapes of the first orthographic projection and the second orthographic projection can be hexagons, and six second regions 42 surround the periphery of the first region. Further, asFigure 6 As shown, in the case where there are multiple first regions 41 in the MOSFET device, the periphery of the second region 42 surrounds the first region 41 and the second region 42, and the first regions 41 and the second regions 42 surrounded by the periphery of one second region 42 are arranged alternately at intervals.

[0047] Specifically, since a hexagonal region can achieve a tight arrangement, it can significantly reduce the chip area, lower the manufacturing cost, also shorten the distance between the source and the drain, reduce the length of the JFET region, thereby reducing the on-resistance of the MOSFET and improving the current-carrying capacity and efficiency of the device. Moreover, six hexagonal second regions surround the periphery of the hexagonal first region. The first region is in contact with the source, and the second region is based on the gate structure. Furthermore, in the MOSFET device, the gate structure and the source are no longer limited by the plus injection region and the size of the source contact hole, making the spacing between regions between cells smaller and reducing the on-resistance. In addition, in the new layout of the "1 + 6" cells, both the first region and the second region are hexagonal structures, forming a tighter arrangement relationship, reducing the isolation gap, enabling the same number of first regions and second regions to be arranged in a smaller space, thus saving the chip area.

[0048] In some optional embodiments, as Figure 3 and Figure 5 shown, the gate structure 31 includes: a gate oxide layer 311, the gate oxide layer 311 is located on the side of the second region 42 away from the substrate 10; a gate 312, the gate 312 is at least located on the side of the gate oxide layer 311 away from the substrate 10.

[0049] Specifically, the epitaxial region in the second region is a JFET region, and the source region is between adjacent JFET regions. So the second region includes a JFET region and a source region. Forming a gate on the second region can precisely control the formation of a channel in the source region, increase the proportion of the channel in the device, thereby optimizing the switching behavior of the MOSFET. And the gate is in close contact with the channel, which can improve the modulation efficiency of the channel conductivity, reduce the on-resistance of the device while ensuring fast and reliable switching actions.

[0050] In the above embodiment, as Figure 7 shown, Figure 7 is Figure 3Cross-sectional view of the structure shown at ee'. The source electrode 32 is located on the side of the first region 41 away from the substrate. The source electrode 32 is in contact with the first doped region 411. Above the side of the second region 42 away from the substrate is the gate electrode 312. Moreover, the gate electrode 312 is part of the gate structure, and the epitaxial region 421 is in contact with the gate structure. The gate electrode 312 surrounds the outer periphery of the source electrode 32, and the source electrode 32 and the gate electrode 312 are isolated by a dielectric layer 313. A channel is formed in the second body region and the third doped region in the second region 42 to increase the proportion of the channel, reduce the on-resistance of the device. And by arranging the gate structure on the second region 42, the design of the MOSFET can be made more compact, improving the integration of the chip. This helps to reduce the chip size and at the same time, more components can be integrated on the same-sized chip, achieving miniaturization of the device and improving the performance of the device.

[0051] In some alternative embodiments, as Figure 8 shown, the MOSFET device further includes at least one diode structure 50. The diode structure 50 is located in at least one second region 42. In any direction parallel to the first surface, there is a portion in the epitaxial region 421 between the diode structure 50 and the second body region 423. The diode structure 50 includes a plurality of fourth doped regions stacked along the second direction A. Any two adjacent fourth doped regions have different doping types. The fourth doped region with the smallest distance from the substrate 10 in the second direction A is the first target doped region 511, and the fourth doped region with the largest distance from the first target doped region 511 is the second target doped region 512. The first target doped region 511 has a different doping type from the epitaxial layer 20. The number of fourth doped regions is greater than or equal to 4 layers, and the first target doped region 511 is in contact with the gate structure 31, and the second target doped region 512 is in contact with the source electrode 32. Here, the second direction A is perpendicular to the first surface, and the first surface is the surface where the substrate 10 and the epitaxial layer 20 are in contact. Additionally, Figure 8 the positional relationship of other structures shown in Figure 3 is the same as that of the structure in

[0052]

[0053] Figure 8 In some alternative embodiments, as Figure 8As shown, the gate structure includes a sub-gate structure 310. The sub-gate structure 310 is in contact with the diode structure 50 shown. The sub-gate structure 310 includes: a sub-gate oxide layer 3110, the sub-gate oxide layer 3110 is at least located on the side of the second body region 423 away from the substrate 10, and the sub-gate oxide layer 3110 is in contact with the second body region 423, the third doped region 422, the sub-epitaxial region and the first target doped region 511 respectively. Among them, the part of the epitaxial region 421 between the diode structure 50 and the second body region 423 is the sub-epitaxial region; a sub-gate 3120, the sub-gate 3120 is at least located on the side of the sub-gate oxide layer 3110 away from the substrate 10, the sub-gate 3120 is also located on the side of the first target doped region 511 away from the substrate 10, and the sub-gate 3120 is in contact with the first target doped region 511.

[0054] Specifically, in the diode structure, the first target doped region is in contact with the sub-gate, and the second target doped region is in contact with the source. Since two adjacent fourth doped regions have different doping types, a plurality of PN junction structures are formed between the plurality of fourth doped regions. Among them, since the number of fourth doped regions is greater than 4, there is a reverse-biased PN junction in the diode structure. Under normal operating conditions of the device, the reverse-biased PN junction can isolate the current from the gate to the source; when ESD occurs, the reverse-biased PN junction is broken down, and the ESD current is released, protecting the gate oxide layer from being broken down and improving the electrostatic discharge resistance of the gate structure.

[0055] In some optional embodiments, such as Figure 8 and Figure 9As shown, the diode structure 50 is located in at least one epitaxial region 421. The fourth doped region in contact with the epitaxial layer 20 is the first target doped region 511, and the fourth doped region farther from the first target doped region 511 is the second target doped region 512. The gate structure 31 in contact with the diode structure 50 includes multiple sub-gate structures 310. The sub-gate structure 310 includes a sub-gate oxide layer 3110 and a sub-gate 3120. Among them, the sub-gate oxide layer 3110 is in contact with the second body region 423, the third doped region 422, the epitaxial region 421, and a part of the first target doped region 511. The sub-gate 3120 is located on the side of the sub-gate oxide layer 3110 away from the substrate 10, and the sub-gate 3120 is also located on the side of a part of the first target doped region 511 away from the substrate 10. The sub-gate 3120 is in contact with the first target doped region 511. A dielectric layer 313 is provided on the side of the sub-gate structure 310 away from the substrate 10, and the dielectric layer 313 is also located on the sidewalls of the sub-gate structure 310. A source electrode 32 is provided between the dielectric layers 313 on the sidewalls of two adjacent and opposite sub-gate structures 310. The source electrode 32 is in contact with the second target doped region 512. When the device undergoes electrostatic discharge, the gate current flows into the diode structure 50 through the first target doped region 511 and flows to the source electrode 32 through the second target doped region 512, so that the electrostatic current is released to avoid breakdown of the gate oxide layer and protect the gate oxide layer.

[0056] In the above embodiment, Figure 9 A top view structural schematic diagram of a device is shown, and Figure 8 is Figure 9 a cross-sectional view of the shown structure at dd′, as Figure 8 and Figure 9 shown, the diode structure 50 is located in the epitaxial region 421. The second target doped region 512 is located in the middle of the epitaxial region 421, and the remaining fourth doped layers surround the outer periphery of the second target doped region 512 to form a "hui" (Chinese character for "return") structure, where the second target doped region 512 is located on the outermost periphery.

[0057] In the above specific implementation manner, the number of the fourth doped regions is 4 layers, so two PN junction structures are formed in the diode structure. The position where the two PN junction structures contact forms an anti-biased PN junction. That is, in the diode structure, two forward-biased PN junctions and an anti-biased PN junction are formed, and the anti-biased PN junction is located between the two forward-biased PN junctions. The above structure can achieve ESD protection for the gate oxide while reducing the process cost.

[0058] Exemplarily, if the epitaxial layer is N-type, the distribution mode of forming multiple fourth doping layers in the diode structure is PNPN type distribution. The PNPN diode is a semiconductor switching device with a four-layer structure and two terminals (i.e., anode and cathode). This diode structure is also called a four-layer diode, and its function is similar to that of an ordinary diode without any trigger input. Under reverse bias conditions, no current flows through it, while under forward bias conditions, when its voltage exceeds its breakdown voltage, current flows through it. The basic structure, analogy of two transistors, and symbol of the PNPN diode are as Figure 10 shown. Among them, J1 is a forward-biased PN junction, J2 is a reverse-biased PN junction, J3 is a forward-biased PN junction, A is the anode (i.e., the gate), K is the cathode (i.e., the source), T1 is the transistor T1 composed of the P region and N region of J1 and the P region of J2, and T2 is the transistor T2 composed of the N region of J2 and the P region and N region of J3. The equivalent circuit of this diode using two transistors is as shown, where the collector of transistor T1 is connected to the base of T2. The junction J1 is formed at the emitter-base junction of T1, J2 is at the common base-collector junction between T1 and T2, and J3 is at the base-emitter junction of T2. Therefore, as the base-emitter junction, J1 and J3 must be forward-biased, and as the collector-base junction, J2 must be reverse-biased for linear operation.

[0059] As described above, the diode structure consists of three junctions J1, J2, and J3. When a voltage is applied to this diode with the anode positive relative to the cathode, the junctions J1 and J3 are forward-biased, while J2 is reverse-biased. Until the voltage across the diode is less than the breakdown voltage, as an open switch, this diode exhibits a very high resistance and does not allow current to flow through it. Once the breakdown voltage is reached (as the forward voltage increases), due to the breakdown of junction J2, it exhibits a very low resistance. Therefore, it is like a short circuit and allows current to flow until the current reaches the holding current level of the diode. The forward current flowing through the diode depends on the applied voltage and the external load resistance.

[0060] When the anode is negative relative to the cathode, the junctions J1 and J3 are reverse-biased, while the junction J2 is forward-biased. If the reverse bias voltage is increased (exceeding the breakdown voltage of the Shockley diode), J1 and J3 are reverse-biased, and then a reverse current will flow through the diode. This reverse current will generate heat, which may further damage the entire diode. Therefore, the PNPN diode must never operate under reverse bias conditions where its voltage is equal to the reverse breakdown voltage. Once the Shockley diode is turned on, it is like a closed switch and provides a very low resistance to current. To turn off the diode (or be like an open switch), the applied voltage must be reduced to a value such that the current flowing through the diode is less than the holding current IH of the diode. In this state, the junction J2 returns to its high resistance from the reverse breakdown state.

[0061] In some optional embodiments, the doping concentrations of the first target doping region and the second target doping region are respectively smaller than the doping concentration of the adjacent fourth doping region.

[0062] Specifically, the breakdown voltage of the reverse-biased PN junction in the diode structure is greater than the gate turn-on voltage and less than the breakdown voltage of the gate oxide layer. Therefore, when the MOSFET device is working normally, no current flows through the diode structure due to the presence of the reverse-biased PN junction. When the gate voltage exceeds the gate turn-on voltage, the reverse-biased PN junction is broken down, allowing the gate current to pass through the diode structure and be released from the source to protect the gate oxide layer from breakdown.

[0063] In some optional embodiments, the second region having the diode structure is the target second region, and the target second region and the second region are spaced apart along the circumference of the first region.

[0064] Specifically, during an electrostatic discharge (ESD) event, current will concentrate in the gate area of the MOSFET, which may cause local overheating and damage to the gate oxide layer. By arranging diode structures at intervals in the second area surrounding the first area, the ESD current can be dispersed into multiple paths, thereby avoiding local damage caused by current concentration and providing more uniform and extensive protection for the device. The diode structure can quickly enter avalanche breakdown mode during an ESD event, forming a low-resistance state to discharge current. The interval-arranged diode structure adds multiple ESD protection units, improving the device's ability to withstand and discharge ESD energy, allowing the MOSFET to operate more safely and reliably when subjected to ESD shocks. In addition, when an ESD event occurs, heat will be concentrated in one point, causing local overheating and affecting the life of the device. The interval-arranged diode structures in the second area surrounding the first area help to disperse the heat, reducing the risk of thermal damage caused by ESD events.

[0065] In the above embodiment, the target second regions and the second regions are alternately arranged along the circumferential direction of the first region.

[0066] Specifically, the target second region is alternately spaced with the second region, resulting in an alternating distribution of JFET regions and diode structures, with the gate located above the JFET region. This alternating distribution achieves optimal protection for the gate oxide. Furthermore, evenly distributing the diode structures around the first region reduces the effects of parasitic capacitance and resistance, which can affect the switching speed and performance of the MOSFET. By optimizing the layout, these adverse effects can be reduced, improving the overall performance of the device.

[0067] For example, Figure 9As shown, the first area 41 is surrounded by three target second areas and three second areas, and the three target second areas and the three second areas are alternately arranged at intervals, wherein the first orthographic projection and the second orthographic projection are both hexagonal.

[0068] Specifically, the gate oxide layer is susceptible to damage from electrostatic discharge (ESD). Three targeted second regions and three second regions, alternating around the first region, ensure that the ESD protection mechanism is evenly distributed across the entire gate structure, preventing any local area from experiencing excessive electrostatic shock, thereby improving overall ESD resistance. The diode structure serves as a path for rapidly dissipating current during an ESD event. Since ESD shocks often have extremely high energy, if only one or a few ESD protection cells are present, they may not fully absorb the ESD energy, causing device damage. The alternating PNPN diode structure provides more parallel current paths, enhancing current discharge capability and protecting the MOSFET from damage. Alternating the diode structures within the six second regions optimizes the spatial layout within the device while maintaining ESD protection. This means that more functional components can be integrated within the limited chip area, enabling a more compact chip design, reducing chip area, and lowering costs.

[0069] In some optional embodiments, the first doping region and the first target doping region have the same doping concentration.

[0070] Specifically, during the preparation process, the first doping region and the first target doping region can be doped using the same process, which simplifies the process steps.

[0071] According to another method of the present application, a method for preparing a MOSFET device is provided, which is used to prepare any type of MOSFET device, such as Figure 11 As shown, the preparation method includes:

[0072] Step S401: providing a substrate;

[0073] Step S402: forming an epitaxial layer on one side of the substrate;

[0074] Step S403: forming at least one first region and multiple second regions in the epitaxial layer, the first region including a first doped region, a second doped region and a first body region, the first doped region being located on a side of the epitaxial layer away from the substrate, the second doped region surrounding the periphery of the first doped region, the first body region being located on a side of the second doped region close to the substrate, the first region being in contact with the source of the MOSFET device, the multiple second regions being distributed around the periphery of the first region, the second region including an epitaxial region, a third doped region and a second body region, the epitaxial region being located on a side of the epitaxial layer away from the substrate, the second body region surrounding the periphery of the epitaxial region, the third doped region being located on a side of the second body region close to the epitaxial region, and the third doped region being located on a side of the second body region close to the substrate, wherein the first body region is in contact with the second body region, the third doped region is in contact with the second doped region, the second doped region and the third doped region respectively have a first doping type, the first doped region, the first body region and the second body region respectively have a second doping type, and the second region is in contact with the gate structure of the MOSFET device.

[0075] Using the above-described fabrication method of the embodiment of the present application, a new cell layout is formed in a MOSFET device. The source region in the new cell includes both the first doped region, the second doped region, and the first body region in the first region, and the third doped region and the second body region in the second region. The second region surrounds the periphery of the first region, and the epitaxial region in the second region serves as the JFET region. Furthermore, the third doped region and the second body region are arranged around the epitaxial region, i.e., the third doped region and the second body region are located between two adjacent epitaxial regions. Therefore, in the new cell, the JFET region does not surround the periphery of the source region, but rather the source region surrounds the periphery of the JFET region, thereby increasing the channel ratio of the device and thereby reducing the on-resistance of the device. Furthermore, in the above-described new cell layout, multiple second regions are arranged around the first region of the cell, with the first region contacting the source and the second region contacting the gate. This eliminates the size restrictions of the first doped region and the source contact hole in the second region. This layout structure can reduce the cell spacing, thereby reducing on-resistance and chip area. In addition, since there is a third doped region between adjacent JFET regions, the third doped region and the second doped region are the plus region in the cell, and the third doped region is in contact with the second doped region, so the new cell increases the area of the plus region in the device, thereby increasing the stability of the channel current conduction of the device.

[0076] The following will describe in more detail exemplary embodiments of the method for preparing a MOSFET device according to the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0077] First, as shown in Figure 12 (a), perform step S401: Provide a substrate 10.

[0078] Specifically, the substrate materials include materials such as silicon carbide, silicon, gallium nitride, gallium oxide, gallium arsenide, and aluminum nitride. Those skilled in the art can reasonably select according to actual needs, and the present application does not make specific limitations. Among them, the substrate has a first doping type.

[0079] After providing the substrate, as shown in Figure 12 (b), perform step S402: Form an epitaxial layer 20 on one side of the substrate 10.

[0080] Specifically, the epitaxial layer has a first doping type.

[0081] Furthermore, the process for forming the epitaxial layer includes but is not limited to deposition processes and epitaxial growth processes. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control, and the activation rate is relatively fixed, making it easy to achieve the target doping profile. It is not only applicable to silicon-based power devices but can also avoid the injection doping difficulties of silicon carbide power devices and improve the efficiency of their terminal structures. The deposition process is relatively mature, simple to operate, and has a low cost. Among them, the deposition process includes but is not limited to Physical Vapor Deposition (abbreviated as PVD), Chemical Vapor Deposition (abbreviated as CVD), and Atomic Layer Deposition (abbreviated as ALD). Among them, Physical Vapor Deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and Chemical Vapor Deposition (CVD) includes but is not limited to Plasma Enhanced Chemical Vapor Deposition (abbreviated as PECVD), Metal-Organic Chemical Vapor Deposition (abbreviated as MOCVD), Laser-induced Chemical Vapor Deposition (abbreviated as LCVD). Those skilled in the art can reasonably select according to actual needs, and the present application does not make specific limitations.

[0082] After forming the epitaxial layer, perform step S403: Form at least one first region and multiple second regions.

[0083] Specifically, the steps of forming the first region and the second region may include: First, a first barrier layer is formed on the epitaxial layer by a deposition process; then, the first barrier layer is patterned, and the pattern exposes the epitaxial layer; then, an ion implantation process is used to form a body region 61 as shown in the top view of Figure 12 Figure (c) in the exposed epitaxial layer; then, the remaining first barrier layer is removed to obtain a structure as shown in Figure 12 Figure (d); a second barrier layer is formed on the epitaxial layer by a deposition process; then, the second barrier layer is patterned, and the pattern exposes the epitaxial layer; then, an ion implantation process is used to form a second doping type implantation region 62 as shown in the top view of Figure 12 Figure (e) in the exposed epitaxial layer; then, the remaining second barrier layer is removed to obtain a structure as shown in Figure 12 Figure (f); then, a third barrier layer is formed on the epitaxial layer by a deposition process; then, the first barrier layer is patterned, and the pattern exposes the epitaxial layer; then, an ion implantation process is used to form a first doping type implantation region 63 as shown in the top view of Figure 12 Figure (g) in the exposed epitaxial layer 20; then, the remaining third barrier layer is removed to obtain a structure as shown in Figure 12 Figure (h).

[0084] Among them, as shown in Figure 12 Figure (h), the body region 61 includes a first body region 413 and a second body region 423, the second doping type implantation region 62 includes a first doping region 411, the first doping type implantation region 63 includes a second doping region 412 and a third doping region 422, the region in the epitaxial layer 20 where no ion implantation is performed constitutes an epitaxial region 421, the first doping region 411, the second doping region 412 and the first body region 413 constitute the first region 41, and the epitaxial region 421, the second body region 423 and the third doping region 422 constitute the second region 42.

[0085] After step S403, the above preparation method further includes step S404: forming a diode structure 50 to obtain a structure as shown in Figure 12 Figure (i).

[0086] Specifically, the steps of forming the diode include: First, multiple ion implantations are performed in the epitaxial region to form multiple fourth doping regions stacked along the second direction. Among them, in any direction parallel to the first surface, for the part between the diode structure and the second body region in the epitaxial region, any two adjacent fourth doping regions have different doping types, the fourth doping region close to the substrate is the target doping region, the target doping region and the epitaxial layer have different doping types, and the number of film layers of the fourth doping region in the diode structure is greater than or equal to 4 layers. Here, the first surface is the surface where the substrate contacts the epitaxial layer, and the second direction is perpendicular to the first surface.

[0087] After step S404, the above preparation method further includes step S405: forming a gate structure 31 to obtain the structure shown in Figure 12 (j), wherein the gate structure 31 includes a gate oxide layer 311 and a gate 312.

[0088] Specifically, the steps of forming the gate structure include: First, a gate oxide layer is formed on the epitaxial layer by a deposition process, and the gate oxide layer contacts the second doped region and the second body region; then, a gate is formed on the gate oxide layer by a deposition process; then, two etching processes are used to form through holes penetrating to the epitaxial region in the gate and the gate oxide layer, wherein the remaining gate oxide layer is located on the side of the first sub-region away from the substrate, the region in the epitaxial region contacting the first sub-body region is the first region, the first sub-body region is the region in the second body region located on the side of the third doped region close to the epitaxial region, and the gate is at least located on the side of the gate oxide layer away from the substrate; then, a dielectric layer is deposited on the side and the side surface of the gate structure away from the substrate to prevent the gate from being short-circuited with the source.

[0089] In addition, the above gate is also located on the side of the first target doped region away from the substrate, so that the first target doped region contacts the gate, so that the diode structure protects the gate oxide.

[0090] In some optional embodiments, the first target doped region and the first doped region are ion-implanted by the ion implantation process in the same process step, which simplifies the process steps.

[0091] After step S405, the above preparation method further includes step S406: forming a source 32 to obtain the structure shown in Figure 3 as shown.

[0092] Specifically, the steps of forming the source and drain include: First, a first conductive layer is formed on the side of the above substrate away from the substrate by a deposition process, wherein the first conductive layer contacts the first doped region, the second doped region and the second target doped region respectively; then, a second conductive layer is formed on the side of the substrate away from the epitaxial layer by a deposition process.

[0093] Wherein, the first conductive layer is the source of the MOSFET device, and the second conductive layer is the drain of the MOSFET device.

[0094] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A MOSFET device, characterized in that: The MOSFET device comprises a substrate, an epitaxial layer, a gate structure and a source, wherein the epitaxial layer is located on one side of the substrate, and further comprises: at least one first region, located in the epitaxial layer, comprising a first doped region, a second doped region, and a first body region, wherein the first doped region is located on a side of the epitaxial layer facing away from the substrate, the second doped region surrounds an outer periphery of the first doped region, the first body region is located on a side of the second doped region close to the substrate, and the first region is in contact with a source of the MOSFET device; a plurality of second regions, located in the epitaxial layer and distributed around the periphery of the first region, the second region including an epitaxial region, a third doped region, and a second body region, the epitaxial region being located on a side of the epitaxial layer facing away from the substrate, the second body region surrounding the periphery of the epitaxial region, the third doped region being located on a side of the second body region facing away from the epitaxial region, and the third doped region being located on a side of the second body region facing away from the substrate, wherein the first body region contacts the second body region, the third doped region contacts the second doped region, the second doped region and the third doped region both have a first doping type, the first doped region, the first body region, and the second body region all have a second doping type, and the second region contacts the gate structure of the MOSFET device, A plurality of second regions are surrounded by one first region, the epitaxial region is a JFET region, and the third doped region and the second body region both surround the periphery of the JFET region.

2. The MOSFET device according to claim 1, wherein The first region has a first orthographic projection on the first surface, the second region has a second orthographic projection on the first surface, the area of the first orthographic projection is greater than or equal to the area of the second orthographic projection, and the first surface is the surface of the substrate in contact with the epitaxial layer.

3. The MOSFET device according to claim 1, wherein There are multiple first regions, and there are two second regions between any two adjacent first regions in a first direction, wherein the first direction is the direction from the first region to the second region.

4. The MOSFET device according to claim 1, wherein It also includes at least one diode structure, which is located in at least one second region. In any direction parallel to the first surface, the epitaxial region has a portion located between the diode structure and the second body region. The diode structure includes a plurality of fourth doping regions stacked along the second direction, and any two adjacent fourth doping regions have different doping types. The fourth doping region with the smallest distance from the substrate in the second direction is the first target doping region, and the fourth doping region with the largest distance from the first target doping region is the second target doping region. The first target doping region and the epitaxial layer have different doping types. The number of the fourth doping regions is greater than or equal to 4 layers, and the first target doping region is in contact with the gate structure, and the second target doping region is in contact with the source. The second direction is perpendicular to the first surface, and the first surface is the surface of the substrate in contact with the epitaxial layer.

5. The MOSFET device according to claim 4, wherein: The gate structure includes a sub-gate structure, the sub-gate structure is in contact with the diode structure, and the sub-gate structure includes: a sub-gate oxide layer, the sub-gate oxide layer being located at least on a side of the second body region facing away from the substrate, the sub-gate oxide layer being in contact with the second body region, the third doped region, the sub-epitaxial region, and the first target doped region, wherein a portion of the epitaxial region between the diode structure and the second body region is the sub-epitaxial region; A sub-gate, wherein the sub-gate is at least located on a side of the sub-gate oxide layer away from the substrate, and the sub-gate is also located on a side of the first target doping region away from the substrate, and the sub-gate is in contact with the first target doping region.

6. The MOSFET device according to claim 4, wherein: The doping concentrations of the first target doping region and the second target doping region are respectively lower than the doping concentration of the adjacent fourth doping region.

7. The MOSFET device according to claim 4, wherein: The second region having the diode structure is a target second region, and the target second region and the second region are spaced apart from each other along the circumference of the first region.

8. The MOSFET device according to claim 4, wherein: The first doping region and the first target doping region have the same doping concentration.

9. A method for preparing a MOSFET device, characterized in that: include: providing a substrate; forming an epitaxial layer on one side of the substrate; At least one first region and a plurality of second regions are formed in the epitaxial layer, the first region including a first doped region, a second doped region and a first body region, the first doped region is located on a side of the epitaxial layer away from the substrate, the second doped region surrounds the periphery of the first doped region, the first body region is located on a side of the second doped region close to the substrate, the first region contacts the source of the MOSFET device, a plurality of second regions are distributed on the periphery of the first region, the second region includes an epitaxial region, a third doped region and a second body region, the epitaxial region is located on a side of the epitaxial layer away from the substrate, the second body region surrounds the periphery of the epitaxial region, the third doped region The region is located on a side of the second body region close to the epitaxial region, and the third doped region is located on a side of the second body region close to the substrate, wherein the first body region is in contact with the second body region, the third doped region is in contact with the second doped region, the second doped region and the third doped region respectively have a first doping type, the first doped region, the first body region and the second body region respectively have a second doping type, the second region is in contact with the gate structure of the MOSFET device, a plurality of second regions are surrounded by one first region, the epitaxial region is a JFET region, and the third doped region and the second body region both surround the periphery of the JFET region.

10. The preparation method according to claim 9, characterized in that The method further includes forming at least one diode structure, wherein the steps of forming the diode structure include: Multiple ion implantations are performed in the epitaxial region to form a plurality of fourth doping regions stacked along a second direction, wherein in any direction parallel to the first surface, the epitaxial region has a portion between the diode structure and the second body region, any two adjacent fourth doping regions have different doping types, the fourth doping region close to the substrate is a target doping region, the target doping region and the epitaxial layer have a different doping type, the number of film layers of the fourth doping region in the diode structure is greater than or equal to 4 layers, wherein the first surface is a surface of the substrate in contact with the epitaxial layer, and the second direction is perpendicular to the first surface.

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