Display driving apparatus for reducing power consumption and method of operating same

Abstract

The invention discloses a display driving device. The display driving apparatus includes: a receiving circuit to receive first display data including a first set of data values; a transmission control circuit for outputting first display data or outputting second display data including a second set of data values according to a result of comparing the first set of data values with a target data value; and a data processing circuit for processing the first display data or the second display data output from the transmission control circuit, in which the transmission control circuit includes an inversion circuit that bypasses the first display data to the data processing circuit if the first set of data values are not the same as the target data values, respectively; if the first set of data values are the same as the target data values, respectively, the inversion circuit converts the first set of data values into second set of data values, respectively having values complementary to the first set of data values, and outputs second display data including the second set of data values to the data processing circuit.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuits, and more particularly to a display driving device for a display device.

[0002] For simplicity of description, this specification describes a source driver integrated circuit (IC) as an example of a display driving device, but the present invention can be applied to any type of display driving device. Background Art

[0003] A source driver integrated circuit (IC) for driving data lines included in a display device includes a digital-to-analog converter (DAC) (hereinafter referred to as "DAC") and a level shifter.

[0004] To control the on or off state of each switch included in the DAC and consuming dynamic current, each level shifter shifts the voltage of each input digital video signal to generate an output digital video signal having a shifted voltage level.

[0005] In response to the output digital video signal having a shifted voltage level output from the level shifter, a switch included in the DAC outputs one of the gray-scale voltages generated by a gray-scale voltage generator to one of the data lines.

[0006] However, as the resolution of the display device increases, the number of source driver ICs also increases in proportion to the resolution, and as the number of source driver ICs increases, the number of level shifters also increases. This results in an increase in current consumption due to the level shifters, thereby increasing the power consumption of the source driver IC. Summary of the Invention

[0007] Technical Problem

[0008] To solve the above problems, the present invention aims to provide a source driver IC capable of reducing power consumption by inverting specific display data values, a display device including the source driver IC, and a method for reducing the power consumption of the source driver IC.

[0009] Technical Solution

[0010] According to an aspect of the present invention, a display driving device for overcoming the above technical problems includes: a receiving circuit configured to receive first display data including a first set of data values; a transmission control circuit configured to output the first display data or second display data including a second set of data values based on a comparison result between the first set of data values and target data values; and a data processing circuit configured to process the first display data or the second display data output from the transmission control circuit, wherein the transmission control circuit includes an inversion circuit configured to bypass the first display data to the data processing circuit when the first set of data values are not respectively the same as the target data values, convert the first set of data values into the second set of data values respectively complementary to the first set of data values when the first set of data values are respectively the same as the target data values, and output the second display data including the second set of data values to the data processing circuit.

[0011] According to another aspect of the present invention, an operation method of a display driving device for overcoming the above technical problems includes: receiving first display data including a first set of data values; determining whether the first set of data values are the same as target data values; bypassing the first display data when the first set of data values are not respectively the same as the target data values; and outputting second display data including a second set of data values instead of the first set of data values when the first set of data values are respectively the same as the target data values, wherein the second set of data values are respectively complementary to the first set of data values.

[0012] Advantageous Effects

[0013] According to the present invention, by dynamically inverting specific display data values, the power consumption of a digital-to-analog converter (DAC) can be reduced, and by reducing the power consumption of the DAC, the power consumption of a source driver IC can be reduced. Brief Description of the Drawings

[0014] Figure 1 is a block diagram of a display device including a source driver IC according to an embodiment of the present invention.

[0015] Figure 2 is Figure 1 a block diagram of the source driver IC shown.

[0016] Figure 3 is a timing diagram showing the operation of a latch circuit that latches odd data and even data provided to Figure 2 the source driver IC.

[0017] Figure 4 shows included in Figure 2An example of a circuit diagram of an inverter circuit in a transmission control circuit of a source driver IC.

[0018] Figure 5 is for explaining Figure 4 An embodiment of display data for the operation of the inverter circuit shown.

[0019] Figure 6 is for explaining Figure 4 Another embodiment of display data for the operation of the inverter circuit shown.

[0020] Figure 7 Shows an example of a transmission control circuit included in Figure 2 the source driver IC, the transmission control circuit including a determination circuit and an inverter circuit.

[0021] Figure 8a is a table showing Figure 7 the operation of the selection signal generation circuit shown.

[0022] Figure 8b is a table showing Figure 2 the input and output signals of each of the first data processing circuit and the second data processing circuit shown.

[0023] Figure 8c Exemplarily shows Figure 2 the levels of each grayscale voltage shown in

[0024] Figure 9 is a circuit diagram of a first level shifter included in Figure 2 the source driver IC.

[0025] Figure 10 is a circuit diagram of a second level shifter included in Figure 2 the source driver IC.

[0026] Figure 11 is a flowchart showing the operation of a transmission control circuit according to an embodiment of the present invention.

[0027] Figure 12 is a flowchart showing Figure 7 the operation of the transmission control circuit shown. DETAILED DESCRIPTION

[0028] Throughout the specification, the same reference numerals denote substantially the same components. In the following description, if configurations and features known in the art are not relevant to the core configuration of the present invention, detailed descriptions thereof may be omitted. The terms used in this specification should be understood as follows.

[0029] Advantages and features of the present invention and methods for realizing them will become apparent from the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the following embodiments, but can be implemented in various different forms; on the contrary, these embodiments are provided to make the description of the present invention complete and allow those skilled in the art to fully understand the scope of the present invention, and the present invention is defined only within the scope of the appended claims.

[0030] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for illustrating the embodiments of the present invention are merely examples, and the present invention is not limited thereto. Throughout the specification, the same reference numerals may denote the same components. In addition, when describing the present invention, detailed descriptions of known related technologies may be omitted if they are considered to unnecessarily obscure the gist of the present invention.

[0031] Terms such as "comprising", "having", "including", etc. used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise specifically stated, references to components in the singular include the plural of that noun.

[0032] When interpreting components, they are interpreted as including a range of errors even if not explicitly stated.

[0033] When describing positional relationships, for example, "on...", "above...", "below...", or "next to..." describe the positional relationship between two parts, and unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0034] When describing temporal context relationships, for example, such as "after...", "thereafter", "next", or "before...", non - consecutive cases may also be included, unless "immediately" or "directly" is used.

[0035] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical concept of the present invention, the first component mentioned herein may also be the second component.

[0036] It should be understood that the term "at least one" includes any combination that can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" may represent each of the first item, the second item, and the third item, and any combination of items that can be presented from two or more of the first item, the second item, and the third item.

[0037] Each feature of the various embodiments of the present invention can be coupled or combined with each other in whole or in part, and can be technically interlocked and operated in various ways, and each embodiment can be executed independently or in combination with each other.

[0038] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram of a display device including a source driver IC according to an embodiment of the present invention.

[0040] Refer to Figure 1 , the display device 1000 includes a display panel 1100, a source driver IC block 1200, a gate driver IC block 1300, and a timing controller 1400.

[0041] The display device 1000 may be a liquid crystal display (LCD) device, a light emitting diode (LED) display device, an organic light emitting diode (OLED) display device, or an active matrix organic light emitting diode (AMOLED) display device. For example, the display device 1000 may be a notebook computer, but is not limited thereto.

[0042] The display panel 1100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX. The plurality of pixels PX are connected to each of the gate lines GL and each of the data lines DL, and are arranged in a matrix form.

[0043] The source driver IC block 1200 includes a plurality of source driver ICs 100 and 100_1 for driving the data lines DL. In one embodiment, the data lines DL may be referred to as channels, and the source driver ICs 100 and 100_1 may be referred to as data driver ICs.

[0044] For example, the first source driver IC 100 drives the first group of data lines DL1 among the data lines DL, and the second source driver IC 100_1 drives the second group of data lines DL2 among the data lines DL. It is assumed that the structures of the source driver ICs 100 and 100_1 are the same.

[0045] The gate driver IC block 1300 includes a plurality of gate driver ICs 1301 and 1302 that generate gate driving signals to drive the gate lines GL.

[0046] For example, the first gate driver IC 1301 generates a first gate driving signal for driving the first group of gate lines GL1 among the gate lines GL, and the second gate driver IC 1302 generates a second gate driving signal for driving the second group of gate lines GL2 among the gate lines GL. It is assumed that the structures of the gate driver ICs 1301 and 1302 are the same.

[0047] The timing controller 1400 generates gate drive control signals GCTL for controlling the operations of each of the plurality of gate driver ICs 1301 and 1302, and outputs them to the plurality of gate driver ICs 1301 and 1302.

[0048] In addition, the timing controller 1400 generates a clock signal CLK, display data DATA, and source drive control signal SCTL, and outputs them to the plurality of source driver ICs 100 and 100_1.

[0049] Figure 2 is Figure 1 a block diagram of the source driver IC shown.

[0050] Reference Figure 1 and Figure 2 , since the source driver ICs 100 and 100_1 have the same structure, the structure and operation of the first source driver IC 100 will be described in detail with reference to Figures 1 to 11 the details.

[0051] The first source driver IC (or the first source driver IC package) 100 includes a control logic circuit 202, a first data processing circuit (or odd data processing circuit) 205_1, a second data processing circuit (or even data processing circuit) 205_2, and a grayscale voltage generation circuit 300.

[0052] The control logic circuit 202 includes a receiving circuit 203 and a transmission control circuit 400. Although Figure 2 not shown in, the control logic circuit 202 may further include a configuration for generating a first latch enable signal EN1 and a second latch enable signal EN2 using the source drive control signal SCTL.

[0053] The receiving circuit 203 receives display data (e.g., RGB data) DATA using the clock signal CLK, and transfers the received display data to the transmission control circuit 400. In this case, the display data may be first display data including a first set of data values.

[0054] When the first display data is received from the receiving circuit 203, based on the comparison result between the first set of data values and the target data values, the transmission control circuit 400 outputs the first display data to the first data processing circuit 205_1 or the second data processing circuit 205_2, or outputs the second display data including the second set of data values to the first data processing circuit 205_1 or the second data processing circuit 205_2. In one embodiment, the transmission control circuit 400 may include a determination circuit 401 and an inversion circuit 402.

[0055] Hereinafter, reference will be made to Figure 11 briefly describe the operation of the transmission control circuit 400 of the present invention. Figure 11 is a flowchart showing the operation of the transmission control circuit according to an embodiment of the present invention. Refer to Figure 2 and Figure 11 , the transmission control circuit 400 receives the first display data DATA including the first set of data values from the receiving circuit 203, and determines whether the first set of data values is the same as the target data values (S110), and if it is determined that the first set of data values is different from the target data values ("No" in S120), the transmission control circuit 400 sets the first display data DATA(=ODDi <n:1>or EVEN <n:1>)Bypass to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S130). On the other hand, as a result of the determination in step S120, if the first set of data values is the same as the target data value ("Yes" in step S120), the transmission control circuit 400 will use the second display data ODDi that includes the second set of data values instead of the first set of data values <n:1>or EVEN <n:1>Output to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S140).

[0056] For example, even if the first data processing circuit 205_1 receives first display data ODDi including a first set of data values <n:1>or a second display data ODDi including a second set of data values <n:1>, the first data processing circuit 205_1 also outputs a grayscale voltage corresponding to the first set of data values among the first set of grayscale voltages VGMA_VH0 to VGMA_VH255 as a first output signal OUT1 (S150).

[0057] In addition, even if the second data processing circuit 205_2 receives the first display data EVENi including the first set of data values <n:1>or a second display data EVENi including a second set of data values <n:1>, the second data processing circuit 205_2 also outputs the gray-scale voltages corresponding to the first set of data values in the second set of gray-scale voltages VGMA_VL0 to VGMA_VL255 as the second output signal OUT2 (S150).

[0058] In Figure 8c the levels of each of the first set of gray-scale voltages VGMA_VH0 to VGMA_VH255 and the levels of each of the second set of gray-scale voltages VGMA_VL0 to VGMA_VL255 are exemplarily shown.

[0059] According to an embodiment, the data value can be either data 1 or data 0.

[0060] According to an embodiment, the target data values can all be the same. For example, when N is 8 and the target data value that is the same as the first set of data values is 00000000 (or 11111111), the second set of data values is 11111111 (or 00000000).

[0061] According to an embodiment, when only one of the target data values is one of data 1 and data 0, each of the remaining target data values can be the other of data 1 and data 0.

[0062] For example, when N is 8 and the target data value that is the same as the first set of data values is 00000001, 00000010, 00000100, 00001000, 00010000, 00100000, 01000000, or 10000000, the second set of data values is 11111110, 11111101, 11111011, 11110111, 11101111, 11011111, 10111111, or 01111111.

[0063] The second set of data values is complementary to the first set of data values respectively. For example, data 1 (also referred to as logic 1) and data 0 (also referred to as logic 0) are considered to be complementary to each other.

[0064] Figure 3 is a timing diagram showing the operation of a latch circuit that latches odd data and even data provided to Figure 2 the source driver IC.

[0065] From the perspective of the timing of the display data DATA input to the control logic circuit 202, Figure 3 each of the display data ODD1 shown <n:1>, EVEN1 <n:1>, ODD2 <n:1>, EVEN2 <n:1>,...... is continuous (or serial) display data (or display data stream).

[0066] For example, each display data ODD1 <n:1>, EVEN1 <n:1>, ODD2 <n:1>, EVEN2 <n:1>, …… are N-bit serial display data, where each of the N bits is data 1 or data 0. The voltage of data 1 is at a high level, and the voltage of data 0 is at a low level.

[0067] Reference Figure 2 and Figure 3 , the transmission control circuit 400 of the control logic circuit 202 extracts (or separates) the odd data ODDi from the serial input display data DATA using the clock signal CLK <n:0>and even data EVENi <n:0>, and the extracted data ODDi is in a time division manner <n:0>or EVENi <n:0>Output to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0068] Therefore, assuming that in response to the first latch enable signal EN1, when the first data processing circuit 205_1 operates, the second data processing circuit 205_2 does not operate, and when the second data processing circuit 205_2 operates, the first data processing circuit 205_1 does not operate.

[0069] The first data processing circuit 205_1 receives the odd data ODDi output from the transmission control circuit 400 <n:1>, process it (for example, sequentially perform a latching operation, a serial-to-parallel conversion operation, a voltage level shifting operation, and a digital-to-analog conversion operation), and output the processing result OUT1 to one of the first data lines DL1. Here, N and i are natural numbers.

[0070] The second data processing circuit 205_2 receives the even data EVENi output from the transmission control circuit 400 <n:1>, it is processed (for example, a latching operation, a serial-to-parallel conversion operation, a voltage level shift operation, and a digital-to-analog conversion operation are sequentially performed), and the processing result OUT2 is output to another one of the first data lines DL1.

[0071] The first data processing circuit 205_1 includes a first latch circuit 210_1, a second latch circuit 220_1, a first level shifter circuit 230_1, a first DAC 240_1, and a first output buffer 250_1.

[0072] The first latch circuit 210_1 includes first latches 212_1 to 212_8, and latches (or converts) 8-bit serial odd data ODDi<8:1> into 8-bit parallel odd data LH1_1 to LH1_8 in response to a first latch enable signal EN1.

[0073] In one embodiment, each of the first latches 212_1 to 212_8 may be a D flip-flop capable of latching a 1-bit data value, and the first latch enable signal EN1 may be a parallel signal starting at different timings, as Figure 3 shown.

[0074] During a first operation time TI1, when 8-bit first odd serial data ODD1<8:1> is sequentially input to the first latch circuit 210_1, the first latches 212_1 to 212_8 latch the corresponding data ODD1<1> to ODD1<8> in response to the corresponding first latch enable signal EN1, and output the latched data LH1_1 to LH1_8 to the second latch circuit 220_1.

[0075] The second latch circuit 220_1 includes second latches 222_1 to 222_8, and the second latches 221_1 to 222_8 latch the corresponding data LH1_1 to LH1_8 in response to a second latch enable signal EN2, and output the latched data 2LH1_1 to 2LH1_8 to the first level shifter circuit 230_1.

[0076] The second data processing circuit 205_2 includes a third latch circuit 210_2, a fourth latch circuit 220_2, a second level shifter circuit 230_2, a second DAC 240_2, and a second output buffer 250_2.

[0077] The third latch circuit 210_2 includes third latches 214_1 to 214_8, and latches (or converts) 8-bit serial even data EVENi<8:1> into 8-bit parallel even data LH2_1 to LH2_8 in response to a first latch enable signal EN1.

[0078] For example, each of the third latches 214_1 to 214_8 can be a D flip-flop capable of latching a 1-bit data value, and the first latch enable signal EN1 can be a parallel signal that starts at different timings, such as Figure 3 as shown.

[0079] The start timing of each first latch enable signal EN1 provided to the first latch circuit 210_1 is different from the start timing of each first latch enable signal EN1 provided to the third latch circuit 210_3. Therefore, when the first latch circuit 210_1 operates, the third latch circuit 210_2 does not operate.

[0080] During the second operation time TI2, when the 8-bit first even serial data EVEN1<8:1> is sequentially input to the third latch circuit 210_2, the third latches 214_1 to 214_8 latch the corresponding data EVEN1<1> to EVEN1<8> in response to the corresponding first latch enable signal EN1, and output the latched data LH2_1 to LH2_8 to the fourth latch circuit 220_2.

[0081] The fourth latch circuit 220_2 includes fourth latches 224_1 to 224_8, and the fourth latches 224_1 to 224_8 latch the corresponding data LH2_1 to LH2_8 in response to the second latch enable signal EN2, and output the latched data 2LH2_1 to 2LH2_8 to the second level shifter circuit 230_2.

[0082] The process of handling the 8-bit second odd serial data ODD2<8:1> during the third operation time TI3 is the same as or similar to the process of handling the 8-bit first odd serial data ODD1<8:1> during the first operation time TI1 described in Figure 3 Therefore, the description of the process of handling the 8-bit second odd serial data ODD2<8:1> is omitted.

[0083] In addition, the process of handling the 8-bit second even serial data EVEN2<8:1> during the fourth operation time TI4 is the same as or similar to the process of handling the 8-bit first even serial data EVEN1<8:1> during the second operation time TI2. Therefore, the description of the process of handling the 8-bit second even serial data EVEN2<8:1> is omitted.

[0084] The process of handling each data EVEN1<8:1>, ODD2<8:1>, EVEN2<8:1>,... is the same as or similar to the process of handling the data ODD1<8:1> described in Figure 3 Therefore, its description is omitted.

[0085] The grayscale voltage generation circuit 300 receives a first operating voltage VDDH and a second operating voltage HVDD, and generates a first set of grayscale voltages VGMA_VH0 to VGMA_VH255 using the first operating voltage VDDH and the second operating voltage HVDD. The grayscale voltage generation circuit 300 outputs the generated grayscale voltages VGMA_VH0 to VGMA_VH255 to the first DAC 240_1.

[0086] The grayscale voltage generation circuit 300 generates a second set of grayscale voltages VGMA_VL0 to VGMA_VL255 using the second operating voltage HVDD and the ground voltage, and outputs the generated grayscale voltages VGMA_VL0 to VGMA_VL255 to the second DAC 240_2. In one embodiment, the second operating voltage HVDD may be half of the first operating voltage VDDH.

[0087] Figure 4 FIG. shows an example of a circuit diagram of an inversion circuit included in a transmission control circuit of a source driver IC included in Figure 2 and is an embodiment of display data for explaining the operation of the inversion circuit shown in Figure 5 is for explaining Figure 4 the operation of the inversion circuit shown.

[0088] Referring to Figure 3 、 Figure 4 and Figure 5 , the inversion circuit 400A includes a first target data value detection circuit 410, a second target data value detection circuit 420, a logic gate circuit 430, and a selection circuit 440. The selection circuit 440 may be implemented as a multiplexer.

[0089] Assume that the first target data value detection circuit 410 is designed to output an output signal S1 with a high level H only when the first set of data values 8'b00000000 is the same as the target data value 8'b00000000, and the second target data value detection circuit 420 is designed to output an output signal S2 with a high level H only when the first set of data values 8'b11111111 is the same as the target data value 8'b11111111. Also assume that the first reference data REFD1 is 8'b11111111 and the second reference data REFD2 is 8'b00000000. The target data value may refer to a specific display data value included in the data DATA.

[0090] 1-1. In the case where the first set of data values included in the first display data DATA(=ODD1<8:1>) is 8'b00000000

[0091] For example, the first target data value detection circuit 410 can be implemented as a NOR gate circuit, and when each of the first set of data values (8'b00000000) is data 0, it outputs an output signal S1 with a high level H.

[0092] The second target data value detection circuit 420 can be implemented as an AND gate circuit, and when each of the first set of data values (8'b11111111) is data 1, it outputs an output signal S2 with a high level H.

[0093] When the first set of data values included in the first display data DATA (= ODD1<8:1>) is 8'b00000000, the first target data value detection circuit 410 generates a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0094] In response to the first output signal S1 with a high level H, the second output signal S2 with a low level L, and the third output signal S3 with a low level L, the multiplexer 440 outputs the first reference data REFD1 (= 8'b11111111) input through the first input terminal IN1 as the output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0095] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:0>) including the second set of data values (REFD1 = 8'b11111111).

[0096] For example, even if the first data processing circuit 205_1 receives the second set of data values (REFD1 = 8'b11111111), the first data processing circuit 205_1 does not output the gray-scale voltage VGMA_VH255 corresponding to the second set of data values (REFD1 = 8'b11111111) as the first output signal OUT1, but outputs the gray-scale voltage VGMA_VH0 corresponding to the first set of data values 8'b00000000 as the first output signal OUT1.

[0097] That is, the first data processing circuit 205_1 outputs the gray-scale voltage VGMA_VH0 corresponding to the first set of data values 8'b00000000 included in the original first display data DATA (= ODD1<8:1>) as the first output signal OUT1.

[0098] 1-2. When the first set of data values included in the first display data DATA (= ODD1<8:1>) is 8'b11111111

[0099] When the first set of data values included in the first display data DATA (= ODD1<8:1>) is 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0100] In response to the first output signal S1 with a low level L, the second output signal S2 with a high level H, and the third output signal S3 with a low level L, the multiplexer 440 outputs the second reference data REFD2 (= 8'b00000000) input through the second input terminal IN2 as the output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0101] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:0>) including the second set of data values (REFD2 = 8'b00000000).

[0102] For example, even if the first data processing circuit 205_1 receives the second set of data values (REFD2 = 8'b00000000), the first data processing circuit 205_1 does not output the gray-scale voltage VGMA_VH0 corresponding to the second set of data values (REFD2 = 8'b00000000) as the first output signal OUT1, but outputs the gray-scale voltage VGMA_VH255 corresponding to the first set of data values 8'b11111111 as the first output signal OUT1.

[0103] That is, the first data processing circuit 205_1 outputs the gray-scale voltage VGMA_VH255 corresponding to the first set of data values 8'b11111111 included in the first display data DATA (= ODD1<8:1>) as the first output signal OUT1.

[0104] 1-3. When the first set of data values included in the first display data DATA (= ODD1<8:1>) is neither 8'b00000000 nor 8'b11111111

[0105] When the first set of data values included in the first display data DATA (= ODD1<8:1>) is neither 8'b00000000 nor 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a high level H.

[0106] In response to the first output signal S1 with a low level L, the second output signal S2 with a low level L, and the third output signal S3 with a high level H, the multiplexer 440 outputs the first set of data values input through the third input terminal IN3 to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0107] Only the first data processing circuit 205_1 receives and processes the first display data (DOUT = ODD1<8:0>) including the first set of data values.

[0108] 2-1. In the case where the first set of data values included in the first display data DATA (= EVEN1<8:1>) is 8'b00000000

[0109] When the first set of data values included in the first display data DATA (= EVEN1<8:1>) is 8'b00000000, the first target data value detection circuit 410 generates a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0110] In response to the first output signal S1 with a high level H, the second output signal S2 with a low level L, and the third output signal S3 with a low level L, the multiplexer 440 outputs the first reference data REFD1 (= 8'b11111111) input through the first input terminal IN1 as the output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0111] Only the second data processing circuit 205_2 receives and processes the second display data (DOUT = EVEN1<8:0>) including the second set of data values (REFD1 = 8'b11111111).

[0112] For example, even if the second data processing circuit 205_2 receives the second set of data values (REFD1 = 8'b11111111), the second data processing circuit 205_2 does not output the gray-scale voltage VGMA_VL255 corresponding to the second set of data values (REFD1 = 8'b11111111) as the second output signal OUT2. Instead, it outputs the gray-scale voltage VGMA_VL0 corresponding to the first set of data values 8'b00000000 as the second output signal OUT2.

[0113] That is, the second data processing circuit 205_2 outputs the gray-scale voltage VGMA_VL0 corresponding to the first set of data values 8'b00000000 included in the original first display data DATA (= EVEN1<8:1>) as the second output signal OUT2.

[0114] 2-2. In the case where the first set of data values included in the first display data DATA (= EVEN1<8:1>) is 8'b11111111

[0115] When the first set of data values included in the first display data DATA (= EVEN1<8:1>) is 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0116] In response to the first output signal S1 with a low level L, the second output signal S2 with a high level H, and the third output signal S3 with a low level L, the multiplexer 440 outputs the second reference data REFD2 (= 8'b00000000) input through the second input terminal IN2 as the output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0117] Only the second data processing circuit 205_2 receives and processes the second display data (DOUT = EVEN1<8:0>) including the second set of data values (REFD2 = 8'b00000000).

[0118] For example, even if the second data processing circuit 205_2 receives the second set of data values (REFD2 = 8'b00000000), the second data processing circuit 205_2 does not output the gray-scale voltage VGMA_VL0 corresponding to the second set of data values (REFD2 = 8'b00000000) as the second output signal OUT2. Instead, it outputs the gray-scale voltage VGMA_VL255 corresponding to the first set of data values 8'b11111111 as the second output signal OUT2.

[0119] That is, the second data processing circuit 205_2 outputs the gray-scale voltage VGMA_VL255 corresponding to the first set of data values 8'b11111111 included in the original first display data DATA (= EVEN1<8:1>) as the second output signal OUT2.

[0120] 2-3. In the case where the first set of data values included in the first display data DATA (= EVEN1<8:1>) is neither 8'b00000000 nor 8'b11111111

[0121] When the first set of data values is neither 8'b00000000 nor 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a high level H.

[0122] In response to the first output signal S1 with a low level L, the second output signal S2 with a low level L, and the third output signal S3 with a high level H, the multiplexer 440 outputs the first set of data values input through the third input terminal IN3 as they are to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0123] Only the second data processing circuit 205_2 receives and processes the first display data (DOUT = EVEN1<8:0>) including the first set of data values.

[0124] Figure 6 is for explaining Figure 4 another embodiment of the display data for the operation of the inversion circuit shown.

[0125] will refer to Figure 3 、 Figure 4 and Figure 6 describe the operation of the transmission control circuit 400 when only one of the target data values is one of data 1 and data 0, and each of the remaining target data values is the other of data 1 and data 0.

[0126] For example, assume that the first target data value detection circuit 410 is designed to output a first output signal with a high level only when the first set of data values 8'b00000001 is the same as the target data value 8'b00000001, and the second target data value detection circuit 420 is designed to output a second output signal with a high level only when the first set of data values 8'b11111110 is the same as the target data value 8'b11111110. Also assume that the first reference data REFD1 is 8'b11111110 and the second reference data REFD2 is 8'b00000001.

[0127] Here, when a specific data value is input to the corresponding detection circuit 410 or 420 and the output signal S1 or S2 with a high level is generated by the corresponding detection circuit 410 or 420, the specific data value is referred to as the target data value.

[0128] According to an embodiment, the first target data value detection circuit 410 can also be designed to output a first output signal with a high level only when the first set of data values 8'b10000000 is the same as the target data value 8'b10000000, and the second target data value detection circuit 420 can also be designed to output a second output signal with a high level only when the first set of data values 8'b01111111 is the same as the target data value 8'b01111111. In this case, the first reference data REFD1 can be set to 8'b01111111 and the second reference data REFD2 can be set to 8'b10000000.

[0129] 3-1. When the first set of data values included in the first display data DATA(=ODD1<8:1>) is 8'b00000001

[0130] The first target data value detection circuit 410 outputs a first output signal S1 with a high level H using the first set of data values 8'b00000001.

[0131] The second target data value detection circuit 420 outputs a second output signal S2 with a high level H using the first set of data values 8'b11111110.

[0132] When the first set of data values is 8'b00000001, the first target data value detection circuit 410 generates a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0133] In response to a first output signal S1 having a high level H, a second output signal S2 having a low level L, and a third output signal S3 having a low level L, the multiplexer 440 outputs the first reference data REFD1 (= 8'b11111110) input through the first input terminal IN1 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0134] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:0>) including the second set of data values (REFD1 = 8'b11111110).

[0135] 3-2. When the first set of data values included in the first display data DATA (= ODD1<8:1>) is 8'b11111110

[0136] When the first set of data values is 8'b11111110, the first target data value detection circuit 410 generates a first output signal S1 having a low level L, the second target data value detection circuit 420 generates a second output signal S2 having a high level H, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 having a low level L.

[0137] In response to a first output signal S1 having a low level L, a second output signal S2 having a high level H, and a third output signal S3 having a low level L, the multiplexer 440 outputs the second reference data REFD2 (= 8'b00000001) input through the second input terminal IN2 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0138] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:0>) including the second set of data values (REFD2 = 8'b00000001).

[0139] 3-3. When the first set of data values included in the first display data DATA (= ODD1<8:1>) is neither 8'b00000001 nor 8'b11111110

[0140] When the first set of data values is neither 8'b00000000 nor 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 having a low level L, the second target data value detection circuit 420 generates a second output signal S2 having a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 having a high level H.

[0141] In response to a first output signal S1 having a low level L, a second output signal S2 having a low level L, and a third output signal S3 having a high level H, the multiplexer 440 outputs a first set of data values input through the third input terminal IN3 to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0142] Only the first data processing circuit 205_1 receives and processes first display data (DOUT = ODD1<8:0>) including the first set of data values.

[0143] Figure 7 Shows an example of a transmission control circuit included in Figure 2 the source driver IC, the transmission control circuit including a determination circuit and an inversion circuit, Figure 8a is a table showing Figure 7 the operation of the selection signal generation circuit shown in

[0144] Referring to Figure 7 , the transmission control circuit 400 includes a determination circuit 400B and an inversion circuit 400A.

[0145] The determination circuit 400B determines whether the first display data is of an inversion target data type. The determination circuit 400B includes a register 402, a selection signal generation circuit 404, and a demultiplexer 406.

[0146] The register 402 stores information indicating (representing) whether the inversion target data type corresponds to odd data or even data.

[0147] The selection signal generation circuit 404 generates a selection signal SEL based on the information stored in the register 402 and whether the display data DATA is odd data ODDi<8:1> or even data EVENi<8:1>.

[0148] As Figure 8a shown, when the inversion target data type is odd data and the display data DATA is odd data ODDi<8:1>, the selection signal generation circuit 404 generates a selection signal SEL having a low level L, and when the inversion target data type is odd data and the display data DATA is even data EVENi<8:1>, the selection signal generation circuit 404 generates a selection signal SEL having a high level L.

[0149] In another example, when the inversion target data type is even data and the display data DATA is odd data ODDi<8:1>, the selection signal generation circuit 404 generates a selection signal SEL with a high level H. When the inversion target data type is even data and the display data DATA is even data EVENi<8:1>, the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0150] When the selection signal SEL is at the high level H, the demultiplexer 406 bypasses the display data DATA to the first data processing circuit 205_1 and the second data processing circuit 205_5.

[0151] However, when the selection signal SEL is at the low level L, the demultiplexer 406 transmits the display data DATA to the inversion circuit 400A.

[0152] The inversion circuit 400A includes a first target data value detection circuit 410, a second target data value detection circuit 420, a logic gate circuit 430, and a multiplexer 440, and is the same as that shown in Figure 4 Therefore, its detailed description is omitted.

[0153] Figure 12 is a flowchart showing the operation of the transmission control circuit shown in Figure 7 the transmission control circuit shown.

[0154] Refer to Figure 3 、 Figure 7 、 Figure 8a 、 Figure 8b and Figure 12 to describe the operation of the transmission control circuit 400. In this case, it is assumed that the inversion target data type is odd data. The first target data value detection circuit 410 is designed to output a first output signal S1 with a high level only when the first set of data values 8'b00000000 is input. The second target data value detection circuit 420 is designed to output a second output signal with a high level only when the first set of data values 8'b11111111 is input. The first reference data REFD1 is 8'b11111111, and the second reference data REFD2 is 8'b00000000.

[0155] First, the selection signal generation circuit 404 receives first display data DATA including the first set of data values 8'b00000000 from the receiving circuit 203, that is, the first odd data ODD1<8:1> (S210).

[0156] The selection signal generation circuit 404 determines whether the first display data DATA (= ODD1<8:1> = 8'b00000000) is the inversion target data type (S220).

[0157] When the first display data DATA (= ODD1<8:1> = 8'b00000000) is of the inversion target data type, that is, when the first display data DATA (= ODD1<8:1>) is odd data ("Yes" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0158] The demultiplexer 406 transfers the first display data DATA (= ODD1<8:1> = 8'b00000000) to the inversion circuit 400B in response to the selection signal SEL with a low level L.

[0159] 4-1. In the case where the first set of data values included in the first display data DATA (= ODD1<8:1>) is 8'b00000000

[0160] When the first set of data values 8'b00000000 is the same as the target data value 8'b00000000, that is, when the first set of data values 8'b00000000 is received ("Yes" in step S240), the first target data value detection circuit 410 outputs a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0161] In response to the first output signal S1 with a high level H, the second output signal S2 with a low level L, and the third output signal S3 with a low level L, the multiplexer 440 outputs the first reference data REFD1 (= 8'b11111111) input through the first input terminal IN1 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S250).

[0162] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:0>) including the second set of data values (REFD1 = 8'b11111111).

[0163] In another example, the selection signal generation circuit 404 receives the first display data DATA (= ODD1<8:1>) including the first set of data values 8'b11111111 from the reception circuit 203 (S210).

[0164] The selection signal generation circuit 404 determines whether the first display data DATA (= ODD1<8:1> = 8'b11111111) is of the inversion target data type (S220).

[0165] When the first display data DATA (= ODD1<8:1> = 8'b11111111) is of the inverted target data type, i.e., when the first display data DATA (= ODD1<8:1> = 8'b11111111) is odd data ("Yes" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0166] The demultiplexer 406 transmits the first display data DATA (= ODD1<8:1> = 8'b11111111) to the inversion circuit 400B in response to the selection signal SEL with a low level L.

[0167] 4-2. In the case where the first set of data values included in the first display data DATA (= ODD1<8:1>) is 8'b11111111

[0168] When the first set of data values 8'b11111111 is the same as the target data value 8'b11111111, i.e., when the first display data DATA (= ODD1<8:1> = 8'b11111111) is received ("Yes" in step S240), the first target data value detection circuit 410 outputs a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a low level L.

[0169] In response to the first output signal S1 with a low level L, the second output signal S2 with a high level H, and the third output signal S3 with a low level L, the multiplexer 440 outputs the second reference data REFD2 (= 8'b00000000) input through the second input terminal IN2 as the output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S250).

[0170] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:0> = 00000000) including the second set of data values (REFD2 = 8'b00000000).

[0171] In another example, the selection signal generation circuit 404 receives the first display data DATA (= ODD1<8:1>) including the first set of data values (e.g., neither 8'b00000000 nor 8'b11111111) from the reception circuit 203 (S210).

[0172] The selection signal generation circuit 404 determines whether the first display data DATA (= ODD1<8:1>) is a data type to be inverted (S220).

[0173] When the first display data DATA (= ODD1<8:1>) is a data type to be inverted, that is, when the first display data DATA (= ODD1<8:1>) is odd data ("Yes" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0174] The demultiplexer 406 transmits the first display data DATA (= ODD1<8:1>) to the inversion circuit 400A in response to the selection signal SEL with a low level L.

[0175] 4-3. In the case where the first set of data values included in the first display data DATA (= ODD1<8:1>) is neither 8'b00000000 nor 8'b11111111

[0176] Since the first set of data values is not the same as the target data value ("No" in step S240), the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430 implemented as a NOR gate circuit generates a third output signal S3 with a high level H.

[0177] In response to the first output signal S1 with a low level L, the second output signal S2 with a low level L, and the third output signal S3 with a high level H, the multiplexer 440 bypasses the first set of data values (neither 8'b00000000 nor 8'b11111111) input through the third input terminal IN3 as it is to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S230).

[0178] Only the first data processing circuit 205_1 receives and processes the first display data (DOUT = ODD1<8:0>) including the first set of data values.

[0179] In another example, the selection signal generation circuit 404 receives the first display data DATA including the first set of data values, that is, the first even data EVEN1<8:1>, from the receiving circuit 203 (S210).

[0180] The selection signal generation circuit 404 determines whether the first display data DATA (= EVEN1<8:1>) is a data type to be inverted (S220).

[0181] When the first display data DATA (= EVEN1<8:1>) is not the data type to be inverted, that is, when the first display data DATA (= EVEN1<8:1>) is not odd data ("No" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a high level H.

[0182] In response to the selection signal SEL with a high level H, the demultiplexer 406 bypasses the first display data DATA (= EVEN1<8:1>) as it is to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S230).

[0183] Only the second data processing circuit 205_2 receives and processes the first display data (DOUT = EVEN1<8:0>) including the first set of data values.

[0184] Figure 8b is shown Figure 2 A table showing the input and output signals of each of the first data processing circuit and the second data processing circuit shown.

[0185] When the data type to be inverted is the even data EVENi <n:1>When the target data values are 8'b00000000 and 8'b11111111, the transmission control circuit 400 will output the odd data ODDi <n:1>Bypass to the first data processing circuit 205_1.

[0186] As Figure 8b shown, the first data processing circuit 205_1 outputs the grayscale voltages VGMA_VH<0:255> in the first group corresponding to those included in the odd data ODDi <n:1>The grayscale voltage VGMA_VH<0:255> corresponding to the first set of data values in is used as the first output signal OUT1 (S260).

[0187] However, when the input includes the even data EVENi of the first set of data values 8'b00000000 <n:1>When, the transmission control circuit 400 reverses the first set of data values to the second set of data values 8'b11111111, and then the even data EVENi including the second set of data values 8'b11111111 <n:1>Transferred to the second data processing circuit 205_2.

[0188] However, even the even data EVENi including the second set of data values 8'b11111111 <n:1>is transmitted to the second data processing circuit 205_2, and the second DAC 240_2 of the second data processing circuit 205_2 does not output the gray-scale voltage VGMA_VL255 corresponding to the second set of data values 8'b11111111 in the second set of gray-scale voltages VGMA_VL<0:255> as the second output signal OUT2, but outputs the gray-scale voltage VGMA_VL0 corresponding to the first set of data values 8'b00000000 in the second set of gray-scale voltages VGMA_VL<0:255> as the second output signal OUT2 (S260).

[0189] For this purpose, the second DAC 240_2 can be manufactured such that the gray-scale voltage VGMA_VL0 is input into the internal path for outputting the gray-scale voltage VGMA_VL255. Specifically, the second DAC 240_2 can be designed such that the gray-scale voltage VGMA_VL0 is input into the input terminal where the gray-scale voltage VGMA_VL255 is input in a typical DAC, and the gray-scale voltage VGMA_VL255 is input into the input terminal where the gray-scale voltage VGMA_VL0 is input.

[0190] When the input includes the even data EVENi including the first set of data values 8'b11111111 <n:1>When, the transmission control circuit 400 reverses the first set of data values 8'b11111111 to the second set of data values 8'b00000000, and then the even data EVENi including the second set of data values 8'b00000000 <n:1>Transferred to the second data processing circuit 205_2.

[0191] Even data EVENi including the second set of data values 8'b00000000 <n:1>It is transmitted to the second data processing circuit 205_2. The second DAC 240_2 of the second data processing circuit 205_2 does not output the gray-scale voltage VGMA_VL0 corresponding to the second set of data values 8'b00000000 in the second set of gray-scale voltages VGMA_VL<0:255> as the second output signal OUT2, but outputs the gray-scale voltage VGMA_VL225 corresponding to the first set of data values 8'b11111111 in the second set of gray-scale voltages VGMA_VL<0:255> as the second output signal OUT2 (S260).

[0192] As described above, since the second DAC 240_2 is designed such that the gray-scale voltage VGMA_VL255 is input to the input terminal where the gray-scale voltage VGMA_VL0 should be input in a typical DAC structure, even when the second set of data values 8'b00000000 is input, the gray-scale voltage VGMA_VL255 that matches the path of the gray-scale voltage VGMA_VL0 can be output as the second output signal OUT2.

[0193] When the first set of data values 8'b00000001 or 11111110, which are neither 8'b00000000 nor 8'b11111111, are input as the even data EVENi <n:1>When, the even data EVENi including the first set of data values 8'b00000001 or 11111110 output from the transmission control circuit 400 <n:1>is transmitted to the second data processing circuit 205_2.

[0194] The second DAC 240_2 of the second data processing circuit 205_2 outputs the gray-scale voltage VGMA_VL1 or VGMA_VL254 in the second set of gray-scale voltages VGMA_VL<0:255> corresponding to the first set of data values 8'b00000001 or 11111110 as the second output signal OUT2 (S260).

[0195] As described above, Figure 2 each of the DACs 240_1 and 240_2 is designed to have a structure capable of performing Figure 11 step S150 of Figure 12 and step S260 of

[0196] Figure 9 is the circuit diagram of the first level shifter included in the Figure 2 source driver IC.

[0197] The first level shifter circuit 230_1 includes a plurality of first level shifters 232_1 to 232_8. Since the structures and operations of the first level shifters 232_1 to 232_8 are the same, the structure and operation of the first level shifter 232_1 are representatively described with reference to Figure 9 the structure and operation of the first level shifter 232_1 are representatively described.

[0198] Transistors MP1_1, MP1_3, and MN1_1 are connected in series between the first gray-scale voltage transmission line 301 for transmitting the first intermediate gray-scale voltage VGMAO1 (=VGMA_VH255) and the ground GND for providing the ground voltage VSSH, and transistors MP1_2, MP1_4, and MN1_2 are connected in series between the first gray-scale voltage transmission line 301 and the ground GND. As Figure 8c shown, the first intermediate gray-scale voltage VGMAO1 can be the voltage closest to the first operating voltage VDDH (or a voltage lower than the first operating voltage VDDH and having the smallest level difference from the first operating voltage VDDH).

[0199] Since a bias voltage LSP having a low level is supplied to each of the gates of the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2, the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2 are turned on. The first PMOS transistor MP1_1 and the second PMOS transistor MP1_2 can be kept in a continuously conducting state by the bias voltage LSP supplied to their gates. When the bias voltage LSP is supplied to the gates of the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2 to turn on the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2, the current flowing through the third PMOS transistor MP1_3 and the fourth PMOS transistor MP1_4 is limited.

[0200] The gate of the third PMOS transistor MP1_3 is connected to the second node ND2, the first terminal of the third PMOS transistor MP1_3 is connected to the first node ND1, and the second terminal of the third PMOS transistor MP1_3 is connected to the first PMOS transistor MP1_1. The gate of the fourth PMOS transistor MP1_4 is connected to the first node ND1, the first terminal of the fourth PMOS transistor MP1_4 is connected to the second node ND2, and the second terminal of the fourth PMOS transistor MP1_4 is connected to the second PMOS transistor MP1_2.

[0201] The output signal (also referred to as "first input data" or "first bit") 2LH1_1 of the first latch 222_1 included in the second latch circuit 220_1 is input to the gate of the first NMOS transistor MN1_1. The first inverter INV1 inverts the output signal 2LH1_1 of the first latch 222_1, and the inverted output signal 2LHB1_1 is input to the gate of the second NMOS transistor MN1_2.

[0202] For example, when the level of the signal 2LH1_1 input to the gate of the first NMOS transistor MN1_1 is high and the level of the signal 2LHB1_1 input to the gate of the second NMOS transistor MN1_2 is low, the first NMOS transistor MN_1 is turned on and the second NMOS transistor MN1_2 is turned off.

[0203] When the first NMOS transistor MN1_1 is turned on, the voltage DB1_1 of the first node ND1 is pulled down to the ground voltage VSSH, and the fourth PMOS transistor MP1_4 is turned on, so that the voltage D1_1 of the second node ND2 is pulled up to the level of the first operating voltage (VGMAO1 = VGMA_VH255). Therefore, the third PMOS transistor MP1_3 is turned off, so that the voltage DB1_1 of the first node ND1 remains at the ground voltage VSSH.

[0204] In contrast, when the level of the signal 2LH1_1 input to the gate of the first NMOS transistor MN1_1 is low and the level of the signal 2LHB1_1 input to the gate of the second NMOS transistor MN1_2 is high, the first NMOS transistor MN_1 is turned off and the second NMOS transistor MN1_2 is turned on.

[0205] When the second NMOS transistor MN1_2 is turned on, the voltage D1_1 of the second node ND2 is pulled down to the ground voltage VSSH, and the third PMOS transistor MP1_3 is turned on, so that the voltage DB1_1 of the first node ND1 is pulled up to the level of the first operating voltage (VGMAO1 = VGMA_VH255). Therefore, the fourth PMOS transistor MP1_4 is turned off, so that the voltage D1_1 of the second node ND2 remains at the ground voltage VSSH.

[0206] The voltage level DB1_1 of the first node ND1 is complementary to the voltage level D1_1 of the second node ND2.

[0207] The output voltage swing range of the voltage levels DB1_1 and D1_1 is between the highest gray scale voltage (VGMAO1 = VGMA_VH255) in the first set of gray scale voltages VGMA_VH0 to VGMA_VH255 and the ground voltage VSSH.

[0208] The first level shifters 232_1 to 232_8 output the complementary signal pairs <D1_1, DB1_1> to <D1_8, DB1_8> to the first DAC 240_1.

[0209] For example, the voltage swing range of the output signals D1_1 to D1_8 of the first level shifters 232_1 to 232_8 is greater than the voltage swing range of the input / output signals of each of the latches 212_1 to 212_8 and 222_1 to 222_8.

[0210] Figure 10 is included in Figure 2 the source driver IC is a circuit diagram of the second level shifter.

[0211] The second level shifter circuit 230_2 includes a plurality of second level shifters 234_1 to 234_8. Since the structures and operations of the second level shifters 234_1 to 234_8 are the same, the structure and operation of the second level shifter 234_1 are described representatively with reference to Figure 7 the structure and operation of the second level shifter 234_1 are described representatively.

[0212] For example, when describing two level shifters 232_j and 234_j (where 1Aj ≤ 8), the first level shifter may refer to level shifter 232_j and the second level shifter may refer to level shifter 234_j.

[0213] Each of the second level shifters 234_1 to 234_8 and each of the first level shifters 232_1 to 232_8 operate independently of each other. In addition, the first level shifters 232_1 to 232_8 operate independently of each other, and the second level shifters 234_1 to 234_8 operate independently of each other.

[0214] For example, the output signal of any one of the first level shifters 232_1 to 232_8, 234_1 to 234_8 has no effect on the input signal of each of the remaining level shifters.

[0215] As Figure 8c shown, transistors MP2_1, MP2_3, and MN2_1 are connected in series between the second gray voltage transmission line 303 for transmitting the second intermediate gray voltage VGMAO8 (=VGMA_VL0) and the ground GND for providing the ground voltage VSSH, and transistors MP2_2, MP2_4, and MN2_2 are connected in series between the second gray voltage transmission line 303 and the ground GND. The second intermediate gray voltage VGMAO8 may be a voltage closest to the second operating voltage HVDD (=0.5VDDH) (or a voltage lower than the second operating voltage HVDD and having the smallest level difference from the second operating voltage VHDD).

[0216] Since a bias voltage LSP with a low level is provided to each of the gates of the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2, the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2 are turned on. The first PMOS transistor MP2_1 and the second PMOS transistor MP2_2 can be maintained in a continuously conducting state by the bias voltage LSP provided to their gates. When the bias voltage LSP is provided to the gates of the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2 to turn on the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2, the current flowing through the third PMOS transistor MP2_3 and the fourth PMOS transistor MP2_4 is limited.

[0217] The gate of the third PMOS transistor MP2_3 is connected to the fourth node ND4, the first terminal of the third PMOS transistor MP2_3 is connected to the third node ND3, and the second terminal of the third PMOS transistor MP2_3 is connected to the first PMOS transistor MP2_1. The gate of the fourth PMOS transistor MP2_4 is connected to the third node ND3, the first terminal of the fourth PMOS transistor MP2_4 is connected to the fourth node ND4, and the second terminal of the fourth PMOS transistor MP2_4 is connected to the second PMOS transistor MP2_2.

[0218] The output signal (also referred to as the "second input data" or "first bit") 2LH2_1 of the first latch 224_1 included in the second latch circuit 220_2 is input to the gate of the first NMOS transistor MN2_1. The second inverter INV2 inverts the output signal 2LH2_1 of the first latch 224_1, and the inverted output signal 2LHB2_1 is input to the gate of the second NMOS transistor MN2_2.

[0219] For example, when the level of the signal 2LH2_1 input to the gate of the first NMOS transistor MN2_1 is high and the level of the signal 2LHB2_1 input to the gate of the second NMOS transistor MN2_2 is low, the first NMOS transistor MN2_1 is turned on and the second NMOS transistor MN2_2 is turned off.

[0220] When the first NMOS transistor MN2_1 is turned on, the voltage DB2_1 of the third node ND3 is pulled down to the ground voltage VSSH, and the fourth PMOS transistor MP2_4 is turned on, so that the voltage D2_1 of the fourth node ND4 is pulled up to the level of the second operating voltage (VGMAO8). Therefore, the third PMOS transistor MP2_3 is turned off, so that the voltage DB2_1 of the third node ND3 remains at the ground voltage VSSH.

[0221] Conversely, when the level of the signal 2LH2_1 input to the gate of the first NMOS transistor MN2_1 is low and the level of the signal 2LHB2_1 input to the gate of the second NMOS transistor MN2_2 is high, the first NMOS transistor MN2_1 is turned off and the second NMOS transistor MN2_2 is turned on.

[0222] When the second NMOS transistor MN2_2 is turned on, the voltage D2_1 of the fourth node ND4 is pulled down to the ground voltage VSSH, and the third PMOS transistor MP2_3 is turned on, so that the voltage DB2_1 of the third node ND3 is pulled up to the level of the second operating voltage (VGMAO8). Therefore, the fourth PMOS transistor MP2_4 is turned off, so that the voltage D2_1 of the fourth node ND4 remains at the ground voltage VSSH.

[0223] The voltage level DB2_1 of the third node ND3 is complementary to the voltage level D2_1 of the fourth node ND4.

[0224] The output voltage swing ranges of the voltage levels DB2_1 and D2_1 are between the highest gray-scale voltage VGMAO8 = VGMA_VL0 in the second set of gray-scale voltages VGMA_VL0 to VGMA_VL255 and the ground voltage VSSH.

[0225] As in the reference Figure 10 As described, the second level shifters 234_1 to 234_8 output the complementary signal pairs <D2_1, DB2_1> to <D2_8, DB2_8> to the second DAC 240_2.

[0226] For example, the voltage swing ranges of the output signals D2_1 to D2_8 of the second level shifters 234_1 to 234_8 are greater than the voltage swing ranges of the input / output signals of each of the latches 212_1 to 212_8 and 222_1 to 222_8, and less than the voltage swing ranges of the output signals D1_1 to D1_8 of the first level shifters 232_1 to 232_8.

[0227] As Figure 2 shown, the first level shifters 232_1 to 232_8 operate independently of the second level shifters 234_1 to 234_8.

[0228] Return to the reference Figure 2 , the first DAC 240_1 outputs any one of the first set of gray-scale voltages VGMA_VH0 to VGMA_VH255 as the first output signal DAC1O in response to the complementary signal pairs <D1_1, DB1_1> to <D1_8, DB1_8> output from the first level shifters 232_1 to 232_8.

[0229] For example, when the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 are 00000000, the first DAC 240_1 outputs the first gray scale voltage VGMA_VH0 as the first output signal DAC1O. When the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 are 00000001, the first DAC 240_1 outputs the second gray scale voltage VGMA_VH1 as the first output signal DAC1O. When the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 are 11111110, the first DAC 240_1 outputs the 255th gray scale voltage VGMA_VH254 as the first output signal DAC1O. When the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 are 11111111, the first DAC 240_1 outputs the 256th gray scale voltage VGMA_VH255 as the first output signal DAC1O.

[0230] The first output buffer 250_1 buffers the first output signal DAC1O of the first DAC 240_1 and outputs the buffered first output signal OUT1 to at least one of the first data lines DL1.

[0231] Reference Figure 2 , the second DAC 240_2 outputs any one of the second set of gray scale voltages VGMA_VL0 to VGMA_VL255 as the second output signal DAC2O in response to the complementary signal pairs <D2_1, DB2_1> to <D2_8, DB2_8> output from the second level shifters 232_1 to 232_8.

[0232] For example, when the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 are 00000000, the second DAC 240_2 outputs the first gray scale voltage VGMA_VL0 as the second output signal DAC2O. When the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 are 00000001, the second DAC 240_2 outputs the second gray scale voltage VGMA_VL1 as the second output signal DAC2O. When the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 are 11111110, the second DAC 240_2 outputs the 255th gray scale voltage VGMA_VL254 as the second output signal DAC2O. When the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 are 11111111, the second DAC 240_2 outputs the 256th gray scale voltage VGMA_VL225 as the second output signal DAC2O.

[0233] The second output buffer 250_2 buffers the second output signal DAC2O of the second DAC 240_2, and outputs the buffered second output signal OUT2 to another one of the first data lines DL1.

[0234] According to the above embodiments, when the first set of data values is the same as the target data values, even if the first set of data values is changed to the second set of data values, the first DAC 240_1 or the second DAC 240_2 outputs the gray-scale voltage corresponding to the first set of data values instead of the gray-scale voltage corresponding to the second set of data values. In this case, since the first DAC 240_1 or the second DAC 240_2 is manufactured such that the gray-scale voltage VGMA_VH0 or VGMA_VL0 is input to the internal path for outputting the gray-scale voltage VGMA_VH255 or VGMA_VL255, and the gray-scale voltage VGMA_VH255 or VGMA_VL255 is input to the internal path for outputting the gray-scale voltage VGMA_VH0 or VGMA_VL0, the DAC outputs the gray-scale voltage corresponding to the original data values even if the data values are inverted, and the number of transistors that require state conversion when the display data is switched can be reduced.

[0235] Outputs the gray-scale voltage corresponding to the first display data including the first set of data values, instead of outputting the gray-scale voltage corresponding to the second display data including the second set of data values.

[0236] Therefore, the peak current generated due to the state conversion of the transistors in the first DAC 240_1 or the second DAC 240_2 is reduced, thereby allowing the load balance in the first DAC 240_1 or the second DAC 240_2 to be appropriately adjusted.

[0237] Those skilled in the art to which the present invention pertains will understand that the above present invention can be implemented in other specific forms without changing its technical concept or basic features.

[0238] Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present invention. The scope of the present invention is represented by the following claims rather than the above specific embodiments, and should be construed as including all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts within the scope of the present invention.

[0239] Implementation forms of the invention

[0240] Various embodiments for implementing the present invention have been fully described in the foregoing table of contents.

[0241] Industrial applicability

[0242] The present invention can be applied to any type of display device, and thus its industrial applicability can be recognized.

Claims

1. A display driving device, comprising: a receiving circuit configured to receive first display data including a first set of data values; a transmission control circuit configured to output the first display data or second display data including a second set of data values based on a comparison result between the first set of data values and target data values; and a data processing circuit configured to process the first display data or the second display data output from the transmission control circuit, wherein the transmission control circuit includes an inversion circuit configured to bypass the first display data to the data processing circuit when the first set of data values are not respectively the same as the target data values, convert the first set of data values into the second set of data values respectively complementary to the first set of data values when the first set of data values are respectively the same as the target data values, and output the second display data including the second set of data values to the data processing circuit.

2. The display driving device according to claim 1, wherein the target data values are equal to each other.

3. The display driving device according to claim 1, wherein: only one of the target data values is one of data 1 and data 0, and each of the remaining target data values is the other of data 1 and data 0.

4. The display driving device according to claim 1, wherein the inversion circuit includes: a first NOR gate circuit configured to output a first output signal at a high level when each of the first set of data values is data 0; an AND gate circuit configured to output a second output signal at a high level when each of the first set of data values is data 1; a second NOR gate circuit configured to output a third output signal at a high level when the levels of the first output signal and the second output signal are the same, and output the third output signal at a low level when the levels of the first output signal and the second output signal are different; and a multiplexer configured to output the second display data in which each of the second set of data values is data 1 in response to the first output signal at a high level, the second output signal at a low level, and the third output signal at a low level, output the second display data in which each of the second set of data values is data 0 in response to the first output signal at a low level, the second output signal at a high level, and the third output signal at a low level, and output the first display data in response to the first output signal at a low level, the second output signal at a low level, and the third output signal at a high level.

5. The display driving device according to claim 1, wherein the transmission control circuit further includes a determination circuit configured to determine whether the first display data is an inversion target data type, Wherein, when the first display data is not the inversion target data type, the determination circuit bypasses the first display data to the data processing circuit, and when the first display data is the inversion target data type, the determination circuit outputs the first display data to the inversion circuit.

6. The display driving device according to claim 5, wherein, the determination circuit includes: a register configured to store information indicating whether the inversion target data type is odd data or even data; a selection signal generation circuit configured to generate a selection signal at a low level when the first display data corresponds to the information stored in the register, and generate the selection signal at a high level when the first display data does not correspond to the information stored in the register; and a demultiplexer configured to bypass the first display data to the data processing circuit when the selection signal is at a high level, and output the first display data to the inversion circuit when the selection signal is at a low level.

7. The display driving device according to claim 5, wherein, the data processing circuit includes a first data processing circuit configured to process odd data and a second data processing circuit configured to process even data, when the inversion target data type corresponds to the even data among the odd data and the even data, if the first display data is not the inversion target data type, the determination circuit enables the first data processing circuit and disables the second data processing circuit, and if the first display data is the inversion target data type, the determination circuit disables the first data processing circuit and enables the second data processing circuit.

8. The display driving device according to claim 7, wherein, when the inversion target data type corresponds to the odd data among the odd data and the even data, if the first display data is not the inversion target data type, the determination circuit disables the first data processing circuit and enables the second data processing circuit, and if the first display data is the inversion target data type, the determination circuit enables the first data processing circuit and disables the second data processing circuit.

9. The display driving device according to claim 1, wherein, the data processing circuit includes a digital-to-analog converter configured to output a first gray-scale voltage corresponding to the first set of data values in the gray-scale voltages for the first display data and the second display data by using an internal path for outputting a second gray-scale voltage corresponding to the second set of data values.

10. An operation method of a display driving device, including: receiving first display data including a first set of data values; determining whether the first set of data values is the same as a target data value; when the first set of data values is not the same as the target data value respectively, bypassing the first display data; and When the first set of data values are respectively the same as the target data value, output second display data including the second set of data values instead of the first set of data values, wherein the second set of data values are respectively complementary to the first set of data values.

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