Enhanced rise and fall transitions for level shifting low voltage input signals
By designing a level shifter including an inverter and a transistor, the problems of high power consumption and high equipment during level shift of low voltage signals in the prior art are solved, and low power consumption and stable level shifting effects are achieved.
Patent Information
- Application Number
- CN202380072553.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-10-20
- Filing Date
- 2023-10-06
- Publication Date
- 2025-05-30
AI Technical Summary
When the existing level shifter level shifters perform high power consumption, large number of equipment and severe distortion of working cycles, it is difficult to meet the effective level shifting requirements of low voltage signals.
A level shifter including a first inverter, a first transistor, a second transistor, a third transistor, a second inverter and a buffer is designed, and through the coordinated operation of these components, effective level shifting to a low voltage signal and reducing power consumption.
The level shifter can steadily level shift the low voltage signal with low power consumption and low equipment use, relaxing transistor matching requirements and simplifying the design and manufacturing process.
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Figure CN120077571A_ABST
Abstract
Description
[0001] Cross - Reference to Related Applications
[0002] This application claims the benefit and priority of U.S. Patent Application No. 17 / 970,519, filed Oct. 20, 2022, the disclosure of which is incorporated herein by reference in its entirety as if set forth in full below and for all applicable purposes. Technical Field
[0003] This application relates to level shifters, and more particularly to a level shifter with enhanced rising and falling transitions for level - shifting a low - voltage input signal. Background Art
[0004] To achieve reduced power consumption and other beneficial effects, integrated circuits may generate relatively low - voltage signals that oscillate between ground and a binary high voltage that may just meet or even be slightly below the transistor threshold voltage. The resulting low - voltage signals may then need to be level - shifted to enter a higher - voltage power domain. Since the binary high state of the low - voltage signal just meets or is even less than the transistor threshold voltage, designing a suitable level shifter is challenging. For example, a cross - coupled latch - based level shifter or an amplifier - based level shifter may consume too much power, require too many devices, and suffer from duty - cycle distortion when used to level - shift low - voltage signals. Summary of the Invention
[0005] A level shifter is provided that includes: a first inverter configured to invert an input signal into an inverted input signal, the first inverter being powered by a first power voltage; a first transistor coupled between an internal node and ground and having a gate coupled to the output terminal of the first inverter; a second transistor coupled between ground and a node for an inverted level - shifted output signal of the level shifter, the second transistor having a gate coupled to the input signal; a third transistor coupled between the internal node and a power node for a second power voltage; a second inverter configured to invert the inverted level - shifted output signal into a level - shifted output signal, the second inverter being powered by the second power voltage; and a buffer configured to buffer the level - shifted output signal into a feedback signal, wherein the gate of the third transistor is coupled to the output terminal of the buffer, and wherein the buffer is powered by the second power voltage.
[0006] In addition, a method for level shifting is provided, the method comprising: charging an inverted input signal to a first power supply voltage in response to discharging of the input signal; turning on a first transistor to discharge an internal node in response to charging of the inverted input signal, while turning off a second transistor coupled between an output signal node of an inverted level shifter and ground in response to discharging of the input signal, and simultaneously turning off a third transistor coupled between the internal node and a power supply node for a second power supply voltage; turning on a fourth transistor coupled between the output signal node of the inverted level shifter and the power supply node for the second power supply voltage in response to discharging of the internal node to charge the inverted level shifter output signal at the inverted level shifter output signal node to the second power supply voltage; discharging the level shifter output signal in response to charging of the inverted level shifter output signal to the second power supply voltage; discharging a feedback signal in response to discharging of the level shifter output signal; and turning on the third transistor in response to discharging of the feedback signal.
[0007] A level shifter is also provided, the level shifter comprising: a first inverter configured to invert an input signal into an inverted input signal, the first inverter being powered by a first power supply voltage; a first transistor coupled between an internal node and ground and having a gate coupled to an output terminal of the first inverter; a second transistor coupled between ground and an output signal node of the inverted level shifter for the inverted level shifter output signal, the second transistor having a gate coupled to the input signal; and a third transistor coupled between the output signal node of the inverted level shifter and a power supply node for a second power supply voltage, wherein a gate of the third transistor is coupled to the internal node.
[0008] These and other advantageous features can be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 is a circuit diagram of an exemplary level shifter according to one aspect of the present disclosure.
[0010] Figure 2 is for Figure 1 the level shifter of the signal timing diagram.
[0011] Figure 3 is a flowchart of an exemplary method for level shifting according to one aspect of the present disclosure.
[0012] Figure 4 Illustrates some example electronic devices including a level shifter according to one aspect of the present disclosure.
[0013] The specific embodiments of the present disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that like reference numerals are used to identify like elements illustrated in one or more of the figures. Detailed Description
[0014] A level shifter is provided that can advantageously shift the level of a relatively low voltage signal (e.g., as low as the threshold voltage of a metal oxide semiconductor field effect transistor (MOSFET)). This level shifting is stable against process, voltage, and temperature (PVT) variations, but has relatively low power consumption and utilizes relatively few devices. Additionally, the matching requirements for the transistors in the level shifter are relaxed, which facilitates the design and manufacturing process. In contrast, amplifier-based and cross-coupled latch-based level shifters may not be able to successfully shift the level of such relatively low voltage signals, consume more power, require more devices, and have more stringent device matching requirements.
[0015] To provide these advantageous features, one specific embodiment of the disclosed level shifter includes a first inverter that inverts an input signal to an inverted input signal. The first inverter is powered by a first supply voltage. In the following discussion, it will be assumed that the input signal is being level shifted to a level shifter output signal in a higher voltage power domain powered by a second supply voltage greater than the first supply voltage. However, it should be understood that alternative specific embodiments of the level shifter may shift the input signal from a high voltage power domain to a level shifter output signal in a lower voltage power domain.
[0016] Assuming the input signal has a high-level active convention, its binary high state can be a relatively low voltage, such as the threshold voltage or even lower, as previously mentioned. To accommodate such low voltage signals, the inverted input signal drives the gate of a first N-type metal oxide semiconductor (NMOS) transistor that functions to discharge an internal node in the level shifter when the inverted input signal is asserted to a binary high logic state. The input signal similarly drives the gate of a second NMOS transistor that functions to discharge the inverted level shifter output signal node when the input signal is asserted to a binary high logic state. A second inverter powered by the second supply voltage functions to invert the inverted level shifter output signal carried on the inverted level shifter output signal node to produce the level shifter output signal. The first transistor and the second transistor form a main input transistor pair for the level shifter, but there are no matching requirements, which facilitates the design and manufacturing of the level shifter.
[0017] In Figure 1An example level shifter 100 is shown. Inverter 105 is an example of the first inverter that inverts an input signal to form an inverted input signal as discussed above. Transistor M1 is an example of the first NMOS transistor that functions in level shifter 100 to discharge internal node V1 in response to an assertion of the inverted input signal (in-). The output terminal of the first inverter 105 is coupled to the gate of transistor M1. The first inverter 105 powered by the first power supply voltage (Vddin) is used to invert the input signal (in+) to form the inverted input signal in-. Similarly, transistor M2 is an example of the second NMOS transistor that functions in level shifter 100 to discharge the inverted level shifter output signal node 140 carrying the inverted level shifter output signal (out-). The input signal in+ drives the gate of transistor M2. The inverted input signal in- is the complement of the input signal in+. Similarly, the inverted level shifter output signal out- is the complement of the level shifter output signal (out+). The second inverter 120 is powered by the output domain power supply voltage (Vddout) and inverts the inverted level shifter output signal out- to form the level shifter output signal out+.
[0018] To provide a strong rising edge (transition from binary low state to binary high state) to the inverted level shifter output signal out-, and thus to form a strong falling edge (transition from binary high state to binary low state) to the level shifter output signal out+, transistor M1 functions as follows to strongly discharge the internal node V1 and trigger a strong charge of the inverted level shifter output signal node 140. To better understand this discharge of the internal node V1, some supporting structures will be discussed first. Transistor M1 has a source coupled to ground and a drain coupled to the source of NMOS transistor M3, which has a drain coupled to the internal node V1. Transistor M3 is also referred to herein as the fifth transistor. The first PMOS transistor P1 has a source coupled to the power node for the output domain power supply voltage Vddout and a drain coupled to the source of the diode-connected PMOS transistor P3. Transistor P1 is also referred to herein as the third transistor. Transistor P3 is also referred to herein as the sixth transistor. The gate and drain of transistor P3 are coupled to the internal node V1. Buffer 135 delays the level shifter output signal out+ to form a feedback signal (Vfb) that drives the gates of transistors P1 and M3. The gates of transistors P1 and M3 are thus coupled to the output terminal of buffer 135. Additionally, PMOS transistor P2 has a source coupled to the power node for the second power supply voltage Vddout and a drain coupled to the inverted level shifter output signal node 140. The internal node V1 is coupled to the gate of transistor P2. Transistor P2 is also denoted herein as the fourth transistor or the third transistor.
[0019] As will be further explained herein, the feedback signal Vfb is delayed with respect to the level shifter output signal out+. Given this delay, the feedback signal Vfb will still be charged to the second power supply voltage Vddout at the rising edge of the inverted input signal in- (which rising edge is a transition from ground to the first power supply voltage Vddin). Thus, at the rising edge of the inverted input signal in-, transistor P1 will turn off and transistor M3 will turn on. Assertion of the inverted input signal in- turns on transistor M1 to quickly discharge the internal node V1, which then strongly turns on transistor P2. Transistor M2 turns off at the rising edge of the inverted input signal in-, such that the turning on of transistor P2 quickly charges the inverted level shifter output signal node 140 to the second power supply voltage Vddout. By the quick discharge of the internal node V1 by transistor M1, the rising edge of the inverted level shifter output signal out- is thus strongly enhanced.
[0020] In the case where the inverted level shifter output signal out- is asserted in response to the assertion of the inverted input signal in-, the inverter 120 then discharges the level shifter output signal out+ to ground, which causes the feedback signal Vfb to also discharge after the propagation delay has elapsed through the buffer 135. The transistor P1 is thus turned on and the transistor M3 is turned off. In a particular implementation where the transistor P3 is eliminated, this turning on of the transistor P1 charges the internal node V1 to the second supply voltage Vddout. Although such an implementation is feasible, it should be noted that such an assertion of the voltage of the internal node V1 will turn off the transistor P2. Since the transistor M2 is turned off due to the discharge of the input signal in+, the inverted level shifter output signal node 140 will then float. This may be controllable because the desired charge state of the inverted level shifter output signal node 140 is asserted at the rising edge of the inverted input signal due to the discharge of the internal node V1 by the transistor M1. But in the case where both the transistors P2 and M2 are turned off, the inverted level shifter output signal node 140 will then float, making its voltage unpredictable and depending on the leakage currents in the transistors P1 and M2. Thus, it is possible that during the binary zero state duration or period of the input signal in+, the inverted level shifter output signal node 140 will undesirably discharge below the threshold voltage of the inverter 120. When the level shifter output signal out+ is to be discharged, such a discharge will then cause the inverter 120 to incorrectly charge the level shifter output signal out+. But when the input signal in+ is discharged, the transistor P3 advantageously prevents such floating of the inverted level shifter output signal node 140.
[0021] When the level shifter 100 is powered on, note that the binary state of the input signal in+ is unknown. This unknown binary state can then result in an ambiguous (and potentially undesirable) binary state for the level shifter output signal out+. To provide a defined and non-ambiguous starting binary state for the level shifter output signals out+ and out-, the level shifter 100 can include an NMOS transistor M4 and a PMOS transistor P4. Transistor M4 has a source coupled to ground and a drain coupled to an internal node V1. Transistor M4 is also referred to herein as the seventh transistor or the fourth transistor, while transistor P4 is also referred to as the eighth transistor or the fifth transistor. The inverted input signal in- drives the gate of transistor M4. Transistor P4 is coupled between the internal node V1 and a power node for the second supply voltage Vddout. A bias voltage Vbp having a value between ground and Vddout (e.g., approximately 1 / 2 Vddout) generated by a bias voltage source 145 biases the gate of transistor P4. Whenever the level shifter 100 is turned on, transistor P4 is thus slightly turned on and will tend to charge the internal node V1. Since the function of the bias voltage Vbp is thus to slightly turn on transistor P4, the bias voltage source 145 does not need to be a high-performance bias voltage source such as a bandgap reference. Thus, a lower-cost design for the bias voltage source 145 can be used in some embodiments.
[0022] When the level shifter 100 is powered on, the input signal in+ can be binary zero or it can be binary one. Assume that, upon power-on, the input signal in+ is binary zero. In this case, the level shifter output signal out+ should also be binary zero. To ensure that the level shifter output signal out+ is actually binary zero while the input signal in+ is binary zero upon power-on, transistor M4 is larger than transistor P4. In the case where the input signal in+ starts as binary zero, the inverter 105 will thus assert the inverted level shifter output signal out- to the first supply voltage Vddin, which turns on transistor M4 and causes the internal node V1 to partially discharge to some intermediate voltage between ground and the second supply voltage Vddout. This intermediate voltage partially turns on transistor P2, which causes the inverted level shifter output signal out- to charge towards the second supply voltage Vddout. Since the input signal in+ is binary zero, transistor M2 is turned off. The inverter 120 will thus discharge the level shifter output signal out+ in response to the input signal in+ being binary zero upon power-on. To ensure that this non-ambiguous state occurs in response to the input signal in+ being binary zero upon power-on, transistor M4 can be larger than transistor P4 (e.g., 8 times larger in one embodiment).
[0023] Conversely, if the input signal in+ is binary one when the level shifter 100 is powered on, the transistor M4 is turned off. As a result, the transistor P4 charges the internal node V1 towards Vddout, which helps to turn off the transistor P2. The transistor M2 can thus discharge the inverted level shifter output signal out- without any struggle with the transistor P2, leading to the possibility of an ambiguous state for the inverted level shifter output signal out-. Therefore, when the input signal in+ is binary one when the level shifter 100 is powered on, the level shifter output signal out+ is binary one. By thus protecting the level shifter 100 from an ambiguous startup state, additional details during the operation of the level shifter 100 will now be discussed.
[0024] As previously described, the transistor M1 functions to strongly discharge the internal node V1 at the rising edge of the inverted input signal in-. Figure 2 The timing diagram of shows this discharge at time B. After the input signal in+ is discharged, the feedback signal Vfb is also discharged to turn off the transistor M3. Therefore, when the inverted input signal in- is charged to Vddin, no significant static current conducts through the transistor M1. At the rising edge of the input signal in+, the transistor M2 turns on to discharge the inverted level shifter output signal node 140. This rising edge of the input signal in+ ultimately creates a corresponding rising edge in the feedback signal Vfb (the transition of the feedback signal Vfb to the second power supply voltage Vddout), as shown at time A in Figure 2 . Before the rising edge of the feedback signal Vfb, the transistor P1 is turned on and the transistor P4 is slightly turned on. The rising edge in the input signal in+ causes the inverted input signal in- to have a falling edge (transition to ground), turning off the transistor M4. With the transistor P1 turned on and the transistor P4 slightly turned on, the voltage of the internal node V1 rises rapidly just before time A. This rise in the internal node voltage V1 is beneficial because it substantially turns off the transistor P2. In this way, when the transistor M2 discharges the inverted level shifter output signal node 140, the transistor M2 does not struggle with the transistor P2. To ensure that there is sufficient delay between the rising edge of the input signal in+ and the rising edge of the feedback signal Vfb to allow for the rapid charging of the internal node V1 voltage, the level shifter 100 includes a fifth inverter 110 and an NMOS transistor M5. The transistor M5 is also referred to herein as the ninth transistor. The operation of the inverter 110 and the transistor M5 will now be discussed in more detail.
[0025] The inverter 110 is powered by a first supply voltage Vddin and inverts the inverted input signal to drive the gate of the transistor M5. Thus, the transistor M5 will turn on only in response to the rising edge of the input signal in+ after the propagation delays of the inverters 105 and 110. The transistor M5 is coupled between ground and the ground terminal of a third inverter 125 in the buffer 135. In response to the rising edge of the input signal in+, the transistor M2 turns on to discharge the inverted level shifter output signal node 140, which causes the inverter 120 to charge the level shifter output signal out+ to a second supply voltage Vddout. Once the transistor M5 turns on, this charging of the level shifter output signal out+ will cause the inverter 125 to discharge its output terminal. The buffer 135 includes a fourth inverter 130 that inverts the level shifter output signal of the inverter 125 to form a feedback signal Vfb. The feedback signal Vfb thus cannot have a rising edge until the transistor M5 turns on after the propagation delays of the inverters 105 and 110 in response to the rising edge of the input signal in+. It should be understood that the transistor M5 and the inverter 110 are optional and can be removed if the inherent propagation delays from the inverters 120 and 135 are large enough. The inverters 125 and 130 in the buffer 135 are powered by a second supply voltage Vddout.
[0026] Note that the transistors M4 and P4 can be regarded as controlling the static state of the level shifter 100, such as preventing ambiguous values of the level shifter output signal out+ (and thus the inverted output signal out-) at startup and maintaining the binary value of the level shifter output signal between its binary transitions. In contrast, the transistors M1, M2, M3, P1, P2, and P3 control the dynamic state of the level shifter 100 (the rising and falling edges of the level shifter output signal out+ and the inverted level shifter output signal out-). Since the sizes of the transistors M4 and P4 are decoupled from the sizes of the transistors M1, M2, M3, P1, P2, and P3, this decoupling of the static and dynamic control of the level shifter 100 is beneficial for simplifying the design of the level shifter 100. Additionally, note that there are no matching transistor pairs for the dynamic state in the level shifter 100. For example, the transistors M1 and M2 do not need to match. The transistor M4 can be relatively small compared to the transistor M1 because the role of the transistor M4 is to conduct a relatively small current for static operation. In contrast, the transistor M1 can be relatively large to ensure that the internal node V1 voltage discharges quickly at time B, as discussed for the Figure 2 timing diagram. For example, in one specific implementation, the transistor M1 can be 6 times larger than the transistor M4, but it should be understood that alternative size ratios for the transistors M1 and M4 can be used in alternative specific implementations.
[0027] Now, an example method of level shifting will be discussed for Figure 3 the flowchart of. The method includes an operation 300 of charging an inverted input signal to a first power supply voltage in response to discharging of an input signal. As Figure 2 shown in the timing diagram of, a rising edge of the inverted input signal in- in response to a falling edge of the input signal in+ is an example of operation 300. The method also includes the following operation 305: turning on a first transistor to discharge an internal node in response to charging of the inverted input signal, while turning off a second transistor coupled between an output signal node of the inverted level shifter and ground in response to discharging of the input signal, and simultaneously turning off a third transistor coupled between the internal node and a power supply node for a second power supply voltage. As Figure 2 shown in the timing diagram of, discharging of the internal node V1 at time B in response to turning on transistor M1 while transistors M2 and P1 are off is an example of operation 305. In addition, the method includes the following operation 310: turning on a fourth transistor coupled between an output signal node of the inverted level shifter and a power supply node for a second power supply voltage in response to discharging of the internal node voltage to charge an inverted level shifter output signal at the inverted level shifter output signal node to the second power supply voltage. Turning on transistor P2 at time B to charge the inverted level shifter output signal node 140 is an example of operation 310. The method also includes an operation 315 of discharging a level shifter output signal in response to charging of the inverted level shifter output signal to the second power supply voltage. Discharging of the level shifter output signal out+ is an example of operation 315. In addition, the method includes an operation 320 of discharging a feedback signal in response to discharging of the level shifter output signal. Discharging of the feedback signal Vfb at time B is an example of operation 320. Finally, the method includes an operation 325 of turning on a third transistor in response to discharging of the feedback signal. Turning on transistor P1 at time B is an example of operation 325.
[0028] A level shifter as disclosed herein can be incorporated into any suitable mobile device or electronic system. For example, as Figure 4 shown, a cellular phone 400, a laptop computer 405, and a tablet PC 410 can each include a level shifter according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with a level shifter constructed according to the present disclosure.
[0029] Now, the present disclosure will be outlined in the following series of clauses:
[0030] Clause 1. A level shifter, the level shifter comprising:
[0031] A first inverter configured to invert an input signal into an inverted input signal, the first inverter being powered by a first power supply voltage;
[0032] A first transistor coupled between an internal node and ground and having a gate coupled to the output terminal of the first inverter;
[0033] A second transistor coupled between ground and an inverted level shifter output signal node for inverting a level shifter output signal, the second transistor having a gate coupled to the input signal;
[0034] A third transistor coupled between the internal node and a power supply node for a second power supply voltage;
[0035] A second inverter configured to invert the inverted level shifter output signal into a level shifter output signal, the second inverter being powered by the second power supply voltage; and
[0036] A buffer configured to buffer the level shifter output signal into a feedback signal, wherein the gate of the third transistor is coupled to the output terminal of the buffer, and wherein the buffer is powered by the second power supply voltage.
[0037] Clause 2. The level shifter according to Clause 1, the level shifter further comprising:
[0038] A fourth transistor coupled between the inverted level shifter output signal node and the power supply node, the fourth transistor having a gate coupled to the internal node.
[0039] Clause 3. The level shifter according to any one of Clauses 1 to 2, the level shifter further comprising:
[0040] A fifth transistor coupled between the first transistor and the internal node, the fifth transistor having a gate coupled to the output terminal of the buffer.
[0041] Clause 4. The level shifter according to Clause 2, wherein the first transistor, the second transistor, and the fifth transistor each comprise an n-type metal oxide semiconductor (NMOS) transistor, and wherein the third transistor and the fourth transistor each comprise a p-type metal oxide semiconductor (PMOS) transistor.
[0042] Clause 5. The level shifter according to any one of Clauses 1 to 4, the level shifter further comprising:
[0043] A sixth transistor, the sixth transistor being coupled between the internal node and the third transistor, the sixth transistor having a gate coupled to the internal node.
[0044] Clause 6. The level shifter according to clause 5, the level shifter further comprising:
[0045] A seventh transistor, the seventh transistor being coupled between the internal node and ground, the seventh transistor having a gate coupled to the output terminal of the first inverter.
[0046] Clause 7. The level shifter according to clause 6, wherein the first transistor is larger than the seventh transistor.
[0047] Clause 8. The level shifter according to clause 6, the level shifter further comprising:
[0048] An eighth transistor, the eighth transistor being coupled between the internal node and the power supply node; and
[0049] A voltage source configured to bias the gate of the eighth transistor with a bias voltage.
[0050] Clause 9. The level shifter according to clause 8, wherein the seventh transistor is larger than the eighth transistor.
[0051] Clause 10. The level shifter according to clause 8, wherein the buffer includes a third inverter configured to invert the level shifter output signal, and includes a fourth inverter configured to invert the output signal from the third inverter to form the feedback signal, the level shifter further comprising:
[0052] A fifth inverter configured to invert the inverted input signal, wherein the fifth inverter is powered by the first power supply voltage, and
[0053] A ninth transistor coupled between ground and the ground terminal of the third inverter, wherein the output terminal of the fifth inverter is coupled to the gate of the ninth transistor.
[0054] Clause 11. The level shifter according to clause 10, wherein both the third inverter and the fourth inverter are powered by the second power supply voltage.
[0055] Clause 12. The level shifter according to any one of clauses 1 to 11, wherein the second power supply voltage is greater than the first power supply voltage.
[0056] Clause 13. The level shifter according to Clause 10, wherein the seventh transistor and the ninth transistor each comprise an n-type metal oxide semiconductor (NMOS) transistor, and wherein the sixth transistor and the eighth transistor each comprise a p-type metal oxide semiconductor (PMOS) transistor.
[0057] Clause 14. The level shifter according to any one of Clauses 1 to 13, wherein the level shifter is included within a cellular phone.
[0058] Clause 15. A method of level shifting, the method comprising:
[0059] Charging an inverted input signal to a first power supply voltage in response to discharging of an input signal;
[0060] Turning on a first transistor to discharge an internal node in response to the charging of the inverted input signal, while turning off a second transistor coupled between an inverted level shifter output signal node and ground in response to the discharging of the input signal, and while a third transistor coupled between the internal node and a power supply node for a second power supply voltage is turned off;
[0061] Turning on a fourth transistor coupled between the inverted level shifter output signal node and the power supply node for the second power supply voltage in response to the discharging of the internal node to charge the inverted level shifter output signal at the inverted level shifter output signal node to the second power supply voltage;
[0062] Discharging a level shifter output signal in response to the charging of the inverted level shifter output signal to the second power supply voltage;
[0063] Discharging a feedback signal in response to the discharging of the level shifter output signal; and
[0064] Turning on the third transistor in response to the discharging of the feedback signal.
[0065] Clause 16. The method according to Clause 15, the method further comprising:
[0066] Turning off the first transistor in response to the charging of the input signal to the first power supply voltage;
[0067] Charging the internal node to substantially turn off the fourth transistor in response to the turning off of the first transistor;
[0068] Turning on the second transistor to discharge the inverted level shifter output signal node in response to the charging of the input signal; and
[0069] In response to the discharging of the inverted level shifter output signal node, the level shifter output signal is charged to the second power supply voltage.
[0070] Clause 17. The method according to clause 16, the method further comprising:
[0071] In response to the charging of the level shifter output signal, the feedback signal is charged to the second power supply voltage;
[0072] And
[0073] In response to the charging of the feedback signal, the third transistor is turned off.
[0074] Clause 18. A level shifter, the level shifter comprising:
[0075] A first inverter configured to invert an input signal into an inverted input signal, the first inverter being powered by a first power supply voltage;
[0076] A first transistor coupled between an internal node and ground and having a gate coupled to an output terminal of the first inverter;
[0077] A second transistor coupled between ground and an inverted level shifter output signal node for the inverted level shifter output signal, the second transistor having a gate coupled to the input signal; and
[0078] A third transistor coupled between the inverted level shifter output signal node and a power supply node for a second power supply voltage, wherein the gate of the third transistor is coupled to the internal node.
[0079] Clause 19. The level shifter according to clause 18, the level shifter further comprising:
[0080] A fourth transistor coupled between the internal node and ground, the fourth transistor having a gate coupled to an output terminal of the first inverter.
[0081] Clause 20. The level shifter according to clause 19, wherein the first transistor is larger than the fourth transistor.
[0082] Clause 21. The level shifter according to any one of clauses 19 to 20, the level shifter further comprising:
[0083] A fifth transistor coupled between the internal node and the power supply node; and
[0084] A voltage source configured to bias the gate of the fifth transistor with a bias voltage.
[0085] Clause 22. The level shifter according to Clause 21, wherein the fourth transistor is larger than the fifth transistor.
[0086] Clause 23. The level shifter according to Clause 21, wherein the first transistor, the second transistor, and the fourth transistor each include an NMOS transistor, and wherein the third transistor and the fifth transistor each include a PMOS transistor.
[0087] It should be understood that many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific embodiments illustrated and described herein (since they are only some examples of the present disclosure), but should be commensurate with the appended claims and their functional equivalents.
Claims
1. An electric level shifter, the electric level shifter comprises: A first inverter configured to invert an input signal into an inverted input signal, the first inverter being powered by a first power supply voltage; A first transistor coupled between an internal node and ground and having a gate coupled to the output terminal of the first inverter; A second transistor coupled between ground and an inverted electric level shifter output signal node for inverting the electric level shifter output signal, the second transistor having a gate coupled to the input signal; A third transistor coupled between the internal node and a power supply node for a second power supply voltage; A second inverter configured to invert the inverted electric level shifter output signal into an electric level shifter output signal, the second inverter being powered by the second power supply voltage; and A buffer configured to buffer the electric level shifter output signal into a feedback signal, wherein the gate of the third transistor is coupled to the output terminal of the buffer, and wherein the buffer is powered by the second power supply voltage.
2. The electric level shifter according to claim 1, the electric level shifter further comprises: A fourth transistor coupled between the inverted electric level shifter output signal node and the power supply node, the fourth transistor having a gate coupled to the internal node.
3. The electric level shifter according to claim 2, the electric level shifter further comprises: A fifth transistor coupled between the first transistor and the internal node, the fifth transistor having a gate coupled to the output terminal of the buffer.
4. The electric level shifter according to claim 3, wherein the first transistor, the second transistor and the fifth transistor each comprise an n-type metal oxide semiconductor (NMOS) transistor, and wherein the third transistor and the fourth transistor each comprise a p-type metal oxide semiconductor (PMOS) transistor.
5. The electric level shifter according to claim 3, the electric level shifter further comprises: A sixth transistor coupled between the internal node and the third transistor, the sixth transistor having a gate coupled to the internal node.
6. The electric level shifter according to claim 5, the electric level shifter further comprises: A seventh transistor coupled between the internal node and ground, the seventh transistor having a gate coupled to the output terminal of the first inverter.
7. The electric level shifter according to claim 6, wherein the first transistor is larger than the seventh transistor.
8. The electric level shifter according to claim 6, the electric level shifter further comprises: An eighth transistor coupled between the internal node and the power supply node; and A voltage source configured to bias the gate of the eighth transistor with a bias voltage.
9. The level shifter according to claim 8, wherein the seventh transistor is larger than the eighth transistor.
10. The level shifter according to claim 8, wherein the buffer includes a third inverter configured to invert the level shifter output signal, and includes a fourth inverter configured to invert the output signal from the third inverter to form the feedback signal. The level shifter further includes: a fifth inverter configured to invert the inverted input signal, wherein the fifth inverter is powered by the first power supply voltage, and a ninth transistor coupled between ground and the ground terminal of the third inverter, wherein the output terminal of the fifth inverter is coupled to the gate of the ninth transistor.
11. The level shifter according to claim 10, wherein both the third inverter and the fourth inverter are powered by the second power supply voltage.
12. The level shifter according to claim 1, wherein the second power supply voltage is greater than the first power supply voltage.
13. The level shifter according to claim 10, wherein the seventh transistor and the ninth transistor each include an n-type metal oxide semiconductor (NMOS) transistor, and wherein the sixth transistor and the eighth transistor each include a p-type metal oxide semiconductor (PMOS) transistor.
14. The level shifter according to claim 1, wherein the level shifter is included within a cellular phone.
15. A method of level shifting, the method includes: charging the inverted input signal to a first power supply voltage in response to discharging of the input signal; turning on a first transistor to discharge an internal node in response to the charging of the inverted input signal, while turning off a second transistor coupled between the inverted level shifter output signal node and ground in response to the discharging of the input signal, and while a third transistor coupled between the internal node and the power supply node for the second power supply voltage is turned off; turning on a fourth transistor coupled between the inverted level shifter output signal node and the power supply node for the second power supply voltage in response to the discharging of the internal node to charge the inverted level shifter output signal at the inverted level shifter output signal node to the second power supply voltage; discharging the level shifter output signal in response to the charging of the inverted level shifter output signal to the second power supply voltage; discharging the feedback signal in response to the discharging of the level shifter output signal; and turning on the third transistor in response to the discharging of the feedback signal.
16. The method according to claim 15, the method further includes: turning off the first transistor in response to charging of the input signal to the first power supply voltage; charging the internal node in response to the turning off of the first transistor to substantially turn off the fourth transistor; Turn on the second transistor in response to the charging of the input signal to discharge the inverted level shifter output signal node; and Charge the level shifter output signal to the second power supply voltage in response to the discharging of the inverted level shifter output signal node.
17. The method according to claim 16, the method further comprises: Charge the feedback signal to the second power supply voltage in response to the charging of the level shifter output signal; and Turn off the third transistor in response to the charging of the feedback signal.
18. A level shifter, the level shifter comprises: A first inverter configured to invert an input signal into an inverted input signal, the first inverter being powered by a first power supply voltage; A first transistor coupled between an internal node and ground and having a gate coupled to the output terminal of the first inverter; A second transistor coupled between ground and an inverted level shifter output signal node for the inverted level shifter output signal, the second transistor having a gate coupled to the input signal; and A third transistor coupled between the inverted level shifter output signal node and a power supply node for a second power supply voltage, wherein the gate of the third transistor is coupled to the internal node.
19. The level shifter according to claim 18, the level shifter further comprises: A fourth transistor coupled between the internal node and ground, the fourth transistor having a gate coupled to the output terminal of the first inverter.
20. The level shifter according to claim 19, wherein the first transistor is larger than the fourth transistor.
21. The level shifter according to claim 19, the level shifter further comprises: A fifth transistor coupled between the internal node and the power supply node; and A voltage source configured to bias the gate of the fifth transistor with a bias voltage.
22. The level shifter according to claim 21, wherein the fourth transistor is larger than the fifth transistor.
23. The level shifter according to claim 21, wherein the first transistor, the second transistor, and the fourth transistor each comprise an NMOS transistor, and wherein the third transistor and the fifth transistor each comprise a PMOS transistor.