Phase change memory cell with heater

Abstract

The embodiment of the invention provides a method for forming a phase change memory device. The method includes forming a bottom electrode on a support structure; sequentially forming a first blanket type dielectric layer, a phase change material layer, a second blanket type dielectric layer and a hard mask on the top of the bottom electrode; forming an inner spacer in the opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; respectively etching the second blanket-covering type dielectric layer, the phase change material layer and the first blanket-covering type dielectric layer into a second dielectric layer, a phase change element and a first dielectric layer; forming a conductive liner surrounding the phase change element; and forming a top electrode on top of the heating element. Structures thus formed are also provided.

Description

BACKGROUND OF THE INVENTION

[0001] This application relates to the manufacture of semiconductor integrated circuits. More specifically, the present invention relates to a phase change memory device having a heating element and a method of manufacturing the same.

[0002] Phase change memories have recently emerged as a viable technology for memory applications and analog computing. In a typical phase change memory (PCM) device, such as a cross-point PCM device, each memory cell includes a storage element and a selector. The storage element is a PCM cell, and the PCM cell can be programmed by melting, quenching, and / or recrystallization. A heater or heating element is typically used during the process of programming the PCM cell.

[0003] In the current prior art, the PCM cells are typically placed on top of a bottom heater or heating element. During a conventional lateral PCM cell integration process, the PCM cells at the top and the heater or heating element at the bottom are typically patterned at different stages. Due to the inevitable overlap error or misalignment between the step of patterning the bottom heater and the step of patterning the top PCM cell (especially the phase change element layer), and in the case where the PCM cell is circular in shape, the heater is not always centered on the PCM cell. In other words, the heater and the PCM cell may be formed non-concentrically. The non-concentric placement of the heating element and the PCM cell may result in, among other defects, a non-uniform distribution of the programming current, which may lead to a reduction in the performance of the PCM device and sometimes be unpredictable. In addition, this conventional integration process introduces cell-to-cell variability in the PCM device. U.S. Patent S / N 7463512 to Lung provides some perspectives on PCM cells based on the conventional lateral PCM cell integration process. SUMMARY OF THE INVENTION

[0004] Embodiments of the present invention provide a phase change memory (PCM) device. The PCM device includes a bottom electrode; a first dielectric layer on top of the bottom electrode; a phase change element on top of the first dielectric layer; a heating element on top of the phase change element; a top electrode on top of the heating element; and a conductive liner at least surrounding the phase change element, wherein the heating element is at a substantially central position of the phase change element and has an equal horizontal distance from the conductive liner surrounding the phase change element. The equal horizontal distance from the heating element to the edge of the phase change element provides substantially uniform conductivity and thus a uniform distribution of the programming current during PCM device operation.

[0005] In one embodiment, the heating element is surrounded by a second dielectric layer and a third dielectric layer, the third dielectric layer being on top of the second dielectric layer and different in material from the second dielectric layer.

[0006] In another embodiment, the second and third dielectric layers have respective outer sidewalls that are aligned with each other and are substantially aligned with the phase change element.

[0007] In yet another embodiment, the conductive lining covers at least a lower portion of the outer sidewall of the second dielectric layer.

[0008] In one embodiment, the PCM device further includes a resistive lining on top of the phase change element, the resistive lining being under the heating element and the second dielectric layer and being surrounded by the conductive lining. When in the RESET state, when at least a portion of the phase change element is in a high resistance state or experiences resistance drift due to its amorphous form, the resistive lining provides a lower resistance path for the read current.

[0009] In another embodiment, in a back-end-of-line (BEOL) structure, the bottom electrode is part of metal level M, the top electrode is part of metal level M+1, and metal level M and metal level M+1 are two adjacent metal levels.

[0010] Embodiments of the present invention also provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a support structure; sequentially forming a first blanket dielectric layer, a phase change material layer, a second blanket dielectric layer, and a hard mask on top of the bottom electrode, the hard mask having an opening exposing a portion of the second blanket dielectric layer; forming an inner spacer in the opening to create a modified opening; extending the modified opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer into a second dielectric layer, a phase change element, and a first dielectric layer respectively; forming a conductive lining at least surrounding the phase change element; and forming a top electrode on top of the heating element. By forming the heating element in the extended opening created or obtained by the inner spacer, the heating element has substantially the same distance to the outer edge or sidewall of the inner spacer.

[0011] In one embodiment, etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer includes removing the hard mask surrounding the inner spacer; and the process etches the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer in an anisotropic etching process to expose the bottom electrode by using the inner spacer and the heating element as etching masks. Using the inner spacer as an etching mask ensures that the heating element has substantially the same distance to the outer edge or sidewall of the phase change element and to the conductive lining surrounding the phase change element.

[0012] In another embodiment, extending the modified opening into the second blanket dielectric layer includes etching the second blanket dielectric layer in an anisotropic etching process by using the inner spacer as an etching mask.

[0013] In one embodiment, the method further includes forming a resistive liner layer over the phase change material layer before forming the second blanket dielectric layer, such that the resistive liner layer is located between the phase change material layer and the second blanket dielectric layer.

[0014] In another embodiment, forming the inner spacer includes depositing a conformal spacer layer covering the top surface of the hard mask and the sidewalls of the openings in the hard mask; and subsequently removing the horizontal portions of the conformal spacer layer during an anisotropic etching process.

[0015] In yet another embodiment, forming the conductive liner includes forming a conductive liner layer covering the top surface of the heating element, the sidewalls of the inner spacer, the sidewalls of the second dielectric layer, the sidewalls of the phase change element, the sidewalls of the first dielectric layer, and the top surface of the bottom electrode; removing the horizontal portions of the conductive liner layer during an anisotropic etching process; and removing at least a portion of the conductive liner layer covering the sidewalls of the inner spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be more fully understood and appreciated from the following detailed description of embodiments of the invention in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device according to an embodiment of the present invention;

[0018] Figure 2 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device after the steps shown in Figure 1 according to an embodiment of the present invention;

[0019] Figure 3 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device after the steps shown in Figure 2 according to an embodiment of the present invention;

[0020] Figure 4 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device after the steps shown in Figure 3 according to an embodiment of the present invention;

[0021] Figure 5 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device after the steps shown in Figure 4 according to an embodiment of the present invention;

[0022] Figure 6 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device after the steps shown in Figure 5Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0023] Figure 7 According to one embodiment of the present invention, after the steps shown in Figure 6 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0024] Figure 8 According to one embodiment of the present invention, after the steps shown in Figure 7 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0025] Figure 9 According to one embodiment of the present invention, after the steps shown in Figure 8 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0026] Figure 10 According to one embodiment of the present invention, after the steps shown in Figure 9 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0027] Figure 11 According to one embodiment of the present invention, after the steps shown in Figure 10 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0028] Figure 12 According to one embodiment of the present invention, after the steps shown in Figure 11 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0029] Figure 13 According to one embodiment of the present invention, after the steps shown in Figure 12 Exemplary illustration of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in

[0030] Figure 14A and Figure 14B are respectively exemplary illustrations of cross-sectional views of a PCM device during the SET state and the RESET state according to one embodiment of the present invention; and

[0031] Figure 15 is an exemplary illustration of a flowchart of a method for manufacturing a PCM device according to an embodiment of the present invention.

[0032] It should be understood that, for purposes of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. Additionally, and if applicable, in various functional block diagrams, two connected devices and / or elements may not necessarily be shown as connected. In some other instances, the grouping of certain elements in a functional block diagram may be for descriptive purposes only and may not necessarily imply that they are in a single physical entity or that they are embodied in a single physical entity. Detailed Description

[0033] In the following detailed description and the figures, it should be understood that the various layers, structures, and regions shown in the figures are illustrative and schematic and are not drawn to scale. Additionally, for ease of explanation, one or more layers, structures, and regions of the type commonly used to form a semiconductor device or structure may not be explicitly shown in a given illustration or figure. This does not mean that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure. Further, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the description provided herein is not intended to include all processing steps that may be required to form a functional semiconductor integrated circuit device. Instead, for the sake of economy of description, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are purposefully not described herein.

[0034] It should be understood that the terms "about" or "substantially" as used herein with respect to thickness, width, percentage, range, etc. are intended to mean close to or approximate but not exact. For example, the terms "about" or "substantially" as used herein mean that there may be a small margin of error, e.g., by way of example only, 1% or less of the stated amount. Similarly, the terms "on", "above", or "top" as used herein to describe the positional relationship between two layers or structures are intended to be broadly interpreted and should not be construed to exclude the presence of one or more intermediate layers or structures.

[0035] To provide a spatial context for the different structural orientations of the semiconductor structures shown in the figures, XYZ Cartesian coordinates may be provided in some of the figures. As used herein, the term "vertical" or "vertical direction" or "vertical height" refers to the Z direction of the Cartesian coordinates shown in the figures, and the terms "horizontal" or "horizontal direction" or "lateral direction" as used herein refer to the X direction and / or Y direction of the Cartesian coordinates shown in the figures.

[0036] In addition, although different reference numerals are used in different figures, the same or similar reference numerals are used in all figures to denote the same or similar features, elements, or structures. Therefore, for the sake of economy of description, the detailed description of the same or similar features, elements, or structures may not be repeated for each figure. In some figures, the reference numerals for the same or similar elements may also be omitted so as not to overcrowd the figures.

[0037] Figure 1 is an exemplary illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device according to an embodiment of the present invention. More specifically, in manufacturing the PCM device 10 (see in more detail Figure 13 ), an embodiment of the present invention provides a receiving support structure 101, such as a semiconductor substrate or a back-end-of-line (BEOL) structure on a semiconductor substrate, on or in which other active and / or passive semiconductor devices, such as transistors, isolation structures, and / or contacts (not shown for simplicity), may be formed.

[0038] An embodiment of the present invention further provides forming a bottom electrode layer 201 on top of the support structure 101 by, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The bottom electrode layer 201 may be, for example, a titanium nitride layer and may be formed to have a thickness in the range of about 50 nm to about 100 nm, but the bottom electrode layer 201 may be made of other suitable materials and / or thicknesses, depending on the specific application of the PCM device 10. For example, the bottom electrode layer 201 may be formed of one or more material layers, such materials as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), tungsten silicide (WSi), and other materials.

[0039] Figure 2 is an illustrative illustration of a cross-sectional view of a PCM device in a manufacturing step of a PCM device after the steps illustrated in Figure 1 . More specifically, an embodiment of the present invention provides patterning the bottom electrode layer 201 into a bottom electrode 202. The bottom electrode 202 may be surrounded by a dielectric material layer or embedded in a dielectric material layer. In one embodiment, the bottom electrode 202 may be formed on top of a metal level (e.g., M2 or M3 layer) in a BEOL structure, or it may itself be part of a metal level (e.g., M2 or M3 layer). When it is part of a metal level such as an M2 or M3 level, for reference convenience only hereinafter, the metal level itself may sometimes be referred to as part of the PCM device 10. As Figure 2The illustrative diagrams described therein illustrate that the bottom electrode 202 can extend, for example, in a left-to-right direction, and the dielectric material layer surrounding the bottom electrode 202 can be behind and in front of the bottom electrode 202, and thus is not shown in Figure 2 it.

[0040] Embodiments of the present invention also provide for forming a first blanket dielectric layer 301 on top of the bottom electrode 202 (and the dielectric material layer therearound), forming a phase change material layer 401 on top of the first blanket dielectric layer 301, forming a resistance liner layer 501 on top of the phase change material layer 401, and forming a second blanket dielectric layer 601 on top of the resistance liner layer 501. The resistance liner layer 501 can be optional, and when not used, the second blanket dielectric layer 601 can be formed directly on top of the phase change material layer 401. The formation of the first blanket dielectric layer 301, the phase change material layer 401, the resistance liner layer 501, and the second blanket dielectric layer 601 can be carried out by (for example) CVD, PVD, or ALD processes.

[0041] In one embodiment, the first blanket dielectric layer 301 and the second blanket dielectric layer 601 can be any suitable dielectric material, such as silicon nitride (SiN), silicon boride (SiB), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), or a combination thereof. The first blanket dielectric layer 301 and the second blanket dielectric layer 601 can be independently formed to have an individual thickness ranging from about 10 nm to about 30 nm, but is not limited thereto.

[0042] In another embodiment, the phase change material layer 401 can be, for example, a germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), or silver-iridium-antimony-telluride (AIST) material layer, but other suitable materials can also be used. Examples of other suitable phase change materials can include, but are not limited to, germanium-tellurium compound materials (GeTe), silicon-antimony-tellurium (Si-Sb-Te) alloys, gallium-antimony-tellurium (Ga-Sb-Te) alloys, germanium-bismuth-tellurium (Ge-Bi-Te) alloys, indium-selenium (In-Se) alloys, arsenic-antimony-tellurium (As-Sb-Te) alloys, silver-indium-antimony-tellurium (Ag-In-Sb-Te) alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, Ge-Te alloys, and combinations thereof. The phase change material layer 401 can be undoped, or can be doped with (for example) one or more elements, such as oxygen (O), nitrogen (N), silicon (Si), and titanium (Ti).

[0043] Embodiments of the present invention provide for forming a thin layer of a conformal phase change material. For example, the phase change material layer 401 can be formed to have a thickness that is thinner than the thickness in conventional PCM devices, which ranges from about 5 nm to about 30 nm, although other thicknesses are possible. Using a thin layer of the phase change material creates a smaller volume of the phase change material that needs to be heated by a heating element (formed later thereon), thereby reducing the time and / or energy required to change the phase change material from a high-resistance amorphous phase or amorphous atomic structure to a low-resistance crystalline phase or crystalline atomic structure during operation of the PCM device. In other words, the smaller volume of the phase change material provides a faster phase change because less heating and / or cooling is required to change the phase or state of the phase change material (e.g., from an amorphous phase to a crystalline phase, or vice versa). By using a heating element with a thinner phase change material layer, embodiments of the present invention provide a PCM device having a semiconductor structure that allows for a faster transition of the phase change material with improved functionality.

[0044] The resistive liner layer 501 can be a thin layer of a resistive material, the resistivity of which can be higher than that of the phase change material layer 401. Suitable materials for the resistive liner layer 501 can include, for example, tantalum nitride (TaN), aluminum nitride (AlN), boron nitride (BN), aluminum oxide (AlO), tungsten nitride (WN), cobalt tungsten (CoW), nickel tungsten (NiW), yttrium oxide (YO), or alloys of these materials. The resistance of the resistive liner 501 can be substantially greater than the resistance of the phase change material layer 401 when it is in a low-resistance state or crystalline state (e.g., ten to thirty times or more higher), but substantially lower than the resistance of the phase change material layer 401 when it is in a high-resistance state or amorphous state (e.g., five to twenty times or more lower).

[0045] Figure 3 is an illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of a PCM device after the steps illustrated in Figure 2 More particularly, embodiments of the present invention provide for forming a hard mask 701 through, for example, a photolithographic patterning process. The hard mask 701 can be formed to have a thickness ranging from about 30 nm to about 100 nm and is patterned to have an opening 711 that exposes the top surface of the second blanket dielectric layer 601. In one embodiment, the opening 711 can be circular in shape when viewed from its top. The hard mask 701 can be made of the same or a different dielectric material as the dielectric material of the second blanket dielectric layer 601.

[0046] Figure 4 is, according to an embodiment of the present invention, in Figure 3An illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown. More particularly, embodiments of the present invention provide for forming an inner spacer 702 at the sidewalls of the opening 711 of the hard mask 701. For example, the inner spacer 702 can be formed by first depositing a conformal spacer layer. The conformal spacer layer can be made of a material such as SiN, SiB, SiON, SiBCN, SiOCN, SiCN, SiCO, or other suitable materials, which line the top surface of the hard mask 701 and the sidewalls of the opening 711. Subsequently, the horizontal portions of the conformal spacer layer can be removed through an anisotropic and directional etching process, such as a reactive ion etching (RIE) process, resulting in the formation of the inner spacer 702. In one embodiment, when viewed from its top, the inner spacer 702 can be annular or ring-shaped. The formation of the inner spacer 702 modifies the opening 711 to a modified opening 712. The inner spacer 702 has substantially the same horizontal thickness at the sidewalls of the opening 711 of the hard mask 701.

[0047] Figure 5 is an illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in accordance with an embodiment of the present invention. Figure 4 More particularly, embodiments of the present invention provide for extending the modified opening 712 into the second blanket dielectric layer 601 to create an extended opening 713. Extending the modified opening 712 into the second blanket dielectric layer 601 can be performed through an anisotropic etching process (e.g., using the inner spacer 702 as an etch mask). The extended opening 713 can expose the top surface of the resist liner layer 501 or directly expose the top surface of the phase change material layer 401 when the resist layer 501 is not used.

[0048] Figure 6 is an illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in accordance with an embodiment of the present invention. Figure 5 More particularly, embodiments of the present invention provide for filling the extended opening 713 with a heating material to form a heating element 703. The heating assembly 703 can be formed through a conformal deposition process and can include a material such as TiN or a multi-layer material such as TaN / TiN / TaN, etc. The heating element 703 is in direct contact with the underlying resist liner layer 501 and / or in direct contact with the phase change material layer 401.

[0049] Figure 7 is an illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in accordance with an embodiment of the present invention. Figure 6. More particularly, embodiments of the present invention provide for removing a hard mask 701 surrounding an inner spacer 702 to expose an underlying second blanket dielectric layer 601. Embodiments of the present invention may further include etching the second blanket dielectric layer 601 into a second dielectric layer 602, etching the underlying resistive liner layer 501 into a resistive liner 502, etching the underlying phase change material layer 401 into a phase change element 402, and etching the underlying first blanket dielectric layer 301 into a first dielectric layer 302, thereby forming a PCM stack 410. The above etching uses the inner spacer 702 and the heating element 703 as an etching mask. PCM stack 410 includes inner spacer 702 and outer sidewalls of second dielectric layer 602, and sidewalls of resistive liner 502, phase change element 402, and first dielectric layer 302, which are substantially aligned with each other and with the outer sidewalls of inner spacer 702 and second dielectric layer 602. Using inner spacer 702 and heating element 703 having uniform thickness as an etching mask ensures that the outer sidewall and inner sidewall of second dielectric layer 602 are made concentric. Therefore, heating element 703 can have substantially equal horizontal distances from the outer sidewalls of second dielectric layer 602 and the sidewalls of phase change element 402. In other words, heating element 703 can be located at substantially the center of phase change element 402, and can be formed to have equal horizontal distances from conductive liner 803 formed later, as described below. Figure 12 Describing in more detail, the conductive liner surrounds the phase change element 402 .

[0050] Figure 8 According to an embodiment of the present invention, Figure 7 4. More specifically, embodiments of the present invention provide for forming a conformal liner layer 801 covering the PCM stack 410. For example, the conformal liner layer 801 covers the heating element 703, the inner spacer 702, the second dielectric layer 602, the resistive liner 502, the phase change element 402, the first dielectric layer 302, and the bottom electrode 202. The conformal liner layer 801 can be a conductive liner layer, such as a metal liner layer of TiN or other suitable conductive material. The conformal liner layer 801 can be formed to have a thickness ranging from about 5 nm to about 20 nm, but is not limited to these thicknesses.

[0051] Figure 9 According to an embodiment of the present invention, Figure 8An illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps described in []. More particularly, embodiments of the present invention provide for removing a horizontal portion of the conformal liner layer 801 through an anisotropic etching process, such as a reactive ion etching (RIE) process. The anisotropic etching process is a directional etching process that removes a portion of the conformal liner layer covering the top surface of the PCM stack 410, which portion includes the top surface of the heating element 703 and the top surface of the inner spacer 702, and which portion covers the top surface of the bottom electrode 202. The anisotropic etching process leaves a vertical portion 802 of the conformal liner layer 801 against the sidewalls of the PCM stack 410. The sidewalls of the PCM stack 410 include the sidewalls of the inner spacer 702, the second dielectric layer 602, the resistive liner 502, the phase change element 402, and the first dielectric layer 302. In one embodiment, the anisotropic etching process may etch into the bottom electrode 202 and also remove the top portion of the bottom electrode 202.

[0052] Figure 10 is, according to an embodiment of the present invention, in Figure 9 An illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown in []. More specifically, embodiments of the present invention provide for depositing a sacrificial layer 811 on top of the structure. The sacrificial layer 811 may be formed on top of the bottom electrode 202 and cover at least a portion of the vertical portion 802 of the conformal liner layer 801. For example, in one embodiment, an organic planarization layer (OPL) may be deposited to initially cover the entire PCM stack 410 and on top of the bottom electrode 202. In other words, the OPL may cover the top surfaces of the heating element 703 and the inner spacer 702 as well as the vertical portion 802 of the conformal liner layer 801. The OPL may then be planarized through a chemical mechanical polishing (CMP) process to produce a flat top surface and subsequently recessed downward to a level below the inner spacer 702 to form the sacrificial layer 811. In one embodiment, the sacrificial layer 811 may have a height that is lower than the inner spacer 702 but higher than the phase change element 402 and the resistive liner 502.

[0053] Figure 11 is, according to an embodiment of the present invention, in Figure 10An illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown. More specifically, embodiments of the present invention provide for removing a portion of the vertical portion 802 of the conformal liner layer 801 that is above the sacrificial layer 811 while the sacrificial layer 811 covers and protects the remaining portion of the vertical portion 802 of the conformal liner layer 801. The removal of the portion of the vertical portion 802 of the conformal liner layer 801 can be carried out by a selective etching process, such as in SC2 chemistry containing strong acids such as hydrochloric acid and hydrogen peroxide, resulting in a conductive liner 803 made of the remaining portion of the conformal liner layer 801. The conductive liner 803 covers at least a portion of the first dielectric layer 302, the phase change element 402, the resistive liner 502, and the second dielectric layer 602. After the removal, embodiments of the present invention provide for selectively removing the sacrificial layer 811 surrounding the conductive liner 803.

[0054] Figure 12 is, according to an embodiment of the present invention, in Figure 11 An illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown. More particularly, embodiments of the present invention provide for depositing a fourth dielectric layer 821 that covers the PCM stack 410. For example, the fourth dielectric layer 821 can be formed adjacent to the sidewalls of the inner spacer 702, a portion of the sidewalls of the second dielectric layer 602, and the conductive liner 803. In one embodiment, the top surface of the fourth dielectric layer 821 can be planarized to be coplanar with the top surfaces of the heating element 703 and the inner spacer 702.

[0055] Figure 13 is, according to an embodiment of the present invention, in Figure 12 An illustrative diagram of a cross-sectional view of a PCM device in the manufacturing steps of the PCM device after the steps shown. More particularly, embodiments of the present invention provide for forming a top electrode 831 on top of the heating element 703. For example, in one embodiment, a fifth dielectric layer 832 can be deposited on top of the PCM stack 410 and the fourth dielectric layer 821. An opening can be created in the fifth dielectric layer 832 to expose the top surface of the heating element 703, and the top electrode 831 can then be deposited in the opening on top of the heating element 703. In another embodiment, a conductive material can be first deposited on top of the PCM stack 410 and then patterned to form the top electrode 831. Then a dielectric layer can be deposited to form the fifth dielectric layer 832 surrounding the top electrode 831.

[0056] In one embodiment, the bottom electrode 202 and the top electrode 831 can be two adjacent metal levels in a BEOL structure. For example, the bottom electrode 202 can be metal level M, and the top electrode 831 can be metal level M+1. The metal level M and the metal level M+1 can extend in the vertical direction such that the bottom electrode 202 (metal level M) can extend from left to right, while the top electrode 831 (metal level M+1) can extend into and / or out of the paper in a direction perpendicular to the left-to-right direction. Here, M can be a number such as 2, 3, 4, etc., representing the metal level.

[0057] Figure 14A and Figure 14B are exemplary illustrations of cross-sectional views of a PCM device during operation in the SET state and the RESET state, respectively, according to various embodiments of the present invention. More specifically, the PCM device 10 can include a resistive liner 502, as described above, which can be deposited to have a thickness of about a few nanometers to ten nanometers. The resistive liner 502 can be formed to improve the electrical functionality of the phase change element 402, such as reducing resistance drift.

[0058] Resistance drift refers to the phenomenon that the resistance of the phase change element 402 of the PCM device 10 does not remain at a constant value after programming, especially after a RESET operation, when at least the switching region 840 of the phase change element 402 is set to an amorphous state or phase. Therefore, after programming, the resistance of the phase change element 402 changes as a function of time.

[0059] In the SET state as Figure 14A shown, the read current 841 from the heating element 703 can enter the phase change element 402 directly through the resistive liner 502 because the resistance of the resistive liner 502 is substantially higher than the resistance of the phase change element 402 in the crystalline state or the low-resistance state. The read current 841 can continue to pass through the phase change element 402 in the lateral direction, through the conductive liner 803, and finally reach the bottom electrode 202.

[0060] In the RESET state as Figure 14B shown, at least a portion of the phase change element 402 (e.g., the portion under the heating element 703) can be changed to an amorphous state. Therefore, the phase change element 402 can exhibit resistance drift over time, and when there is no resistive liner 502, the read current 842 can pass through the amorphous state of the phase change element 402 with a resistance that can adversely affect the performance of the PCM device.

[0061] According to one embodiment of the present invention, the resistive liner 502 may migrate the resistance drift. When the resistive liner 502 shunts the read current 842 from the switching region 840 of the phase change element 402 in the amorphous state, the resistance drift is mitigated by the resistive liner 502. With the resistive liner 502, the read current 842 can pass laterally through the resistive liner 502 to reach the crystalline portion of the phase change element 402, and the resistive liner is above the non-crystalline portion of the phase change element 402, and the non-crystalline portion has a resistance substantially higher than that of the resistive liner 502. In other words, the read current 842 bypasses the switching region 840 (in the amorphous state) of the phase change element 402 through the resistive liner 502, thus exhibiting stable electrical performance.

[0062] Figure 15 FIG. is an exemplary illustration of a flowchart of a method for manufacturing a PCM device according to an embodiment of the present invention. The method includes (910) forming a bottom electrode on a support structure, such as a substrate or a BEOL structure on top of a substrate; (920) forming a stack that includes, from bottom to top, a first blanket dielectric layer on top of the bottom electrode, a phase change material layer, a second blanket dielectric layer, an optional resistive liner, and a hard mask having an opening; (930) forming inner spacers at the sidewalls of the opening in the hard mask to modify the opening, thereby creating a modified opening; (940) extending the modified opening into the second blanket dielectric layer to create an extended opening; (950) filling the extended opening with a heating material to form a heating element surrounded by the second blanket dielectric layer and the inner spacers; (960) removing the hard mask, and etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer into a second dielectric layer, a phase change element, and a first dielectric layer to form a PCM stack; (970) forming a conductive liner at least surrounding the phase change element; and (980) forming a top electrode on top of the heating element.

[0063] It should be understood that the exemplary methods discussed herein can be readily combined with other semiconductor processing flows, semiconductor devices, and integrated circuits having various analog and digital circuits or mixed-signal circuits. In particular, integrated circuit dies can be fabricated with various devices, such as field effect transistors, bipolar transistors, metal oxide semiconductor transistors, diodes, capacitors, inductors, etc. The integrated circuit according to the present invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention can include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid-state media storage devices, functional circuits, etc. Systems and hardware incorporating such integrated circuits are considered to be part of the embodiments described herein. Given the teachings of the present invention provided herein, those of ordinary skill in the art will be able to envision other implementations and applications of the technology of the present invention.

[0064] Accordingly, at least portions of one or more of the semiconductor structures described herein can be implemented in an integrated circuit. The manufacturer can distribute the resulting integrated circuit chip in the form of an original wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip can be mounted in a single chip package (e.g., a plastic carrier with leads fixed to a motherboard or other high-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface and / or buried interconnections). In any case, the chip can then be integrated with other chips, discrete circuit elements, and / or other signal processing devices, as part of an intermediate or final product such as a motherboard. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device, and a central processing unit.

[0065] The description of the various embodiments of the present invention has been presented for purposes of illustration, and they are not exhaustive, and the present invention is not limited to the disclosed embodiments. The terms used herein have been chosen to best explain the principles of the embodiments, the practical application, or the improvement of the technology found in the marketplace, and to enable those skilled in the art to understand the embodiments disclosed herein. However, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modifications, and / or alternative embodiments can be made without departing from the scope of the present invention, and accordingly, all such changes, modifications, and / or alternative embodiments are contemplated and considered to be within the scope of the present invention. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the present invention.

Claims

1. A phase change memory (PCM) device, comprising: a bottom electrode; a first dielectric layer on top of the bottom electrode; a phase change element on top of the first dielectric layer; a heating element on top of the phase change element; a top electrode on top of the heating element; and a conductive liner at least surrounding the phase change element, wherein the heating element is at a substantially central position of the phase change element and has an equal horizontal distance from the conductive liner surrounding the phase change element.

2. The PCM device according to claim 1, wherein the heating element is surrounded by a second dielectric layer and a third dielectric layer, the third dielectric layer being on top of the second dielectric layer and being different in material from the second dielectric layer.

3. The PCM device according to claim 2, wherein the second dielectric layer and the third dielectric layer have respective outer sidewalls that are aligned with each other and substantially aligned with the phase change element.

4. The PCM device according to claim 3, wherein the conductive liner covers at least a lower portion of the outer sidewall of the second dielectric layer.

5. The PCM device according to claim 1, further comprising a resistive liner on top of the phase change element, the resistive liner being below the heating and surrounded by the conductive liner.

6. The PCM device according to claim 1, wherein the bottom electrode is part of a metal level M in a back-end-of-line (BEOL) structure, and the top electrode is part of a metal level M+1 in the BEOL structure, and metal level M and metal level M+1 are two adjacent metal levels.

7. A method of forming a phase change memory device, the method comprising: forming a bottom electrode on a support structure; successively forming a first blanket dielectric layer, a phase change material layer, a second blanket dielectric layer, and a hard mask on top of the bottom electrode, the hard mask having an opening exposing a portion of the second blanket dielectric layer; forming an inner spacer in the opening of the hard mask to create a modified opening; extending the modified opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer into a second dielectric layer, a phase change element, and a first dielectric layer respectively; forming a conductive liner at least surrounding the phase change element; and forming a top electrode on top of the heating element.

8. The method according to claim 7, wherein etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer comprises: removing the hard mask surrounding the inner spacer; and etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer in an anisotropic etching process to expose the bottom electrode by using the inner spacer and the heating element as etching masks.

9. The method according to claim 7, wherein extending the modified opening into the second blanket dielectric layer includes etching the second blanket dielectric layer in an anisotropic etching process by using the inner spacer as an etch mask.

10. The method according to claim 7, further comprising forming a resist liner layer over the phase change material layer before forming the second blanket dielectric layer, such that the resist liner layer is located between the phase change material layer and the second blanket dielectric layer.

11. The method according to claim 7, wherein forming the inner spacer comprises: depositing a conformal spacer layer covering a top surface of the hard mask and sidewalls of the opening of the hard mask; and subsequently removing a horizontal portion of the conformal spacer layer in an anisotropic etching process.

12. The method according to claim 7, wherein forming the conductive liner comprises: forming a conductive liner layer that covers a top surface of the heating element, sidewalls of the inner spacer, sidewalls of the second dielectric layer, sidewalls of the phase change element, sidewalls of the first dielectric layer, and a top surface of the bottom electrode; removing a horizontal portion of the conductive liner layer in an anisotropic etching process; and removing at least a portion of the conductive liner layer covering the sidewalls of the inner spacer.

13. A method of forming a phase change memory device, the method comprises: providing a bottom electrode; sequentially forming a first blanket dielectric layer, a phase change material layer, and a second blanket dielectric layer on top of the bottom electrode; forming a hard mask on top of the second blanket dielectric layer, the hard mask having an opening exposing the second blanket dielectric layer; forming a conformal spacer layer covering a top surface of the hard mask and sidewalls of the opening of the hard mask; removing a horizontal portion of the conformal spacer layer to form an inner spacer against the sidewalls of the opening; using the inner spacer as an etch mask to etch the second blanket dielectric layer to create an extended opening; and filling the extended opening with a heating element.

14. The method according to claim 13, further comprising forming a resist liner layer over the phase change material layer before forming the second blanket dielectric layer, such that the resist liner layer is located between the phase change material layer and the second blanket dielectric layer.

15. The method according to claim 14, further comprises: etching the second blanket dielectric layer, the resist liner layer, the phase change material layer, and the first blanket dielectric layer into a second dielectric layer, a resist liner, a phase change element, and a first dielectric layer, respectively, wherein the heating element and the inner spacer are used as etch masks in the etching; and forming a conductive liner at least vertically surrounding the resist liner and the phase change element.

16. The method according to claim 15, wherein forming the conductive liner comprises: forming a conductive liner layer that covers the heating element, the inner spacer, the second dielectric layer, the resist liner, the phase change element, the first dielectric layer, and the bottom electrode; Remove the horizontal portion of the conductive liner layer; and Remove at least a portion of the conductive liner layer covering the sidewalls of the second dielectric layer.

17. The method according to claim 16, wherein the conductive liner contacts the resistive liner, the phase change element, and the bottom electrode.

18. The method according to claim 16, wherein the inner spacer is a third dielectric layer, and the method further comprises forming a fourth dielectric layer surrounding the conductive liner, the outer sidewalls of the third dielectric layer, and at least a portion of the sidewalls of the second dielectric layer.

19. The method according to claim 13, further comprising: Forming an electrode material layer on top of the support structure; and Patterning the electrode material layer into the bottom electrode.

20. The method according to claim 13, wherein the inner spacer comprises a third dielectric material different from the second dielectric layer.

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