Improvement process for back separated silicon of epitaxial wafer
By etching and wrapping the base before epitaxial growth and optimizing the stage structure, the problem of polycrystalline silicon growing on the back of the substrate is solved, reducing the chance of back-dissecting silicon and improving chip quality.
Patent Information
- Application Number
- CN202510213475.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-03
AI Technical Summary
In the existing epitaxial growth technology, polycrystalline silicon is easily grown on the back of the substrate, resulting in uneven chip edges, affecting lithographic focus, and even causing chip scrapping.
Before epitaxial growth, the base in the furnace cavity is etched and silicon-covered, and the stage structure is optimized so that its diameter is smaller than the substrate diameter, reducing the area where the stage contacts the back of the substrate.
By absorbing self-doped impurities at the edge of the base and optimizing the stage structure, the probability of back silicon analysis is reduced, the back seal film is damaged and the probability of silicon growth is avoided, and the chip quality is improved.
Smart Images
Figure CN120082961A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of semiconductor epitaxial wafer processing, and particularly relates to an improved process for backside polysilicon of epitaxial wafers. Background Art
[0002] Backside polysilicon refers to a phenomenon where polysilicon grows at the backside of the substrate, mainly occurring in the edge region of the backside of the epitaxial wafer. There are two main ways of forming backside polysilicon: during high-temperature epitaxial growth, when there is a gap between the substrate and the wafer pit, the silicon source undergoes a reduction reaction at this position (SiHCl 3 +H 2 →Si + 3HCl); on the other hand, after the backside passivation film (silicon dioxide film) is damaged, the damaged position is in a metastable state, which is more conducive to the silicon source generating polysilicon through a reduction reaction at this position. The silicon deposited on the edge region of the backside of the silicon wafer will affect the local flatness of the edge of the silicon wafer, and in severe cases, it may even cause poor focus in the subsequent photolithography, resulting in the scrapping of local or even the entire chip. Summary of the Invention
[0003] This application provides an improved process for backside polysilicon of epitaxial wafers, solving the technical problem that polysilicon is likely to grow on the backside of the substrate during existing epitaxial growth, which seriously affects the chip quality.
[0004] To solve at least one of the above technical problems, the technical solution adopted in this application is:
[0005] An improved process for backside polysilicon of epitaxial wafers, the steps include:
[0006] Etch and siliconize the susceptor in the furnace cavity before epitaxial growth;
[0007] Remove the ungrown substrate from the carrier outside the furnace cavity and place it on the susceptor in the furnace cavity for epitaxial growth to obtain an epitaxial wafer; wherein, the diameter of the carrier is different from the diameter of the substrate;
[0008] Then take out the epitaxial wafer from the furnace cavity and return it to the carrier.
[0009] Further, when etching and siliconizing the susceptor, specifically:
[0010] Control the temperature in the furnace to rise to a preset temperature first, and introduce hydrogen until the siliconization is completed;
[0011] Control the temperature in the furnace to rise to the etching temperature;
[0012] Start introducing HCl into the furnace cavity at the etching temperature to etch the susceptor;
[0013] After etching for a certain time, lower the temperature in the furnace to the siliconization temperature;
[0014] Introduce SiHCl at the silicon coating temperature 3 to coat a layer of silicon on the surface of the susceptor.
[0015] Furthermore, it also includes that when the silicon coating is completed and the temperature of the furnace chamber is controlled to drop to 350 °C, stop introducing hydrogen, and prepare to start the epitaxial process operation; among them, the preset temperature when introducing hydrogen is 1040 °C; the etching temperature is 1120 °C, and the etching time is 300 - 1000 s.
[0016] Furthermore, when coating silicon, control the flow rate of SiHCl 3 introduced to be 10 - 20 SLM, and its reaction time is 60 - 120 s; the silicon coating thickness of the susceptor obtained is 1.5 - 7 μm.
[0017] Furthermore, when taking wafers, first use the atmospheric manipulator to take out the substrates one by one from the wafer basket in the back - side wafer - taking manner, and transfer them to the said susceptor;
[0018] Then use the vacuum manipulator to take out the substrate from the said susceptor in the front - side wafer - taking manner, and transfer it to the wafer pit in the susceptor after silicon coating;
[0019] Repeat taking wafers and transferring them into the furnace chamber until all the wafer pits in the susceptor are filled with substrates.
[0020] Furthermore, when the atmospheric manipulator places the substrate on the said susceptor, the front side of the substrate faces upward; the outer diameter of the susceptor is smaller than the diameter of the substrate, and a U - shaped notch is constructed on the side close to the atmospheric manipulator.
[0021] Furthermore, the difference between the outer diameter of the susceptor and the diameter of the substrate is at least 5 mm and at most the radius of the substrate.
[0022] Furthermore, the depth of the U - shaped notch is not less than the radius of the susceptor and less than 2 / 3 of the radius of the susceptor.
[0023] Furthermore, during epitaxial growth, control the temperature in the furnace chamber to rise to 1000 °C, and simultaneously introduce hydrogen into the furnace chamber until the epitaxial growth ends; then control the furnace temperature to rise from 1000 °C to 1500 °C; then introduce SiHCl 3 into the furnace body to grow an epitaxial film and obtain an epitaxial wafer; after the growth is completed, then control the furnace temperature to drop to 350 °C to prepare for wafer output.
[0024] Furthermore, after the growth is completed, the vacuum manipulator sucks the epitaxial wafer by negative pressure in the front - side wafer - taking manner and transfers it out of the furnace chamber, and then controls the epitaxial wafer to be reversely transferred to the same said susceptor;
[0025] Then use the atmospheric manipulator to take out the epitaxial wafer from the said susceptor in the back - side wafer - taking manner and put it back into the wafer basket;
[0026] Until all the epitaxial wafers in this batch are transferred into the wafer basket.
[0027] An improved process for backside silicon segregation of epitaxial wafers designed in this application can not only absorb the self-doped impurities at the edge of the susceptor to reduce the probability of backside silicon segregation, but also reduce the contact area between the susceptor and the backside of the substrate by optimizing the susceptor structure, avoid the damage of the backseal film caused by the contact between the susceptor and the backside of the substrate, and at the same time can also reduce the probability of silicon growth on the backside of the substrate. Brief Description of the Drawings
[0028] Figure 1 is a flowchart of the improved process for backside silicon segregation of epitaxial wafers in this application;
[0029] Figure 2 is a schematic diagram of the epitaxial wafer transfer structure in this application;
[0030] Figure 3 is a schematic diagram of the cooperation between the susceptor and the epitaxial wafer in this application;
[0031] Figure 4 is a backside photo of the epitaxial wafer obtained in Example 1;
[0032] Figure 5 is a backside photo of the epitaxial wafer obtained in Example 2;
[0033] Figure 6 is a backside photo of the epitaxial wafer obtained in Example 3;
[0034] Figure 7 is a backside photo of the epitaxial wafer obtained in Example 4;
[0035] Figure 8 is a backside photo of the epitaxial wafer obtained in Example 5;
[0036] Figure 9 is a backside photo of the epitaxial wafer obtained in Example 6.
[0037] In the figure:
[0038] 10. Atmospheric manipulator 20. Vacuum manipulator 30. Susceptor
[0039] 31. Notch 40. Substrate Detailed Description of the Embodiments
[0040] The present application will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0041] This embodiment proposes an improved process for backside silicon segregation of epitaxial wafers, as Figure 1 shown, the steps include:
[0042] S1. Before epitaxial growth, first etch and silicon coat the susceptor in the furnace chamber.
[0043] Before epitaxial growth, the susceptor in the furnace chamber is pre-coated with silicon, but before coating with silicon, the impurities on the surface of the susceptor need to be removed. Among them, the susceptor is a base placed in the furnace chamber and used to place the epitaxial wafer. It has a disc structure, and several wafer pits are provided on the susceptor, and the wafer pits are evenly arranged along the circumference of the susceptor. In this application, the silicon wafer without epitaxial growth is the substrate, and the silicon wafer with epitaxial growth is the epitaxial wafer, and they are silicon wafers of the same diameter size. Specifically,
[0044] S11. First, control the temperature in the furnace to rise to the preset temperature of 1040 °C, and simultaneously introduce hydrogen into the furnace chamber until the silicon coating is completed.
[0045] S12. Then, control the temperature in the furnace to rise from the preset temperature of 1040 °C to the etching temperature of 1120 °C.
[0046] S13. At the etching temperature of 1120 °C, start introducing HCI into the furnace chamber and etch for 300 - 1000 s to etch the susceptor, aiming to remove the impurities on the surface of the susceptor.
[0047] S14. After etching for a certain time, the etching ends, and then control the temperature in the furnace to decrease to the silicon coating temperature of 1080 °C.
[0048] S15. At the furnace temperature of 1080 °C, introduce SiHCl 3 , to coat a layer of silicon on the surface of the susceptor. Because there is both hydrogen and SiHCl 3 gas (i.e., TCS) in the furnace chamber, the chemical reaction SiHCl 3 +H 2 →Si + 3HCl can occur, so that a silicon layer can be grown on the etched susceptor.
[0049] Among them, the flow rate of the introduced SiHCl 3 is 10 - 20 SLM, and the silicon coating reaction time is 60 - 120 s; the silicon coating thickness of the susceptor obtained is 1.5 - 7 μm. The silicon coating thickness should not be too thick nor too thin. In this embodiment, the thinnest is 1.5 μm and the thickest is 7 μm. If it is too thick, it will be extremely easy to combine with the substrate during the high-temperature process, and finally become serious silicon slag, and the surface flatness of the grown epitaxial wafer is very poor and cannot be processed into chips. During the high-temperature epitaxial growth process, after silicon coating, the gap between the epitaxial wafer and the wafer pit can be reduced, and the probability of the reduction reaction of the silicon source at this gap can be reduced, and thus the risk of backside epitaxial silicon at the peripheral position on the back of the epitaxial wafer can be reduced.
[0050] This silicon encapsulation process can not only increase the resistivity at the edge of the epitaxial layer by absorbing some self-doped impurities on the pedestal, achieving the purpose of reducing the resistivity uniformity, but also improve the backside epitaxial silicon effect of the epitaxial wafer in this way.
[0051] S16. After the silicon encapsulation is completed, control the furnace chamber temperature to drop to 350 °C, stop introducing hydrogen at this time, and prepare to start the epitaxial process operation.
[0052] S2. Remove the ungrown substrate from the carrier outside the furnace chamber and place it on the pedestal inside the furnace chamber for epitaxial growth to obtain an epitaxial wafer; wherein, the diameter of the carrier is different from the diameter of the substrate.
[0053] S21. As Figure 2 shown, when taking the wafer, first use the atmospheric manipulator 10 to take out each wafer from the wafer basket (not shown in the figure) in the way of taking the wafer from the back side, and transfer it to the carrier 30.
[0054] As Figure 2 shown, when the atmospheric manipulator 10 takes the wafer from the wafer basket, it takes out the substrate 40 in the way of taking the wafer from the back side, its vacuum chuck adsorbs the back side of the substrate 40, and drives the substrate 40 to be pulled out of the wafer basket; then control the substrate 40 to be transferred to the carrier 30. The atmospheric manipulator 10 first identifies and locates the position of the carrier 30, and drives the substrate 40 to move along the Figure 2 direction shown by the red arrow in the figure towards the center of the carrier 30. After identification and positioning, slowly control the substrate 40 to drop until the substrate 40 is placed on the carrier 30, and then the atmospheric manipulator 10 withdraws from the bottom of the carrier 30 along the reverse direction of the red arrow. During the whole process of placing the substrate 40 on the carrier, the front side of the substrate 40 is always placed facing up.
[0055] As Figure 3 shown, the diameter of the carrier 30 is not the same as the diameter of the substrate 40. Preferably, the outer diameter of the carrier 30 is smaller than the diameter of the substrate 40, and the difference between the outer diameter D1 of the carrier 30 and the diameter D of the substrate 40 is at least 5 mm and at most the radius of the substrate 40, that is, 5 mm ≤ D - D1 ≤ D / 2. After the size of the carrier 30 becomes smaller, when the epitaxial wafer after epitaxial growth is transferred to the carrier, the contact area between the edge of the epitaxial wafer and the carrier 30 is reduced, thereby avoiding the direct contact between the outer edge of the back side of the epitaxial wafer and the carrier 30, reducing the risk of back seal film breakage caused by direct contact with the back edge, avoiding the metastable state at the breakage position, and reducing the probability of polycrystalline silicon generated by the reduction reaction on the back side of the epitaxial wafer, thereby reducing the occurrence of backside epitaxial silicon.
[0056] If the difference between the outer diameter D1 of the carrier 30 and the diameter D of the substrate 40 is greater than the radius of the substrate 40, it will directly affect the stability of the carrier 30 in placing and supporting the epitaxial wafer. If the contact area of the epitaxial wafer placed flat is too large, there will be a risk of the epitaxial wafer shaking. If the difference between the outer diameter D1 of the carrier 30 and the diameter D of the substrate 40 is less than 5 mm, the periphery of the epitaxial wafer will still contact the carrier 30, which will increase the risk of the back-sealing film being damaged, and further increase the probability of back-etching silicon at this position.
[0057] Further, a U-shaped notch 31 is formed on one side of the carrier 30 close to the atmospheric manipulator 10, aiming to leave a space for the atmospheric manipulator 10 to place the wafer, so as to facilitate the atmospheric manipulator 10 to place the epitaxial wafer on the carrier 30 in the way of picking up the wafer from the back. On the basis of ensuring the placement strength and stability of the carrier 30, preferably, the depth H of the U-shaped notch 31 is not less than the radius of the carrier 30 and less than 2 / 3 of the radius of the carrier 30, which can further improve the convenience of the operation of the atmospheric manipulator 10.
[0058] S22. Then, the substrate 40 is taken out from the carrier 30 by the vacuum manipulator 20 in the way of picking up the wafer from the front, and transferred to the wafer pit in the pedestal after silicon encapsulation in the furnace cavity.
[0059] The vacuum manipulator 20 is located above the substrate 40, then descends and directly contacts the front of the substrate 40. After sucking the substrate 40 by negative pressure, it can drive the substrate 40 away from the carrier 30. Then, the vacuum manipulator 30 drives the substrate 40 to move above the specified wafer pit in the furnace cavity, and finally moves to the position of the wafer pit and releases the negative pressure to put the substrate 40 into the specified wafer pit.
[0060] S23. Repeat the steps of picking up the wafer and transferring it into the furnace cavity until all the wafer pits in the pedestal are filled with the substrates 40 to be grown.
[0061] S24. During epitaxial growth, control the temperature in the furnace cavity to rise to 1000 °C, and simultaneously introduce hydrogen into the furnace cavity until the epitaxial growth is completed. Then control the furnace temperature to rise from 1000 °C to 1500 °C; when the furnace temperature is 1500 °C, introduce SiHCl 3 to grow the epitaxial film, and then the epitaxial wafer can be obtained. After the growth is completed, control the furnace temperature to drop to 350 °C, and simultaneously stop the hydrogen and SiHCl 3 gas. After cooling, the epitaxial wafer can be taken out of the furnace cavity.
[0062] S3. Then take out the epitaxial wafer from the furnace cavity and return it to the carrier.
[0063] S31. After the growth is completed, control the vacuum manipulator 20 to pick up the epitaxial wafer by negative pressure in the way of picking up the wafer from the front, then take it out of the furnace cavity, and then control the epitaxial wafer to be transferred in the reverse direction to the same carrier 30.
[0064] S32. Then, after the epitaxial wafer is taken out from the carrier 30 in a back-side wafer-taking manner by the atmospheric manipulator 10, it is put back into the wafer basket.
[0065] S33. Repeat this step until all the epitaxial wafers in this batch are transferred to the wafer basket.
[0066] To enable those skilled in the art to further understand the method of the present invention, the technical solution of the present invention will be explained in detail below in conjunction with specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.
[0067] Embodiment 1:
[0068] S1. Before epitaxial growth, the susceptor in the furnace chamber is etched and silicon-coated first.
[0069] S11. First, control the temperature in the furnace to rise to the preset temperature of 1040 °C, and simultaneously introduce hydrogen into the furnace chamber until the silicon coating is completed.
[0070] S12. Then, control the temperature in the furnace to rise from the preset temperature of 1040 °C to the etching temperature of 1120 °C.
[0071] S13. At the etching temperature of 1120 °C, start introducing HCI into the furnace chamber and etch for 300 - 1000 s to etch the susceptor.
[0072] S14. After the etching is completed, then control the temperature in the furnace to decrease to the silicon coating temperature of 1080 °C.
[0073] S15. At the furnace temperature of 1080 °C, introduce SiHCl 3 ; wherein, the flow rate of introducing SiHCl 3 is 17 SLM, and the silicon coating reaction time is 60 s, and the silicon coating thickness of the susceptor is obtained as 2.8 μm.
[0074] S16. When the silicon coating is completed, then control the temperature of the furnace chamber to decrease to 350 °C. At this time, stop introducing hydrogen and prepare to start the epitaxial process operation.
[0075] S2. Take the ungrown substrate from the carrier outside the furnace chamber and place it on the susceptor in the furnace chamber for epitaxial growth to obtain an epitaxial wafer.
[0076] S21. When taking the wafer, first take it out from the wafer basket one by one in a back-side wafer-taking manner by the atmospheric manipulator 10 and transfer it to the carrier 30. In this embodiment, the outer diameter of the carrier 30 is smaller than the outer diameter of the epitaxial wafer, and the difference is 5 mm.
[0077] S22. Then, use the vacuum manipulator 20 to pick up the substrate 40 from the carrier 30 in a face-up picking manner and transfer it to the wafer pit in the silicon-coated pedestal in the furnace chamber.
[0078] S23. Repeat the steps of picking up the wafer and transferring it into the furnace chamber until all the wafer pits in the pedestal are filled with the substrates 40 to be grown.
[0079] S24. During epitaxial growth, control the temperature in the furnace chamber to rise to 1000°C, and simultaneously introduce hydrogen into the furnace chamber until the epitaxial growth ends. Then control the furnace temperature to rise from 1000°C to 1500°C; when the furnace temperature is 1500°C, introduce SiHCl 3 to grow the epitaxial film, and then an epitaxial wafer can be obtained. After the growth is completed, control the furnace temperature to drop to 350°C, and simultaneously stop the hydrogen and SiHCl 3 gases, and prepare to pick up the wafer and take it out of the furnace.
[0080] S3. Then take out the epitaxial wafer and return it to the carrier.
[0081] S31. After the growth is completed, control the vacuum manipulator 20 to suck the epitaxial wafer by negative pressure in a face-up picking manner and transfer it out of the furnace chamber, and then control the epitaxial wafer to be transferred reversely to the same carrier 30.
[0082] S32. Then, use the atmospheric manipulator 10 to pick up the epitaxial wafer from the carrier 30 in a back-side picking manner and put it back into the wafer basket.
[0083] S33. Repeat this step until all the epitaxial wafers in this batch are transferred into the wafer basket.
[0084] After adopting the process of this embodiment, the back-side photo of the obtained epitaxial wafer is as Figure 4 shown. It can be seen from the figure that there is no back-side polysilicon phenomenon on the back side. The optimized structure of the carrier 30 not only avoids the contact between the carrier 30 and the back edge of the epitaxial wafer, but also fundamentally eliminates the problem of back-side polysilicon caused by the breakage of the back-sealing film. At the same time, before epitaxial processing, silicon coating the pedestal can also reduce the gap between the epitaxial wafer and the wafer pit, thereby further avoiding the risk of SiHCl 3 entering the gap to form back-side polysilicon.
[0085] Embodiment 2:
[0086] In this embodiment, compared with Embodiment 1, the biggest difference is that the outer diameter of the carrier 30 is the same as the diameter of the substrate 40. The back-side photo of the epitaxial wafer obtained by adopting this process is as Figure 5 shown. It can be seen from the figure that there is a back-side polysilicon phenomenon at the epitaxial part where the back side contacts the carrier, while there is no back-side polysilicon problem at other positions.
[0087] Embodiment 3:
[0088] In this embodiment, compared with the first embodiment, the biggest difference is that the flow rate of SiHCl 3 is 8 SLM, and the silicon coating reaction time is 60 s, and the silicon coating thickness of the pedestal is 1.0 um. The backside photo of the epitaxial wafer obtained by this process is as Figure 6 shown. It can be seen from the figure that there is slight backside polysilicon at a position 3 mm away from the edge on the backside. Although silicon coating before the process can make the substrate fit better with the chip pit, due to the insufficient silicon coating thickness, a part of TCS still enters through the gap during the process to form backside polysilicon.
[0089] Example 4:
[0090] In this embodiment, compared with the first embodiment, the biggest difference is that the flow rate of SiHCl 3 is 10 SLM, and the silicon coating reaction time is 60 s, and the silicon coating thickness of the pedestal is 1.5 um; and the outer diameter of the carrier 30 is equal to the outer diameter of the epitaxial wafer. The backside photo of the epitaxial wafer obtained by this process is as Figure 7 shown. It can be seen from the figure that there is backside polysilicon at the position where the backside of the epitaxial wafer contacts the carrier 30, and there is slight backside polysilicon at a position 3 mm away from its edge.
[0091] Example 5:
[0092] In this embodiment, compared with the first embodiment, the biggest difference is that only the pedestal is etched without silicon coating; and the outer diameter of the carrier 30 is equal to the outer diameter of the epitaxial wafer. The backside photo of the epitaxial wafer obtained by this process is as Figure 8 shown. It can be seen from the figure that there is backside polysilicon at the position where the backside of the epitaxial wafer contacts the carrier 30, and there is serious backside polysilicon at a position 3 mm away from its edge. It is clearly shown that whether there is silicon coating and the relationship between the carrier diameter and the epitaxial wafer diameter directly affect the generation of backside polysilicon of the epitaxial wafer.
[0093] Example 6:
[0094] In this embodiment, compared with the first embodiment, the biggest difference is that TCS is introduced, the flow rate is 25 SLM, and the time is 120 s, and the silicon coating thickness of the pedestal is 9 um. In this embodiment, although its silicon coating time is within the standard range, its flow rate exceeds the standard range, resulting in a relatively thick silicon coating thickness, exceeding the standard range. Furthermore, the backside photo of the epitaxial wafer obtained by this process is as Figure 9 shown. It can be seen from the figure that there is serious silicon slag on the backside of the epitaxial wafer. This is because too much silicon pre-grown on the pedestal combines with the substrate during the high-temperature process and finally becomes serious silicon slag. The surface flatness of the grown epitaxial wafer is very poor and cannot be processed for wafer flow.
[0095] As can be seen from the above analysis, only by etching and silicon coating the pedestal before epitaxial growth, and when silicon coating, the flow rate of SiHCl 3 introduced into the furnace chamber is 10 - 20 SLM, and the silicon coating reaction time is 60 - 120 s, can a silicon coating thickness of 1.5 - 7 μm on the pedestal be obtained. At the same time, it is also necessary to make the outer diameter of the carrier 30 smaller than the diameter of the substrate 40, and the difference between the outer diameter D1 of the carrier 30 and the diameter D of the substrate 40 is at least 5 mm and at most the radius of the substrate 40, that is, 5 mm ≤ D - D1 ≤ D / 2. Not only is the contact area between the edge of the epitaxial wafer and the carrier 30 reduced, thus avoiding the direct contact between the outer edge of the back of the epitaxial wafer and the carrier 30, thereby reducing the risk of back-seal film breakage caused by direct contact with the back edge, and then also avoiding the metastable state at the breakage position, and reducing the probability of polysilicon generated by the reduction reaction on the back of the epitaxial wafer, thus reducing the occurrence of back-segregated silicon. Moreover, the gap between the edge of the epitaxial wafer and the pedestal can be reduced by silicon coating, reducing the probability of the reduction reaction of the silicon source at this gap, that is, reducing the risk of back-segregated silicon at the peripheral position of the back of the epitaxial wafer, thereby improving the problem of back-segregated silicon of the epitaxial wafer.
[0096] Adopting an improved process for back-segregated silicon of an epitaxial wafer designed by the present application can not only absorb self-doped impurities at the edge of the pedestal to reduce the probability of back-segregated silicon, but also reduce the contact area between the carrier and the back of the substrate by optimizing the carrier structure, avoid the breakage of the back-seal film caused by the contact between the carrier and the back of the substrate, and at the same time can also reduce the probability of silicon growth on the back of the substrate.
[0097] The above has described the embodiments of the present application in detail. The above content is only the preferred embodiments of the present application and cannot be considered as limiting the scope of implementation of the present application. All equivalent changes and improvements made according to the scope of the present application should still fall within the scope covered by the patent of the present application.
Claims
1. An improved process for epitaxial wafer back-extraction of silicon, characterized in that the steps include: Before epitaxial growth, the base in the furnace chamber is etched and coated with silicon; Removing the ungrown substrate from the carrier outside the furnace chamber and placing it on the susceptor inside the furnace chamber for epitaxial growth to obtain an epitaxial wafer; wherein the diameter of the carrier is different from the diameter of the substrate; Then the epitaxial wafer is taken out from the furnace chamber and returned to the carrier.
2. The process for improving silicon backscattering of epitaxial wafer according to claim 1, characterized in that: When etching and siliconizing the base, specifically: The temperature in the furnace is controlled to rise to the preset temperature, and hydrogen is introduced until the silicon coating is completed; Control the temperature in the furnace to rise to the etching temperature; Start to introduce HCI into the furnace chamber at the etching temperature to etch the base; After etching for a certain period of time, lower the temperature in the furnace to the silicon package temperature; SiHCI3 is introduced at the silicon coating temperature to coat a layer of silicon on the surface of the base.
3. The process for improving the back-sampling of silicon on an epitaxial wafer according to claim 2, characterized in that: It also includes controlling the furnace chamber temperature to drop to 350°C after silicon coating is completed, stopping the introduction of hydrogen, and preparing to start the epitaxial process operation; wherein, the preset temperature when introducing hydrogen is 1040°C; the etching temperature is 1120°C, and the etching time is 300-1000s.
4. The process for improving silicon backscattering of epitaxial wafer according to claim 3, characterized in that: When coating silicon, the flow rate of SiHCI3 is controlled to be 10-20SLM, and the reaction time is 60-120s; the thickness of the silicon coating on the base is obtained to be 1.5-7um.
5. The process for improving silicon back-extraction of epitaxial wafer according to any one of claims 1 to 4, characterized in that: When taking out the film, the atmospheric manipulator first takes out the substrate from the film basket piece by piece in a back-side taking manner, and transfers it to the carrier; Then, the substrate is taken out from the carrier by a vacuum robot in a front-side wafer taking manner, and is transferred to a wafer pit in the base after silicon coating; The wafers are repeatedly taken out and transferred to the furnace chamber until all the wafer pits in the base are covered with substrates.
6. The process for improving back-segmentation of silicon on an epitaxial wafer according to claim 5, characterized in that: When the atmospheric manipulator places the substrate on the carrier, the front side of the substrate faces upwards; the outer diameter of the carrier is smaller than the diameter of the substrate, and a U-shaped notch is constructed on the side close to the atmospheric manipulator.
7. The process for improving back-segmentation of silicon on an epitaxial wafer according to claim 6, characterized in that: The difference between the outer diameter of the carrier and the diameter of the substrate is 5 mm at minimum and the radius of the substrate at maximum.
8. The process for improving back-segmentation of silicon on an epitaxial wafer according to claim 6, characterized in that: The depth of the U-shaped notch is not less than the radius of the carrier and is less than 2 / 3 of the radius of the carrier.
9. The process for improving silicon back-extraction of epitaxial wafer according to any one of claims 6 to 8, characterized in that: During epitaxial growth, the temperature in the furnace chamber is controlled to rise to 1000°C, and hydrogen is simultaneously introduced into the furnace chamber until the epitaxial growth is completed; the furnace temperature is then controlled to rise from 1000°C to 1500°C; SiHCI3 is then introduced into the furnace body to grow an epitaxial film to obtain an epitaxial wafer; after the growth is completed, the furnace temperature is controlled to drop to 350°C to prepare for wafer output.
10. The process for improving back-segmentation of silicon on epitaxial wafers according to claim 9, characterized in that: After the growth is completed, the vacuum manipulator sucks the epitaxial wafer by negative pressure in a front-side wafer taking manner and then moves it out of the furnace chamber, and then controls the epitaxial wafer to be transferred in the reverse direction to the same carrier; Then, the atmospheric manipulator takes out the epitaxial wafer from the carrier in a back-side wafer taking manner and puts it back into the wafer basket; Until all epitaxial wafers of the batch are transferred to the wafer basket.