Optical engine based on 3D packaging and packaging method

Abstract

The invention provides an optical engine based on 3D packaging and a packaging method. The optical engine comprises an optical chip, an electric chip, an optical fiber module and a heat dissipation substrate. The heat dissipation substrate comprises a main body part and a sunken part extending out of the side face, provided with the optical port, of the optical chip; the optical chip comprises a first surface and a second surface, the first surface of the optical chip is connected with the second surface of the electric chip, the second surface of the optical chip is adhered to the main body part of the heat dissipation substrate, and the bottom of the optical fiber module is adhered to the concave part of the heat dissipation substrate. The electric chip is placed on the high-frequency substrate material, and the expansion coefficient of the substrate material is similar to that of the chip, so that the reliability of the chip after bonding can be ensured; the PIC and the FA are packaged in a coplanar manner by using the external heat dissipation substrate at the top, and a plurality of bonding surfaces are provided for the FA, so that the difficulty that the relative positions of the PIC and the FA are not matched due to thermal stress is solved.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic transmission technologies, and particularly to an optical engine based on 3D packaging and a packaging method. Background Art

[0002] Currently, Artificial Intelligence (AI) has become the focus of social attention. AI has not only attracted the attention of the technology community but also caught the attention of the whole society. Due to reasons such as more and more participants in AI, more and more complex models, and more and more parameters, the market's demand for AI computing clusters is getting higher and higher. Since a Graphics Processing Unit (GPU) can achieve large-scale parallel computing, a GPU server can achieve large-scale all-round interconnection through the interconnection of the front-end network, the interconnection of the back-end Scaleout network, and the interconnection of the back-end Scaleup network, etc., to obtain a GPU-based AI computing cluster.

[0003] Whether inside the servers of an intelligent computing center or inside a data center for data exchange, higher requirements are put forward for the hardware bandwidth density and power consumption density that support computing power. This has promoted the key interconnection device as a relay transmission - the optical engine - to continuously evolve towards technical standards of low loss and high bandwidth. The CPO technology has natural technical advantages in aspects such as inter-chip interconnection in HPC and high-density optical fan-out inside switches due to its performance characteristics of small size, high bandwidth density, and low insertion loss.

[0004] The optical module disclosed in the publication number CN218767433U includes a circuit board, an electrical chip, and an optical chip. The electrical chip is stacked on the surface of the circuit board through the first solder balls. The electrical chip includes a first front surface and a first back surface, and a plurality of through-conductive vias are provided thereon. One side of the conductive via is connected to the first solder ball; signal lines are provided on the first front surface, and one side of the signal line is connected to the other side of the conductive via; the optical chip includes a second front surface and a second back surface, and the second front surface is stacked on the electrical chip through the second solder balls, and the second solder balls are connected to the other side of the signal line. In this application, the electrical chip is used as an interposer, and the optical chip is mounted on the electrical chip. Using the mature TSV process of the electrical chip, high-frequency signal transmission between the optical chip, the electrical chip, and the circuit board is achieved with the shortest path, ensuring the integrity of high-frequency signals to the greatest extent; the wire bonding process is completely eliminated, improving the connection port density between the optoelectronic chips and the circuit board, and achieving a high-density layout of the circuit board to the greatest extent. In this optical module, the electrical chip is placed on the PCB circuit board. The thermal expansion coefficient of the PCB is very different from the Si material of the EIC. Direct mounting will cause the EIC to split. There is also bump material between the EIC and the PIC. Coupled with the change in the thermal expansion coefficient of the PCB, the FA light source cannot maintain a constant relative position with the PIC optical port, and it is almost impossible to achieve optical coupling. Summary of the Invention

[0005] The purpose of the present application is to provide an optical engine based on 3D packaging and a packaging method, so as to solve the problem of misalignment between the FA module and the PIC optical port in the prior art.

[0006] In the first aspect, an optical engine based on 3D packaging is provided, including: an optical chip, an electrical chip, an optical fiber module, and a heat dissipation substrate; an optical port is arranged on the side of the optical chip for emitting and receiving optical signals externally; the electrical chip is used to drive the optical chip and modulate the electrical signals output by the optical chip, and it includes a first surface and a second surface, and connection layers are arranged on both the first surface and the second surface respectively for realizing the mechanical and electrical connections between the electrical chip and the high-frequency substrate, and between the electrical chip and the optical chip; the heat dissipation substrate includes a main body part and a recessed part extending out of the side of the optical chip where the optical port is arranged; the optical chip includes a first surface and a second surface, the first surface of the optical chip is connected to the second surface of the electrical chip, the second surface of the optical chip is bonded to the main body part of the heat dissipation substrate, and the bottom of the optical fiber module is bonded to the recessed part of the heat dissipation substrate.

[0007] In an optional implementation manner, one end of the main body part of the heat dissipation substrate extends out of the side of the optical chip where the optical port is arranged, and one side of the optical fiber module is bonded to this end.

[0008] In an optional implementation manner, one side of the optical fiber module is bonded to the side of the optical chip where the optical port is arranged.

[0009] In an optional implementation manner, the connection layer is a under-bump metallization layer, through-silicon vias and a redistribution layer are arranged inside the electrical chip, and the optical chip, the electrical chip and the high-frequency substrate are electrically connected through the under-bump metallization layer, the through-silicon vias and the redistribution layer.

[0010] In an optional implementation manner, the optical fiber module and the optical port are sealed with an optical matching adhesive.

[0011] In an optional implementation manner, the gap between the electrical chip and the optical chip is filled with a first layer of underfill, and the gap between the electrical chip and the high-frequency substrate and the periphery of the electrical chip are filled with a second layer of underfill.

[0012] In an optional implementation manner, the vertical projection of the optical port on the high-frequency substrate falls outside the vertical projection range of the electrical chip on the high-frequency substrate.

[0013] In an optional implementation manner, the material of the heat dissipation substrate is tungsten copper.

[0014] In the second aspect, an optical engine packaging method is provided, where the optical engine is the optical engine based on 3D packaging described in the first aspect, and the method includes:

[0015] Step 1: Evaporate an electroplating seed layer on the second side of the electrical chip;

[0016] Step 2: Apply photoresist based on the electroplating seed layer, and etch an electroplating window at the position corresponding to the under-bump metallization layer on the second side of the electrical chip through photolithography and developing processes;

[0017] Step 3: Based on the electroplating window, fabricate micro-bumps and low-temperature solder for support and electrical interconnection, and remove the excess photoresist and electroplating seed layer;

[0018] Step 4: Flip the electrical chip, and weld the micro-bumps of the electrical chip to the under-bump metallization pads of the optical chip through low-temperature solder by means of a thermal reflow process;

[0019] Step 5: Use the underfill process to fill the gap between the optical chip and the electrical chip with underfill adhesive;

[0020] Step 6: Paste the optical chip onto the main body of the heat dissipation substrate;

[0021] Step 7: Align and couple the optical port of the fiber optic module with the optical chip, bond the fiber optic module to the recessed part of the heat dissipation substrate, fill an optical matching adhesive between the fiber optic module and the optical port of the optical chip, and complete UV curing.

[0022] In an optional implementation manner, Step 3 further includes:

[0023] Based on the electroplating window, electroplate copper and low-temperature solder metal in sequence to form the Cu pillar and low-temperature solder of the micro-bump;

[0024] Strip the photoresist on the second side of the optoelectronic chip through a de-glue process;

[0025] Perform dry etching to remove the electroplating seed layer around the micro-bump;

[0026] Perform high-temperature reflow to form a hemispherical low-temperature solder cap on the top of the copper bump.

[0027] In an optional implementation manner, after Step 7 is completed, flip the bonded optical engine, establish a C4 bump structure between the high-frequency substrate and the first side of the electrical chip to achieve electrical interconnection and mechanical connection, and then fill the gap between the electrical chip and the high-frequency substrate and the periphery of the electrical chip with underfill adhesive.

[0028] The beneficial effects of the present application are as follows: The electrical chip is placed on a high-frequency substrate material, and the expansion coefficient of the substrate material is similar to that of the chip, which can ensure the reliability of the chip after bonding. First, the EIC is pasted onto the PIC wafer, and after the underfill process is completed, then the wafer is diced. The underfill ensures the bonding strength of the PIC-EIC module for the next soldering, and at the same time, the packaging efficiency at the wafer level is much higher than the SMT efficiency of a single DiE. By using an externally added heat dissipation substrate on the top to achieve coplanar packaging of the PIC and the FA, the problem of the relative position mismatch due to thermal stress between the PIC and the FA is solved. Advanced packaging processes such as molding and underfill are likely to contaminate the optical port. The PIC and the FA are assembled in the last process. The PIC does not participate in the advanced packaging process, and the PIC optical port is always in a non-contact state, avoiding the contamination of the optical port by processes such as molding and underfill. The temperature of the bump soldering usually exceeds 180°C. In order to avoid the optical glue being exposed to this temperature for a long time, the optical glue bonding between the FA and the PIC is completed in the last process. After the optical engine is prepared, the optical glue only undergoes one reflow soldering at a temperature exceeding 180°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0030] Figure 1 It is a schematic diagram of the COB packaging of the internal optical engine of the traditional optical module in the embodiment of the present application;

[0031] Figure 2 It is a schematic diagram of the CPO packaging of the internal optical engine of the traditional optical module in the embodiment of the present application;

[0032] Figure 3 It is a schematic diagram of the process of step one in the optical engine packaging method in the embodiment of the present application;

[0033] Figure 4 It is a schematic diagram of the process of step two in the optical engine packaging method in the embodiment of the present application;

[0034] Figure 5 It is a schematic diagram of the process of step three in the optical engine packaging method in the embodiment of the present application;

[0035] Figure 6 It is a schematic diagram of the process of step four in the optical engine packaging method in the embodiment of the present application;

[0036] Figure 7 It is a process schematic diagram of Step Five in the optical engine encapsulation method in the embodiment of the present application;

[0037] Figure 8 It is a process schematic diagram of Step Six in the optical engine encapsulation method in the embodiment of the present application;

[0038] Figure 9 It is a process schematic diagram of Step Seven in the optical engine encapsulation method in the embodiment of the present application;

[0039] Figure 10 It is a process schematic diagram of Step Eight in the optical engine encapsulation method in the embodiment of the present application;

[0040] Figure 11 It is a structural schematic diagram of the optical engine based on 3D packaging in the embodiment of the present application.

[0041] As shown in the figure, 1, optical chip; 2, electrical chip; 3, optical fiber module; 4, heat dissipation substrate; 5, high-frequency substrate; 100, edge coupler; 10, electroplating seed layer; 11, electroplating window; 13, low-temperature solder metal; 131, copper; 14, underfill; 15, glue layer; 16, optical matching glue; 17, C4 bump; 18, through-silicon via; 19, connection layer; 22, redistribution layer; 21, micro bump; 23, mask via. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application. Unless otherwise defined, the technical terms or scientific terms used in the present application shall have the ordinary meaning understood by those of ordinary skill in the art in the field to which the present invention belongs. The "first", "second" and similar terms used in the present application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0043] For better understanding by those skilled in the art, the following is a brief introduction to the technical terms involved in this application.

[0044] Optical Engine, a module integrating optical elements and electronic devices, is used to generate, modulate, transmit or detect optical signals. An optical engine usually integrates optoelectronic devices such as lasers, modulators, and detectors, and works in coordination with an electronic drive circuit to achieve high-speed and efficient generation, modulation, and reception of optical signals.

[0045] The gold finger of an optical module is a conductive contact piece on the optical module (such as SFP, QSFP, etc.) that connects to the device slot, and it is a component for realizing electrical signal transmission and power supply between the optical module and the host device (such as a switch, router). It mainly consists of contact pieces, an insulating substrate, and a dust cover (optional). The contact pieces are neatly arranged metal pins (usually made of copper substrate), with a gold plating on the surface (thickness 0.5 - 1.5μm), and the length matches the insertion and extraction stroke of the optical module. The insulating substrate is FR4 or a flexible printed circuit board (FPC), which fixes the contact pieces and isolates the signal channels.

[0046] COB (Chip on Board) is a packaging technology that directly mounts a bare die on a substrate (such as a PCB, ceramic substrate, or metal substrate), realizes electrical connection through wire bonding or flip-chip, and encapsulates and protects the chip with epoxy resin or silicone. It eliminates the housing of traditional packaging (such as QFN, BGA) to achieve high-density and low-cost integration. The process flow of COB includes:

[0047] Substrate preparation: The substrate material uses FR4 PCB, ceramic (AlO / AlN), or a metal substrate (such as copper or aluminum). The surface is treated with gold plating / silver plating to improve conductivity and corrosion resistance.

[0048] Chip bonding (Die Attach): Use conductive adhesive (silver paste) or solder (SAC305) to fix the bare die on the substrate. Precision requirement: position deviation ≤ ±25μm. Electrical connection: Wire bonding uses gold wire / copper wire bonding (WireBonding) to connect the chip pads and the substrate solder joints. Direct flip-chip soldering through micro-bumps (applicable to high-frequency scenarios).

[0049] Encapsulation and protection: Coat with epoxy resin or silicone to protect the chip and leads from the environment (moisture, dust). Thermal curing or UV curing to form a dense protective layer.

[0050] Testing and sorting: Electrical performance testing (such as optical power, impedance), aging testing (high temperature and high humidity).

[0051] CPO integrates the optical signal processing unit (laser, modulator, detector, etc.) and the electrical signal processing chip (such as ASIC) through advanced packaging technology (such as silicon interposer), shortens the optical-electrical interconnection distance (from centimeter level to millimeter level), and realizes optoelectronic co-packaging.

[0052] Photonic Integrated Circuit (abbreviated as PIC) is a technology that integrates multiple optical components (such as lasers, modulators, waveguides, detectors, etc.) on a single chip. The basic components include: optical waveguide: transmits optical signals (such as silicon-based waveguide, silicon nitride waveguide); laser: generates light of a specific wavelength (such as DFB laser, external modulation laser EML); modulator: controls the optical signal with an electrical signal (such as Mach-Zehnder modulator, microring resonator); detector: converts the optical signal into an electrical signal (such as GeSi APD, PIN photodiode); coupler: optical signal input / output interface (such as grating coupler, edge coupler).

[0053] Electronics Integrated Circuit (abbreviated as EIC) is a circuit that integrates electronic components such as transistors, resistors, and capacitors on a single chip through semiconductor processes, focusing on the generation, processing, and transmission of electrical signals. In an optical module, EIC and PIC achieve complementary functions through optoelectronic co-design and jointly complete the efficient conversion and processing of optical-electrical signals. The main devices of the EIC in the embodiments of this application are driver amplifiers, transimpedance amplifiers (TIA), and application-specific integrated circuits. The driver amplifier provides a driving signal for the electro-optical modulator in the optical chip, and the transimpedance amplifier amplifies the electrical signal generated by the photodetector in the optical chip. The application-specific integrated circuit is a specially designed integrated circuit used to optimize and control the performance of the amplifier.

[0054] Chiplet splits the functions of a traditional single chip (Monolithic) into multiple small chips (such as CPU cores, I / O, memory controllers, etc.) and interconnects them through packaging. It has a wide range of applications in high-performance computing, AI, and optoelectronics.

[0055] High-frequency substrate: In the embodiments of this application, the high-frequency substrate is a component that supports the ultra-high bandwidth, low latency, and stable signal transmission of the GPU. It is a dedicated circuit board designed to support the ultra-high bandwidth and high-speed signal transmission requirements of the graphics processor. It uses advanced materials with low dielectric constant (Dk < 3.5) and low loss factor (Df < 0.005) (such as Rogers RO4000 series or Panasonic MEGTRON7), and through a multi-layer stacked structure and precise impedance control (such as 100Ω differential pair), it realizes low-latency (<0.2dB / inch loss) and high-stability signal transmission between the GPU core, HBM memory, and PCIe interface; at the same time, combined with 2.5D / 3D packaging technology (such as silicon interposer, TSV vertical interconnection) and embedded heat dissipation solutions (microchannels or thermal conductive fillers), it meets the bandwidth density (>5Tbps / cm 2 ) and thermal management requirements in high-computing scenarios such as AI training and real-time rendering within a limited space, becoming the core hardware carrier for the GPU to break through the "memory wall" and "power consumption wall". It includes a multi-layer stacked structure:

[0056] Signal layer: High-frequency material (Rogers RO4350B) optimizes high-speed signal transmission.

[0057] Power supply layer: Low-impedance copper layer (thickness ≥ 2oz) provides stable power supply.

[0058] Ground layer: Continuous copper foil reduces electromagnetic interference (EMI).

[0059] After introducing the technical terms involved in this application, the design concept of this application will be briefly introduced next.

[0060] The internal optical engine of the traditional optical module based on the switch architecture is packaged in the COB packaging method. As Figure 1 shown, that is, through surface mounting and wire bonding, gold wires or aluminum wires are used to achieve electrical interconnection between the drive chip - optical chip and the electrical chip - gold finger. According to the current common QSFP and OSFP packaging standards, the width of the internal PCB is approximately between 17 - 19mm. As the module rate increases, the packaging space of the internal optoelectronic chips has become very crowded, and at the same time, wire bonding will also occupy a large layout area, resulting in the design complexity of chip mounting and internal PCB routing.

[0061] Existing CPO optical-electrical co-packaging solutions such as Figure 2As shown, the electrical chip is located above the optical chip and is interconnected through microbumps 21, a redistribution layer 22, and a mask via 23. The optical chip is interconnected with the substrate through C4 bumps 17. The optical fiber module 3 is arranged at the optical port of the PIC. The pluggable connection method between the PCB gold finger and the switch side is cancelled, and the optical engine and the ASIC chip are co-packaged onto the same substrate to achieve the purpose of increasing the bandwidth and reducing the loss on the electrical I / O side. However, advanced co-packaged optics technology faces problems such as PIC optical port protection, lack of effective heat dissipation paths, and package warping in the specific wafer packaging process. At the same time, with the further increase in the single-channel rate of the optical engine (>200 Gbps / channel), different from the optical engine design of 100 Gbps per channel, the high-frequency and low-loss link requirements also pose new challenges in terms of the wiring distance of chiplets and the electrical characteristics of dielectric materials. The chiplet co-packaging process of the CPO optical engine also faces problems such as the high-temperature tolerance of optical glue, PIC optical port protection, and difficulty in shipping in a complete package.

[0062] The optical engine of the traditional COB packaging solution faces the situation of low integration and high electrical link loss; for advanced packaging CPO at the wafer level, whether using the chip-last (first package the electronic chip and then integrate the photonic chip) or chip-first (first integrate the photonic chip and then package the electronic chip) process, the Molding compound in the Molding process (a key technology that injects packaging materials to protect the chip, enhance mechanical strength, and achieve electrical insulation. The mold presses the liquid or solid packaging material, such as epoxy resin, into shape to cover structures such as chips and wires, forming a protective layer and fixing the device form) will contact the side wall of the optical I / O port of the PIC, causing optical port occlusion and device failure; at the same time, since the electrical chip is also co-packaged within the Molding Compound, the thermal conductivity of Molding is low, and the electrical chip lacks an effective heat dissipation path; the underfill process restricts the chiplet assembly scheme, making its chip mounting sequence usually from bottom to top, limiting the shipping of the optical engine in a complete package; the glue used for optical coupling is usually an epoxy resin material, and its TG (glass transition temperature) is usually lower than 120°C. The multiple thermal reflow processes (flip-chip thermal reflow temperature > 280°C) during the CPO packaging process will increase the reliability risk of the optical coupling glue.

[0063] Therefore, the embodiments of the present application provide a new co-packaged optics component and the corresponding process flow, set a vertical heat dissipation path for the electrical chip, and solve the chip mounting limitation that the CPO optical engine can only be from bottom to top through double-layer underfill, enabling the co-packaging and shipping of EIC and PIC; at the same time, solve the problem of the chip mounting support strength during the FC process.

[0064] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only for the purpose of illustrating and explaining the present application, and are not used to limit the present application. And without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0065] Figure 11 A 3D-packaging-based optical engine provided by an embodiment of the present application includes an optical chip 1, an electrical chip 2, an optical fiber module 3, and a heat dissipation substrate 4. The optical port of the optical chip is a physical interface on the optical chip for inputting or outputting optical signals, and is responsible for connecting the internal optical waveguide of the chip to external optical devices. In this embodiment, the optical port can be implemented by providing an edge coupler 100 on the side of the optical chip. The edge coupler 100 is the core structure for efficiently coupling external optical signals (such as fiber input) into the internal optical waveguide of the chip. The mode field diameter (MFD, about 9-10 μm) of the external optical fiber is much larger than that of the PIC waveguide (sub-micron level). It is necessary to achieve mode field conversion through the edge coupler to reduce the mode mismatch loss. The edge coupler relaxes the requirements for the lateral / longitudinal alignment accuracy of the optical fiber and the PIC (such as ±1 μm vs. ±0.1 μm for direct coupling), reduces the packaging difficulty, and supports a wide wavelength range (such as the C band of 1530-1565 nm) and polarization-insensitive design. The optical chip is directly connected to the optical fiber through the edge coupler. The edge coupler is usually designed as an inverse taper or a grating coupler. The optical fiber is fixed on the chip edge through a V-groove or a silicon-based precision structure and aligned with the edge coupler.

[0066] The electrical chip 2 is used to drive the optical chip and modulate the electrical signals output by the optical chip. It includes a first surface and a second surface, and connection layers 19 are provided on both the first surface and the second surface, respectively for realizing the mechanical and electrical connections between the electrical chip and the high-frequency substrate, and between the electrical chip and the optical chip. The connection layer 19 is an Under Bump Metallization (UBM). Through-silicon vias 18 and redistribution layers 22 are provided inside the electrical chip. The optical chip, the electrical chip, and the high-frequency substrate 5 are electrically connected through the under-bump metallization layer, through-silicon vias, and redistribution layers. The under-bump metallization layer is a key structure in advanced packaging technology, located between the chip pad and the solder bump (such as solder ball, copper pillar), and plays a core role in electrical connection, mechanical support, and interface protection. The core functions of UBM include electrical interconnection (serving as a conductive bridge between the pad and the bump to ensure low-resistance electrical connection), adhesion enhancement (providing high-strength adhesion to the chip surface metal and bump material to prevent peeling), diffusion barrier (blocking the diffusion of bump material to the chip pad to avoid brittle failure caused by excessive growth of intermetallic compounds), anti-oxidation / corrosion (protecting the pad from environmental moisture, oxidation, and electrochemical corrosion), and stress buffering (relieving mechanical stress caused by the mismatch of thermal expansion coefficients and improving fatigue life). The through-silicon via (TSV) vertically penetrates the silicon substrate inside the electrical chip to achieve high-density interconnection between multiple layers or between the chip and the substrate. The redistribution layer (RDL) relocates the pads at the edge of the electrical chip to any position required for packaging (such as the chip center or array arrangement), improving design flexibility, achieving high-density connection through micron-scale wires (line width / spacing can reach 2μm / 2μm), enabling multi-chip integration, designing differential pairs, shielding layers, and impedance matching structures, reducing crosstalk and loss of high-speed signals (such as 112Gbps PAM4), optimizing the signal path, and connecting TSV and UBM. The RDL usually consists of alternating stacked metal wire layers and dielectric layers, and also includes vias and passivation layers. The metal layer includes electroplated copper (Cu) wires with a thickness of 1 - 5μm and a line width of 2 - 10μm; the dielectric layer is a polymer (such as polyimide PI, benzocyclobutene BCB) or an inorganic material (SiO) with a thickness of 5 - 20μm; the via connects the copper pillars of different metal layers with a diameter of 5 - 20μm; the passivation layer is silicon nitride (SiN) or oxide (SiO) to protect the wires from environmental erosion.

[0067] The optical chip 1 includes a first surface and a second surface, and the first surface of the optical chip is connected to the second surface of the electrical chip. Regarding the implementation method of the connection between the optical chip and the electrical chip, it has been introduced in detail above and is realized through the under-bump metallization layer, through-silicon vias, and redistribution layers, and will not be elaborated here.

[0068] The heat dissipation substrate 4 is made of tungsten copper. The length of the heat dissipation substrate in the direction perpendicular to the high-frequency substrate is greater than the size of the optical chip, and the vertical projection of the optical port on the high-frequency substrate falls outside the vertical projection range of the electrical chip on the high-frequency substrate. Making the vertical projection of the optical port on the high-frequency substrate fall outside the vertical projection range of the electrical chip on the high-frequency substrate can avoid the influence of the glue during the underfill process of the electrical chip on the optical port. The heat dissipation substrate 4 is in a stepped shape and includes two parts, namely a main body part 41 and a recessed part 42 extending out of the side of the optical chip where the optical port is provided. The second surface of the optical chip is bonded to the main body part 41 of the heat dissipation substrate, and the bottom of the optical fiber module is bonded to the recessed part 42 of the heat dissipation substrate. In an embodiment of the present application, one end of the main body part of the heat dissipation substrate extends out of the side of the optical chip where the optical port is provided, and one side of the optical fiber module is bonded to this end. In this way, the heat dissipation substrate can provide two bonding surfaces in two vertical directions for the optical module, ensuring the bonding strength of the optical fiber module (FA). In another embodiment of the present application. One side of the optical fiber module is bonded to the side of the optical chip where the optical port is provided. Here, by using the PIC side and the recessed part of the heat dissipation substrate, two bonding surfaces can also be provided for the optical fiber module, ensuring the bonding strength of the optical fiber module (FA). The optical fiber module and the optical port are sealed with an optical matching glue.

[0069] The gap between the electrical chip and the optical chip is filled with the first layer of underfill 14, and the gap between the electrical chip and the high-frequency substrate and the periphery of the electrical chip are filled with the second layer of underfill 14. The high-frequency substrate and the electrical chip have the same coefficient of thermal expansion. If the CTE difference between the substrate and the chip is large (such as silicon CTE≈2.6 ppm / °C vs, FR-4 substrate≈15 ppm / °C), temperature changes will cause interfacial stress, leading to solder joint cracking, delamination or chip warping. The expansion coefficient of the high-frequency substrate material is similar to that of the chip, which can ensure the reliability of the chip after bonding.

[0070] In the traditional case, the electrical chip is placed on the PCB board, and there is also bump material between the EIC-PIC. Coupled with the change in the coefficient of thermal expansion of the PCB, the FA light source cannot maintain a constant relative position with the PIC optical port, and it is almost impossible to achieve optical coupling. In the embodiments of the present application, by using an additional heat dissipation substrate on the top, the PIC and the FA are coplanarly packaged, and multiple bonding surfaces are provided for the FA, solving the difficulty of the relative position mismatch between the PIC and the FA due to thermal stress.

[0071] Based on the same inventive concept, the present application also provides an optical engine packaging method. The optical engine is the above-mentioned optical engine based on 3D packaging. The packaging method includes the following steps:

[0072] Step 1, as Figure 3 shown, an electroplating seed layer 10 is deposited on the second surface of the electrical chip. The electroplating seed layer is a key metal layer that provides a conductive substrate for subsequent electroplating processes. The functions of the electroplating seed layer are as follows:

[0073] Conductive substrate: Provides a continuous conductive path for electroplated metals (such as copper and gold) to ensure electroplating uniformity. Adhesion enhancement: Enhances the bonding force between the metal and the substrate (silicon, oxide) through an intermediate layer (such as Ti, Cr). Diffusion barrier: Prevents the electroplated metal (such as Cu) from diffusing into the chip interior (commonly using TaN, TiN barrier layers). Surface planarization: Fills the microscopic unevenness of the substrate to reduce electroplating defects (such as voids, dendrites).

[0074] Step two, as Figure 4 shown, apply photoresist based on the electroplating seed layer, and etch an electroplating window 12 through photolithography and development processes at the position corresponding to the second side of the electrochip and the under-bump metallization layer;

[0075] Step three, as Figure 5 shown, based on the electroplating window, electroplate copper 131 and low-temperature solder metal 13 on the EIC in sequence to form the Cu pillar and low-temperature solder of the micro bump. The micro bump is used for support and electrical interconnection, and remove the excess photoresist and electroplating seed layer; Strip the photoresist on the second side of the optoelectronic chip through the degluing process; Perform dry etching to remove the electroplating seed layer around the micro bump, and form a hemispherical low-temperature solder cap on the top of the copper bump through high-temperature reflow.

[0076] Step four, as Figure 6 shown, flip the electrochip, and weld the micro bump of the electrochip and the under-bump metallization pad of the optical chip through the low-temperature solder by the thermal reflow process;

[0077] Step five, as Figure 7 shown, flip the welded electrochip and optical chip, and fill the gap between the optical chip and the electrochip with underfill glue 14 using the underfill process; The underfill process is a key step in semiconductor packaging, mainly used in flip-chip technology. It enhances the structural reliability by filling the bottom material. Alleviates the mechanical stress caused by the difference in the coefficient of thermal expansion (CTE) between the chip and the substrate; Prevents the solder bump from cracking during temperature cycling or vibration and protects the solder joints; Seals the voids to prevent moisture or contaminants from invading. Inject under pressure through a precision dispensing device and cure thermally (such as 150 °C, 30 minutes) or by ultraviolet (UV) curing to harden the colloid.

[0078] Step six, as Figure 8 shown, paste the optical chip on the main body of the heat dissipation substrate through the glue layer 15;

[0079] Step seven, as Figure 9As shown, the optical fiber module is coupled and aligned with the optical port of the optical chip, and the optical fiber module is bonded to the recessed portion of the heat dissipation substrate. An optical matching adhesive 16 is filled between the optical fiber module and the optical port of the optical chip and UV curing is completed.

[0080] Step eight, as Figure 10 shown, flip the bonded optical engine, establish a C4 bump structure between the high-frequency substrate and the first surface of the electrical chip to achieve electrical interconnection and mechanical connection, and then fill the gap between the electrical chip and the high-frequency substrate and the periphery of the electrical chip with underfill glue.

[0081] In this packaging process, the electrical chip is placed on the high-frequency substrate material, and the expansion coefficient of the substrate material is similar to that of the chip, which can ensure the reliability of the chip after bonding; first, the EIC is pasted onto the PIC wafer to complete the underfill process, and then the wafer is diced. Underfill ensures the bonding strength of the PIC-EIC module during the next soldering, and at the same time, the packaging efficiency at the wafer level is much higher than the SMT efficiency of a single DiE; the use of an externally added heat dissipation substrate on the top enables coplanar packaging of the PIC and the FA, solving the problem of the relative position mismatch due to thermal stress between the PIC and the FA. Advanced packaging processes such as molding and underfill are likely to contaminate the optical port. The PIC and the FA are assembled in the last process. The PIC does not participate in the advanced packaging process, and the PIC optical port is always in a non-contact state, avoiding the contamination of the optical port by processes such as molding and underfill. The temperature of the bump soldering usually exceeds 180°C. In order to avoid the optical glue being exposed to this temperature for a long time, the optical glue bonding between the FA and the PIC is completed in the last process. After the optical engine is prepared, the optical glue only undergoes one reflow soldering at a temperature exceeding 180°C.

[0082] It should be noted that although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of the two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0083] Obviously, those skilled in the art can make various changes and modifications to the embodiments in the embodiments of the present application without departing from the spirit and scope of the embodiments in the embodiments of the present application. Thus, if these modifications and variations of the embodiments in the embodiments of the present application fall within the scope of the claims of the embodiments in the present application and their equivalent technologies, the embodiments in the present application are also intended to include these changes and modifications.

Claims

1. A light engine based on 3D packaging, characterized in that: include: An optical chip, an electrical chip, an optical fiber module, and a heat dissipation substrate; an optical port is provided on the side of the optical chip for transmitting and receiving optical signals externally; The electric chip is used to drive the optical chip and modulate the electric signal output by the optical chip, and includes a first surface and a second surface, both of which are provided with connection layers, which are respectively used to realize the mechanical and electrical connection between the electric chip and the high-frequency substrate, and between the electric chip and the optical chip; the heat dissipation substrate includes a main body and a recessed portion extending out of the side of the optical chip where the optical port is set; the optical chip includes a first surface and a second surface, the first surface of the optical chip is connected to the second surface of the electric chip, the second surface of the optical chip is bonded to the main body of the heat dissipation substrate, and the bottom of the optical fiber module is bonded to the recessed portion of the heat dissipation substrate.

2. The 3D packaging-based light engine according to claim 1, characterized in that: One end portion of the main body of the heat dissipation substrate extends out of the side surface of the optical chip to set the optical port, and one side surface of the optical fiber module is bonded to the end portion.

3. The 3D packaging-based light engine according to claim 1, characterized in that: One of the side surfaces of the optical fiber module is bonded to the side surface of the optical chip where the optical port is arranged.

4. The 3D packaging-based light engine according to claim 1, characterized in that: The connection layer is an under-bump metallization layer, a through-silicon via and a redistribution layer are arranged inside the electric chip, and the optical chip, the electric chip and the high-frequency substrate are electrically connected through the under-bump metallization layer, the through-silicon via and the redistribution layer.

5. The 3D packaging-based light engine according to claim 2, wherein: The optical fiber module and the optical port are sealed by optical matching glue.

6. The 3D packaging-based light engine according to claim 2, characterized in that: The gap between the electric chip and the optical chip is filled with a first layer of underfill glue, and the gap between the electric chip and the high-frequency substrate and the surroundings of the electric chip are filled with a second layer of underfill glue.

7. The 3D packaging-based light engine according to claim 6, characterized in that: The vertical projection of the optical port on the high-frequency substrate falls outside the vertical projection range of the electrical chip on the high-frequency substrate.

8. The 3D packaging-based light engine according to claim 1, wherein: The heat dissipation substrate is made of tungsten copper.

9. The 3D packaging-based light engine according to claim 1, 2 or 3, characterized in that: The high frequency substrate and the electric chip have the same thermal expansion coefficient.

10. A light engine packaging method, characterized in that: The light engine is a light engine based on 3D packaging as claimed in any one of claims 4 to 9, and the method comprises: Step 1, evaporating an electroplating seed layer on the second surface of the electric chip; Step 2: applying photoresist based on the electroplating seed layer, and etching an electroplating window at a position corresponding to the under-bump metallization layer on the second side of the electric chip through photolithography and development processes; Step 3: Based on the electroplating window, micro bumps and low-temperature solder for support and electrical interconnection are made, and excess photoresist and electroplating seed layer are removed; Step 4, flipping the electrical chip, and soldering the micro-bumps of the electrical chip to the under-bump metallization pads of the optical chip using a low-temperature solder through a thermal reflow process; Step 5: fill the gap between the optical chip and the electrical chip with underfill glue using an underfill process; Step 6, pasting the optical chip onto the main body of the heat dissipation substrate; Step seven, align the optical fiber module with the optical port of the optical chip, and bond the optical fiber module to the recessed portion of the heat dissipation substrate, fill optical matching glue between the optical fiber module and the optical port of the optical chip and complete UV curing.

11. The light engine packaging method according to claim 10, wherein: The step three also includes: Based on the electroplating window, copper and low-temperature solder metal are electroplated in sequence to form Cu pillars and low-temperature solder of micro-bumps; Stripping off the photoresist on the second side of the optoelectronic chip through a stripping process; Perform dry etching to remove the electroplating seed layer around the micro-bumps; A high temperature reflow is performed to form a low temperature solder cap in a hemispherical shape on the top of the copper bump.

12. The light engine packaging method according to claim 10, wherein: After step seven is completed, the bonded light engine is flipped over to establish a C4 bump structure between the high-frequency substrate and the first side of the electronic chip to achieve electrical interconnection and mechanical connection, and then the gap between the electronic chip and the high-frequency substrate and around the electronic chip are filled with underfill.

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