Power consumption suppression method and apparatus, electronic device, and chip

Abstract

The present disclosure relates to a power consumption suppression method and device, electronic equipment and chip, and relates to the technical field of integrated circuit power consumption management. The method specifically comprises: in response to a power supply unit being at risk of power supply limitation, determining load information of each of N processors, wherein N is an integer greater than or equal to 2; and according to the load information, suppressing power consumption of the N processors. Thus, the present disclosure suppresses power consumption of the processors according to the load information, improves flexibility and automation of suppressing power consumption of the processors, fully releases the performance of the chip, and can be applied to various power supply limitation risk scenarios.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit power management, and in particular to a power suppression method, apparatus, electronic device, and chip. Background Technology

[0002] For complex System-on-Chip (SoC) chips, especially mobile SoC chips using advanced processes, the increasing demand for various upper-layer applications, such as Artificial Intelligence (AI), large models, high-resolution and high-frame-rate videos and games, coupled with users' growing requirements for user experience, further increases the performance requirements for mobile SoC chips. However, the improvement in chip performance leads to higher requirements for power supply capabilities. Yet, power supply capabilities are limited by the finite board area and thermal constraints, preventing unlimited upgrades to power supply specifications. Therefore, how to fully unleash the chip's performance under limited power supply capabilities has become an urgent problem to be solved. Summary of the Invention

[0003] This disclosure provides a power consumption suppression method, apparatus, electronic device, computer-readable storage medium, computer program product, and chip.

[0004] The technical solution disclosed herein is as follows:

[0005] According to a first aspect of the present disclosure, a power consumption suppression method is provided, the method comprising: in response to a power supply unit experiencing a power supply limitation risk, determining load information for each of N processors, wherein N is an integer greater than or equal to 2; and suppressing power consumption for the N processors based on the load information.

[0006] According to a second aspect of the present disclosure, a power consumption suppression device is provided, the device comprising: a determining module, configured to determine load information of N processors respectively in response to a power supply unit experiencing a power supply limitation risk, wherein N is an integer greater than or equal to 2; and a power consumption suppression module, configured to suppress power consumption of the N processors according to the load information.

[0007] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the power consumption suppression method provided in the first aspect of the present disclosure.

[0008] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided that, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform a power consumption suppression method as provided in the first aspect of the present disclosure.

[0009] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, characterized in that, when the computer program is executed by a processor, it implements the power consumption suppression method provided in the first aspect of the present disclosure.

[0010] According to a sixth aspect of the present disclosure, a chip is provided, including a processing unit and an interface circuit. The processing unit obtains program instructions through the interface circuit, and the program instructions are executed by the processing unit. The processing unit is used to perform the steps of the power consumption suppression method provided in the first aspect.

[0011] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0012] A power consumption suppression method according to an embodiment of this disclosure, in response to the risk of power supply limitation in the power supply unit, determines the load information of each of N processors, where N is an integer greater than or equal to 2, and performs power consumption suppression on the N processors according to the load information. Thus, this disclosure improves the flexibility and automation of power consumption suppression for processors based on load information, fully releases the performance of the chip, and can be applied to various scenarios with power supply limitation risks.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0015] Figure 1 This is a flowchart illustrating a power consumption suppression method according to an exemplary embodiment.

[0016] Figure 2 This is a flowchart illustrating another power consumption suppression method according to an exemplary embodiment.

[0017] Figure 3 This is a flowchart illustrating another power consumption suppression method according to an exemplary embodiment.

[0018] Figure 4 This is a flowchart illustrating another power consumption suppression method according to an exemplary embodiment.

[0019] Figure 5 This is a flowchart illustrating a power consumption suppression method according to an exemplary embodiment.

[0020] Figure 6 This is a flowchart illustrating another power consumption suppression method according to an exemplary embodiment.

[0021] Figure 7 This is a flowchart illustrating a power consumption suppression method according to an exemplary embodiment.

[0022] Figure 8 This is an architecture diagram of a system according to an exemplary embodiment.

[0023] Figure 9 This is a block diagram illustrating a power consumption suppression device according to an exemplary embodiment.

[0024] Figure 10 This is a block diagram illustrating an electronic device according to an exemplary embodiment.

[0025] Figure 11 This is a block diagram illustrating a chip system according to an exemplary embodiment. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0027] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0028] Figure 1 This is a flowchart illustrating a power consumption suppression method provided in an embodiment of this disclosure.

[0029] like Figure 1 As shown, the power consumption suppression method includes the following steps:

[0030] S101, in response to the risk of power supply limitation in the power supply unit, determine the load information of each of the N processors, where N is an integer greater than or equal to 2.

[0031] The power supply unit can be a power source or a battery, and it can simultaneously power N processors.

[0032] In this embodiment of the disclosure, a first power consumption value of each processor can be obtained, a second power consumption value of the total power consumption of N processors can be determined based on the first power consumption value of each processor, a third power consumption value corresponding to the maximum power supply capacity of the power supply unit can be obtained, and in response to the second power consumption value being greater than the third power consumption value, it can be determined that the power supply unit is at risk of power supply limitation.

[0033] For example, when N processors are working concurrently, in order to improve the accuracy of determining the risk of power supply limitation in the power supply unit, the power supply unit is determined to have a power supply limitation risk if the total second power consumption value of the N processors is greater than the third power consumption value corresponding to the maximum power supply capacity of the power supply unit, and the duration for which the total second power consumption value of the N processors is greater than the third power consumption value corresponding to the maximum power supply capacity of the power supply unit is greater than a preset duration threshold.

[0034] It should be noted that this disclosure does not limit the type of processor. The processor can be any complex digital circuit, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), an image signal processor (ISP), etc.

[0035] In this embodiment of the disclosure, the processor can be sampled for power consumption-related features to obtain the processor's power consumption feature values. Based on the power consumption feature values, the processor's power consumption can be calculated to obtain the processor's first power consumption value.

[0036] The power consumption characteristics include, but are not limited to, the processor's voltage, current, temperature, and frequency.

[0037] For example, a power consumption feature sampler can be used to sample the power consumption features of the processor to obtain the power consumption feature value of the processor. A power consumption calculation model can be built based on the power consumption feature value, and the power consumption of the processor can be calculated according to the power consumption calculation model to obtain the first power consumption value of the processor.

[0038] In this embodiment of the disclosure, in response to the risk of power supply limitation in the power supply unit, it is necessary to determine the load information of each of the N processors, wherein the load information includes at least one of the following: monitored temperature, load priority, and monitored power consumption.

[0039] Optionally, the monitoring temperature of each of the N processors can be determined by a temperature waterline detector. For example, the temperature waterline detector can receive the monitoring temperature output by the temperature sensors of each of the N processors via a hardwired connection to determine the monitoring temperature of each of the N processors.

[0040] Optionally, the load priority of each of the N processors can be determined by a load priority determiner. For example, the priority information of the task is updated before the N processors execute the task, the updated priority information is sent to the load priority determiner via hardwire, and the load priority of each of the N processors is sorted from low to high according to the priority information to determine the load priority of each of the N processors.

[0041] Optionally, the power consumption information of each of the N processors can be determined by a power consumption level indicator.

[0042] S102, based on load information, performs power consumption suppression on N processors.

[0043] In this embodiment of the disclosure, after obtaining the load information, power consumption suppression can be performed on N processors based on the load information. For example, power consumption suppression can be achieved by reducing the frequency of the processors. By suppressing the power consumption of the processors, the utilization efficiency of the processors can be optimized, thereby reducing the overall power consumption of the system and improving the overall performance of the system.

[0044] For example, power consumption can be suppressed for N processors based on any one of the following: monitored temperature, load priority, and monitored power consumption.

[0045] For example, the importance of monitoring temperature, load priority, and power consumption information can be determined. Based on the importance, the order of information for power consumption suppression corresponding to monitoring temperature, load priority, and power consumption information can be determined. Based on the order of information for power consumption suppression, power consumption suppression can be performed on N processors.

[0046] For example, monitoring temperature, load priority, and power consumption information can be combined to obtain at least one combination and the corresponding power suppression order. Based on the information in the combination, power suppression can be performed on N processors according to the power suppression order.

[0047] It should be noted that this disclosure does not limit the specific method of power consumption suppression for the processor. Optionally, the processor can be downclocked to suppress power consumption.

[0048] A power consumption suppression method according to an embodiment of this disclosure, in response to the risk of power supply limitation in the power supply unit, determines the load information of each of N processors, where N is an integer greater than or equal to 2, and performs power consumption suppression on the N processors according to the load information. Thus, this disclosure improves the flexibility and automation of power consumption suppression for processors based on load information, fully releases the performance of the chip, and can be applied to various scenarios with power supply limitation risks.

[0049] Figure 2 This is a flowchart illustrating a power consumption suppression method according to an embodiment of the present disclosure. Based on the above embodiment, it further incorporates... Figure 2 The specific process of the power consumption suppression method is explained, including the following steps:

[0050] S201, in response to the risk of power supply limitation in the power supply unit, determines the monitoring temperature, load priority and monitoring power consumption information of each of the N processors.

[0051] S202: Sort the N processors according to their load priority from low to high, and obtain the first power suppression order corresponding to the N processors.

[0052] In this embodiment of the disclosure, after obtaining the load priorities of each of the N processors, the N processors can be sorted in order of load priority from low to high to obtain the first power suppression order corresponding to the N processors, that is, power suppression is performed on the processors in order of load priority from low to high.

[0053] S203 performs power suppression on N processors according to the first power suppression order until the power suppression termination condition is met.

[0054] In this embodiment of the disclosure, for N processors, a frequency reduction instruction can be generated and sent to the clock frequency adjustment unit corresponding to the N processors. The clock frequency adjustment unit then performs frequency reduction processing on the N processors based on the frequency reduction instruction.

[0055] For example, for N processors, a preset frequency value can be obtained for each processor. Based on the preset frequency value, a frequency reduction instruction can be generated and sent to the clock frequency adjustment unit corresponding to the N processors. The clock frequency adjustment unit then reduces the frequency of the N processors to the corresponding preset frequency value.

[0056] For example, for N processors, a preset frequency reduction margin can be obtained for each processor. Based on the preset frequency reduction margin, a frequency reduction instruction is generated and sent to the clock frequency adjustment unit corresponding to the N processors. The clock frequency adjustment unit then performs frequency reduction processing on the N processors according to the corresponding preset frequency reduction margin.

[0057] It should be noted that this disclosure does not impose any restrictions on the setting of the power consumption suppression termination condition, which can be set according to the actual situation.

[0058] Optionally, the second power consumption of N processors after power suppression is obtained, and in response to the second power consumption after power suppression being less than the third power consumption value, it is determined that the power suppression termination condition is met.

[0059] Optionally, in response to the fact that all processors requiring power suppression among the N processors have undergone power suppression, it is determined that the processors meet the power suppression termination condition.

[0060] S204, for any one of the monitored temperature and monitored power consumption information, determine the M first processors among the N processors that have issued a warning, where the warning is related to any one of the monitored temperature and power consumption information, and M is an integer greater than or equal to 1.

[0061] It should be noted that the monitoring temperature threshold and monitoring power consumption threshold of each of the N processors can be configured in advance to obtain the monitoring temperature threshold and monitoring power consumption threshold of each of the N processors.

[0062] In this embodiment of the disclosure, after obtaining the monitoring temperature threshold and monitoring power consumption threshold of each of the N processors, the monitoring temperature of each of the N processors can be compared with the monitoring temperature threshold and the monitoring power consumption information can be compared with the monitoring power consumption threshold. In response to the processor's monitoring temperature being greater than the monitoring temperature threshold and / or the monitoring power consumption information being greater than the monitoring power consumption threshold, it is determined that the processor has issued a warning, and thus the M first processors that have issued warnings among the N processors can be identified.

[0063] S205 performs power suppression on M first processors until the power suppression termination condition is met.

[0064] In this embodiment of the disclosure, for M first processors, a frequency reduction instruction is generated and sent to the clock frequency adjustment unit corresponding to the M first processors that require power suppression. The clock frequency adjustment unit performs frequency reduction processing on the processors that require power suppression based on the frequency reduction instruction.

[0065] For example, for M first processors, a preset frequency value corresponding to each first processor can be obtained. Based on the preset frequency value, a frequency reduction instruction can be generated and sent to the clock frequency adjustment unit corresponding to each first processor. The clock frequency adjustment unit then reduces the frequency of each first processor to the corresponding preset frequency value.

[0066] For example, for M first processors, a preset frequency reduction margin can be obtained for each first processor. Based on the preset frequency reduction margin, a frequency reduction instruction is generated and sent to the clock frequency adjustment units corresponding to N processors. The clock frequency adjustment units then perform frequency reduction processing on each first processor according to the corresponding preset frequency reduction margin.

[0067] It should be noted that this disclosure does not impose any restrictions on the setting of the power consumption suppression termination condition, which can be set according to the actual situation.

[0068] Optionally, the second power consumption of M first processors after power consumption suppression is obtained, and in response to the second power consumption after power consumption suppression being less than the third power consumption value, it is determined that the power consumption suppression termination condition is met.

[0069] Optionally, in response to the fact that all M first processors have undergone power suppression, it is determined that the processor meets the power suppression termination condition.

[0070] In this embodiment of the disclosure, in response to the removal of the power supply limitation risk of the power supply unit, power consumption is restored for the processors among the N processors that have undergone power suppression.

[0071] For example, the target power consumption value of each processor can be obtained, and the total target power consumption value of N processors can be determined based on the target power consumption value of each processor. In response to the total target power consumption value being less than or equal to the third power consumption value, it is determined that the power supply limitation risk of the power supply unit is eliminated.

[0072] In this embodiment of the disclosure, the load priority of the processors that have undergone power suppression is determined, and the processors that have undergone power suppression are sorted from high to low according to the load priority to obtain the power recovery order. Then, the power recovery is performed on the processors that have undergone power suppression according to the power recovery order.

[0073] Optionally, an upclocking instruction is generated for the power-suppressed processor, and the upclocking instruction is sent to the clock frequency adjustment unit corresponding to the power-suppressed processor. The clock frequency adjustment unit then performs upclocking processing on the power-suppressed processor based on the upclocking instruction to restore the power consumption of the power-suppressed processor.

[0074] For example, for N processors, the target frequency value of each processor before power consumption suppression can be obtained. Based on the target frequency value, an upclocking instruction is generated and sent to the clock frequency adjustment unit corresponding to the N processors. The clock frequency adjustment unit then upclocks the N processors to the corresponding target frequency value.

[0075] The following explains the specific process of power consumption suppression for N processors based on load priority.

[0076] For example, such as Figure 3 As shown, the target for identifying the risk of power supply limitation is determined when the power supply unit is a single power source, and the third power consumption value P corresponding to the maximum power supply capacity of the single power source is determined. th When the power supply unit is a battery, determine the third power consumption value P corresponding to the maximum power supply capacity of the battery. b_thWhen a system consisting of N processors is powered on, each processor initializes its operating voltage and frequency based on service performance requirements, obtains its first power consumption value, and accumulates these first power consumption values ​​to determine the total second power consumption value P of the N processors. accu In response to the second power consumption value P accu Greater than the third power consumption value P th Or the second power consumption value P accu Greater than the third power consumption value P b_th The process involves identifying a power supply limitation risk in the power supply unit, determining the load priority of each of the N processors, sorting the N processors according to their load priority from low to high, obtaining a first power suppression order for each of the N processors, and then applying power suppression to the N processors according to this first power suppression order until a second power consumption value P is obtained for the N processors after power suppression. accu Less than the third power consumption value P th Or the second power consumption value P accu Less than the third power consumption value P th The process involves determining that the power supply limitation risk of the power supply unit has been eliminated, determining the load priority of the processors that have undergone power suppression, sorting the processors that have undergone power suppression according to the load priority from high to low, obtaining the power recovery order, and performing power recovery on the processors that have undergone power suppression according to the power recovery order.

[0077] A power consumption suppression method according to an embodiment of this disclosure, in response to a power supply unit experiencing a power supply limitation risk, determines the monitored temperature, load priority, and monitored power consumption information of N processors. The N processors are sorted according to load priority from low to high to obtain a first power consumption suppression order. Power consumption suppression is performed on the N processors according to the first power consumption suppression order until the power consumption suppression termination condition is met. For any one of the monitored temperature and monitored power consumption information, M first processors among the N processors that have issued a warning are determined based on that information, where the warning is related to any one of the monitored temperature and monitored power consumption information, and M is an integer greater than or equal to 1. Power consumption suppression is performed on the M first processors until the power consumption suppression termination condition is met. Thus, this disclosure, based on any one of the monitored temperature, load priority, and monitored power consumption information, uses a clock frequency adjustment unit to perform frequency reduction processing on the processor based on a frequency reduction instruction to achieve power consumption suppression of the processor. This improves the accuracy of power consumption suppression, ensures the real-time performance and flexibility of power consumption suppression, and fully releases the chip's performance.

[0078] Figure 4 This is a flowchart illustrating a power consumption suppression method according to an embodiment of the present disclosure. Based on the above embodiment, it further incorporates... Figure 4The specific process of the power consumption suppression method is explained, including the following steps:

[0079] S401, in response to the risk of power supply limitation in the power supply unit, determines the monitoring temperature, load priority and monitoring power consumption information of each of the N processors.

[0080] S402 determines the relative importance of monitoring temperature, load priority, and power consumption information.

[0081] It should be noted that this disclosure does not limit the specific methods for determining the importance of monitoring temperature, load priority, and monitoring power consumption information, and these methods can be selected according to the actual situation.

[0082] Optionally, the importance of monitoring temperature, load priority, and power consumption information can be determined according to the performance requirements of different business types.

[0083] For example, for business type 1, the importance of monitoring temperature is determined to be the highest, followed by load priority, and then the importance of monitoring power consumption information is determined to be the lowest.

[0084] S403 determines the order of information used for power suppression corresponding to monitored temperature, load priority, and monitored power consumption information based on their importance.

[0085] In this embodiment of the disclosure, after obtaining the importance level, the information sequence for power consumption suppression corresponding to the monitored temperature, load priority, and monitored power consumption information is obtained according to the importance level from high to low.

[0086] S404 performs power suppression on N processors based on the order of information used for power suppression, and on the monitoring temperature, load priority and monitoring power information, until the power suppression termination condition is met.

[0087] In this embodiment of the disclosure, after power consumption suppression is performed on N processors based on any one piece of information, it is determined whether the power supply unit still has a power supply limitation risk. In response to the power supply unit having a power supply limitation risk, the next piece of information is used to continue power consumption suppression on N processors.

[0088] It should be noted that the specific process of suppressing power consumption for N processors until the power consumption suppression termination condition is met can be found in the above embodiments, and will not be repeated here.

[0089] In this embodiment of the disclosure, in response to the removal of the power supply limitation risk of the power supply unit, power consumption is restored for the processors among the N processors that have undergone power suppression.

[0090] Optionally, the load priority of the processors that have undergone power suppression is determined, and the processors that have undergone power suppression are sorted from high to low according to the load priority to obtain the power recovery order. Then, the power recovery is performed on the processors that have undergone power suppression according to the power recovery order.

[0091] Optionally, an upclocking instruction is generated for the power-suppressed processor, and the upclocking instruction is sent to the clock frequency adjustment unit corresponding to the power-suppressed processor. The clock frequency adjustment unit then performs upclocking processing on the power-suppressed processor based on the upclocking instruction to restore the power consumption of the power-suppressed processor.

[0092] The following explains the specific process of power suppression for N processors based on monitored temperature, load priority, and power consumption information.

[0093] For example, such as Figure 5 As shown, the target for identifying the risk of power supply limitation is determined when the power supply unit is a single power source, and the third power consumption value P corresponding to the maximum power supply capacity of the single power source is determined. th When the power supply unit is a battery, determine the third power consumption value P corresponding to the maximum power supply capacity of the battery. b_th When a system consisting of N processors is powered on, each processor initializes its operating voltage and frequency based on service performance requirements, obtains its first power consumption value, and accumulates these first power consumption values ​​to determine the total second power consumption value P of the N processors. accu In response to the second power consumption value P accu Greater than the third power consumption value P th Or the second power consumption value P accu Greater than the third power consumption value P b _ thTo determine if the power supply unit is at risk of power limitation, the importance of monitoring temperature, load priority, and power consumption information is determined. If the importance is ranked from highest to lowest as monitoring temperature, power consumption information, and load priority, the monitoring temperature of each of the N processors is first compared with its monitoring temperature threshold. If a processor's monitoring temperature exceeds the threshold, the processor with the warning is identified. A frequency reduction instruction is sent to the clock frequency adjustment unit corresponding to the processor with the warning. The clock frequency adjustment unit then reduces the frequency of the processor requiring power suppression based on the frequency reduction instruction until the power suppression termination condition is met. If, after power suppression of the first processor based on monitoring temperature, the power supply unit still faces a risk of power limitation, the monitoring power consumption information of the processor is further compared with the monitoring power consumption threshold. If the monitored power consumption of a processor exceeds the monitored power consumption threshold, the processor that triggered the warning is identified. A frequency reduction instruction is sent to the clock frequency adjustment unit corresponding to the processor that triggered the warning. The clock frequency adjustment unit then reduces the frequency of the processor requiring power suppression based on the frequency reduction instruction until the power suppression termination condition is met. If the power supply unit still faces a risk of power supply limitation, the load priority of each processor is determined. Power suppression is then performed on the processors in ascending order of load priority until the power suppression termination condition is met, and the power supply limitation risk of the power supply unit is determined. The load priority of the processors that have undergone power suppression is then determined. The processors that have undergone power suppression are sorted in descending order of load priority to obtain the power recovery order. Power recovery is then performed on the processors that have undergone power suppression according to the power recovery order.

[0094] A power consumption suppression method according to an embodiment of this disclosure, in response to the risk of power supply limitation in the power supply unit, determines the monitoring temperature, load priority, and monitoring power consumption information of each of N processors, determines the importance of each of the monitoring temperature, load priority, and monitoring power consumption information, determines the information order for power consumption suppression corresponding to the monitoring temperature, load priority, and monitoring power consumption information according to the importance, and performs power consumption suppression on the N processors based on the monitoring temperature, load priority, and monitoring power consumption information according to the information order for power consumption suppression, until the power consumption suppression termination condition is met. Thus, this disclosure improves the accuracy of power consumption suppression by determining the importance of each of the monitoring temperature, load priority, and monitoring power consumption information, and performs frequency reduction processing on the processors based on frequency reduction instructions through a clock frequency adjustment unit, thereby fully releasing the performance of the chip.

[0095] Figure 6 This is a flowchart illustrating a power consumption suppression method according to an embodiment of the present disclosure. Based on the above embodiment, and in further conjunction with the figures, the specific process of the power consumption suppression method is explained and described, including the following steps:

[0096] S601, in response to the risk of power supply limitation in the power supply unit, determines the monitoring temperature, load priority and monitoring power consumption information of each of the N processors.

[0097] S602 combines the monitored temperature, load priority, and monitored power consumption information to obtain at least one combination and a second power consumption suppression order corresponding to the combination.

[0098] For example, monitoring temperature and load priority can be combined, as can monitoring power consumption information and load priority.

[0099] S603, following the second power suppression order, performs power suppression on N processors based on the information in the combination until the power suppression termination condition is met.

[0100] In this embodiment of the disclosure, for the first item of information in the monitoring temperature and monitoring power consumption information, based on the first item of information, T second processors among N processors that have issued warnings are determined, where the warning is related to the first item of information, and T is an integer greater than or equal to 1. The T second processors are sorted from low to high according to the load priority to obtain a second power consumption suppression order. Power consumption suppression is performed on the T second processors according to the second power consumption suppression order until the power consumption suppression termination condition is met.

[0101] For example, if the monitored temperature is the first piece of information and the monitored power consumption is the second piece of information, the monitored temperature of each of the N processors is compared with the monitored temperature threshold. If the monitored temperature of a processor is greater than the monitored temperature threshold, it is determined that the processor has issued a warning. Then, the T second processors that have issued warnings among the N processors can be identified, and the T second processors are sorted from low to high according to the load priority to obtain the second power consumption suppression order. Power consumption suppression is performed on the T second processors according to the second power consumption suppression order until the power consumption suppression termination condition is met.

[0102] In this embodiment of the disclosure, after power consumption suppression is applied to T second processors, it is determined whether the power supply unit still has a risk of power supply limitation. In response to the fact that the power supply unit still has a risk of power supply limitation, the second item of the monitored temperature and monitored power consumption information is used to determine S third processors among the T processors that have issued warnings, where the warnings are related to the second item of information and S is an integer greater than or equal to 1. The S third processors are sorted according to the load priority from low to high to obtain the third power consumption suppression order. Power consumption suppression is applied to the S third processors according to the third power consumption suppression order until the power consumption adjustment end condition is met.

[0103] For example, if the monitored temperature is the first piece of information and the monitored power consumption is the second piece of information, after suppressing the power consumption of T second processors according to the second power consumption suppression order, if the power supply unit still has a risk of power supply limitation, the monitored power consumption information of each of the N processors is compared with the monitored power consumption threshold. If the monitored power consumption information of a processor is greater than the monitored power consumption threshold, it is determined that the processor has a warning. Then, the S third processors with warnings among the T processors can be identified, and the S third processors are sorted from low to high according to the load priority to obtain the third power consumption suppression order. The power consumption of the S third processors is suppressed according to the third power consumption suppression order until the power consumption adjustment end condition is met.

[0104] In this embodiment of the disclosure, after power suppression is performed on T second processors according to the second power suppression order and on S third processors according to the third power suppression order, in response to the fact that the power supply unit still has the risk of power supply limitation, the N processors are sorted from low to high according to the current load priority of the N processors to obtain the fourth power suppression order, and power suppression is performed on the N processors according to the fourth power suppression order until the power adjustment end condition is met.

[0105] The following explains the specific process of power consumption suppression for N processors based on the information in the combination.

[0106] For example, such as Figure 7 As shown, the target for identifying the risk of power supply limitation is determined when the power supply unit is a single power source, and the third power consumption value P corresponding to the maximum power supply capacity of the single power source is determined. th When the power supply unit is a battery, determine the third power consumption value P corresponding to the maximum power supply capacity of the battery. b_th When a system consisting of N processors is powered on, each processor initializes its operating voltage and frequency based on service performance requirements, obtains its first power consumption value, and accumulates these first power consumption values ​​to determine the total second power consumption value P of the N processors. accu In response to the second power consumption value P accu Greater than the third power consumption value P th Or the second power consumption value P accu Greater than the third power consumption value P b _ thTo determine if a power supply unit is at risk of power limitation, the monitoring temperature of each of the N processors is first compared to its monitoring temperature threshold. If a processor's monitoring temperature exceeds the threshold, the second processor triggering the warning is identified. The second processors are then sorted according to load priority from low to high to obtain a second power suppression order. Power suppression is applied to the second processors according to this order until the power suppression termination condition is met. If, after power suppression according to the second power suppression order, a power supply unit still faces a risk of power limitation, the monitoring power consumption information of the second processor is compared to its monitoring power consumption threshold. If the monitoring power consumption information exceeds the threshold, the third processor triggering the warning is identified. The third processor is then further processed according to load priority from low to high. The process involves sorting the processors to obtain a third power suppression order, then suppressing the power consumption of the third processor according to this order until the power suppression termination condition is met. If, after suppressing the power consumption of the third processor according to the third power suppression order, the power supply unit still faces a power supply limitation risk, the N processors are sorted from low to high according to their current load priorities to obtain a fourth power suppression order. This process continues until the power adjustment termination condition is met, thus confirming that the power supply limitation risk of the power supply unit is eliminated. The load priorities of the processors that have undergone power suppression are then determined. Based on these load priorities, the processors are sorted from high to low to obtain a power recovery order. Finally, the processors that have undergone power suppression are restored according to this order.

[0107] A power consumption suppression method according to an embodiment of this disclosure, in response to the risk of power supply limitation in the power supply unit, determines the monitoring temperature, load priority, and monitoring power consumption information of each of N processors, combines the monitoring temperature, load priority, and monitoring power consumption information to obtain at least one combination and a second power consumption suppression order corresponding to the combination, and performs power consumption suppression on the N processors according to the second power consumption suppression order and based on the information in the combination until the power consumption suppression termination condition is met. Thus, this disclosure combines the monitoring temperature, load priority, and monitoring power consumption information, and performs frequency reduction processing on the processors based on the frequency reduction instruction through a clock frequency adjustment unit to achieve power consumption suppression of the processors, thereby improving the accuracy of power consumption suppression of the processors, ensuring the real-time performance and flexibility of power consumption suppression of the processors, and fully releasing the performance of the chip.

[0108] The system architecture consisting of N processors based on the power consumption suppression method is explained below.

[0109] For example, such as Figure 8As shown, the system architecture includes N clock frequency adjustment units 101, N processors 102, N power consumption monitoring units 200, and a power consumption redistribution unit 300. Each power consumption monitoring unit includes a power consumption characteristic sampler 201 and a power consumption calculation model 202. The power consumption redistribution unit 300 includes a power supply limitation risk determination module 301, a frequency modulation command generator 302, and a power consumption suppression target selector 400. The power consumption suppression target selector 400 can receive information from three dimensions: monitored temperature, load priority, and monitored power consumption information. The monitored temperature is determined by a temperature waterline determiner 401, the load priority is determined by a load priority determiner 402, and the monitored power consumption information is determined by a power consumption waterline determiner 403.

[0110] Specifically, the power consumption feature sampler in the power consumption monitoring unit corresponding to each processor samples the power consumption-related features of the processor to obtain the power consumption feature value of the processor. Using the power consumption calculation model, the power consumption of the processor is calculated based on the power consumption feature value to obtain the first power consumption value of each processor. The power supply limitation risk determination module 301 receives the first power consumption value output by each power consumption monitoring unit, calculates the total second power consumption value of N processors, and determines whether the total second power consumption value of N processors is greater than the third power consumption value corresponding to the maximum power supply capacity of the power supply unit. In response to the second power consumption value being greater than the third power consumption value, it is determined that the power supply unit has a power supply limitation risk.

[0111] In this process, after determining that the power supply unit is at risk of power limitation, the power suppression target selector 400 determines the monitoring temperature, load priority, and monitoring power consumption information of each of the N processors. The power suppression target selector 400 can determine the processors among the N processors that require power suppression based on at least one of the monitoring temperature, load priority, and monitoring power consumption information. It then generates a frequency reduction instruction through the frequency adjustment command generator and sends the frequency reduction instruction to the clock frequency adjustment unit corresponding to the processor that requires power suppression. The clock frequency adjustment unit performs frequency reduction processing on the processor that requires power suppression based on the frequency reduction instruction to suppress power consumption until the power adjustment end condition is met. The specific process of suppressing power consumption of the N processors based on at least one of the monitoring temperature, load priority, and monitoring power consumption information is not described in detail here, but can be found in the above embodiment.

[0112] In response to the removal of the power supply limitation risk of the power supply unit, the load priority of the processors that have undergone power suppression is determined. The processors that have undergone power suppression are sorted from high to low according to the load priority to obtain the power recovery order. The frequency adjustment command generator generates an up-frequency instruction for the processors that have undergone power suppression. According to the power recovery order, the up-frequency instruction is sent to the clock frequency adjustment unit corresponding to the processors that have undergone power suppression. The clock frequency adjustment unit performs up-frequency processing on the processors that have undergone power suppression based on the up-frequency instruction.

[0113] In summary, the power consumption suppression method of this disclosure can accurately and automatically determine whether a power supply unit is at risk of power supply limitation. When a power supply unit is determined to be at risk of power supply limitation, power consumption suppression is performed on the processor based on at least one of the processor's monitored temperature, load priority, and monitored power consumption information, minimizing the impact on the performance of other loads. Furthermore, regardless of whether the power supply limitation risk occurs at a single power source or a battery, it can effectively address the problem of power supply limitation risk in power supply units when multiple processors are working concurrently, demonstrating strong versatility. Additionally, the power supply limitation risk determination, temperature monitoring, and other methods described in this disclosure... Multiple processes, including load prioritization, monitoring power consumption information, and generating and issuing frequency adjustment commands, are all implemented automatically in hardware. The total latency from determining the risk of power supply limitation in the power supply unit to suppressing the processor's power consumption can be controlled within the order of 1µs, ensuring the real-time performance of processor power consumption suppression. Furthermore, the clock frequency adjustment unit performs frequency reduction processing on the processor based on the frequency reduction command to achieve processor power consumption suppression, improving the accuracy of processor power consumption suppression. By finely controlling the frequency of each processor through the frequency reduction command, the total power consumption can be kept close to the power supply capacity to the greatest extent possible, thereby ensuring that the chip performance is fully released.

[0114] Figure 9 This is a block diagram illustrating a power consumption suppression device according to an exemplary embodiment.

[0115] like Figure 9 As shown, the power consumption suppression device 1000 includes: a determination module 110 and a power consumption suppression module 120.

[0116] The determination module 110 is used to determine the load information of each of the N processors in response to the risk of power supply limitation in the power supply unit, where N is an integer greater than or equal to 2;

[0117] The power consumption suppression module 120 is used to suppress the power consumption of the N processors based on the load information.

[0118] Furthermore, the load information includes at least one of the following: monitored temperature, load priority, and monitored power consumption.

[0119] Furthermore, the device 1000 is configured to: acquire a first power consumption value for each processor; determine a second power consumption value for the total power consumption of the N processors based on the first power consumption value for each processor; acquire a third power consumption value corresponding to the maximum power supply capacity of the power supply unit; and determine that the power supply unit is at risk of power supply limitation in response to the second power consumption value being greater than the third power consumption value.

[0120] Furthermore, the device 1000 is configured to: sample the power consumption-related features of the processor to obtain the power consumption feature value of the processor; and calculate the power consumption of the processor based on the power consumption feature value to obtain a first power consumption value of the processor.

[0121] Furthermore, the power suppression module 120 is configured to: sort the N processors according to the load priority from low to high to obtain a first power suppression order corresponding to the N processors; and suppress the power consumption of the N processors according to the first power suppression order until the power suppression termination condition is met.

[0122] Furthermore, the power consumption suppression module 120 is configured to: for any one of the monitored temperature and monitored power consumption information, determine M first processors among the N processors that have issued a warning, wherein the warning is related to the any one of the monitored temperature and monitored power consumption information, and M is an integer greater than or equal to 1; and perform power consumption suppression on the M first processors until the power consumption suppression termination condition is met.

[0123] Furthermore, the power suppression module 120 is configured to: determine the importance of the monitored temperature, load priority, and monitored power consumption information; determine the order of information for power suppression corresponding to the monitored temperature, load priority, and monitored power consumption information according to the importance; and perform power suppression on the N processors based on the monitored temperature, load priority, and monitored power consumption information according to the order of information for power suppression, until the power suppression termination condition is met.

[0124] Furthermore, the power consumption suppression module 120 is configured to: after suppressing the power consumption of the N processors based on any one piece of information, determine whether the power supply unit still has a power supply limitation risk; in response to the power supply unit having a power supply limitation risk, continue to use the next piece of information to suppress the power consumption of the N processors.

[0125] Furthermore, the power suppression module 120 is configured to: combine the monitored temperature, load priority, and monitored power consumption information to obtain at least one combination and a second power suppression order corresponding to the combination; and, according to the second power suppression order, suppress the power consumption of the N processors based on the information in the combination until the power suppression termination condition is met.

[0126] Furthermore, the power consumption suppression module 120 is configured to: for the first item of information in the monitored temperature and monitored power consumption information, determine T second processors among the N processors that have issued warnings, wherein the warnings are related to the first item of information, and T is an integer greater than or equal to 1; sort the T second processors according to the load priority from low to high to obtain a second power consumption suppression order; and perform power consumption suppression on the T second processors according to the second power consumption suppression order until the power consumption suppression termination condition is met.

[0127] Furthermore, the power consumption suppression module 120 is configured to: after suppressing the power consumption of the T second processors, determine whether the power supply unit still has a risk of power supply limitation; in response to the fact that the power supply unit still has a risk of power supply limitation, continue to determine the S third processors among the T processors that have issued warnings based on the second item of the monitored temperature and monitored power consumption information, wherein the warnings are related to the second item of information, and S is an integer greater than or equal to 1; sort the S third processors according to the load priority from low to high to obtain a third power consumption suppression order; and suppress the power consumption of the S third processors according to the third power consumption suppression order until the power consumption adjustment end condition is met.

[0128] Furthermore, the power suppression module 120 is configured to: respond to the fact that the power supply unit still has a risk of power supply limitation, sort the N processors according to their current load priority from low to high to obtain a fourth power suppression order; and suppress the power consumption of the N processors according to the fourth power suppression order until the power adjustment end condition is met.

[0129] Furthermore, the device 1000 is configured to: obtain the second power consumption of the N processors after power suppression; and determine that the power suppression termination condition is met in response to the second power consumption being less than the third power consumption value; or, determine that the processors satisfying the power suppression termination condition in response to the fact that all processors requiring power suppression among the N processors have undergone power suppression.

[0130] Furthermore, the device 1000 is configured to: generate a frequency reduction instruction for the processor among the N processors that requires power suppression; send the frequency reduction instruction to the clock frequency adjustment unit corresponding to the processor that requires power suppression; and perform frequency reduction processing on the processor that requires power suppression based on the frequency reduction instruction through the clock frequency adjustment unit.

[0131] Furthermore, the device 1000 is configured to: in response to the removal of the power supply limitation risk of the power supply unit, restore the power consumption of the processors among the N processors that have undergone power suppression.

[0132] Furthermore, the device 1000 is configured to: determine the load priority of the power-suppressed processor; sort the power-suppressed processors from high to low according to the load priority to obtain a power recovery order; and perform power recovery on the power-suppressed processors according to the power recovery order.

[0133] Furthermore, the device 1000 is configured to: generate an upclocking instruction for the power-suppressed processor; send the upclocking instruction to the clock frequency adjustment unit corresponding to the power-suppressed processor; and perform upclocking processing on the power-suppressed processor based on the upclocking instruction by the clock frequency adjustment unit.

[0134] According to an embodiment of the present disclosure, a power consumption suppression device, in response to a power supply unit experiencing a power supply limitation risk, determines the load information of each of N processors, where N is an integer greater than or equal to 2. Based on the load information, power consumption suppression is performed on the N processors. Thus, the present disclosure improves the flexibility and automation of power consumption suppression for processors by performing power consumption suppression based on load information, fully releasing the performance of the chip, and can be applied to various scenarios with power supply limitation risks.

[0135] To implement the above embodiments, this disclosure also provides an electronic device, such as... Figure 10 As shown, the electronic device 2000 includes: a processor 210; and one or more memories 220 for storing instructions executable by the processor 210; wherein the processor 210 is configured to execute the power consumption suppression method described in the above embodiments. The processor 210 and the memories 220 are connected via a communication bus.

[0136] To implement the above embodiments, this disclosure also provides a computer-readable storage medium including instructions, such as a memory 220 including instructions, which can be executed by the processor 210 of the device 1000 to perform the above methods. Optionally, the computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0137] To implement the above embodiments, this disclosure also provides a computer program product, including a computer program, characterized in that the computer program, when executed by a processor, implements the power consumption suppression method described in the above embodiments.

[0138] To implement the above embodiments, this disclosure also provides a chip, such as... Figure 11As shown, the chip includes at least one processor 310 and at least one interface circuit 320. The processor 310 and the interface circuit 320 are interconnected via lines. For example, the interface circuit 320 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 320 can be used to send signals to other devices (e.g., the processor 310). Exemplarily, the interface circuit 320 can read instructions stored in memory and send those instructions to the processor 310. When the instructions are executed by the processor 310, the port selection device can perform the steps of the power consumption suppression method described in the above embodiments. Of course, the chip may also include other discrete devices, and some embodiments of this disclosure do not specifically limit this.

[0139] In some embodiments of this disclosure, the interface circuit 320 can acquire data, program instructions, and / or information from the internal storage area of ​​the chip; it can also acquire data, program instructions, and / or information from outside the chip system.

[0140] Optionally, the chip may also include memory for storing necessary computer programs and data.

[0141] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0142] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0143] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A power consumption suppression method, characterized in that, Belonging to the field of integrated circuit power management, the method includes: In response to the risk of power supply limitation in the power supply unit, determine N The load information for each processor includes: load priority, in the... N Before each processor executes a task, it updates the task's priority information and sends the updated priority information to the load priority determiner via hardwire. Based on the priority information, the N processors are sorted from low to high according to their respective load priorities to determine the load priorities of the N processors. N The value is an integer greater than or equal to 2; wherein: the process of determining the risk of power supply limitation in the power supply unit includes: obtaining a first power consumption value for each processor; determining a second power consumption value for the total power consumption of the N processors based on the first power consumption value for each processor; obtaining a third power consumption value corresponding to the maximum power supply capacity of the power supply unit; and determining that the power supply unit has a risk of power supply limitation in response to the second power consumption value being greater than the third power consumption value. Based on the load information, for the N Power consumption is suppressed in each processor; In response to the elimination of the power supply limitation risk of the power supply unit, the determination of the N The load priority of the power-suppressed processors among the processors is determined, and the power-suppressed processors are sorted from high to low according to the load priority to obtain a power recovery order. Power recovery is then performed on the power-suppressed processors according to the power recovery order. The power recovery process includes: generating an upclocking instruction for each power-suppressed processor; sending the upclocking instruction to the clock frequency adjustment unit corresponding to each power-suppressed processor; and using the clock frequency adjustment unit to upclock the power-suppressed processor based on the upclocking instruction.

2. The method according to claim 1, characterized in that, The load information also includes: At least one of the following information: monitoring temperature and monitoring power consumption.

3. The method according to claim 1, characterized in that, The process of obtaining the first power consumption value for each processor includes: The processor is sampled for power consumption-related features to obtain the power consumption feature values ​​of the processor; The power consumption of the processor is calculated based on the power consumption characteristic value to obtain the first power consumption value of the processor.

4. The method according to claim 2, characterized in that, The method based on the load information is as follows: N Each processor performs power consumption suppression, including: According to the load priority from low to high, the following are the orders: N Sort the processors and obtain the... N The first power consumption suppression order corresponding to each processor; According to the first power consumption suppression order, for the N Each processor performs power suppression until the power suppression termination condition is met.

5. The method according to claim 2, characterized in that, The method based on the load information is as follows: N Power consumption suppression for each processor also includes: For any one of the monitored temperature and monitored power consumption information, determine the following based on the monitored temperature and monitored power consumption information: N Warnings appeared in one of the processors. M A first processor, wherein the warning is related to any of the aforementioned pieces of information. M It is an integer greater than or equal to 1; Regarding the M The first processor performs power suppression until the power suppression termination condition is met.

6. The method according to claim 2, characterized in that, The method based on the load information is as follows: N Power consumption suppression for each processor also includes: Determine the relative importance of the monitored temperature, load priority, and power consumption information; Based on the importance level, determine the order of information for power consumption suppression corresponding to the monitored temperature, load priority, and monitored power consumption information; Based on the information order used for power consumption suppression, and based on the monitored temperature, load priority, and monitored power consumption information, the following is applied: N Each processor performs power suppression until the power suppression termination condition is met.

7. The method according to claim 6, characterized in that, The method further includes: Based on any one of the information, the above N After each processor performs power consumption suppression, it is determined whether the power supply unit still faces the risk of power supply limitation. In response to the risk of power supply limitation in the power supply unit, the next piece of information is used to continue to the power supply unit. N Power consumption is suppressed in each processor.

8. The method according to claim 2, characterized in that, The method based on the load information is as follows: N Power consumption suppression for each processor also includes: The monitored temperature, load priority, and monitored power consumption information are combined to obtain at least one combination and a second power consumption suppression order corresponding to the combination. According to the second power consumption suppression order, based on the information in the combination, the power consumption suppression is... N Each processor performs power suppression until the power suppression termination condition is met.

9. The method according to claim 8, characterized in that, The method further includes: Regarding the first item of the monitored temperature and monitored power consumption information, based on the first item of information, determine the... N Warnings appeared in one of the processors. T A second processor, wherein the warning is related to the first piece of information. T It is an integer greater than or equal to 1; According to the load priority from low to high, the T The second processors are sorted to obtain the second power consumption suppression order; According to the second power consumption suppression order, the T The second processor performs power suppression until the power suppression termination condition is met.

10. The method according to claim 9, characterized in that, The method further includes: Regarding the T After the second processor performs power consumption suppression, it is determined whether the power supply unit still has a risk of power supply limitation. In response to the continued risk of power supply limitation in the power supply unit, the second piece of information from the monitored temperature and monitored power consumption information is used to determine the... T Warnings appeared in one of the processors. S A third processor, wherein the warning is related to the second piece of information. S It is an integer greater than or equal to 1; According to the load priority from low to high, the S The third processors are sorted to obtain the third power consumption suppression order; According to the third power consumption suppression order, the S The third processor performs power suppression until the power adjustment termination condition is met.

11. The method according to claim 9 or 10, characterized in that, The method further includes: In response to the fact that the power supply unit still faces the risk of power limitation, according to the N The current load priority of each processor is from low to high. N The processors are sorted to obtain the fourth power consumption suppression order; According to the fourth power consumption suppression order, the N Each processor performs power suppression until the power adjustment termination condition is met.

12. The method according to any one of claims 4-10, characterized in that, The method further includes: Obtain the N The second power consumption of a processor after power suppression, in response to the second power consumption after power suppression being less than the third power consumption value, determines that the power suppression termination condition is met; or... In response to the N All processors requiring power suppression have undergone power suppression, confirming that the processors meet the power suppression termination condition.

13. The method according to any one of claims 1-10, characterized in that, The power consumption suppression process includes: Regarding the above N For processors that require power suppression, generate downclocking instructions; Send the frequency reduction command to the clock frequency adjustment unit corresponding to the processor that requires power suppression; The clock frequency adjustment unit performs frequency reduction processing on the processor requiring power suppression based on the frequency reduction instruction.

14. A power consumption suppression device, characterized in that, Belonging to the field of integrated circuit power management, the device includes: The determination module is used to determine the risk of power supply limitation in response to the power supply unit. N The load information for each processor includes: load priority, in the... N Before each processor executes a task, it updates the task's priority information and sends the updated priority information to the load priority determiner via hardwire. Based on the priority information, the N processors are sorted from low to high according to their respective load priorities to determine the load priorities of the N processors. N The value is an integer greater than or equal to 2; wherein: the process of determining the risk of power supply limitation in the power supply unit includes: obtaining a first power consumption value for each processor; determining a second power consumption value for the total power consumption of the N processors based on the first power consumption value for each processor; obtaining a third power consumption value corresponding to the maximum power supply capacity of the power supply unit; and determining that the power supply unit has a risk of power supply limitation in response to the second power consumption value being greater than the third power consumption value. The power consumption suppression module is used to suppress the power consumption of the load information. N Power consumption is suppressed in each processor; The device further includes: in response to the power supply limitation risk of the power supply unit being eliminated, determining the... N The power suppression processors among the processors are prioritized according to their load priority from high to low. The power suppression processors are then sorted to obtain a power recovery order, and power recovery is performed on the power suppression processors according to this order. The power recovery process includes: generating an upclocking instruction for each power suppression processor; sending the upclocking instruction to the clock frequency adjustment unit corresponding to each power suppression processor; and using the clock frequency adjustment unit to upclock the power suppression processor based on the upclocking instruction.

15. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the power consumption suppression method as described in any one of claims 1-13.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the power consumption suppression method as described in any one of claims 1-13.

17. A computer program product comprising a computer program that, when executed by a processor, implements... The power consumption suppression method according to any one of claims 1-13.

18. A chip, characterized in that, The chip includes a processing unit and an interface circuit. The processing unit obtains program instructions through the interface circuit, and the program instructions are executed by the processing unit. The processing unit is used to perform the steps of the power consumption suppression method according to any one of claims 1-13.

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