Anti-deadlock method and device based on AXI bus data reordering

Abstract

The invention relates to an anti-deadlock method and device based on AXI bus data reordering, and the method comprises the steps: introducing data caching, reordering and a virtual handshake mechanism in a data transmission process, and guaranteeing that the communication between a plurality of master devices and a plurality of slave devices can avoid a deadlock phenomenon caused by out-of-order transmission. By dynamically adjusting the transmission sequence and the response sequence of the data, the data transmission efficiency of the system can be effectively improved, and the stability and the reliability of the AXI bus in a complex multi-master-device and multi-slave-device system are guaranteed.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and particularly relates to a deadlock prevention method and device based on AXI bus data reordering. Background Art

[0002] The AXI (Advanced eXtensible Interface) protocol is designed by ARM, which has high flexibility and scalability, supports parallel data transmission of multiple master devices and multiple slave devices, and is widely used in modern systems that require efficient data exchange. The control of its address and data is separated, and there are a total of five channels, including: read address channel (AR channel), read data channel (R channel), write address channel (AW channel), write data channel (W channel), and write response channel (B channel). Its core design concept is to improve data transmission efficiency through multiple independent channels, forming a full-duplex working mechanism.

[0003] The AXI 4.0 protocol is a kind of AMBA (Advanced Microcontroller Bus Architecture) protocol proposed by ARM. This protocol controls the order of data transmission through ID flags. For data transmission, the AW channel carries the ID flag AWID of the current write request, and the AR channel carries the ID flag ARID of the current read request. The data transmission between the slave device and the master device Master can be completed through multiple responses with ID flags. These responses will carry the requests with ID flags. The R channel carries the read data ID flag RID for responding to the read request, and the B channel carries the write data written ID flag BID for responding to the write request.

[0004] The Outstanding mechanism in the AXI protocol refers to the ability of the host to initiate multiple read and write requests without receiving a response. This mechanism allows the host to continue sending new requests while waiting for a response, thereby improving the efficiency of data transfer. Without the Outstanding mechanism, the behavior of the bus Master in a read operation would be to send a read address command through the AR channel and wait for the read data to be returned on the R channel; in a write operation, the behavior would be to send a write address command through the AW channel, then send the write data through the W channel, and finally wait for the write response to be returned on the B channel. If the Outstanding mechanism is supported, the bus can continuously send multiple read or write commands without waiting for a response and then wait for the return of each command one by one. The bus Master will continuously send multiple read address commands through the AR channel in a read operation and then wait for the read data for different read requests to be returned on the R channel; in a write operation, the behavior will be to continuously send multiple write address commands through the AW channel, and at the same time, after preparing the data, send multiple write data for different write requests through the W channel, and finally wait for the B channel to return the response that the data for multiple different write commands has been written.

[0005] One use of the ID in the AXI protocol is that we can disrupt the order of data transmission. In a complex SOC system, there are different types of Slave spatial addresses. Some of the memory corresponding to the Slave spatial addresses has a relatively fast response speed, while some have a relatively slow response. Taking read requests as an example, when the bus Master reads data from a memory with a relatively slow response speed, the data will arrive at the bus Master later than when reading data from a memory with a relatively fast response speed. If the bus Master first issues a read request for data from the slow memory and then sends a read request for data from the fast memory, if the Master has to wait for the response from the slow memory all the time, it will block the response of the fast memory, and the bus performance will decrease. Therefore, the Out of order mechanism of the AXI bus is to solve such a problem. Out of order is based on the Outstanding mechanism. In the implementation of read out of order, the bus Master can issue multiple read commands with the same ARID. The read data under the same ARID read request must return in the order of the Master's read address command. For read address commands with different ARIDs, the read data can be returned to the bus Master in a different order from the order in which the read address commands are sent. For write out of order, the use of the WID signal in the W channel has been cancelled in AXI4, and write out of order is no longer supported. That is, the write data sent through the W channel is completely sent in the order of the write address command in the AW channel. However, the B channel still supports out of order transmission. If the Slave device has completed all the writes of the write data, the device with a faster response can first transmit the write response to the bus Master without having to respond in the order of the write address command.

[0006] Although the AXI protocol provides an efficient data transfer mechanism and supports parallel operations, it will face deadlock problems in complex multi-master and multi-slave systems. Deadlocks are usually caused by circular dependencies between multiple masters and multiple slaves. For example, when two bus Masters read two slaves, if Master1 sends requests with ARID all equal to 0 to Slave1 and Slave2 successively, and at the same time Master2 also sends requests with ARID all equal to 0 to Slave2 and Slave1 successively. In the designed interconnect structure, the Slave will add some bits to the ARIDs from different sources to distinguish different masters. For example, the ARID sent by Master1 becomes 10 after passing through the interconnect structure, and the ARID sent by Master2 becomes 20 after passing through the interconnect structure. For the Slave, these are different ARID numbers and can be transmitted out of order. For the two Masters, it is the data transfer with the same ARID, and the data should be transmitted in the order of the read address commands. Master1 can only receive the data from Slave1 first and then the data from Slave2, and Master2 can only receive the data from Slave2 first and then the data from Slave1. They have only one correct response order. Because of out-of-order transmission, Slave1 and Slave2 have two correct response orders, either responding to Master1 first or Master2 first. If Slave1 responds to Master2 first and Slave2 responds to Master1 first at this time, it violates the principle that data transmission with the same ID must be in the order of the read address commands, resulting in both masters and both slaves waiting and causing a system deadlock. This is the reason for the deadlock caused by out-of-order transmission of read requests.

[0007] The Outstanding transfer access mechanism of the AXI protocol allows the bus Master to issue the next write data address command without waiting for the completion of the previous write data address command. Although a Master can initiate multiple commands simultaneously on the AW channel to negotiate access rights to multiple Slaves, within one transfer cycle, only one Slave is allowed to exchange data with the uniquely authorized Master on the W channel. Due to the above mechanism, in multi-Master multi-Slave data exchange, there is another risk of deadlock caused by the Outstanding mechanism. For example, when two bus masters perform write access to two Slaves, at the beginning, Master1 sequentially and continuously issues two write address commands to Slave2 and Slave1; then, Master2 sequentially and continuously issues two write address commands to Slave1 and Slave2. Since the path delay between Slave1 and Master1 is less than the path delay between Slave2 and Master1, the write address command sent by Master1 to Slave1 arrives first despite being sent later, arriving at Slave1 before the write address command sent by Master2 to Slave1, and obtaining the access right to Slave1. At this time, Slave1 opens the W channel and waits for the write data from Master1. Similarly, since the path delay between Slave2 and Master2 is less than the path delay between Slave2 and Master1, the write address command sent by Master2 to Slave2 arrives first despite being sent later, arriving at Slave2 before the write address command sent by Master1 to Slave2, and obtaining the access right to Slave2. At this time, Slave2 opens the W channel and waits for the write data from Master2. For the Master, the write data must be transmitted in the order of the write address commands. Master1 has to send data to Slave2 first, and Master2 has to send data to Slave1 first. However, now Slave1 is waiting for the data from Master1 and does not accept the data from Master2, and Slave2 is waiting for the data from Master2 and does not accept the data from Master1. Thus, a situation of circular waiting is formed, and the bus transmission falls into deadlock. This is the reason for the deadlock caused by the Outstanding mechanism for write requests.

[0008] Due to issues such as out-of-order transmission allowed by the AXI protocol and transmission path delays, when data does not match the request, the master and slave devices will enter a deadlock state. When one master-slave device affects multiple master-slave devices, a system bus deadlock will occur.

[0009] To avoid the deadlock problem in the AXI protocol, there are mainly two existing solutions: the Single Slave method and the Single Slave Per ID method. In the Single Slave method, if the read and write address commands sent through the Outstanding mechanism are sent to different Slave devices, the continuous sending of subsequent read and write address commands is suspended. After ensuring that the current read and write address request is completed, the next request is sent to prevent deadlocks. This method is simple and easy to understand and implement, but its main problem is that it will cause a reduction in data bandwidth because the master device cannot initiate a new request while waiting for the previous request to complete, resulting in a delay in data transmission. It can only implement the Outstanding transmission mechanism for the same device.

[0010] Single Slave Per ID is more flexible than the Single Slave mechanism. If the corresponding IDs of the read and write address commands sent through the Outstanding mechanism are inconsistent or the IDs are the same but they are sent to the same Slave device, the Outstanding mechanism is still supported. If the IDs are the same and they are sent to different Slave devices, the continuous sending of subsequent read and write address commands is suspended. After ensuring that the current read and write address request is completed, the next request is sent to prevent deadlocks. This method has better support for out-of-order transmission of read requests, but it cannot solve the deadlock problem faced when writing data. Summary of the Invention

[0011] The object of the present invention is to provide a deadlock prevention method and device based on AXI bus data reordering in view of the deficiencies of the existing methods.

[0012] To achieve the above object, the present invention adopts the following technical solutions: A deadlock prevention method based on AXI bus data reordering, the method comprising: Monitoring the response time of the master-slave device interaction; When the response time exceeds a preset threshold, constructing a virtual handshake signal to complete the response to the master device or the slave device, and reading the write data from the master device or the read data from the slave device transmitted on the bus; Storing the write data or the read data into a cache module; After reordering the data in the cache module according to the address order of the read request command or the write request command, sending the data to the master device or the slave device in sequence.

[0013] As a preferred embodiment, the monitoring of the response time of the master-slave device interaction includes monitoring the response time of the master device to the write data sent by the slave device, and monitoring the response time of the slave device to the read data returned by the master device.

[0014] As a preferred implementation, the method of monitoring the response time of the master-slave device interaction is: Monitor the time that the DATA and VAILD signals of the R channel and the W channel remain valid. If the time that the signal remains valid exceeds the preset threshold, perform subsequent virtual handshake signal processing.

[0015] As a preferred implementation, when the master device sends a read request command or a write request command, the cache module sequentially caches the sending address of the read request command or the sending address of the write request command as a label; The write data from the master device or the read data from the slave device is stored under the corresponding tag.

[0016] As a preferred implementation, the virtual handshake signal includes a slave device handshake signal simulating a response mechanism of the slave device, and a master device handshake signal simulating a response mechanism of the master device; According to the deadlocked device, a corresponding virtual handshake signal is triggered to release the deadlock state of the device.

[0017] A second object of the present invention is to provide an anti-deadlock device based on AXI bus data reordering, the device comprising: A deadlock monitoring unit, monitoring the response time of the interaction between the master and slave devices, and starting the virtual handshake unit when the response time exceeds a preset threshold; A data cache unit, which sequentially caches the sending addresses of the read request command or the write request command as tags; A virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module; the host handshake unit or the slave handshake unit sends a simulated response signal to the master device or the slave device according to the deadlocked channel, and receives data from the bus, the bus channel judgment module judges the channel ID of the data received from the bus according to the bus interconnection channel information, and stores it in the address label corresponding to the data buffer module, and sends the data to the master device or the slave device in the order of the address labels.

[0018] As a preferred implementation, the anti-deadlock device is integrated into the bus interconnection channel and the AXI bus interface of the master device or the slave device.

[0019] As a preferred implementation, the data cache unit uses BRAM to cache data.

[0020] A third object of the present invention is to provide a computer device, comprising a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0021] The fourth object of the present invention is to provide a computer-readable storage medium, on which a computer program / instructions are stored, and when the computer program / instructions are executed by a processor, the steps of the above method are implemented.

[0022] The fifth object of the present invention is to provide a computer program product, which includes a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the above method are implemented.

[0023] The present invention has the following beneficial effects: (1) By introducing data caching, reordering, and virtual handshake mechanisms during data transmission, the method of the present invention ensures that data can be transmitted in the correct order, avoids the occurrence of deadlocks, and at the same time maintains the high throughput and flexibility of the system as much as possible. By dynamically adjusting the data transmission order and response order, the present invention can effectively improve the data transmission efficiency of the system and ensure the stability and reliability of the AXI bus in a complex multi-master and multi-slave device system.

[0024] (2) The device of the present invention is suitable for masters with high requirements for real-time performance and has a low tolerance for bus latency, such as high-frame-rate LCD devices. By combining a data caching unit, a virtual handshake unit, and a deadlock monitoring unit, the deadlock problem caused by bus latency or out-of-order transmission is effectively solved, ensuring the data transmission stability and real-time performance of high-frame-rate display devices. At the same time, the device of the present invention can maintain a high throughput in a complex multi-master and multi-slave device environment, meeting the stringent requirements for high performance and low latency in similar scenarios.

[0025] (3) Different from the method of solving deadlocks by suspending requests and abandoning the Outstanding feature of the AXI bus, the present invention can configure the data depth of the data caching unit according to the device's requirements for latency, and to a certain extent, restore the transmission ability of the bus Outstanding transmission mechanism. Description of the Drawings

[0026] Figure 1 Schematic diagrams of data transmission in different situations for read data.

[0027] Figure 2 Schematic diagrams of data transmission in different situations for write data status.

[0028] Figure 3 Schematic diagram of the structure of the device of the present invention.

[0029] Figure 4 Schematic diagram of the device of the present invention accessing an AXI interconnect device.

[0030] Figure 5 Flowchart of the method of the present invention. Detailed Embodiments

[0031] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0032] Figure 1 、 Figure 2 Illustrates the data transmission situations in different cases when reading data and writing data in the present invention and the prior art, so as to explain the action mechanism of the method of the present invention.

[0033] In the case of read deadlock, multiple master devices send read requests to multiple slave devices. When the AR channel IDs are the same, the master device expects to receive responses in the order of the addresses of the sent requests. However, due to the out-of-order transmission of the slave device or the transmission path delay, the master device cannot receive the data responses sent in the order of the transmission addresses, resulting in a deadlock. This leads to a situation where multiple master devices wait for multiple slave devices, causing a deadlock in the system. The data reordering mechanism can accept the read data transmitted from the bus and reorder it when the response data of multiple read requests does not arrive in the order of the read address commands, causing a deadlock, and send the sorted data to the master device to ensure that the data is received in the correct order of the read address commands, avoiding the occurrence of deadlock, as Figure 1 shown.

[0034] In the case of write deadlock, multiple master devices send write requests to multiple slave devices. Due to path delay, register insertion for clock gating to relieve timing tension, or other hardware factors, the write requests received by the slave device may not arrive in the order of the write address commands sent by the master device, thus incorrectly opening the write data channel to the master device. The master device needs to send write data according to the write address command, but the sent write data does not conform to the order of the write address commands accepted by the slave device, resulting in a write deadlock for a single master-slave device, and also leading to a situation where multiple master-slave devices wait for each other, causing a deadlock in the system. The data reordering mechanism can accept the write data transmitted from the bus and reorder it when the master device sends write data and the slave device does not accept it, resulting in a deadlock, and send the sorted data to the slave device to ensure that the data is received in the order of the write address commands accepted by the slave device, avoiding the occurrence of deadlock, as Figure 2 shown.

[0035] Based on the above principles, the present invention designs a deadlock prevention device based on AXI bus data reordering, as Figure 3 shown. This device has a total of three modules: a data cache unit, a virtual handshake unit, and a deadlock monitoring unit. The deadlock prevention device is integrated into the bus interface of the master and slave devices, as Figure 4 shown.

[0036] The deadlock monitoring unit monitors the response time of the interaction between the master and slave devices, and starts the virtual handshake unit when the response time exceeds a preset threshold.

[0037] The data cache unit sequentially caches the sending addresses of the read address command or the write address command as tags; The virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module; the host handshake unit or the slave handshake unit sends a simulated response signal to the master device or the slave device according to the channel where the deadlock occurs, and receives data from the bus, and the bus channel judgment module judges the address corresponding to the channel of the data received from the bus according to the bus interconnection channel information, and stores it in the address label corresponding to the data buffer module, and sends the data to the master device / slave device in the order of the address labels.

[0038] In one embodiment, the deadlock monitoring unit monitors whether the current master and slave devices are in a deadlock state. If, when data arrives, the master device or the slave device does not respond to the data, and the response time exceeds the monitoring judgment threshold, it is determined that a deadlock has occurred and the data is no longer sent to the corresponding master and slave devices, and the data is received by the virtual handshake unit.

[0039] In one embodiment, the deadlock monitoring unit monitors the response of the R channel and the W channel to perform deadlock monitoring. Specifically, when deadlock occurs, the data of the DATA channel and the valid flag of the VAILD channel (RDATA and RVALID of the R channel, WDATA and WVALID of the W channel) will be kept. In this embodiment, the upper limit threshold of time is set to determine whether the retention time of the valid flag of the data is normal. If it exceeds the normal retention upper limit set by the threshold, it will be determined that a deadlock has occurred. Then the virtual handshake unit is activated to respond to release the deadlock.

[0040] In the process of reading data, the R channel responds to the read request and returns the data. In the R channel, if the master device cannot accept the read data, RRESP and RREADY will not be in the valid position. When the slave device is on the R channel, RDATA and RVALID will always maintain valid data and the valid position of the data, which will cause deadlock.

[0041] In the process of writing data, the master device sends the write data to the slave device through the W channel. In the W channel, if the slave device cannot accept the write data, WREADY will not be in the valid position. When the master device is on the W channel, WDATA and WVALID will always maintain valid data and the valid position of the data, which will cause deadlock.

[0042] Based on the above deadlock formation mechanism, we monitor the response of the R channel and the W channel to determine whether a deadlock occurs.

[0043] In one embodiment, the data cache unit uses BRAM to store address tags and read / write data. The BRAM is configured into multiple independent storage blocks according to the data depth, and the number of blocks is determined by the data cache depth. As Figure 3 shown, the content cached by the data cache unit includes address tags (ADDR1, ARRD2... ADDRN), and BURST transfer data packets corresponding to the address tags.

[0044] For read deadlock, the data cache unit caches the address of the read request command sent by the master device as a tag, and rearranges the different slave device data returned by different AXI channels according to this tag. The final result can meet the requirement that the read data returned by the master device under the same ID must be in the same order as the sent read request command.

[0045] For write deadlock, the data cache unit caches the address of the write request command sent by the master device as a tag, and caches the master device data that is sent to different AXI channels but falls into write deadlock according to this tag. If the write data is sent to the slave device in the order of the cached addresses, it does not conform to the order of the write request addresses accepted by the slave device, because the order of the write data in the cache unit is the order of the addresses of the write requests sent by the master device. Due to other hardware reasons such as path delay and register insertion for pipelining, the order of the write requests accepted by the slave device is unknown to the master device. Therefore, only by reordering and sending the data in the data cache unit can it be seen whether it conforms to the order of the accepted addresses of the slave device (in this patent, it is to select the cached write data under the next address tag in the data cache unit, and the virtual handshake unit simulates the master device to send the write data to the slave device under the corresponding address tag again to see whether the slave device accepts).

[0046] Specifically, in the case of reading data, the data cache unit sequentially caches the sending address of the read address command as a label. The storage method is to start storage from the last block of the BRAM. When there is a next read address command sending address, the label previously stored in the last storage block is moved to the previous storage block, and the new read command address is stored in the last storage block, and so on. When the read command address has been moved to the first storage block, and there is a new read address command sending address, the address of the first storage block is moved out, and the new read address command is stored in the last storage block. If a read deadlock occurs, the address of the slave module that responds to the read request and sends back the read data is determined through the bus interconnection channel, and the read data is stored in the corresponding label of the data cache unit to reorder the read data. In the case of read deadlock, since the read data does not conform to the read address sequence initiated by the master device, the master device cannot accept it. The virtual handshake unit responds to the handshake of the slave device and accepts the read data, and stores it in the data cache unit under the corresponding label according to the bus interconnection channel information to complete the reordering. When the address sequence of the read request initiated by the master device is met, the virtual handshake unit simulates the slave device sending the read data in the address sequence.

[0047] In the case of writing data, the data cache unit caches the sending address of the write address command in sequence as a label. The method is consistent with the storage method in the case of reading data. If a write deadlock occurs, the address of the slave module that has not responded to the write request to write the write data is determined through the bus interconnection channel, and the write data is stored in the corresponding label of the data cache unit for subsequent selection of the W channel. In the case of write deadlock, since the write data does not conform to the write address command sequence accepted by the slave device, the slave device cannot accept it. The virtual handshake unit responds to the handshake of the master device and accepts the write data, which is stored in the data cache unit under the corresponding label according to the bus interconnection channel information. The virtual handshake unit can simulate the master device sending write data to the slave device. If no response is detected from the slave device, the cached write data under the next address label in the data cache unit is selected, and the virtual handshake unit simulates the master device to send write data to the slave device again.

[0048] In one embodiment, the execution process of each unit of the virtual handshake unit is described as follows: The virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module.

[0049] The host handshake unit is used to imitate the response mechanism of the slave device to release the deadlock state of the master device, or to send sorted read data to the master device. The execution process is as follows: (1)Release the master device deadlock state: The master device enters the deadlock state because write data cannot be written to the slave device. On the W channel, WDATA and WVALID will always maintain valid data and the valid bit of this data. The host handshake unit is responsible for pulling up WREADY and sending a signal to the master device that the slave device is ready to accept write data. After receiving the WREADY signal, the master device starts to update WDATA until the last batch of data and pulls up WLAST. After detecting the pull-up of WLAST, restore WREADY and pull up BRESP and BVAILD on the B channel. When detecting the BREADY signal of the master device, restore BRESP and BVAILD on the B channel to release the master device deadlock.

[0050] (2)Send data to the master device: During the read data process, in the case of the same ID, the master device needs to receive the data sent by the slave device in the order in which the master device sends the read address. On the R channel, the host handshake unit sends data in RDATA and pulls up RVAILD. When detecting that both RREADY and RRESP are pulled up, send the next batch of data until the last batch of data is sent. When sending the last batch of data, pull up RLAST, and then restore the RDATA, RVAILD, and RLAST signals.

[0051] The slave handshake unit is used to imitate the response mechanism of the master device to release the deadlock state of the slave device or send sorted write data to the slave device. Its execution processes are as follows: (1)Release the slave device deadlock state: The slave device enters the deadlock state because read data cannot be written to the master device. On the R channel, RDATA and RVALID will always maintain valid data and the valid bit of this data. The slave handshake unit is responsible for pulling up RREADY and RRESP and sending a signal to the slave device that the master device is ready to accept read data. After the slave device receives the RREADY signal and the RRESP signal, it starts to update RDATA until the last batch of data and pulls up RLAST. After detecting the pull-up of RLAST, restore the WREADY and RRESP signals to release the slave device deadlock.

[0052] (2)Send data to the slave device: Sending data to the slave device is because during the write data process, the slave device needs to receive the data sent by the master device in the order in which the slave device accepts the write address. On the W channel, the slave handshake unit sends data in WDATA and pulls up WVAILD. When detecting the pull-up of WREADY, send the next batch of data until the last batch of data is sent. When sending the last batch of data, pull up WLAST, and then restore the WDATA and WVAILD signals and pull up the BREADY signal on the B channel. When detecting the BRESP and BVAILD signals of the slave device, restore the BREADY signal on the B channel.

[0053] The bus channel judgment module determines the high - order address information based on the AXI channel through which data is transmitted in the bus interconnection channel, and thus stores the transmitted data under the corresponding address label in the data cache unit.

[0054] Specifically, in the case of read deadlock, since the slave device does not transmit out - of - order when receiving read requests sent by the same master device with the same ID, but transmits read data in the order of receiving requests, the bus channel judgment module determines the high - order address information of the read data sent by the slave device according to the channel through which the read data is transmitted in the bus interconnection channel, and then can cache it according to the order of the address labels already cached in the data cache unit.

[0055] In the case of write deadlock, the master device sends write data according to the order of the addresses of the write requests it sends. The bus channel judgment module determines the high - order address information of the write data sent by the master device according to the channel through which the write data is transmitted in the bus interconnection channel, and then can cache it according to the order of the address labels already cached in the data cache unit.

[0056] Based on the above - shown process, in the case of read deadlock, the slave handshake unit simulates the response of the master device to release the deadlock state of the slave device, and the master handshake unit sends the sorted read data to the master device. In the case of write deadlock, the master handshake unit simulates the response of the slave device to release the deadlock state of the master device, and the slave handshake unit sends the sorted write data to the slave device.

[0057] During use, connect the deadlock prevention device to the bus interfaces of the master and slave devices.

[0058] In one embodiment, the deadlock prevention device is connected to the bus interfaces of the master and slave devices, as Figure 4 shown. Due to the instability of the slave device, in this embodiment, it is selected to integrate the deadlock prevention device into the master device end.

[0059] In one embodiment, the execution processes of the modules in the deadlock prevention device are as Figure 5 shown, including the following processes: Step 1: The deadlock monitoring unit monitors whether there is a situation where no response occurs even after exceeding the detection and judgment threshold during the data interaction between the master and slave devices. If so, start the virtual handshake unit.

[0060] Step 2: The master handshake unit or the slave handshake unit of the virtual handshake unit simulates the response of the slave device or the master device, and receives the read data from the slave device or the write data from the master device.

[0061] Step 3: The bus channel judgment module judges the address information corresponding to the transmitted data according to the information of the bus interconnection channel, and stores the data under the corresponding address label in the data cache unit. Each piece of data entering this unit has an address label for data identification.

[0062] Step 4: The host handshake unit or the slave handshake unit simulates the master device to send data to the slave device, or simulates the slave device to send data to the master device to solve the deadlock problem.

Claims

1. An anti-deadlock method based on AXI bus data reordering, characterized in that: The method comprises: Monitor the response time of master-slave device interactions; When the response time exceeds a preset threshold, a virtual handshake signal is constructed to complete the response to the master device or the slave device, and the write data from the master device or the read data from the slave device transmitted by the bus is read; storing the write data or read data in a cache module; After reordering the data in the cache module according to the address sequence of the read request command or the write request command, the data is sent to the master device or the slave device in sequence.

2. The method according to claim 1, characterized in that The monitoring of the response time of the interaction between the master and slave devices includes monitoring the response time of the master device to the write data sent by the slave device, and monitoring the response time of the slave device to the read data returned by the master device.

3. The method according to claim 1, characterized in that The method of monitoring the response time of the master-slave device interaction is: Monitor the time that the DATA and VAILD signals of the R channel and the W channel remain valid. If the time that the signal remains valid exceeds the preset threshold, perform subsequent virtual handshake signal processing.

4. The method according to claim 1, characterized in that: When the master device sends a read request command or a write request command, the cache module sequentially caches the sending address of the read request command or the sending address of the write request command as a label; The write data from the master device or the read data from the slave device is stored under the corresponding tag.

5. The method according to claim 1, characterized in that The virtual handshake signal includes a slave device handshake signal simulating a response mechanism of the slave device, and a master device handshake signal simulating a response mechanism of the master device; According to the deadlocked device, a corresponding virtual handshake signal is triggered to release the deadlock state of the device.

6. An anti-deadlock device based on AXI bus data reordering, characterized in that: The device comprises: A deadlock monitoring unit, monitoring the response time of the interaction between the master and slave devices, and starting the virtual handshake unit when the response time exceeds a preset threshold; A data cache unit, which sequentially caches the sending addresses of the read request command or the write request command as tags; A virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module; the host handshake unit or the slave handshake unit sends a simulated response signal to the master device or the slave device according to the deadlocked channel, and receives data from the bus, the bus channel judgment module judges the channel ID of the data received from the bus according to the bus interconnection channel information, and stores it in the address label corresponding to the data buffer module, and sends the data to the master device or the slave device in the order of the address labels.

7. The anti-deadlock device according to claim 6, characterized in that: The anti-deadlock device is integrated into the bus interconnection channel and the AXI bus interface of the master device or the slave device.

8. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method described in any one of claims 1 to 5 are implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method described in any one of claims 1 to 5 are implemented.

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