Command stream detection method and device, electronic equipment and storage medium

Abstract

The invention relates to a command stream detection method and device, electronic equipment and a storage medium, and the method comprises the steps: receiving a to-be-processed command stream driven and issued by a first processor in response to a target simulation model, and obtaining type configuration information from the to-be-processed command stream, the target simulation model being used for simulating a second processor; according to the type configuration information, an analysis unit group matched with the to-be-processed command stream is determined, and the analyzer comprises an analysis unit group used for being matched with different second processors; and according to the target simulation model and the analysis unit group, performing analysis processing on the to-be-processed command stream, and determining analysis information. According to the embodiment of the invention, the process of executing the to-be-processed command stream by the second processor can be analyzed and inspected, so that the detection process of the to-be-processed command stream becomes clear and visual, and the efficiency of debugging driver development is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a command stream detection method and apparatus, an electronic device, and a storage medium. Background Art

[0002] In fields such as graphics rendering, scientific computing, and artificial intelligence, in order to improve task processing efficiency, a Central Processing Unit (CPU) and a Graphic Processing Unit (GPU) work together. The CPU is responsible for the overall scheduling and logical control of tasks, and the GPU is responsible for executing specific computing tasks. For example, in deep learning, the CPU can be responsible for data loading, preprocessing, and model scheduling, and the GPU can be responsible for executing the model training and inference processes. This division of labor enables deep learning tasks to be completed in a shorter time.

[0003] In the above process, the CPU driver usually configures a lot of control commands and distributes them to corresponding memory organizations. Each time the CPU driver issues a command and passes it to the GPU, it determines the operation sequence and operation logic of the GPU pipeline. The combination of these control command structures can be called a command stream. The command stream will be filled and assembled in segments by the CPU driver. Command stream inspection plays an important role in the process of driver development and maintenance, and can help developers improve the efficiency of debugging driver development. Summary of the Invention

[0004] The present disclosure proposes a technical solution for command stream detection.

[0005] According to one aspect of the present disclosure, there is provided a command stream detection method, which is applied to a parser and includes: in response to a target simulation model receiving a to-be-processed command stream sent by a first processor driver, obtaining type configuration information from the to-be-processed command stream, where the target simulation model is used to simulate a second processor; determining a parsing unit group matching the to-be-processed command stream according to the type configuration information, where the parser includes parsing unit groups for matching different second processors; and parsing the to-be-processed command stream according to the target simulation model and the parsing unit group to determine parsing information.

[0006] In a possible implementation manner, parsing the to-be-processed command stream according to the target simulation model and the parsing unit group to determine parsing information includes: registering at least one type of access callback function to the target simulation model by using the parsing unit group; and receiving, by using the parsing unit group, the parsing information returned by the access callback function, where the access callback function is triggered when the target simulation model executes the to-be-processed command stream.

[0007] In a possible implementation, the access callback function includes a register access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the register access callback function to the register access interface of the target simulation model, where the register access callback function is used to read values from the registers of the target simulation model; receiving the parsing information returned by the access callback function, including: receiving the register parsing information returned by the register access callback function, where the register parsing information includes the values read from the registers of the target simulation model by the to-be-processed command stream when the target simulation model executes the to-be-processed command stream. Among them, the trigger condition of the register access callback function is: the read operation performed by the target simulation model on the registers in the target simulation model according to the indication of the to-be-processed command stream.

[0008] In a possible implementation, the access callback function includes a first video memory access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the first video memory access callback function to the video memory access interface of the target simulation model, where the first video memory access callback function is used to obtain the structural information between multiple commands included in the to-be-processed command stream; receiving the parsing information returned by the access callback function, including: receiving the command structure parsing information returned by the first video memory access callback function, where the command structure parsing information includes the structural information between multiple commands included in the to-be-processed command stream when the target simulation model executes the to-be-processed command stream. Among them, the trigger condition of the first video memory access callback function is: the read operation performed by the target simulation model on the to-be-processed command stream stored in the video memory of the target simulation model according to the indication of the to-be-processed command stream.

[0009] In a possible implementation, the access callback function includes a second video memory access callback function and an instruction parsing callback function. Registering at least one type of access callback function to the target simulation model includes: registering the second video memory access callback function to the video memory access interface of the target simulation model, and registering the instruction parsing callback function to the instruction execution module of the target simulation model. The second video memory access callback function is used to obtain the current command of the command stream to be processed, and the instruction parsing callback function is used to obtain the instruction data of the current command in the command stream to be processed; receiving the parsing information returned by the access callback function, including: receiving the first parsing information returned by the second video memory access callback function, and the second parsing information returned by the instruction parsing callback function. The first parsing information includes the current command in the command stream to be processed executed by the target simulation model, and the second parsing information includes the instruction data of the current command. Wherein, the triggering conditions of the second video memory access callback function and the instruction parsing callback function are: the target simulation model performs a read operation on the instruction data in the target simulation model according to the indication of the command stream to be processed, and the instruction data includes the operation data of the arithmetic logic unit in the target simulation model; determining the instruction parsing information according to the first parsing information and the second parsing information.

[0010] In a possible implementation, in response to the target simulation model receiving the command stream to be processed sent by the first processor driver, obtaining the type configuration information from the command stream to be processed includes: in response to the front-end module of the target simulation model receiving the command stream to be processed sent by the first processor driver, receiving the command stream to be processed forwarded by the front-end module; obtaining the type configuration information according to the identification information carried by the command stream to be processed.

[0011] In a possible implementation, the type configuration information includes chip type configuration information and pipeline type configuration information. Determining the parsing unit group matching the command stream to be processed according to the type configuration information includes: determining at least one group of parsing unit groups matching the chip type of the second processor according to the chip type configuration information; determining the parsing unit group matching the pipeline type of the command stream to be processed from at least one group of parsing unit groups matching the second processor according to the pipeline type configuration information, where the pipeline type includes a graphics display pipeline and a computing pipeline.

[0012] In a possible implementation, the method further includes: generating a log file according to the type configuration information and the parsing information, each log file corresponding to a command stream to be processed; writing the log file into the storage space of the parser in the order in which the target simulation model receives the command stream to be processed.

[0013] According to one aspect of the present disclosure, a command stream detection device is provided. The device is applied to a parser and includes: an acquisition module configured to obtain type configuration information from a to-be-processed command stream in response to a target simulation model receiving the to-be-processed command stream driven and issued by a first processor, where the target simulation model is used to simulate a second processor; a first determination module configured to determine a set of parsing units matching the to-be-processed command stream according to the type configuration information, where the parser includes sets of parsing units for matching different second processors; and a second determination module configured to perform parsing processing on the to-be-processed command stream according to the target simulation model and the set of parsing units to determine parsing information.

[0014] In a possible implementation, the second determination module is configured to: register at least one type of access callback function to the target simulation model by using the set of parsing units; and receive parsing information returned by the access callback function by using the set of parsing units, where the access callback function is triggered when the target simulation model executes the to-be-processed command stream.

[0015] In a possible implementation, the access callback function includes a register access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the register access callback function to a register access interface of the target simulation model, where the register access callback function is used to read a value from a register of the target simulation model; and receiving parsing information returned by the access callback function includes: receiving register parsing information returned by the register access callback function, where the register parsing information includes a value read from a register of the target simulation model by the to-be-processed command stream when the target simulation model executes the to-be-processed command stream, and a trigger condition of the register access callback function is: a read operation performed on a register in the target simulation model by the target simulation model according to an instruction of the to-be-processed command stream.

[0016] In a possible implementation, the access callback function includes a first video memory access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the first video memory access callback function to the video memory access interface of the target simulation model. The first video memory access callback function is used to obtain the structural information between multiple commands included in the command stream to be processed. Receiving the parsing information returned by the access callback function includes: receiving the command structure parsing information returned by the first video memory access callback function. The command structure parsing information includes the structural information between multiple commands included in the command stream to be processed when the target simulation model executes the command stream to be processed. Wherein, the trigger condition of the first video memory access callback function is: the target simulation model performs a read operation on the command stream to be processed stored in the video memory of the target simulation model according to the indication of the command stream to be processed.

[0017] In a possible implementation, the access callback function includes a second video memory access callback function and an instruction parsing callback function. Registering at least one type of access callback function to the target simulation model includes: registering the second video memory access callback function to the video memory access interface of the target simulation model, and registering the instruction parsing callback function to the instruction execution module of the target simulation model. The second video memory access callback function is used to obtain the current command of the command stream to be processed, and the instruction parsing callback function is used to obtain the instruction data of the current command in the command stream to be processed. Receiving the parsing information returned by the access callback function includes: receiving the first parsing information returned by the second video memory access callback function and the second parsing information returned by the instruction parsing callback function. The first parsing information includes the current command in the command stream to be processed executed by the target simulation model, and the second parsing information includes the instruction data of the current command. Wherein, the trigger conditions of the second video memory access callback function and the instruction parsing callback function are: the target simulation model performs a read operation on the instruction data in the target simulation model according to the indication of the command stream to be processed. The instruction data includes the operation data of the arithmetic logic unit in the target simulation model. Determining the instruction parsing information according to the first parsing information and the second parsing information.

[0018] In a possible implementation, the obtaining module is configured to: in response to the front-end module of the target simulation model receiving the command stream to be processed sent by the first processor, receive the command stream to be processed forwarded by the front-end module; and obtain the type configuration information according to the identification information carried by the command stream to be processed.

[0019] In a possible implementation, the type configuration information includes chip type configuration information and pipeline type configuration information. The first determination module is configured to: determine at least one set of parsing unit groups that match the chip type of the second processor according to the chip type configuration information; and determine a parsing unit group that matches the pipeline type of the command stream to be processed from at least one set of parsing unit groups that match the second processor according to the pipeline type configuration information, where the pipeline type includes a graphics display pipeline and a computing pipeline.

[0020] In a possible implementation, the apparatus further includes a generation module, configured to: generate a log file according to the type configuration information and the parsing information, where each log file corresponds to a command stream to be processed; and write the log file into the storage space of the parser in the order of receiving the command streams to be processed by the target simulation model.

[0021] According to one aspect of the present disclosure, there is provided an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0022] According to one aspect of the present disclosure, there is provided a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented.

[0023] In contrast to the related art, by examining the data results of the second processor obtained by running on a real second processor chip or a hardware emulation platform (Emulation / Haps), to infer whether the command stream of the drive configuration is correct, software developers need to run on a real second processor chip after tape-out or a hardware emulation platform before chip tape-out, and based on limited log files and data results, statically analyze whether the second processor conforms to the expected operating logic, so as to infer whether the command stream configured by the host driver layer meets the software and hardware requirements. The analysis takes a long time, the debugging efficiency is low, and the intuitiveness of the inspection is poor.

[0024] The command stream detection method according to the embodiments of the present disclosure can parse and inspect the process of the second processor executing the command stream to be processed by setting up a simple and easy-to-use parser, making the detection process of the command stream to be processed clear and intuitive, improving the efficiency of debugging driver development, and enhancing the speed of locating software and hardware interaction problems. Among them, the parser may include a set of parsing units for matching different second processors, and can determine the parsing unit group that matches the command stream to be processed according to the obtained type configuration information, so as to match various second processors, greatly improving the applicability of the command stream detection method according to the embodiments of the present disclosure. In addition, since the target simulation model can replace the real second processor hardware, the performance of the second processor can be verified without real chip fabrication, which is beneficial to advancing the development progress in the pre-chip-fabrication verification stage and ensuring the development quality.

[0025] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, rather than limiting the present disclosure. According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. Brief Description of the Drawings

[0026] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification. These drawings show embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure.

[0027] Figure 1 The flowchart showing the command stream detection method according to the embodiments of the present disclosure.

[0028] Figure 2 The schematic diagram showing the command stream detection method according to the embodiments of the present disclosure.

[0029] Figure 3 The block diagram showing the command stream detection device according to the embodiments of the present disclosure.

[0030] Figure 4 The block diagram showing an electronic device according to an embodiment of the present disclosure. Detailed Embodiments

[0031] The following will detail various exemplary embodiments, features, and aspects of the present disclosure with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] The special term "exemplary" here means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" here does not necessarily need to be construed as superior to or better than other embodiments.

[0033] As used herein, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, both A and B exist simultaneously, and B exists alone. In addition, the term "at least one" as used herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set composed of A, B, and C.

[0034] In addition, to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail to highlight the gist of the present disclosure.

[0035] Figure 1 A flowchart showing a command stream detection method according to an embodiment of the present disclosure is as Figure 1 shown, and the command stream detection method includes:

[0036] In step S11, in response to the target simulation model receiving a command stream to be processed sent by the first processor, type configuration information is obtained from the command stream to be processed, and the target simulation model is used to simulate the second processor.

[0037] In step S12, according to the type configuration information, a set of parsing units matching the command stream to be processed is determined, where the parser includes a set of parsing units for matching different second processors.

[0038] In step S13, according to the target simulation model and the set of parsing units, the command stream to be processed is parsed to determine parsing information.

[0039] In a possible implementation manner, the command stream detection method is applied to a parser, and the command stream detection method can be executed by an electronic device such as a terminal device or a server installed with the parser. The parser is installed in the electronic device, and the electronic device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0040] Exemplarily, the parser can cooperate with a target simulation model for simulating a second processor, and be an application program or software for parsing and processing the command stream to be processed sent by the first processor. For different first processor chip products and the logic of the command stream to be processed in different pipelines, the parser can be used to parse the command stream data sent from the first processor driver layer to the target simulation model for simulating the second processor each time. Among them, the parser can be implemented through programming languages such as assembly language, high-level languages (such as C, C++ etc.), and script languages. The embodiments of the present disclosure do not limit the type of programming code for implementing the parser.

[0041] Exemplarily, the first processor and the second processor can work together. The first processor can be responsible for the overall scheduling and logical control of tasks, and the second processor can perform graphics processing and large-scale parallel computing. The first processor can include but is not limited to: Central Processing Unit (CPU), Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Tensor Processing Unit (TPU), Field Programmable Gate Array (FPGA), etc. The second processor can include but is not limited to Graphic Processing Unit (GPU), General-Purpose Computing on Graphics Processing Units (GPGPU), etc. The embodiments of the present disclosure do not limit the types of the first processor and the second processor.

[0042] In a possible implementation, during the design and verification process before the second processor is taped out, the target simulation model of the second processor can be obtained. For example, the second processor can be software modeled to obtain the target simulation model of the second processor; alternatively, the target simulation model provided by the manufacturer of the second processor can be obtained; or, the simulation model of other processors can be modified to obtain the target simulation model of the second processor. Among them, the target simulation model of the second processor can be implemented through a hardware description language, assembly language, high-level language (such as C, C++ etc.), or scripting language. The embodiments of the present disclosure do not limit the acquisition method of the target simulation model of the second processor. In this way, even if there is no real chip of the second processor, the parser can be used in combination with the target simulation model for simulating the second processor to parse the command stream to be processed sent by the first processor driver, and determine the parsing information. The parser combined with the target simulation model for simulating the second processor can advance the development progress, improve the development efficiency, and temper the software quality in advance for the stage before the chip is taped out, so as to achieve the goal of quickly launching software products after the tape-out.

[0043] Optionally, the target simulation model of the second processor can be set as a lightweight model with accurate data flow, which is used to simulate the software and hardware interfaces and rendering pipeline functions of the second processor. Using the lightweight model can simplify the software design complexity and facilitate the provision of data flow interfaces and software and hardware interaction interfaces.

[0044] Optionally, the target simulation model of the second processor can be set as a heavyweight model with a higher degree of hardware simulation. It can not only be used to simulate the software and hardware interfaces and rendering pipeline functions of the second processor, but also compare and check the data at the register transfer level (RTL). At the same time, it is also more convenient to expose interfaces at the front end of the model to transmit the command stream to be processed sent by the first processor driver.

[0045] In a possible implementation, the parser and the target simulation model of the second processor can be installed on the electronic device where the first processor is located, or the parser and the target simulation model of the second processor can be installed on other electronic devices that can communicate with the electronic device of the first processor.

[0046] Suppose there is a first processor in electronic device A. When electronic device A can communicate with electronic device B and electronic device C through Peripheral Component Interconnect Express (PCIE), Universal Serial Bus (USB), Internet, etc., the target simulation model and parser of the second processor can be installed on the same electronic device, such as electronic device A with the first processor, or electronic device B or electronic device C that can communicate with electronic device A. Optionally, the target simulation model and parser of the second processor can also be installed on different electronic devices. For example, the parser can be installed on electronic device B and the target simulation model of the second processor can be installed on electronic device C; or, the parser can be installed on electronic device A and the target simulation model of the second processor can be installed on electronic device B. The embodiments of the present disclosure do not limit this.

[0047] In a possible implementation manner, in step S11, the first processor driver can configure and encapsulate the command streams to be processed with various structures according to the different behaviors of different application programs. The command streams to be processed can carry the corresponding registers and the instruction data of the second processor. The first processor driver can pass the encapsulated command streams to be processed to the kernel layer, and then through the virtual memory protocol of the virtual prototype platform, pass the command streams to be processed to the target simulation model used to simulate the second processor. The processing command streams can carry the configuration information of the relevant registers and the instruction data indicating various operations of the second processor. In response to the target simulation model used to simulate the second processor receiving the command streams to be processed sent by the first processor driver, the parser can obtain the type configuration information from the command streams to be processed.

[0048] For example, the front-end module (such as the input interface) of the target simulation module used to simulate the second processor receives the command streams to be processed and exposes the data interface to forward them to the parser. After receiving the command streams to be processed sent by the target simulation model used to simulate the second processor, the parser can determine the type configuration information from the command streams to be processed. The type configuration information can include information such as the chip category and pipeline category of the second processor. After obtaining the type configuration information, the parser can be used to identify which type of second processor chip the current command stream to be processed belongs to and which pipeline of this type of second processor it belongs to.

[0049] After obtaining the type configuration information in step S11, the parser can, in step S12, determine the parsing unit group that matches the command streams to be processed according to the type configuration information.

[0050] In the example, multiple parser unit groups can be set in the parser. Different parser unit groups match second processors of different types (or different pipelines). Through the type configuration information, the parser can enter different parsing paths and select the parser unit group that matches the command stream to be processed, so as to be compatible with various second-processor chip products and the graphics display pipeline or computing pipeline of each second-processor chip product.

[0051] In step S12, the parser unit group is determined. In step S13, the command stream to be processed can be parsed according to the target simulation model and the parser unit group to determine parsing information, which is used to parse and inspect the logic of the second-processor pipeline, facilitating software or hardware developers to query or inspect the content of the command stream to be processed based on the parsing information, so as to quickly locate software and hardware problems and greatly improve the efficiency of debugging driver development.

[0052] It should be understood that since the parser is built on the target simulation model for simulating the second processor, the parser has high software interface scalability and can be paired with the target simulation model for simulating different second processors to implement its own parsing function. The more accurate the data of the target simulation model for simulating the second processor, the more accurate the parsing information obtained by the parser.

[0053] In contrast to the related art, where the command stream of the driver configuration is inferred to be correct by inspecting the data results of the second processor obtained by running on a real second-processor chip or a hardware emulation platform (Emulation / Haps), software developers need to run on a real second-processor chip after tape-out or a hardware emulation platform before chip tape-out, and statically analyze whether the second processor conforms to the expected running logic according to limited log files and data results, so as to infer whether the command stream configured by the host driver layer meets the software and hardware requirements. This analysis takes a long time, has low debugging efficiency, and poor visual inspection.

[0054] The command stream detection method of the present disclosure embodiment can parse and inspect the process of the second processor executing the command stream to be processed by setting a simple and easy-to-use parser, making the detection process of the command stream to be processed clear and intuitive, improving the efficiency of debugging driver development, and increasing the speed of locating software and hardware interaction problems. Among them, the parser can include parser unit groups for matching different second processors, and can determine the parser unit group that matches the command stream to be processed according to the obtained type configuration information, so as to match various second processors, greatly improving the applicability of the command stream detection method of the present disclosure embodiment. In addition, since the target simulation model can replace the real second-processor hardware, the performance of the second processor can be verified without real tape-out, which is beneficial to advancing the development progress in the pre-tape-out verification stage and ensuring the development quality.

[0055] Figure 2 A schematic diagram showing a command flow detection method according to an embodiment of the present disclosure is as follows Figure 2 As shown, the command flow detection method can be applied to a parser, which may include a chip selection unit, a pipeline selection unit, a group of parsing units for matching different second processors, and a log collection unit. Each group of parsing units may include a register parsing unit, a control command structure parsing unit, and an instruction parsing unit. Hereinafter, taking Figure 2 as an example, the command flow detection method based on the parser will be described in detail.

[0056] In step S11, in response to the target simulation model receiving the command flow to be processed sent by the first processor, the type configuration information can be obtained from the command flow to be processed.

[0057] In a possible implementation manner, step S11 may include: in response to the front-end module of the target simulation model receiving the command flow to be processed sent by the first processor, receiving the command flow to be processed forwarded by the front-end module; and obtaining the type configuration information according to the identification information carried in the command flow to be processed. The front-end module may be the input interface that first receives data.

[0058] As Figure 2 shown, in response to the input interface of the target simulation model of the second processor receiving the command flow to be processed sent by the first processor, in the target simulation model of the second processor, the input interface as the front-end module can expose the interface to the parser, so as to complete the forwarding of the command flow to be processed. Invoking the parser at the front-end module of the target simulation model of the second processor is the best timing node for inspecting the command flow to be processed. Because after the command flow to be processed encapsulated by the first processor passes through multiple layers of forwarding in the first processor kernel layer and the second processor firmware layer, software developers cannot determine whether the command flow to be processed received by the second processor is correct, and thus cannot predict in advance whether the behavior of the second processor pipeline meets the expectations. However, the input interface as the front-end module in the target simulation model of the second processor does not perform any encapsulation or modification on the command flow to be processed, but forwards it to the parser intact, which helps the parser to inspect the command flow to be processed at the most accurate timing. The parser can obtain the type configuration information according to the identification information carried in the command flow to be processed. The identification information is used to indicate the position of the type configuration information in the command flow to be processed, and may be composed of at least one of text, numbers, letters, and special symbols. The embodiments of the present disclosure do not limit the specific form of the identification information.

[0059] It should be understood that the input interface of the target simulation model of the second processor is a software interface, such as an Application Programming Interface (API), which allows interaction between different software applications. Through the API interface, one software application can request services or data from another software application.

[0060] It can be seen that in the command flow detection method of the embodiments of the present disclosure, since both the target simulation model and the parser are software written in code, their functions, states, operation processes, etc. are transparent to users (such as software developers). The parser can be called at the front-end module of the target simulation model of the second processor as the best timing node for inspecting the command flow to be processed.

[0061] Compared with the method of inspecting the command flow to be processed driven by the first processor in the related art, that is, the correctness and logic of the configuration of the command flow to be processed are completed inside the first processor drive. For example, a large number of logical checks and prints are performed by the first processor drive layer. However, after being forwarded layer by layer through the host kernel layer and the firmware layer, software developers cannot determine whether the command flow to be processed received by the second processor still meets the software requirements and hardware logic, and thus cannot perceive in advance whether the behavior of the second processor pipeline meets the expectations. This method is not accurate enough and cannot inspect the command flow to be processed at the most appropriate level, so it cannot accurately determine whether the interaction logic between software and hardware is correct.

[0062] The command flow detection method of the embodiments of the present disclosure can send the command flow to be processed to the parser at the front-end module of the target simulation model, without performing any encapsulation or modification on the command flow to be processed, but can forward it without any changes, so that the parser can obtain a more accurate command flow to be processed, thereby improving the detection efficiency and accuracy of the command flow.

[0063] The type configuration information obtained in step S11 can be used in step S12 to determine a set of parsing unit groups that match the command flow to be processed according to the type configuration information.

[0064] In a possible implementation manner, the type configuration information includes chip type configuration information and pipeline type configuration information. Step S12 may include: determining at least one set of parsing unit groups that match the chip type of the second processor according to the chip type configuration information; and determining, from the at least one set of parsing unit groups that match the second processor, a set of parsing unit groups that match the pipeline type of the command flow to be processed according to the pipeline type configuration information. The pipeline type includes a graphics display pipeline and a computing pipeline.

[0065] Such as Figure 2As shown in the figure, the parser receives the command stream to be processed forwarded by the input interface of the target simulation model of the second processor. First, the chip selection unit of the parser can perform the first classification process on the command stream to be processed according to the chip type configuration information carried in the command stream to be processed, determine the type of the second processor to which the command stream to be processed belongs, and determine at least one set of parsing unit groups that match the chip type of the second processor. It can be seen that the parser can enter different parsing paths to be compatible with a variety of second processor chip products.

[0066] Because the command logics of different second processor chips are not exactly the same, the chip selection unit can be used as a primary module of the parser so that the chip selection unit can receive the command stream to be processed first, and distinguish which second processor chip the current control command stream belongs to by reading the chip type configuration information from the chip unique identification code register carried in the command stream to be processed, and complete the first data shunt.

[0067] Then, as Figure 2 shown in the figure, the pipeline selection unit of the parser can perform the second shunt on the command stream to be processed, and determine the parsing unit group that matches the pipeline type of the command stream to be processed from at least one set of parsing unit groups that match the second processor according to the pipeline type configuration information, so that the command stream to be processed enters the graphics display pipeline or the computing pipeline.

[0068] Because the functions of different pipelines on the same second processor chip are completely different, the pipeline selection unit can be used as a secondary module of the parser so that the pipeline selection unit can distinguish which pipeline the current command stream to be processed belongs to, such as the graphics display pipeline or the computing pipeline, by reading the pipeline type configuration information from the pipeline register carried in the command stream to be processed, and complete the second data shunt.

[0069] In step S11 and step S12, the parsing unit group that matches the second processor is obtained. In step S13, the command stream to be processed can be parsed according to the target simulation model and the parsing unit group to determine the parsing information.

[0070] In a possible implementation manner, step S13 may include: registering at least one type of access callback function to the target simulation model by using the parsing unit group; receiving the parsing information returned by the access callback function by using the parsing unit group, where the access callback function is triggered when the target simulation model executes the command stream to be processed.

[0071] As Figure 2As shown, the command stream to be processed screened by the chip selection unit and the pipeline selection unit can be passed to the parsing unit group that matches the second processor. The parsing unit group may include a register parsing unit, a control command structure parsing unit, and an instruction parsing unit pointed to by the control command structure. The three parsing units can perform parsing and inspection according to the logic of the pipeline of the matched second processor chip.

[0072] For example, at least one of the register parsing unit, the control command structure parsing unit, and the instruction parsing unit pointed to by the control command structure can be used to register at least one type of access callback function among the register access callback function, the first video memory access callback function, the second video memory access callback function, and the instruction parsing callback function to the target simulation model; use the corresponding parsing unit among the register parsing unit, the control command structure parsing unit, and the instruction parsing unit pointed to by the control command structure to receive the parsing information returned by it.

[0073] In this way, when the parser needs to add new parsing functions or process new command streams, new access callback functions can be written and registered to the target simulation model, which is beneficial to improving the scalability and applicability of the parser, without the need to perform large-scale modifications or reconstructions on the parser and the target simulation model, reducing the development and maintenance costs.

[0074] In a possible implementation manner, the access callback function includes a register access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the register access callback function to the register access interface of the target simulation model. The register access callback function is used to read values from the registers of the target simulation model; receiving the parsing information returned by the access callback function includes: receiving the register parsing information returned by the register access callback function. The register parsing information includes the values read by the to-be-processed command stream from the registers of the target simulation model when the target simulation model executes the to-be-processed command stream. Among them, the trigger condition of the register access callback function is: the read operation performed by the target simulation model on the registers in the target simulation model according to the indication of the to-be-processed command stream.

[0075] For example, the parser registers a register access callback function with the register access interface of the target simulation model. The register access callback function is used to read a value from the register of the target simulation model. In response to the target simulation model performing a read operation on the register in the target simulation model according to the instruction of the to-be-processed command stream, the register access callback function is triggered. The parser receives the register parsing information returned by the register access callback function. The register parsing information includes the value read from the register of the target simulation model by the to-be-processed command stream when the target simulation model executes the to-be-processed command stream.

[0076] Among them, the register access callback function may include a first function pointer and a first function body. The first function pointer is used to register the register access callback function with the register access interface. When the register access interface detects a read operation on any register in the target simulation model, it triggers the execution of the first function body through the first function pointer. The first function body is used to read the value from the register of the target simulation model to the parser, so that the parser can determine the parsing information according to the value read from the register.

[0077] Exemplarily, in order to identify some configuration situations of the to-be-processed command stream, the register value pointed to by this part of the configuration in the target simulation model can be read out, so as to form a corresponding format of log for software developers to view later. As Figure 2 shown, the register access function of the target simulation model of the second processor can be implemented through the register parsing unit of the parser. For example, the register access callback function can be registered with the register access interface of the target simulation model of the second processor. When the parser reads the register value, the register access callback function is triggered, realizing a software-visible register, and the value of this register is consistent and accurate in terms of both the parser's perspective and the perspective of the target simulation of the second processor.

[0078] In a possible implementation, the access callback function includes a first video memory access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the first video memory access callback function to the video memory access interface of the target simulation model. The first video memory access callback function is used to obtain the structural information between multiple commands included in the command stream to be processed. Receiving the parsing information returned by the access callback function includes: receiving the command structure parsing information returned by the first video memory access callback function. The command structure parsing information includes the structural information between multiple commands included in the command stream to be processed when the target simulation model executes the command stream to be processed. Wherein, the trigger condition of the first video memory access callback function is: the target simulation model performs a read operation on the command stream to be processed stored in the video memory of the target simulation model according to the indication of the command stream to be processed.

[0079] For example, the parser registers the first video memory access callback function to the video memory access interface of the target simulation model. The first video memory access callback function is used to obtain the structural information between multiple commands included in the command stream to be processed. In response to the target simulation model performing a read operation on the command stream to be processed stored in the video memory of the target simulation model according to the indication of the command stream to be processed, the first video memory access callback function is triggered. The parser receives the command structure parsing information returned by the first video memory access callback function. The command structure parsing information includes the structural information between multiple commands included in the command stream to be processed when the target simulation model executes the command stream to be processed.

[0080] Wherein, the first video memory access callback function may include a second function pointer and a second function body. The second function pointer is used to register the first video memory access callback function to the video memory access interface. When the video memory access interface detects a read operation on the command stream to be processed stored in the video memory of the target simulation model, it will trigger the execution of the second function body through the second function pointer. The second function body is used to return the structural information between multiple commands included in the command stream to be processed to the parser, so that the parser can determine the parsing information according to the structural information between multiple commands included in the command stream to be processed.

[0081] Exemplarily, the command stream to be processed may be composed of a multi-level nested control command structure, and these structures indicate the working logic of each hardware module in the second processor pipeline. In order to make the second processor pipeline work properly, software developers can make the content of these control command structures conform to the software configuration logic and hardware processing requirements. For example Figure 2As shown, through the control command structure parsing unit of the parser, the multi-level nested control command structure chain in the command stream to be processed can be parsed. Since the command stream to be processed is stored in the video memory of the target simulation model of the second processor, the control command structure parsing unit of the parser can register the first video memory access callback function into the video memory access interface of the second processor model. When the parser reads the control command structure, the first video memory access callback function is triggered, realizing the command stream to be processed that is visible to the software. Whether from the perspective of the parser or from the perspective of the target simulation model of the second processor, the two are consistent and the data is accurate.

[0082] In a possible implementation manner, the access callback function includes a second video memory access callback function and an instruction parsing callback function. Registering at least one type of access callback function into the target simulation model includes: registering the second video memory access callback function into the video memory access interface of the target simulation model, and registering the instruction parsing callback function into the instruction execution module of the target simulation model. The second video memory access callback function is used to obtain the current command of the command stream to be processed, and the instruction parsing callback function is used to obtain the instruction data of the current command in the command stream to be processed; receiving the parsing information returned by the access callback function, including: receiving the first parsing information returned by the second video memory access callback function and the second parsing information returned by the instruction parsing callback function. The first parsing information includes the current command in the command stream to be processed executed by the target simulation model, and the second parsing information includes the instruction data of the current command. Among them, the triggering conditions of the second video memory access callback function and the instruction parsing callback function are: the target simulation model performs a read operation on the instruction data in the target simulation model according to the indication of the command stream to be processed, and the instruction data includes the operation data of the arithmetic logic unit in the target simulation model; determining the instruction parsing information according to the first parsing information and the second parsing information.

[0083] For example, the parser registers a second video memory access callback function to the video memory access interface of the target simulation model, and registers an instruction parsing callback function to the instruction execution module of the target simulation model. The second video memory access callback function is used to obtain the current command of the command stream to be processed, and the instruction parsing callback function is used to obtain the instruction data of the current command in the command stream to be processed. In response to the target simulation model performing a read operation on the instruction data in the target simulation model according to the indication of the command stream to be processed, the second video memory access callback function and the instruction parsing callback function are triggered. The instruction data includes the operation data of the arithmetic logic unit in the target simulation model. The parser receives the first parsing information returned by the second video memory access callback function and the second parsing information returned by the instruction parsing callback function. The first parsing information includes the current command in the command stream to be processed executed by the target simulation model, and the second parsing information includes the instruction data of the current command. The parser determines the instruction parsing information according to the first parsing information and the second parsing information.

[0084] Wherein, the second video memory access callback function includes a third function pointer and a third function body. The third function pointer is used to register the second video memory access callback function to the video memory access interface, and the third function body is used to obtain the current command of the command stream to be processed. The instruction parsing callback function includes a fourth function pointer and a fourth function body. The fourth function pointer is used to register the instruction parsing callback function to the target simulation model, and the fourth function body is used to obtain the instruction data of the current command in the command stream to be processed.

[0085] Exemplarily, the command stream to be processed further includes the instruction data of the second processor. The instruction data of the second processor will act on the arithmetic logic unit (ALU) of the second processor, enabling the second processor to complete various different logical data operations. The instruction data of the second processor is often included in a certain structure within a multi-level nested control command structure. For example Figure 2As shown, the instruction parsing unit of the parser is responsible for reading and parsing the second processor instruction data. Since the command stream to be processed is stored in the video memory of the target simulation model of the second processor, the parser can register the second video memory access callback function to the video memory access interface of the target simulation model of the second processor, and at the same time register the instruction parsing callback function for parsing the second processor instruction data to the instruction execution module of the second processor model. When the parser reads the second processor instruction data, it triggers the second video memory access callback function and the instruction parsing callback function at the same time, realizing the second processor instruction data visible to the software. Whether from the perspective of controlling the parser or the target simulation model of the second processor, the two are consistent and the data is accurate.

[0086] In a possible implementation manner, the method further includes: the parser generates a log file according to the type configuration information and the parsing information, and each log file corresponds to a command stream to be processed; the parser writes the log file into the storage space of the parser in the order in which the target simulation model receives the command stream to be processed.

[0087] Exemplarily, as Figure 2 shown, the log collection unit can form a plurality of log files that are consistent with the order of the first processor driver's issuance according to a user-friendly and highly readable format for a large number of parsing strings output by the register parsing unit, the control command structure parsing unit, and the instruction parsing unit. That is to say, every time the first processor driver issues a command stream to be processed, the parser will, based on the chip selection unit and the pipeline selection unit, convert the current command stream to be processed into a command stream to be processed that matches the target simulation model of the second processor, and perform parsing processing on the command stream to be processed in the register parsing unit, the control command structure parsing unit, and the instruction parsing unit respectively. The parsing information output can be written into the same log. This is to facilitate software developers to correspond the logs with the command streams to be processed one by one, and clearly view the content of each command stream to complete the inspection process of development or debugging.

[0088] In summary, the command stream detection method of the embodiments of the present disclosure can be applied to a parser. In response to the target simulation model of the second processor receiving the command stream to be processed sent by the first processor, the parser classifies the command stream to be processed to obtain category information including at least one of the chip category and the pipeline category, and configures the target simulation model as the target simulation model according to the type configuration information, and converts the command stream to be processed into a command stream to be processed that matches the target simulation model; the parser parses the command stream to be processed according to the target simulation model to determine the parsing information. Then, the parser can generate a corresponding log file for each command stream to be processed according to the type configuration information and the parsing information. The log file can not only include the chip category of the second processor and the pipeline category corresponding to the command stream to be processed, but also include the software and hardware interaction process simulated by the simulation model of the second processor, such as the value read from the register of the target simulation model by the command stream to be processed, the structural information between multiple commands included in the command stream to be processed, and the instruction data corresponding to the current command in the command stream to be processed executed by the target simulation model.

[0089] According to the command stream detection method of the embodiments of the present disclosure, in the target simulation model of the second processor, the input interface as the front-end module can expose the interface to the parser, so that the inspection timing of the command stream can be intercepted more accurately. The parser has higher compatibility, clearer parsing results, simpler and easier-to-use inspection methods, and higher efficiency.

[0090] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not elaborate. Those skilled in the art can understand that in the above methods of the specific implementation manner, the specific execution order of each step should be determined according to its function and possible internal logic.

[0091] In addition, the present disclosure also provides a command stream detection device, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any command stream detection method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be elaborated here.

[0092] Figure 3 The block diagram showing the command stream detection device according to the embodiments of the present disclosure is as Figure 3 shown. The device is applied to a parser, and the device includes:

[0093] An obtaining module 31, configured to obtain type configuration information from the command stream to be processed in response to the target simulation model receiving the command stream to be processed sent by the first processor, where the target simulation model is used to simulate the second processor;

[0094] The first determination module 32 is configured to determine a set of parsing units that match the to-be-processed command stream according to the type configuration information, where the parser includes a set of parsing units for matching different second processors;

[0095] The second determination module 33 is configured to perform parsing processing on the to-be-processed command stream according to the target simulation model and the set of parsing units to determine parsing information.

[0096] In a possible implementation manner, the second determination module 33 is configured to: register at least one type of access callback function to the target simulation model by using the set of parsing units; receive the parsing information returned by the access callback function by using the set of parsing units, where the access callback function is triggered when the target simulation model executes the to-be-processed command stream.

[0097] In a possible implementation manner, the access callback function includes a register access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the register access callback function to the register access interface of the target simulation model, where the register access callback function is used to read a value from the register of the target simulation model; receiving the parsing information returned by the access callback function includes: receiving the register parsing information returned by the register access callback function, where the register parsing information includes the value read from the register of the target simulation model by the to-be-processed command stream when the target simulation model executes the to-be-processed command stream, and the triggering condition of the register access callback function is: the read operation performed by the target simulation model on the register in the target simulation model according to the indication of the to-be-processed command stream.

[0098] In a possible implementation manner, the access callback function includes a first video memory access callback function. Registering at least one type of access callback function to the target simulation model includes: registering the first video memory access callback function to the video memory access interface of the target simulation model, where the first video memory access callback function is used to obtain the structure information between multiple commands included in the to-be-processed command stream; receiving the parsing information returned by the access callback function includes: receiving the command structure parsing information returned by the first video memory access callback function, where the command structure parsing information includes the structure information between multiple commands included in the to-be-processed command stream when the target simulation model executes the to-be-processed command stream, and the triggering condition of the first video memory access callback function is: the read operation performed by the target simulation model on the to-be-processed command stream stored in the video memory of the target simulation model according to the indication of the to-be-processed command stream.

[0099] In a possible implementation, the access callback function includes a second video memory access callback function and an instruction parsing callback function. Registering at least one type of access callback function to the target simulation model includes: registering the second video memory access callback function to the video memory access interface of the target simulation model, and registering the instruction parsing callback function to the instruction execution module of the target simulation model. The second video memory access callback function is used to obtain the current command of the command stream to be processed, and the instruction parsing callback function is used to obtain the instruction data of the current command in the command stream to be processed; receiving the parsing information returned by the access callback function, including: receiving the first parsing information returned by the second video memory access callback function, and the second parsing information returned by the instruction parsing callback function. The first parsing information includes the current command in the command stream to be processed executed by the target simulation model, and the second parsing information includes the instruction data of the current command. Wherein, the triggering conditions of the second video memory access callback function and the instruction parsing callback function are: the target simulation model performs a read operation on the instruction data in the target simulation model according to the indication of the command stream to be processed, and the instruction data includes the operation data of the arithmetic logic unit in the target simulation model; determining the instruction parsing information according to the first parsing information and the second parsing information.

[0100] In a possible implementation, the obtaining module 31 is configured to: in response to the front-end module of the target simulation model receiving the command stream to be processed sent by the first processor, receive the command stream to be processed forwarded by the front-end module; obtain the type configuration information according to the identification information carried by the command stream to be processed.

[0101] In a possible implementation, the type configuration information includes chip type configuration information and pipeline type configuration information. The first determining module 32 is configured to: determine at least one set of parsing unit groups that match the chip type of the first processor according to the chip type configuration information; determine the parsing unit group that matches the pipeline type of the command stream to be processed from at least one set of parsing unit groups that match the first processor according to the pipeline type configuration information, where the pipeline type includes a graphics display pipeline and a computing pipeline.

[0102] In a possible implementation, the device further includes a generating module, configured to: generate a log file according to the type configuration information and the parsing information, and each log file corresponds to a command stream to be processed; write the log file into the storage space of the parser in the order in which the target simulation model receives the command stream to be processed.

[0103] In some embodiments, the functions or modules included in the apparatus provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0104] The embodiments of the present disclosure also propose a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above methods are implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0105] The embodiments of the present disclosure also propose an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to call the instructions stored in the memory to execute the above methods.

[0106] The embodiments of the present disclosure also provide a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in the processor of an electronic device, the processor in the electronic device executes the above methods.

[0107] The electronic device can be provided as a terminal, a server or other forms of devices.

[0108] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. For example, the electronic device can be provided as a server or a terminal device. Referring to Figure 4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 can include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to execute the above methods.

[0109] The electronic device 1900 can also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as the Microsoft server operating system (Windows Server TM ), the graphical user interface-based operating system (Mac OS X TM ) launched by Apple Inc., and the multi-user and multi-process computer operating system (Unix TM), the free and open-source Unix-like operating system (Linux TM ), the open-source Unix-like operating system (FreeBSD TM ) or the like.

[0110] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, and the computer program instructions can be executed by a processing component 1922 of the electronic device 1900 to complete the above method.

[0111] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0112] The computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, (but is not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device, such as a punched card or raised structures in grooves storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage medium used herein is not construed as a transitory signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0113] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0114] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state - setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present disclosure.

[0115] Aspects of the present disclosure are described herein with reference to the flowchart and / or block diagram of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart and / or block diagram, and the combinations of blocks in the flowchart and / or block diagram, can be implemented by computer - readable program instructions.

[0116] These computer - readable program instructions can be provided to a processor of a general - purpose computer, a special - purpose computer, or other programmable data - processing apparatus to produce a machine such that when the instructions are executed by the processor of the computer or other programmable data - processing apparatus, a device is produced that implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer - readable program instructions can also be stored in a computer - readable storage medium, which causes a computer, a programmable data - processing apparatus, and / or other devices to operate in a particular manner. Thus, the computer - readable medium storing the instructions includes a manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0117] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other devices implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0118] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur in an order different from that noted in the figures. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0119] The computer program product may be implemented specifically in the form of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), and so on.

[0120] The above descriptions of the various embodiments tend to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to each other. For the sake of brevity, they will not be elaborated herein.

[0121] Those skilled in the art can understand that in the above methods of the specific implementation manners, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0122] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0123] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A command flow detection method, characterized in that: The method is applied to a parser, and the method comprises: In response to the target simulation model receiving a to-be-processed command stream driven by the first processor, acquiring type configuration information from the to-be-processed command stream, the target simulation model being used to simulate the second processor; Determining, according to the type configuration information, a parsing unit group matching the command stream to be processed, wherein the parser includes a parsing unit group for matching different second processors; According to the target simulation model and the parsing unit group, the command stream to be processed is parsed to determine parsing information.

2. The method according to claim 1, characterized in that According to the target simulation model and the parsing unit group, the command stream to be processed is parsed to determine parsing information, including: registering at least one type of access callback function to the target simulation model using the parsing unit group; The parsing unit group is used to receive parsing information returned by the access callback function, wherein the access callback function is triggered when the target simulation model executes the command stream to be processed.

3. The method according to claim 2, characterized in that The access callback function includes a register access callback function, Registering at least one type of access callback function to the target simulation model includes: Registering the register access callback function to the register access interface of the target simulation model, wherein the register access callback function is used to read a value from a register of the target simulation model; Receiving parsing information returned by the access callback function includes: Receive register parsing information returned by the register access callback function, the register parsing information including values ​​read from registers of the target simulation model by the pending command stream when the target simulation model executes the pending command stream, wherein a triggering condition of the register access callback function is that the target simulation model performs a read operation on registers in the target simulation model in accordance with instructions of the pending command stream.

4. The method according to claim 2, characterized in that: The access callback function includes a first video memory access callback function, Registering at least one type of access callback function to the target simulation model includes: Registering a first video memory access callback function to a video memory access interface of the target simulation model, wherein the first video memory access callback function is used to obtain structural information between multiple commands included in the command stream to be processed; Receiving parsing information returned by the access callback function includes: Receive command structure parsing information returned by the first video memory access callback function, the command structure parsing information including structural information between multiple commands included in the command stream to be processed when the target simulation model executes the command stream to be processed, wherein the triggering condition of the first video memory access callback function is: the target simulation model performs a read operation on the command stream to be processed stored in the video memory of the target simulation model according to the instruction of the command stream to be processed.

5. The method according to claim 2, characterized in that: The access callback function includes a second video memory access callback function and an instruction parsing callback function. Registering at least one type of access callback function to the target simulation model includes: Registering a second video memory access callback function to the video memory access interface of the target simulation model, and registering an instruction parsing callback function to the instruction running module of the target simulation model, wherein the second video memory access callback function is used to obtain the current command of the command stream to be processed, and the instruction parsing callback function is used to obtain the instruction data of the current command in the command stream to be processed; Receiving parsing information returned by the access callback function includes: Receive first parsing information returned by the second video memory access callback function, and second parsing information returned by the instruction parsing callback function, wherein the first parsing information includes a current command in a pending command stream executed by the target simulation model, and the second parsing information includes instruction data of the current command, wherein a triggering condition of the second video memory access callback function and the instruction parsing callback function is: the target simulation model performs a read operation on the instruction data in the target simulation model according to an instruction of the pending command stream, and the instruction data includes operation data of an arithmetic logic unit in the target simulation model; Instruction parsing information is determined according to the first parsing information and the second parsing information.

6. The method according to any one of claims 1 to 5, characterized in that In response to the target simulation model receiving a to-be-processed command stream driven by the first processor, acquiring type configuration information from the to-be-processed command stream, including: In response to the front-end module of the target simulation model receiving the to-be-processed command stream driven by the first processor, receiving the to-be-processed command stream forwarded by the front-end module; The type configuration information is acquired according to the identification information carried by the command stream to be processed.

7. The method according to any one of claims 1 to 5, characterized in that The type configuration information includes chip type configuration information and pipeline type configuration information. According to the type configuration information, determining a parsing unit group matching the command stream to be processed includes: Determining, according to the chip type configuration information, at least one set of parsing unit groups matching the chip type of the second processor; According to the pipeline type configuration information, a parsing unit group matching the pipeline type of the command stream to be processed is determined from at least one parsing unit group matching the second processor, and the pipeline type includes a graphics display pipeline and a calculation pipeline.

8. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Generate a log file according to the type configuration information and the parsing information, each log file corresponding to a command stream to be processed; The log file is written into the storage space of the parser in the order in which the target simulation model receives the command stream to be processed.

9. A command flow detection device, characterized in that: include: The device is applied to a parser, and comprises: an acquisition module, configured to acquire type configuration information from a command stream to be processed in response to a target simulation model receiving a command stream to be processed issued by a first processor driver, wherein the target simulation model is used to simulate a second processor; a first determination module, configured to determine, according to the type configuration information, a parsing unit group matching the command stream to be processed, wherein the parser includes parsing unit groups for matching different second processors; The second determination module is used to parse the command stream to be processed according to the target simulation model and the parsing unit group to determine parsing information.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 8.

11. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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