Optical module working method and optical module based on I3C communication

Abstract

The present invention belongs to the field of communication technologies, and relates to an optical module working method and an optical module based on I3C communication. Among them, the method includes: the optical module MCU continuously monitors whether a dynamic address has been assigned by the I3C controller by monitoring the dynamic address update interrupt generated by the I3C peripheral; when it is monitored that the dynamic address assignment is successful, the I3C peripheral, the receive-end DMA channel bound to the I3C peripheral, and the transmit-end DMA channel bound to the I3C peripheral are configured. After the configuration is completed, wait for an operation instruction issued by the I3C controller; when an operation instruction is received, the optical module MCU responds to the private read operation or the private write operation initiated by the I3C controller. The optical module applies the above method to perform data processing work. This method enables the optical module to greatly improve the communication rate and the device management efficiency, etc. by virtue of the characteristics of I3C communication, such as dynamic address assignment and interrupts based on I3C communication.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and specifically discloses an optical module working method and an optical module based on I3C communication. Background Art

[0002] With the rapid development of modern electronic devices, the demand for communication interfaces is increasing continuously. Due to its simple and efficient characteristics, the traditional communication bus such as I2C (Inter-Integrated Circuit) is widely used in many embedded systems.

[0003] The I2C protocol was released by Philips in 1982 and was initially used to achieve low-speed and low-cost communication between chips on a circuit board. It adopts a two-wire design, namely SDA (Serial Data Line) and SCL (Serial Clock Line), supports master-slave mode and multi-master architecture, and provides multiple communication bandwidth modes. When using the I2C protocol for optical module control and communication, the optical module receives read and write operations of the master device through the SCL and SDA buses of I2C to achieve the reading of the I2C optical module status and the configuration and control of parameters, and the I2C data parsing adopts a single-byte interrupt processing method. The existing communication method of the optical module based on the I2C protocol has the following deficiencies:

[0004] 1. Bandwidth rate limitation: In practice, the optical module can use at most the "Fast Mode Plus" of I2C, and its maximum bandwidth is only 1Mpbs, which limits the high-bandwidth data transmission.

[0005] 2. Low processing efficiency of the I2C interrupt mode: When the module receives data through I2C, it adopts single-byte interrupt processing, that is, an interrupt is generated every time a byte is received or sent. Frequent entry of the MCU (Microcontroller Unit) into the interrupt has problems such as low efficiency, high MCU occupancy, poor real-time performance, and high power consumption.

[0006] 3. Problem that DMA (Direct Memory Access) can only process fixed-length data: The traditional communication peripheral DMA transmission can only transmit fixed-length data, that is, the slave device must know in advance the length of the data to be sent by the master device so that the slave device can set a fixed length when initializing the DMA receive and send channels, which cannot meet the requirement of the optical module master device for dynamically reading and writing data lengths to the optical module slave device.

[0007] In order to improve the communication efficiency of the optical module, the I3C (Improved Inter-Integrated Circuit) protocol is proposed to be used as the communication protocol for the optical module. This application aims to propose a technology for adapting the I3C communication protocol to the optical module. Summary of the Invention

[0008] The object of the present invention is to provide a working method and an optical module for an optical module based on I3C communication, and to solve the problem of adapting the I3C communication protocol to the optical module. The specific solutions are as follows:

[0009] In the first aspect, a working method for an optical module based on I3C communication is provided. The method includes:

[0010] The optical module MCU continuously monitors whether a dynamic address has been assigned by the I3C controller by monitoring the dynamic address update interrupt generated by the I3C peripheral.

[0011] When it is detected that the dynamic address assignment is successful, the I3C peripheral, the receive-end DMA channel bound to the I3C peripheral, and the transmit-end DMA channel bound to the I3C peripheral are configured. After the configuration is completed, wait for an operation instruction issued by the I3C controller. When an operation instruction is received, the optical module MCU responds to the private read operation or the private write operation initiated by the I3C controller.

[0012] Further, when it is detected that the dynamic address assignment is successful, configuring the I3C peripheral, the receive-end DMA channel bound to the I3C peripheral, and the transmit-end DMA channel bound to the I3C peripheral includes configuring to enable the STOP interrupt of the I3C peripheral to cooperate with the receive-end DMA channel to receive variable-length data sent by the I3C controller, and configuring the receive-end DMA channel to respond to the DMA private write operation. Configuring the receive-end DMA channel specifically includes:

[0013] Setting the source address of the receive-end DMA to the I3C receive data register in the I3C peripheral;

[0014] Setting the destination address of the receive-end DMA to at least two memory areas in the RAM of the optical module MCU as receive buffer areas;

[0015] Setting the receive byte length of the receive-end DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receive byte length of the receive-end DMA > (the maximum byte length of the EPL extended payload page + one byte);

[0016] Enabling the receive-end DMA channel;

[0017] Enabling the receive-end DMA request.

[0018] Further, when it is detected that the dynamic address allocation is successful, configure the I3C peripheral, the receiving DMA channel bound to the I3C peripheral, and the transmitting DMA channel bound to the I3C peripheral, including configuring to enable the STOP interrupt of the I3C peripheral to cooperate with the transmitting DMA channel to send variable-length data to the I3C controller, and configuring the transmitting DMA channel to respond to the DMA private read operation; the specific configuration of the transmitting DMA channel includes:

[0019] Set the source address of the transmitting DMA to a memory area in the RAM of the optical module MCU as the transmission buffer;

[0020] Set the destination address of the transmitting DMA to the I3C transmit data register in the I3C peripheral;

[0021] Set the transmitting byte length of the transmitting DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the transmitting byte length of the transmitting DMA > the maximum byte length of the EPL extended payload page;

[0022] Enable the transmitting DMA channel;

[0023] Enable the transmitting DMA request.

[0024] Further, the working process of the private write is as follows:

[0025] After the receiving DMA is triggered, move the received data from the receiving DMA source address into the receiving buffer in the receiving DMA destination address; when the private write data transmission is completed, generate an I3C peripheral STOP interrupt based on the stop bit in the data to implement the receiving of variable-length data by the receiving DMA;

[0026] Calculate the actual received data length in the STOP interrupt of the I3C peripheral;

[0027] In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the transmitting DMA channel bound to the I3C peripheral to enable the optical module to respond to the next private read operation of the I3C controller;

[0028] In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the receiving DMA channel bound to the I3C peripheral to enable the optical module to respond to the next private write operation of the I3C controller;

[0029] Process the data in the receiving buffer based on the management memory mapping in the CMIS protocol.

[0030] Further, the working process of the private read is as follows:

[0031] After the transmitting DMA is triggered, the transmitting DMA transfers data from the currently configured transmitting DMA source address to the destination address of the transmitting DMA; when the private read data transfer is completed, an I3C peripheral STOP interrupt is generated based on the stop bit in the data to achieve variable-length data transmission of the transmitting DMA.

[0032] Calculate the actual data length transmitted in the I3C peripheral STOP interrupt.

[0033] Configure the I3C peripheral and the transmitting DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral to enable the optical module to respond to the next private read operation of the I3C controller.

[0034] Process the data in the transmission buffer based on the management memory mapping in the CMIS protocol.

[0035] Further, configuring the I3C peripheral and the receiving DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral to enable the optical module to respond to the next private write operation of the I3C controller specifically includes:

[0036] Disable the receiving DMA request;

[0037] Disable the receiving DMA channel;

[0038] Empty the RX-FIFO queue of the I3C;

[0039] Set the receiving byte length of the receiving DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receiving byte length of the receiving DMA > (the maximum byte length of the EPL extended payload page + one byte);

[0040] Modify the destination address of the receiving DMA to the memory area in the RAM of the MCU of the optical module as the receiving buffer;

[0041] Enable the receiving DMA channel;

[0042] Enable the receiving DMA request.

[0043] Further, configuring the I3C peripheral and the transmitting DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral to enable the optical module to respond to the next private read operation of the I3C controller specifically includes:

[0044] Disable the transmitting DMA request;

[0045] Disable the transmitting DMA channel;

[0046] Empty the TX-FIFO queue of the I3C;

[0047] Set the transmitting end DMA transmission byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the transmitting end DMA transmission byte length > the maximum byte length of the EPL extended payload page;

[0048] Modify the transmitting end source address based on the optical module register address in the receive buffer and the page mapping value of the 127th byte in Lower Memory for the optical module to respond to the next current read operation;

[0049] Enable the transmitting end DMA channel;

[0050] Enable the transmitting end DMA request.

[0051] Furthermore, the private write operation is based on a random write frame format, where the random write frame format consists of a start bit, an optical module address, a write flag bit, an optical module acknowledgment bit, an optical module register address, a first check bit, a first data, a second check bit,..., an Nth data bit, an (N + 1)th check bit, and a stop bit in sequence.

[0052] Furthermore, the private read operation is based on a random read frame format, where the random read frame format consists of a start bit, an optical module address, a write flag bit, an optical module acknowledgment bit, an optical module register address, a check bit, a repeated start bit, an optical module address, a read flag bit, an optical module acknowledgment bit, a first data, a first end judgment bit,..., an Nth data, an Nth end judgment bit, and a stop bit in sequence.

[0053] Furthermore, the current read operation is based on a current read frame format, where the current read frame format consists of a start bit, an optical module address, a read flag bit, an optical module acknowledgment bit, a first data, a first end judgment bit,..., an Nth data, an Nth end judgment bit, and a stop bit in sequence.

[0054] Furthermore, it is characterized in that it further includes an optical module communication error recovery method, specifically as follows:

[0055] When the I3C peripheral enters an error interrupt, the optical module MCU obtains and records the error source;

[0056] Enable the I3C peripheral STOP interrupt and configure the transmitting end DMA channel in the error interrupt of the I3C peripheral; the transmitting end DMA channel configuration specifically includes:

[0057] Disable the transmitter DMA request; disable the transmitter DMA channel; clear the TX-FIFO queue of I3C; set the transmitter DMA transmission byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the transmitter DMA transmission byte length > the maximum byte length of the EPL extended payload page; modify the transmitter DMA source address based on the CMIS memory mapped address of the current communication error; enable the transmitter DMA channel; enable the transmitter DMA request;

[0058] Enable the STOP interrupt of the I3C peripheral and configure the receiver DMA channel in the error interrupt of the I3C peripheral; the specific configuration of the receiver DMA channel includes:

[0059] Disable the receiver DMA request; disable the receiver DMA channel; clear the RX-FIFO queue of I3C; set the receiver DMA receive byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receiver DMA receive byte length > (the maximum byte length of the EPL extended payload page + one byte); modify the destination address of the receiver DMA to the memory area in the RAM of the MCU of the optical module as the receive buffer; enable the receiver DMA channel; enable the receiver DMA request.

[0060] In a second aspect, an optical module is provided, and the working method of the optical module adopts the working method of the optical module based on I3C communication provided in the first aspect.

[0061] The beneficial effects of the present invention are as follows:

[0062] A data processing working method of an optical module combining I3C communication and DMA mechanism is provided. Based on the dynamic address allocation, interrupt and other functions of I3C communication, the optical module can greatly improve the communication rate and the device management efficiency by virtue of the characteristics of I3C communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 It is the hardware structure diagram of the optical module of the present invention;

[0064] Figure 2 It is the schematic diagram of the random write frame format in the working method of the optical module of the present invention;

[0065] Figure 3 It is the schematic diagram of the random read frame format in the working method of the optical module of the present invention;

[0066] Figure 4 It is the schematic diagram of the current read frame format in the working method of the optical module of the present invention;

[0067] Figure 5 It is the flowchart of the working method of the optical module of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0069] With the development of optical communication technology, optical modules need to support higher-bandwidth data transmission and lower power consumption. However, existing optical modules generally rely on the I2C protocol and use single-byte interrupts to process data. This protocol has problems such as limited bandwidth, low data processing efficiency, high power consumption, and insufficient scalability.

[0070] Therefore, the present invention intends to design an operating method for an optical module based on the I3C protocol.

[0071] As Figure 1 shown, first, clarify the hardware architecture of the optical module in the present invention, which mainly includes an optical fiber interface, an electrical interface, a transmitting unit, a receiving unit, a DSP (Digital Signal Processing), an MCU, and a power supply unit.

[0072] Among them, the optical fiber interface: Connects to the transmitting unit and the receiving unit and is used to transmit and receive optical signals. If it is an AEC (Active Electrical Cable) module, it does not include the receiving and transmitting units and the optical fiber interface in the above block diagram.

[0073] The electrical interface: 1. Includes the SCL and SDA signal lines of I3C. The optical module is connected to the SCL and SDA buses of the I3C controller (switch, network card, etc.) through the I3C bus of the electrical interface / golden finger, and the optical module communicates with the I3C controller as a target device through I3C. 2. Multiple low-speed signal control pins, such as ModPrsL (Module Present Low, module presence detection signal (low level effective)), IntL (Interrupt Low, interrupt signal), LPMode (Low Power Mode), ModSel (Mode Selection), and ResetL (Reset Low, reset signal) are used to implement functions such as module presence indication, status indication, power consumption mode control, module selection, and reset control. 3. Includes high-speed signal line data pins, which are divided into differential signal pairs at the transmitting end of Tx1, Tx2...Txn (representing multiple independent transmission channels of the optical module) and differential signal pairs at the receiving end of Rx1, Rx2...Rxn (representing multiple independent receiving channels of the optical module). 4. Power lines and ground lines are used to supply power to the optical module.

[0074] Transmitter unit: mainly includes a laser, a modulator and a driver, responsible for converting electrical signals into optical signals and transmitting them to the receiving unit of the remote optical module through an optical fiber. If it is an AEC module, it does not include the receiving and transmitting units and the optical fiber interface in the above block diagram.

[0075] Receiving unit: mainly includes a photodetector and a TIA (Transimpedance Amplifier), responsible for converting optical signals into electrical signals, amplifying the electrical signals and then outputting them to the DSP.

[0076] DSP: mainly used to process complex signal modulation and transmission problems. It improves the performance and transmission quality of the optical module through efficient digital signal processing algorithms. Some DSPs have integrated the driver in the above transmitter unit and the TIA in the receiving unit.

[0077] MCU: is the management core of the module, responsible for coordinating and controlling the work of each part of the module to ensure the efficient operation of the module.

[0078] Power supply unit: supplies power to the MCU, DSP, transmitter unit and receiving unit.

[0079] Before elaborating on the method of the present invention in detail, first, some professional terms in the context of the present invention are listed and explained.

[0080] Optical module: a key hardware module in an optical communication system, which realizes the mutual conversion between electrical signals and optical signals and is used for high-speed data transmission between network devices. The optical module also has an MCU, which is formed by encapsulating a core, peripherals electrically connected to the core, and storage (Flash / RAM), etc.; the I3C peripheral in the present invention is the aforementioned peripheral that constitutes the MCU. As the management core of the optical module, the MCU is responsible for coordinating and controlling the work of each part of the module to ensure the efficient operation of the module, and the I3C peripheral is managed by the MCU core. The I3C peripheral is managed by the MCU of the optical module and works according to the MIPI (Mobile Industry Processor Interface) protocol.

[0081] The I3C controller (I3C Controller), i.e., the master device, is an I3C peripheral located in hardware devices such as switches or network cards, and this peripheral acts as a controller (Controller) role, while the I3C peripheral of the optical module acts as a target device (Target) role.

[0082] The I3C peripheral in the present invention refers to a hardware module integrated in the MCU and supporting the I3C communication protocol. It can be configured into two roles, Target and Controller. The I3C peripheral of the optical module MCU is usually configured as the role of the target device (Target), called the slave device. The I3C peripherals in hardware devices such as switches or card networks are usually configured as controllers (Controller), called the master device.

[0083] DMA (Direct Memory Access): It is a technology for data transfer. In the present invention, it is used to directly transfer data between the peripheral and the memory without the CPU intervening byte by byte, which can greatly improve efficiency and reduce power consumption.

[0084] DMA channel: It refers to the logical path used to complete a specific data transfer task, just like a "conveyor belt", which automatically transfers data from one location to another based on a specific trigger signal.

[0085] STOP interrupt: It is an interrupt mechanism in the I3C peripheral. In hardware devices of different manufacturers, its name may be different. For example, in the STM32 series products produced by STMicroelectronics Group, it can also be called the completion interrupt.

[0086] Variable-length data: It refers to data frames or data packets with variable lengths. Correspondingly, in traditional DMA communication, only data frames with fixed lengths can be transmitted, that is, the target device knows in advance the length of the data to be sent or received by the master device.

[0087] Enable: It means to make a certain functional module, subsystem or signal path in an operable, responsive or effective state by setting relevant control parameters, register bits or logic signals, so as to execute the predetermined function. It usually means that the system has the permission or conditions to execute a certain function.

[0088] Disable: It is the antonym of Enable. It means to make a specific function, module or path in an inoperable, unresponsive or invalid state by clearing or modifying the corresponding control parameters, register bits or signal states, so as to achieve the purpose of closing, pausing or stopping the function.

[0089] EPL (Extended Payload Length) Extended Payload Page Maximum Byte Length: In the optical module management communication based on the CMIS (Common Management Interface Specification) protocol, data is exchanged in the form of command frames through the I2C or I3C bus. The command frame usually includes fields such as the Command Code, Payload Length, and Payload. To adapt to the scenario of large-capacity data transmission, the CMIS protocol introduces the EPL (Extended Payload Length) mechanism based on the standard Payload Length field. This field is enabled when the value of the Payload Length field is the maximum value 0xFF (255), and is used to indicate the situation where the actual data payload length exceeds 255 bytes. When the EPL mechanism is enabled, the original Payload field is stored and transmitted immediately after the EPL field. Through this mechanism, large-capacity data interaction scenarios such as EEPROM data block access and firmware download can be supported, significantly improving the protocol's expansion ability and data throughput efficiency.

[0090] Enable the 127th byte of Lower Memory: Lower Memory refers to an address space of 128 bytes, ranging from 0x00 to 0x7F. This area contains some global control and module status information. Among them, the 127th byte (address 0x7F) refers to that in CMIS, the 127th byte (0x7F) is the Page Select byte, that is, the page index; the page index value determines which page (or page in a certain Bank) is accessed when the host accesses a certain byte in the page (address range from 128 to 255). Generally speaking, by writing different values (from 128 to 255) to this byte, different "pages" can be accessed. Each "page" represents a complete 128-byte register mapping area for accessing more information or control functions.

[0091] Based on the above description of professional terms, the method of the present invention is further elaborated as follows:

[0092] In the present invention, the optical module uses the I3C protocol for communication. Based on the advantages of the I3C protocol, dynamic address allocation for the I3C peripherals in the optical module can be achieved. After the I3C peripherals are assigned dynamic addresses, the I3C peripherals will generate dynamic address update interrupts, and the optical module MCU will monitor in real time whether it receives the dynamic address update interrupts generated by the I3C peripherals to determine whether the I3C peripherals have completed address allocation based on the monitoring results.

[0093] It should be noted that when the optical module MCU monitors the dynamic address allocation of the I3C peripheral, the optical module can perform normal tasks. During dynamic address allocation, the I3C optical module can receive and respond to the ENTDAA (Enter Dynamic Address Assignment) instruction, RSTDAA (Reset Dynamic Address Assignment) instruction, and SETNEWDA (Set New Dynamic Address) instruction sent by the I3C controller, and then dynamically allocate a 7-bit address to ensure the uniqueness of the dynamic address on the I3C bus. It should be noted that the I3C controller here is the master device, which is the I3C peripheral in hardware devices such as switches or network cards, and this peripheral acts as the controller role, while the I3C peripheral of the optical module acts as the target device role.

[0094] When the dynamic address allocation is successful, the hardware module in the optical module can communicate with the hardware module in the master device (such as a switch or network card) to implement internal system operations, and achieve access to and modification of specific functions, configurations, or status information of the device. The operations here mainly include the optical module MCU responding to the private read or private write operations of the I3C controller based on the operation instructions.

[0095] Before performing the private read or private write operation, it is first necessary to configure the I3C peripheral. Specifically, enable the STOP interrupt of the I3C peripheral (which has different names in different hardware device manufacturers, such as the completion interrupt in STM32 series products), which is used to implement the end flag of the DMA variable-length data transfer between the I3C receive data register or the I3C transmit data register and the optical module MCU memory. Its working principle is that when the data transfer between the I3C receive data register or the I3C transmit data register and the optical module MCU memory (including the optical module MCU sending or receiving data) is completed, the optical module MCU will immediately sense the I3C peripheral STOP interrupt signal on the I3C bus (the process in which the SDA level drops from 1 to 0 while the SCL remains high, that is, the falling edge of the level). Variable-length data means that compared with the traditional DMA method where the data transfer is of a fixed length, the variable-length data here means that the data length is not fixed or unique.

[0096] Instead of using the traditional DMA method to receive data and determine whether the reception is complete based on a preset fixed transmission data length, it is based on the I3C peripheral STOP interrupt. For ease of understanding, taking the actual data written by the control device as 2047 bytes as an example, after 2047 bytes are transmitted on the I3C hardware bus, the I3C STOP interrupt will be generated, and the DMA transmission completion interrupt at the transmitting end will not be generated (because at this time, the DMA has only transferred 2047 bytes of data, which is less than the maximum received byte length of 2050 bytes at the receiving end DMA). Furthermore, relevant processing after data reading can be further carried out in the I3C STOP interrupt, such as preparing the next transmitting end or receiving end configuration to support the next private read or private write operation.

[0097] After the I3C peripheral is configured, the receiving end DMA channel bound to the I3C peripheral is configured to respond to the DMA private write operation. Here, the private write means that the I3C controller (master device) transfers data to the I3C receive data register in the I3C peripheral of the optical module, and then transfers the data from the I3C receive data register to the receive buffer of the optical module MCU. That is to say, after the data is written into the I3C receive data register, it is transferred to the optical module MCU memory through the DMA transfer mechanism. Therefore, before further transferring the data to the optical module MCU memory, it is necessary to first configure the DMA channel between the optical module MCU memory and the I3C peripheral in the optical module. Based on the optical module MCU, the DMA channel here is the receiving end DMA channel. The specific content of the receiving end DMA channel configuration is as follows: Set the source address of the receiving end DMA to the I3C receive data register in the I3C peripheral. Here, the source address can also be understood as: The I3C receive data register in the I3C peripheral is used to receive the data sent by the master device (switch, network card, test card, etc.) through the bus to implement the private write.

[0098] Set the destination address of the receiving end DMA to at least two memory areas in the RAM of the optical module MCU as the receive buffer. The purpose of setting multiple receive buffers is that they can be used alternately to receive multiple data.

[0099] In this embodiment, the receive buffer can be two, named the first receive buffer and the second receive buffer respectively. Among them, the first receive buffer and the second receive buffer are two memory areas in the RAM of the I3C optical module MCU. In subsequent private write operations, the I3C optical module will alternately use the first receive buffer and the second receive buffer to receive data to implement the Ping-Pong mechanism. Here, the first receive buffer is used.

[0100] Regarding the Ping-Pong mechanism, that is, in the case of multiple buffer areas, the data to be processed received for the first time is cached in one of the receive buffer areas and the data is processed. When the data is still being processed and new data needs to be received and processed, the data is stored in another receive buffer area and waits to be processed after the previous data is processed; similarly, when new data to be received and processed arrives while the data in the previous two buffer areas has not been processed yet, the data can be cached in the third receive buffer area. Generally, setting two receive buffer areas can basically meet most application scenarios. Therefore, in the embodiments of the present invention, two buffer areas are taken as examples.

[0101] It should also be noted that when there are multiple receive buffer areas, a receive priority can be set for each buffer area. The purpose is that when waiting to receive data, the address of the idle receive buffer area with a higher priority is configured as the destination address to give priority to receiving data. When the previous data is still being processed and the occupied receive buffer area has not been vacated, the new data will be cached in the receive buffer area with the highest priority among the idle receive buffer areas.

[0102] In order to cooperate with the I3C peripheral STOP interrupt to achieve variable-length data reception, in the configuration of the receive end DMA channel, there is also a setting for the receive end DMA receive byte length; this length setting is based on the maximum byte length of the EPL (Extended Payload Length) extended payload page in the CMIS (Common Management Interface Specification) protocol; it needs to be larger than the maximum byte length of the EPL extended payload page plus one byte; that is, the receive end DMA receive byte length > (the maximum byte length of the EPL extended payload page + one byte). This one byte refers to the address byte of the data register. For ease of understanding, the following is an example: One setting can be that when the current maximum EPL length is 2048 bytes, adding one byte of the optical module data register address makes a total of 2049 bytes. Therefore, in order to achieve DMA variable-length reception, a length value larger than 2049 needs to be set. For example, when the receive end DMA receive byte length here is set to 2050 bytes, since the maximum EPL length is 2048 bytes and an additional one-byte register length is required, a total of 2049 bytes, so when receiving data, data larger than 2049 bytes will not be received, and thus the DMA transfer complete interrupt will not be triggered. At this time, it is possible to determine whether the reception is complete based on identifying the I3C peripheral STOP interrupt, thereby achieving the reception of variable-length data.

[0103] After the above configuration is set up, the receiver DMA channel can be enabled and the receiver DMA request can be enabled to make the DMA channel and DMA request available. This is to facilitate triggering the DMA channel request corresponding to the I3C peripheral after the private write data of the master device is transferred to the I3C receive data register in the optical module I3C peripheral, and transferring the data from the I3C receive data register to the optical module MCU memory through the receiver DMA channel.

[0104] After the I3C peripheral configuration is completed, the transmitter DMA channel bound to the I3C peripheral is configured to respond to the DMA private read operation; through the above private write process, it can be known that the private read means that the I3C controller (master device) reads the data transferred by DMA from the memory area of the optical module MCU in the I3C transmit data register of the I3C peripheral of the optical module. That is to say, the data transfer process of the private read is: the optical module MCU transfers the data to the I3C transmit data register through the transmitter DMA channel, and the I3C transmit data register then transfers the data to the I3C controller (master device). Similarly, before the optical module MCU transfers the data to the I3C transmit data register through the transmitter DMA channel, the transmitter DMA channel in the optical module needs to be configured first; the specific content is as follows:

[0105] Set the source address of the transmitter DMA to a memory area in the RAM of the optical module MCU as the transmit buffer; in practice, specifically: set the source address of the transmitter DMA to the Management Memory map specified by the CMIS protocol (management memory mapping mechanism), which is the start address of the Lower Memory specified by the CMIS protocol here, and it is also a memory area in the RAM (Random Access Memory) of the I3C optical module MCU, named the transmit buffer here. At this time, if the I3C controller performs a Current Read operation, the Lower Memory content can be successfully read out. It should be noted that the Lower Memory in CMIS refers to an address space of 128 bytes in size, with a range of 0x00 to 0x7F. This area contains some global control and module status information. Specifically, for the 127th byte (address 0x7F), in CMIS, it is used for page selection. That is, by writing different values to the 127th byte, different "pages" can be accessed. Each "page" represents a complete 128-byte register mapping area for accessing more information or control functions.

[0106] Set the destination address of the transmitting DMA to the I3C transmit data register in the I3C peripheral; the destination address here can be understood as: the I3C transmit data register in the I3C peripheral is used to send the transmit address of the data for implementing private read to the master device (switch, network card, test card, etc.) through the bus.

[0107] Similarly, in order to cooperate with the I3C peripheral STOP interrupt to achieve variable-length data transmission, it also includes the setting of the transmitting DMA byte length; this length setting is based on setting the transmitting DMA byte length with the maximum byte length of the EPL extended payload page in the CMIS protocol, and the transmitting DMA byte length just needs to be greater than the maximum byte length of the EPL extended payload page; for easy understanding, an example is given as follows: one of the settings can be that when the current maximum EPL length is 2048 bytes, in order to achieve DMA variable-length reception, a length value greater than 2048 also needs to be set, which can be set to 2049 bytes here, that is, greater than the maximum byte length of the EPL extended payload page. Different from private read, a register address byte also needs to be carried in the data of private write, so the receiving DMA receive byte length is set to 2050 bytes, while in private read, since there is no register address byte in the data, it can be set to 2049 bytes.

[0108] After the above configurations are set, the transmitting DMA channel and the transmitting DMA request can be enabled; so that the DMA channel and the DMA request are in an available state; when a private read request from the master device is received, the corresponding DMA channel request of the I3C peripheral is triggered, and the optical module MCU transfers the data to the I3C transmit data register through the transmitting DMA channel; then the data is transmitted from the I3C transmit data register to the master device through the I3C bus.

[0109] The above content details the hardware device configuration before performing the private read operation or the private write operation and the specific data transmission process during the private read or private write operation. Based on this configuration description and data transmission process description, the following will further detail the specific operation process and data communication principle when performing the private write or private read operation.

[0110] It should be noted that the triggering of both the private write or private read operation is based on the operation instruction of the I3C controller (master device); that is, after the optical module MCU receives the operation instruction of the I3C controller (master device), the corresponding private write or private read operation will be executed.

[0111] First, the execution process of the private write operation is described:

[0112] Receive and respond to the private write operation of the I3C controller.

[0113] When the optical module MCU receives a private write operation from the I3C controller, the data for the private write has already been transferred by the I3C controller to the I3C receive data register. To transfer the private write data in the I3C receive data register to the receive buffer in the optical module MCU, first trigger the receive DMA to transfer the data received in the I3C receive data register from the receive DMA source address (i.e., the address of the I3C receive data register) to the first receive buffer or the second receive buffer at the receive DMA destination address (the memory area address in the RAM of the optical module MCU). When the transfer of the private write data is complete, generate an I3C peripheral STOP interrupt based on the stop bit. The stop bit is the last byte in the private write data, as can be seen from the random write frame format defined later.

[0114] In practice, it can be specifically: the receive DMA is triggered by the not-empty flag of the RX-FIFO (Receive First-In-First-Out buffer), and automatically transfers the received data from the receive DMA source address (I3C receive data register) to the receive DMA destination address (the first receive buffer and the second receive buffer in the RAM of the optical module MCU alternate to receive data). The data transferred by the DMA is the optical module register address in the random write frame format, as well as the first data to the Nth data. When the transfer of the private write data is complete, generate an I3C peripheral STOP interrupt based on the stop bit to achieve the reception of variable-length data.

[0115] Calculate the actual received data length in the I3C peripheral STOP interrupt.

[0116] After completing the data transfer work in the private write operation, it is also necessary to configure the I3C peripheral in the I3C peripheral STOP interrupt; and configure the transmit DMA channel bound to the I3C peripheral for the optical module to respond to the next private read operation of the I3C controller; and configure the receive DMA channel bound to the I3C peripheral for the optical module to respond to the next private write operation of the I3C controller.

[0117] Among them, the I3C peripheral configuration is the same as the I3C peripheral configuration before the DMA channel configuration for the aforementioned private read or private write operation, which is also to enable the I3C peripheral STOP interrupt to achieve the transfer of variable-length data between the I3C receive data register or the I3C transmit data register and the memory of the optical module MCU. Then configure the corresponding DMA channel.

[0118] Take the private read as an example first:

[0119] Before configuring the transmit DMA channel again; first, it is necessary to disable the transmit DMA request and the transmit DMA channel, that is, before the configuration is completed, the transmit DMA is in a non-operating state.

[0120] Then clear the TX-FIFO (Transmit First-In-First-Out) queue of I3C. Then set the byte length of the DMA sender based on the maximum byte length of the EPL extended load page in the CMIS protocol. The byte length of the DMA sender is greater than the maximum byte length of the EPL extended load page. As above, the byte can be set to 2049 bytes. The principle here is as mentioned above, and there are many principles in the following text that can refer to the above content of DMA channel configuration, so it will not be repeated here and in the following text.

[0121] Based on the optical module register address in the first receiving buffer and / or the second receiving buffer and the page mapping value of LowerMemory byte 127, the source address of the transmitting end is modified so that the optical module responds to the next current read operation; in practice, the source address of the transmitting end is modified, which is based on the Management Memory map management memory mapping specified by the CMIS protocol, and the specific source address is determined according to the optical module register address in the latest received receiving buffer (the first receiving buffer or the second receiving buffer) and the page mapping value of LowerMemory byte 127. After the above work is completed, the transmitting end DMA channel is reconfigured. In order to respond to subsequent private read operations, the transmitting end DMA channel and the transmitting end DMA request are enabled again at this time.

[0122] Similarly, in response to a new private write operation, the specific configuration process is as follows:

[0123] Before configuring the receiving DMA channel again, you first need to disable the receiving DMA request and the receiving DMA channel, that is, before the configuration is completed, the receiving DMA is in an inoperative state.

[0124] Clear the RX-FIFO queue of I3C. Set the receiving DMA receiving byte length based on the maximum byte length of the EPL extended load page in the CMIS protocol, and the receiving DMA receiving byte length is greater than the maximum byte length of the EPL extended load page plus a byte of register length; as above, the byte here can be set to 2050 bytes. Modify the destination address of the receiving DMA to two memory areas in the RAM of the optical module MCU as the first receiving buffer area and the second receiving buffer area; in subsequent private write operations, the first receiving buffer area and the second receiving buffer area are set alternately. The use of the Ping-pong mechanism can minimize the risk of delay and data loss. After the above work is completed, the receiving DMA channel is reconfigured. In order to respond to subsequent private write operations, the receiving DMA channel and the receiving DMA request are enabled again at this time.

[0125] After completing the above DMA channel configuration, the data in the first receiving buffer area and / or the second receiving buffer area is processed based on the management memory mapping in the CMIS protocol. Among them, the received data in the receiving buffer area is the optical module register address in the random write frame format, and the first data to the Nth data (such as Figure 2 Refer to the CMIS protocol and find the optical module control register that the I3C controller wants to control according to the current lower memory page mapping value and the optical module register address to perform corresponding control.

[0126] Among them, Figure 2 As shown, the random write frame format is composed of a start bit, an optical module address, a write flag bit, an optical module response bit, an optical module register address, a first check bit, a first data, a second check bit, ..., the Nth data, the N+1th check bit, and a stop bit. For ease of understanding, each component in the frame format will be further described.

[0127] Start bit (START): The starting condition on the I3C bus, used to start a communication, usually initiated by the master device, indicating the beginning of a new transaction.

[0128] Optical module address (Address): 7-bit or dynamically assigned I3C device address, used to uniquely identify the location of the target device (optical module).

[0129] Write Bit: A value of 0 indicates that the master device will write data to the target device (in this case, the write register address).

[0130] Optical module acknowledgement bit (ACK): The target device responds to the address and direction bits. Pulling it low indicates successful reception and readiness for communication.

[0131] Optical module register address (Register Address): Specifies the register address to be written inside the target device. This address will be used in subsequent reading.

[0132] Parity bit: After the host device writes the optical module register address, an odd parity bit is added to perform odd parity check on the address byte, which requires that the number of "1"s in all bits including the parity bit is an odd number. If the odd parity check fails, the target device may not respond or return an error flag, thereby ensuring the reliability of communication.

[0133] Optical module acknowledgement bit (ACK): The target device confirms again that it is ready to send data to the master device.

[0134] First data (Data 1): The first byte of data written to the register address, sent by the I3C controller.

[0135] Data N: The last data byte.

[0136] STOP: Indicates the completion of the current communication and releases the bus.

[0137] The above is the description of the execution process of the private write operation. Next, a brief description of the working process of the private read is as follows:

[0138] Receive and respond to the private read operation of the I3C controller.

[0139] The transmitting DMA transfers the data from the currently configured transmitting DMA source address into the I3C transmit data register in the destination of the transmitting DMA; when the private read data transfer is completed, an I3C peripheral STOP interrupt is generated based on the stop bit; in practice, the transmitting DMA automatically transfers the data from the configured transmitting DMA source address to the transmitting DMA destination address (the I3C transmit data register of the I3C peripheral). The source address here is determined by the optical module register address in the first receive buffer and the second receive buffer and the Lower Memory page mapping value. The private read operation is based on the above random read frame format; after the private read data transfer is completed, an I3C peripheral STOP interrupt is generated based on the stop bit.

[0140] Among them, as Figure 3 shown, the random read frame format consists of a start bit, an optical module address, a write flag bit, an optical module acknowledgment bit, an optical module register address, a parity bit, a repeated start bit, an optical module address, a read flag bit, an optical module acknowledgment bit, the first data, the first end judgment bit,..., the Nth data, the Nth end judgment bit, and a stop bit in sequence. Among them,

[0141] Repeated START: Restarts a frame of communication without sending STOP, used to switch from a write operation to a read operation.

[0142] Address: Sends the target device address again to prepare for the upcoming read operation.

[0143] Read Bit: A value of 1 indicates that the master device will read data from the target device.

[0144] The first end judgment bit (T bit): The response bit sent by the target device, used to notify the master device whether the target device itself continues to transmit data. Among them:

[0145] T bit = 1 indicates: Continue to transmit data, and the transmission is ended by the stop signal.

[0146] T bit = 0 indicates that the target device has ended data transmission.

[0147] The Nth end judgment bit (T bit): A response bit sent by the target device used to notify the master device whether the target device itself continues to transmit data. Among them:

[0148] T bit = 1 indicates that data transmission continues and is ended by the stop signal.

[0149] T bit = 0 indicates that the target device has ended data transmission. Calculate the actual data transmission length in the I3C peripheral STOP interrupt.

[0150] After completing the data transfer work in the private read operation, it is also necessary to configure the I3C peripheral in the STOP interrupt of the I3C peripheral; and configure the transmitting DMA channel bound to the I3C peripheral for the optical module to respond to the next private read operation of the I3C controller.

[0151] Among them, the I3C peripheral configuration is the same as the I3C peripheral configuration before the DMA channel configuration of the aforementioned private read or private write operation, which is also to enable the I3C peripheral STOP interrupt to realize the transfer of variable-length data between the I3C transmit data register and the optical module MCU memory. Then configure the corresponding DMA channel.

[0152] The process of reconfiguring the DMA channel for private read is as follows: Before reconfiguring the transmitting DMA channel again; first, it is necessary to disable the transmitting DMA request and the transmitting DMA channel, that is, before the configuration is completed, the transmitting DMA is in an inoperative state.

[0153] Empty the TX-FIFO queue of the I3C. Then set the transmission byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol. The transmitting DMA transmission byte length is greater than the maximum byte length of the EPL extended payload page; similarly, 2049 bytes can be set here for the byte.

[0154] Modify the transmitting source address based on the optical module register address in the first receive buffer and / or the second receive buffer and the LowerMemory byte 127 page mapping value for the optical module to respond to the next current read operation. Among them, as Figure 4 shown, the current read frame format consists of a start bit, an optical module address, a read flag bit, an optical module acknowledgment bit, the first data, the first end judgment bit,..., the Nth data, the Nth end judgment bit, and a stop bit in sequence. After the above work is completed, the transmitting DMA channel is reconfigured. To respond to subsequent private read operations, enable the transmitting DMA channel and the transmitting DMA request at this time.

[0155] After completing the above DMA channel configuration, the data in the transmit buffer is processed based on the managed memory mapping in the CMIS protocol. This mainly includes reading and clearing the registers of the Lower memory and the upper page (high page).

[0156] In addition, as Figure 5 shown, before executing the above working method, it also includes:

[0157] Step 1: Initialize the low-speed control pins of the optical module electrical interface.

[0158] Step 2: Initialize DMA. Specifically, it includes:

[0159] Step 2.1: Initialize the module I3C transmitter DMA channel.

[0160] Step 2.1.1: Configure the hardware request protocol of the transmitter DMA channel as burst.

[0161] Step 2.1.2: Configure the transmitter DMA direction as memory to peripheral.

[0162] Step 2.1.3: Configure the DMA source address mode as auto-increment mode.

[0163] Step 2.1.4: Configure the DMA destination address mode as fixed mode.

[0164] Step 2.2: Initialize the module I3C receiver DMA channel.

[0165] Step 2.2.1: Configure the hardware request protocol of the receiver DMA channel as burst (burst).

[0166] Step 2.2.2: Configure the receiver DMA direction as peripheral to memory.

[0167] Step 2.2.3: Configure the DMA source address mode as fixed mode.

[0168] Step 2.2.4: Configure the DMA destination address mode as auto-increment mode.

[0169] Step 3: Initialize the I3C peripheral, which mainly includes the following configurations:

[0170] Step 3.1: Configure the optical module as an I3C target device (Target).

[0171] Step 3.2: Configure the Provisioned ID (pre-configured identifier).

[0172] Step 3.3: Set the maximum read data length to 2048 bytes to support the reading of the EPL extended payload page with a maximum length of 2048 bytes specified in the CMIS protocol.

[0173] Step 3.4: Set the maximum write data length to 2049 to support the simultaneous writing of the EPL extended payload page with a maximum length of 2048 bytes specified in the CMIS protocol plus 1 byte of the optical module register address.

[0174] Step 3.5: Configure to support the maximum transmission rate. In the SDR (Single Data Rate) mode, it supports a maximum bandwidth of 12.5Mpbs.

[0175] Step 3.6: Enable the I3C transfer complete interrupt and the I3C error interrupt.

[0176] Step 3.7: Enable the event response interrupt of the I3C CCC (Common Command Codes) instructions including the dynamic address assignment instruction ENTDAA.

[0177] Step 4: Initialize the DSP, the transmitting unit, and the receiving unit.

[0178] In the above optical module working method based on I3C communication, after receiving the data sent by the I3C controller from the I3C bus, the data is transferred from the I3C peripheral to the RAM of the I3C optical module MCU through DMA, and the data in the RAM of the I3C optical module MCU is transferred to the I3C peripheral through DMA. The method of using DMA transfer can improve the I3C communication throughput and reduce the CPU load.

[0179] According to the maximum length of the EPL extended payload in the CMIS protocol, by setting the transmission lengths of the data sent and received by DMA to be greater than the actual data lengths received and sent by the I3C optical module, and combining with the completion interrupt of the I3C peripheral, the variable-length transmission of DMA is achieved.

[0180] In the process of receiving data by the I3C optical module, the Ping-Pong mechanism is used, that is, the data is received by alternately using the first receiving buffer and the second receiving buffer, which can minimize the risk of delay and data loss. The destination address of the receiving end DMA is two memory areas defined in the RAM of the I3C optical module MCU, which are named receiving buffer 1 and receiving buffer 2 here. In the private write operation, the I3C optical module will alternately use the first receiving buffer and the second receiving buffer to receive data to implement the Ping-Pong mechanism.

[0181] The above method has the following advantages:

[0182] 1. Improve the communication rate of the optical module to meet the high - bandwidth requirements;

[0183] In modern communication, optical modules need to handle high - speed data transmission. The I3C protocol can support the SDR mode with a maximum bandwidth of 12.5Mpbs and the HDR - DDR mode with a communication bandwidth of 25Mpbs, significantly improving the bus communication rate and meeting the requirements of optical modules for high bandwidth and high speed. Compared with the Fast Mode Plus (1Mpbs) used by traditional I2C modules in practice, I3C has achieved an order - of - magnitude improvement in data throughput, thus accelerating the data transmission between the optical module and the master device and the efficiency of control command processing. It is especially suitable for application scenarios that require high - speed and large - volume data exchange, such as firmware updates of the optical module's MCU and DSP. For firmware downloads of the same size, it takes 20.34s to update the firmware using I2C as the master device test board and an I2C optical module, while it only takes 6.28s to update the firmware using I3C as the controller test board and an I3C optical module.

[0184] 2. Use DMA to transfer data, reduce MCU occupancy, and improve real - time performance;

[0185] Using DMA to transfer data reduces the MCU occupancy rate, avoids frequently entering the interrupt to process data reception and transmission, enables the other tasks of the optical module to run more smoothly, and improves the real - time performance of the optical module.

[0186] 3. Operate with low power consumption;

[0187] The present invention utilizes the low - power - consumption characteristics of the I3C protocol to enable the I3C bus of the optical module to automatically enter the low - power mode in the non - communication state, thereby reducing the overall power consumption of the optical module. Especially in scenarios where a large number of devices are densely deployed, this optimization can significantly reduce the overall power consumption, extend the service life of the optical module, and reduce the maintenance cost.

[0188] 4. Improve the stability of the optical module and reduce signal interference;

[0189] The improved design of the I3C protocol includes better signal integrity and bus arbitration mechanisms, which can reduce communication conflicts and signal interference inside the optical module. Through these characteristics, the present invention improves the stability and reliability of the optical module, ensuring the long - term stable operation of the system.

[0190] In addition to disclosing the above - mentioned working method process, the present invention also proposes an optical module communication error recovery method, which is as follows:

[0191] When the I3C peripheral enters an error interrupt, the optical module MCU obtains and records the error source;

[0192] Configure and enable the STOP interrupt of the I3C peripheral in the error interrupt of the I3C peripheral and perform the configuration of the transmit DMA channel; the specific configuration of the transmit DMA channel includes:

[0193] First, it is necessary to disable the transmit DMA request and the transmit DMA channel, that is, before the configuration is completed, the transmit DMA is in an inoperative state; then clear the TX-FIFO (Transmit First-In-First-Out) queue of the I3C; then set the transmit DMA transmit byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, and the transmit DMA transmit byte length is greater than the maximum byte length of the EPL extended payload page; similarly, 2049 bytes can be set here for the byte; then modify the transmit DMA source address based on the CMIS memory mapped address where the current communication error occurs; then enable the transmit DMA channel and the transmit DMA request; among them, modifying the transmit DMA source address is specifically in practice: modify the transmit DMA source address, and this address is based on the Management Memory map management memory mapping specified in the CMIS protocol, and the specific source address is the CMIS memory mapped address where the current communication error occurs. Enable the I3C controller to read out the data with communication errors in the previous "random read" operation when performing the "current read" operation next time.

[0194] Configure and enable the completion interrupt of the I3C peripheral in the error interrupt of the I3C peripheral and perform the configuration of the receive DMA channel; the specific configuration of the receive DMA channel includes:

[0195] Before configuring the receive DMA channel again, first, it is necessary to disable the receive DMA request and the receive DMA channel, that is, before the configuration is completed, the receive DMA is in an inoperative state; clear the RX-FIFO queue of the I3C; set the receive DMA receive byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, and the receive DMA receive byte length is greater than the maximum byte length of the EPL extended payload page plus the register length of one byte; similarly, 2050 bytes can be set here for the byte; modify the destination address of the receive DMA to the memory area in the RAM of the MCU of the optical module as the receive buffer; then enable the receive DMA channel and the receive DMA request.

[0196] Based on the above working method of the optical module, an optical module is also provided, and the working method of this optical module adopts the above working method of the optical module based on I3C communication.

[0197] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A working method of an optical module based on I3C communication, characterized in that, The method includes: The optical module MCU continuously monitors whether a dynamic address has been allocated by the I3C controller by monitoring the dynamic address update interrupt generated by the I3C peripheral; The I3C peripheral is a peripheral electrically connected to the core of the optical module MCU; When it is detected that the dynamic address allocation is successful, configure the I3C peripheral, the receive DMA channel bound to the I3C peripheral, and the transmit DMA channel bound to the I3C peripheral. After the configuration is completed, wait for an operation instruction issued by the I3C controller; when the operation instruction is received, the optical module MCU responds to the private read operation or private write operation initiated by the I3C controller.

2. The working method of the optical module based on I3C communication according to claim 1, characterized in that, When it is detected that the dynamic address allocation is successful, configure the I3C peripheral, the receive DMA channel bound to the I3C peripheral, and the transmit DMA channel bound to the I3C peripheral, including enabling the STOP interrupt of the I3C peripheral to cooperate with the receive DMA channel to receive variable-length data sent by the I3C controller, and configuring the receive DMA channel to respond to the DMA private write operation; Specifically configuring the receive DMA channel includes: Setting the source address of the receive DMA to the I3C receive data register in the I3C peripheral; Setting the destination address of the receive DMA to at least two memory areas in the RAM of the optical module MCU as receive buffer areas; Setting the receive byte length of the receive DMA based on the maximum byte length of the EPL extended payload page in the General Management Interface Specification Protocol, where the receive byte length of the receive DMA > (the maximum byte length of the EPL extended payload page + one byte); Enabling the receive DMA channel; Enabling the receive DMA request.

3. The method for operating an optical module based on I3C communication according to claim 1, characterized in that, When it is detected that the dynamic address allocation is successful, configure the I3C peripheral, the receive DMA channel bound to the I3C peripheral, and the transmit DMA channel bound to the I3C peripheral, including configuring and enabling the STOP interrupt of the I3C peripheral to cooperate with the transmit DMA channel to send variable-length data to the I3C controller, and configuring the transmit DMA channel to respond to the DMA private read operation; Specifically configuring the transmit DMA channel includes: Setting the source address of the transmit DMA to a memory area in the RAM of the optical module MCU as a transmit buffer area; Setting the destination address of the transmit DMA to the I3C transmit data register in the I3C peripheral; Setting the transmit byte length of the transmit DMA based on the maximum byte length of the EPL extended payload page in the General Management Interface Specification Protocol, where the transmit byte length of the transmit DMA > the maximum byte length of the EPL extended payload page; Enabling the transmit DMA channel; Enabling the transmit DMA request.

4. The method for operating an optical module based on I3C communication according to claim 2, wherein, The working process of the private write is as follows: After the receive DMA is triggered, the received data is moved from the receive DMA source address to the receive buffer area in the receive DMA destination address; when the private write data transmission is completed, the STOP interrupt of the I3C peripheral is generated based on the stop bit in the data to implement the reception of variable-length data by the receive DMA; Calculating the actual received data length in the STOP interrupt of the I3C peripheral; Configure the I3C peripheral and the transmitting end DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private read operation of the I3C controller; Configure the I3C peripheral and the receiving end DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private write operation of the I3C controller; Process the data in the receive buffer based on the management memory mapping in the general management interface specification protocol.

5. The operating method of the optical module based on I3C communication according to claim 3, characterized in that, The working process of the private read is as follows: After the transmitting end DMA is triggered, the transmitting end DMA moves the data from the currently configured transmitting end DMA source address to the destination address of the transmitting end DMA; when the private read data transmission is completed, an I3C peripheral STOP interrupt is generated based on the stop bit in the data to achieve variable-length data transmission of the transmitting end DMA; Calculate the actual data transmission length in the STOP interrupt of the I3C peripheral; Configure the I3C peripheral and the transmitting end DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private read operation of the I3C controller; Process the data in the transmit buffer based on the management memory mapping in the general management interface specification protocol.

6. The method for operating an optical module based on I3C communication according to claim 4, wherein, The configuration of the I3C peripheral and the receiving end DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private write operation of the I3C controller, specifically includes: Disable the receiving end DMA request; Disable the receiving end DMA channel; Empty the RX-FIFO queue of the I3C; Set the receiving byte length of the receiving end DMA based on the maximum byte length of the EPL extended payload page in the general management interface specification protocol, where the receiving byte length of the receiving end DMA > (the maximum byte length of the EPL extended payload page + one byte); Modify the destination address of the receiving end DMA to the memory area in the RAM of the MCU of the optical module as the receive buffer; Enable the receiving end DMA channel; Enable the receiving end DMA request.

7. The optical module working method based on I3C communication according to claim 4 or 5, characterized in that, The configuration of the I3C peripheral and the transmitting end DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private read operation of the I3C controller, specifically includes: Disable the transmitting end DMA request; Disable the transmitting end DMA channel; Empty the TX-FIFO queue of the I3C; Set the transmitting byte length of the transmitting end DMA based on the maximum byte length of the EPL extended payload page in the general management interface specification protocol, where the transmitting byte length of the transmitting end DMA > the maximum byte length of the EPL extended payload page; Modify the transmitting end source address based on the optical module register address in the receive buffer and the page mapping value of the 127th byte of the Lower Memory, so that the optical module can respond to the next current read operation; Enable the transmitting end DMA channel; Enable the transmitting end DMA request.

8. The working method of the optical module based on I3C communication according to claim 6, characterized in that The private write operation is based on a random write frame format, where the random write frame format consists of a start bit, an optical module address, a write flag bit, an optical module response bit, an optical module register address, a first check bit, a first data, a second check bit, ……, an Nth data bit, an (N + 1)th check bit, and a stop bit in sequence.

9. The method for operating an optical module based on I3C communication according to claim 7, wherein The private read operation is based on a random read frame format, where the random read frame format consists of a start bit, an optical module address, a write flag bit, an optical module response bit, an optical module register address, a check bit, a repeated start bit, an optical module address, a read flag bit, an optical module response bit, a first data, a first end judgment bit, ……, an Nth data, an Nth end judgment bit, and a stop bit in sequence.

10. The method for operating an optical module based on I3C communication according to claim 7, wherein, The current read operation is based on a current read frame format, where the current read frame format consists of a start bit, an optical module address, a read flag bit, an optical module response bit, a first data, a first end judgment bit, ……, an Nth data, an Nth end judgment bit, and a stop bit in sequence.

11. The method for operating an optical module based on I3C communication according to any one of claims 1-5, characterized in that, It also includes an optical module communication error recovery method, which is as follows: When the I3C peripheral enters an error interrupt, the optical module MCU acquires and records the error source; Enable the I3C peripheral STOP interrupt and configure the transmitter DMA channel in the error interrupt of the I3C peripheral; The specific configuration of the transmitter DMA channel includes: Disable the transmitter DMA request; disable the transmitter DMA channel; clear the TX-FIFO queue of the I3C; set the transmitter DMA transmission byte length based on the maximum byte length of the EPL extended payload page in the general management interface specification protocol, where the transmitter DMA transmission byte length > the maximum byte length of the EPL extended payload page; modify the transmitter DMA source address based on the memory mapped address of the general management interface specification where the current communication error occurs; enable the transmitter DMA channel; enable the transmitter DMA request; Enable the I3C peripheral STOP interrupt and configure the receiver DMA channel in the error interrupt of the I3C peripheral; The specific configuration of the receiver DMA channel includes: Disable the receiver DMA request; disable the receiver DMA channel; clear the RX-FIFO queue of the I3C; set the receiver DMA reception byte length based on the maximum byte length of the EPL extended payload page in the general management interface specification protocol, where the receiver DMA reception byte length > (the maximum byte length of the EPL extended payload page + one byte); modify the destination address of the receiver DMA to the memory area in the RAM of the MCU of the optical module as the reception buffer; enable the receiver DMA channel; enable the receiver DMA request.

12. An optical module, characterized in that, The working method of the optical module adopts the working method of the optical module based on I3C communication described in any one of claims 1-11.

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