Time sequence convergence risk prediction method and device, electronic equipment and storage medium

Abstract

The invention relates to a time sequence convergence risk prediction method and device, electronic equipment and a storage medium. The time sequence convergence risk prediction method comprises the steps of obtaining a gate-level netlist of RTL codes; the gate-level netlist comprises a plurality of time sequence paths, and each time sequence path comprises a plurality of functional units; determining all target time sequence paths in the gate-level netlist; the target time sequence path is a time sequence path having data interaction with at least one other time sequence path; if clock paths of a starting point function unit and an end point function unit of the target time sequence path are provided with gated clocks, and the logic series of the target time sequence path exceeds a preset threshold value, a first prediction result is output, and the first prediction result represents that the target time sequence path is a risk path possibly having a time sequence convergence risk. According to the time sequence convergence risk prediction method, the time sequence convergence risk can be predicted in advance, the time sequence path with the time sequence convergence risk is modified in advance, and the design efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular, to a method, apparatus, electronic device, and storage medium for predicting timing convergence risks. Background Art

[0002] A clock gating (or "gated clock") unit can control the on / off of a clock using logic gates. A timing path includes a clock path and a data path. The clock gating unit is set in the clock path. The clock path and the data path are in a competitive relationship in terms of signal transmission. When the clock path and the data path do not meet the preset conditions, a timing convergence risk (Timing Violation) will occur. The timing convergence risk can also be understood as a timing difference between the clock of the gated clock unit itself and the enable signal of the gated clock.

[0003] The hardware design process of an integrated circuit sequentially includes: a functional design stage, design description and behavioral-level verification, logic synthesis, gate-level verification, and placement and routing. Currently, the timing convergence risk is usually checked and determined after the clock tree synthesis stage is completed. Among them, the clock tree synthesis is a task performed in the placement and routing stage.

[0004] Since the placement and routing stage has completed the previous design and verification work, if a timing convergence risk occurs in the gated clock unit, it may be necessary to modify the design code, adjust the code and verify it, which takes a lot of time and affects the chip design progress. Summary of the Invention

[0005] In view of this, this application aims to provide a method, apparatus, electronic device, and storage medium for predicting timing convergence risks, so as to realize the prediction of timing convergence risks in advance, reduce the adjustments required in the later stage, and reduce the cycle required for integrated circuit design.

[0006] In a first aspect, an embodiment of this application provides a method for predicting timing convergence risks, including: obtaining a timing constraint file and a gate-level netlist of RTL (Register Transfer Level) code; the gate-level netlist includes multiple timing paths, and each timing path includes multiple functional units; determining all target timing paths in the gate-level netlist; where the target timing path is: a timing path that has data interaction with at least one other timing path; the timing path includes a clock path and a data path; if the clock paths of the starting functional unit and the ending functional unit of the target timing path are both set with gated clocks, and the logical level of the target timing path exceeds a preset threshold, then output a first prediction result, where the first prediction result represents that the target timing path is a risk path that may have a timing convergence risk; the logical level is the number of logical gate devices connected in the data path of the target timing path.

[0007] The gate-level netlist can record the connection relationships between functional units. Therefore, in the embodiments of the present application, all timing paths can be determined using the gate-level netlist. If the data path and clock path of a timing path do not meet the preset conditions, there will be a timing convergence risk. When performing timing configuration for timing paths, multiple interacting timing paths are prone to not meeting the preset conditions. Therefore, target timing paths with data interaction can be determined from the gate-level netlist. For a timing path with a timing convergence risk, the clock paths of its starting functional unit and ending functional unit usually have gated clock units, and the more logic levels there are on its data path, the more likely a risk will occur. Therefore, it is possible to determine whether the starting functional unit and the ending functional unit have gated clocks and to determine the number of logic levels of the data path, so as to predict the risk paths that may have a timing convergence risk, and then provide the result of this prediction to the designer to assist the designer in troubleshooting the timing convergence risk. Among them, since the gate-level netlist can be obtained after the logic synthesis stage of integrated circuit design, using the gate-level netlist to predict the timing convergence risk can eliminate the need to wait for the completion of clock tree synthesis in the placement and routing stage, predict the timing convergence risk in advance, and the designer can reduce the waiting time for obtaining the timing convergence risk, without waiting for the completion of clock tree synthesis, so as to make modifications in advance, reduce the workload that needs to be adjusted later, and reduce the iteration time required for integrated circuit design.

[0008] In one embodiment, the gate-level netlist includes the timing violation margin of each timing path, and in the case where any timing path has a timing convergence risk, the timing violation margin of this timing path is negative; the determination of all target timing paths in the gate-level netlist includes: configuring the detection condition of the timing path to be that the timing violation margin is positive infinity; determining all timing paths in the gate-level netlist based on the configured detection condition; and determining all target timing paths from all timing paths.

[0009] If the timing violation margin of a timing path is negative, then this timing path has a timing convergence risk. Since the present application predicts the timing convergence risk in advance before placement and routing or clock tree synthesis, and some timing paths will cause new timing convergence risks due to placement and routing or other adjustments, therefore, in the embodiments of the present application, configuring the detection condition to be that the timing violation margin is positive infinity can determine all target timing paths, so as to judge some timing paths that do not have a timing convergence risk in the logic synthesis stage and determine whether they may have a timing convergence risk later, making the determination of risk paths more complete, reducing the workload that needs to be adjusted later, reducing the iteration time required for integrated circuit design, and thus improving the design efficiency of integrated circuits.

[0010] In one embodiment, obtaining the gate-level netlist of the timing constraint file includes: obtaining the RTL code and the timing constraint file corresponding to the RTL code; performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist.

[0011] In the design of integrated circuits, logic synthesis is usually performed. In the embodiments of the present application, the RTL code describes the conversion and circuit between register signals at all levels in the timing logic, and the timing constraint file is used to constrain the timing of each circuit in the RTL code. Therefore, through the timing constraint file, logic synthesis can be performed on the RTL code to obtain the gate-level netlist of the RTL code. And logic synthesis itself is a process in chip design. Through logic synthesis, a gate-level netlist for predicting timing convergence risk can be obtained without performing other additional work, simplifying the integrated circuit design process and improving the design efficiency of integrated circuits.

[0012] In one embodiment, after performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist, the method further includes: detecting the target logic function in the gate-level netlist, where the target logic is the logic function that does not involve timing in the gate-level netlist; filtering out the functional units corresponding to the target logic function from the gate-level netlist; correspondingly, determining all the target timing paths in the gate-level netlist, including: determining all the target timing paths in the gate-level netlist from the gate-level netlist after filtering out the functional units corresponding to the target logic.

[0013] In the embodiments of the present application, some logic functions in the gate-level netlist are irrelevant to the timing convergence risk. Filtering them out from the gate-level netlist to determine the target timing paths from the filtered gate-level netlist can reduce the workload of determining the target timing paths and improve the efficiency of determining the target timing paths.

[0014] In one embodiment, after performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist, the method further includes: classifying each timing path in the gate-level netlist based on the transmission direction of the clock signal in each timing path to obtain a set of timing paths corresponding to each of multiple classifications; determining all the target timing paths in the gate-level netlist, including: determining all the target timing paths from the set of timing paths corresponding to the target classification among the multiple classifications; the target classification is a preset classification type that may have a timing convergence risk.

[0015] There are multiple types of timing paths, and some timing paths will not have a gated-clock timing convergence risk. Therefore, in the embodiments of the present application, the target timing paths can be determined only from the set of timing paths corresponding to the target classification that may have a timing convergence risk, so as to reduce the workload required to determine the target timing paths and improve the efficiency of determining the target timing paths.

[0016] In one embodiment, the method further includes: for each of the risk paths, determining the logical level number of the risk path; and determining the risk level of the risk path based on the corresponding relationship between the preset logical level number and the risk level and the logical level number of the risk path.

[0017] It can be understood that a timing path generally includes a data path and a clock path, and the data path is usually composed of logic gate devices. The timing convergence risk is caused by the competition between the data path and the clock path, such that the signal transmission by the two does not meet the preset conditions. If the number of logic gate devices connected between the starting functional unit and the ending functional unit of the target timing path is larger, it is more difficult for the clock path of this timing path to match the data path, and it is more difficult for the data path and the clock path to meet the preset conditions for signal transmission. Then, the possibility of the target timing path having a timing convergence risk is higher. Therefore, in the embodiments of the present application, the risk path of the risk path can be judged by the number of logical levels to prompt the user to perform different processing.

[0018] In one embodiment, the corresponding relationship between the preset logical level number and the risk level includes: the risk level corresponding to the logical level number greater than the first threshold is a high risk; the high risk indicates that code modification is required for the risk path; the risk level corresponding to the logical level number greater than the second threshold and less than or equal to the first threshold is a medium risk; the risk path with the medium risk indicates that the risk path waits to detect the timing convergence risk after clock tree synthesis; the risk level corresponding to the logical level number less than or equal to the second threshold is a low risk.

[0019] The present application predicts the timing convergence risk in advance, and can provide guiding suggestions on whether to modify the code in the timing constraint file. In the above implementation manner, by classifying the risk paths into high risks, medium risks, and low risks, it is convenient for the user to timely adjust the timing paths with high risks, wait for the clock tree synthesis for the medium-risk paths to determine whether adjustment is required, and not adjust the low-risk timing paths. Thus, guiding suggestions for modification are provided for the designers, enabling the designers to quickly determine the timing paths that need to be adjusted and make adjustments according to the actual situation, improving work efficiency, and further improving the chip design efficiency. In addition, compared with determining the timing convergence risk after the clock tree synthesis of the placement and routing, the data volume of the design file without placement and routing is smaller, and the retrieval efficiency of the timing paths will be higher, which can further improve work efficiency and chip design efficiency.

[0020] Second aspect, an embodiment of the present application provides a timing convergence risk prediction device, including: a comprehensive module, configured to obtain a gate-level netlist of RTL code; the gate-level netlist includes multiple timing paths, and each of the timing paths includes multiple functional units; a detection module, configured to determine all target timing paths in the gate-level netlist; the target timing path is: a timing path that has data interaction with at least one other timing path; the timing path includes a clock path and a data path; a prediction module, configured to output a first prediction result if both the clock paths of the starting functional unit and the ending functional unit of the target timing path are set with gated clocks, and the logic level of the target timing path exceeds a preset threshold, where the first prediction result indicates that the target timing path is a risk path that may have a timing convergence risk; the logic level is the number of logic gate devices connected in the data path of the target timing path.

[0021] Third aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, where computer-readable instructions are stored in the memory, and the computer-readable instructions are executed by the processor to execute the method as described in the first aspect.

[0022] Fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer program is stored in the readable storage medium, and when the computer program runs on a computer, the computer is caused to execute the method as described in the first aspect. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a flowchart of a timing convergence risk prediction method provided by an embodiment of the present application; Figure 2 It is an implementation flowchart of a timing convergence risk prediction method provided by an embodiment of the present application; Figure 3 It is a schematic diagram of a timing convergence risk prediction device provided by an embodiment of the present application; Figure 4 It is a schematic diagram of an electronic device provided by an embodiment of the present application.

[0025] Icons: Timing convergence risk prediction device 200; Comprehensive module 210; Detection module 220; Prediction module 230; Electronic device 300; Processor 310; Memory 320. Detailed implementation manners

[0026] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] Please refer to Figure 1 , Figure 1 which is a flowchart of a timing convergence risk prediction method provided by an embodiment of the present application. The timing convergence risk prediction method includes: S110, obtaining a gate-level netlist of the RTL code.

[0028] The RTL code is used to describe the circuit of the chip design, and the gate-level netlist is used to record the connection relationships between the gate-level devices in the integrated circuit design. One or more gate-level devices can form a functional unit, and different functional units are connected according to the design requirements to form a path for implementing certain functions. Data can be transmitted between the functional units on this path. Therefore, it can also be called a data path (or "Data path"). At the same time, if multiple functional units on the same path also transmit clock signals, then this path is also a clock path (or "Clock path").

[0029] In the embodiment of the present application, the timing path (or "Timing path") consists of two parts: the data path and the clock path. The information of the data path and the clock path will be configured in the timing constraint file and recorded in the gate-level netlist. The specific definitions of the RTL code and the gate-level netlist can refer to the prior art and will not be elaborated here.

[0030] Therefore, in the embodiment of the present application, the gate-level netlist can record multiple timing paths, and each timing path can include multiple functional units.

[0031] In one embodiment, obtaining the gate-level netlist of the RTL code may include: obtaining a timing constraint file and the RTL code; performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist.

[0032] In this embodiment, the gate-level netlist of the RTL code can be obtained. Usually, to obtain the gate-level netlist, the corresponding timing constraint file of the RTL, that is, the SDC (Synopsys design constraints, design constraint file), needs to be obtained. The SDC configures the timing constraints of each circuit, functional unit or device in the integrated circuit design. For example, the type and quantity of repeaters allowed to be connected to the port of a certain functional unit. Among them, the repeater is used to adjust the timing by adjusting the delay.

[0033] The RTL code includes registers at all levels in the sequential logic, as well as combinational logic in the sequential logic, etc. The timing constraint file is used to constrain the circuit described by the RTL code. In the embodiments of the present application, the gate-level netlist of the timing constraint file can also be understood as the gate-level netlist of the RTL code. Therefore, in the embodiments of the present application, the gate-level netlist of the RTL code can be obtained by performing logic synthesis on the timing constraint file and the RTL code in the logic synthesis stage. The specific process of logic synthesis can refer to the prior art, for example, using the logic synthesis function in some existing integrated circuit design software, which will not be elaborated here.

[0034] In the process of integrated circuit design, logic synthesis is usually performed. The embodiments of the present application can directly adopt the gate-level netlist in the logic synthesis stage without performing other additional processes to obtain the gate-level netlist, simplifying the work required for timing convergence risk verification and improving the design efficiency of the integrated circuit.

[0035] In one embodiment, after obtaining the gate-level netlist, the target logic function in the gate-level netlist can also be detected, and the functional unit corresponding to the target logic function can be filtered out from the gate-level netlist. Among them, the target logic is the logic function that does not involve timing in the gate-level netlist.

[0036] The logic function can be implemented by one or more functional units together. The gate-level netlist describes the connection relationship between all devices in the timing constraint file and is presented in the form of code. In the timing constraint file, devices for port connection of different functional modules are defined. Although some devices or functional units define timing, they may not participate in timing-related work, so it is impossible for them to have timing convergence risks. In the embodiments of the present application, such logic functions that do not involve timing can be filtered out from the gate-level netlist so that they do not participate in the determination of the target timing path, reducing the workload of determining the target timing path and improving the determination efficiency.

[0037] In the embodiments of the present application, it can be to filter out the functional unit corresponding to the target logic function from the gate-level netlist. Among them, some functional units may involve multiple logic functions. If any one of the logic functions involved in the functional unit is related to timing, the functional unit will be retained. The implementation of filtering out the target logic function can refer to the prior art. For example, using optimization functions such as enable optimize unload flipflop and remove useless logic in some logic synthesis tools, which will not be elaborated here.

[0038] In one embodiment, after obtaining the gate-level netlist, the timing paths can also be classified based on the transmission direction of the clock signal in each timing path in the gate-level netlist to obtain a set of timing paths corresponding to each of the multiple classifications.

[0039] Timing paths can be classified according to the transmission direction of the clock signal. For example, the clock signal is input from the clock signal source to the register, the clock signal is output from the register to the register, and output to the memory, etc. And the timing convergence risk may only occur in some types of timing paths. In the embodiments of the present application, the timing paths can be classified first, and then the timing convergence risk can be predicted from the set of timing paths corresponding to the classification where the timing convergence risk may occur.

[0040] For example, in some embodiments of the present application, the classification of timing paths can include: IN2REG (input to register path group), REG2REG (register to register path group), TOMEM (to memory path group), FROMMEM (from memory path group), IN2OUT (in to out path group), FEEDTHROUGH (feedthrough path group). In the above classification, the timing convergence risk only appears in REG2REG, TOMEM, and FROMMEM. Then REG2REG, TOMEM, and FROMMEM can be used as the preset classification types where the timing convergence risk may occur, that is, as the target classification.

[0041] Among them, the filtering of the functions corresponding to the preset logic functions and the classification of the timing paths can be used simultaneously or separately.

[0042] S120, determine all the target timing paths in the gate-level netlist.

[0043] The timing convergence risk is caused by the competition between the clock path and the data path in the timing path, resulting in the signal transmission between the two not meeting the preset conditions. Usually, for an independent timing path, the data on this timing path is not transmitted to other paths, then the data path and the clock path on this timing path are easy to configure to meet the preset conditions.

[0044] A timing path includes a data path. There may be functional units interconnected between different data paths for data transmission, that is, there is data interaction. If there is data interaction between different timing paths, the mutual transmission of data will compete with the clock signal for the path. If they are not accurately configured during design, it may occur that the transmission of data and clock signal does not meet the preset conditions. For example, during the design process, when a designer configures the data path and clock path of a certain timing path, some other paths connected to the data path may be ignored. When configuring the data path and clock path under the condition of ignoring some paths, when data is transmitted between the timing path and the ignored part of the path, it may affect the transmission of the clock signal, and the competition between the data path and the clock path does not meet the preset conditions, resulting in a timing convergence risk for the timing path.

[0045] Therefore, the target timing path is a timing path that has data interaction with at least one other timing path. In the embodiments of the present application, the target timing path can be determined first, and then the timing convergence risk of the target timing path can be predicted. In this embodiment, it can be determined whether there is data interaction by judging whether there is signal transmission between different timing paths or whether there is a connection on the circuit, which will not be elaborated here.

[0046] In some embodiments, all the target timing paths in the gate-level netlist can be determined from the gate-level netlist after filtering out the functional units corresponding to the target logic function. In some embodiments, it can also be to determine all the target timing paths from the set of timing paths corresponding to the target classification among multiple classifications. In some embodiments of the present application, the gate-level netlist may include the timing violation margin (also known as "Slack", "timing margin", "timing allowance", etc.) of each timing path.

[0047] The timing violation margin is the difference between the actual time used and the designed required time, which is a term indicating whether the design meets the timing. A positive timing violation margin indicates that the timing is met, and a negative Slack indicates that the timing is not met. The timing violation margin of each timing path is usually recorded in the gate-level netlist, or the timing violation margin is calculated during the logic synthesis stage. The specific content of the timing violation margin will not be elaborated here. Therefore, when there is a timing convergence risk for any timing path, the timing violation margin of this timing path is negative. Therefore, the timing violation margin can currently be used to detect the timing path that may have a timing convergence risk.

[0048] However, in the embodiments of the present application, it lies in predicting the timing convergence risk in advance. After logic synthesis of an integrated circuit, new timing convergence risks may still occur due to adjustments in the gate-level verification and placement and routing phases. Therefore, the timing violation margin cannot be directly used for predicting the timing convergence risk. However, all paths involving timing have a timing violation margin. Therefore, in the embodiments of the present application, the timing violation margin can be used as a detection condition to detect timing paths.

[0049] In an embodiment of the present application, the detection condition for a timing path can be configured such that the timing violation margin is positive infinity; all timing paths in the gate-level netlist are determined based on the configured detection condition; and finally, all target timing paths are determined from all the timing paths. Thus, by using a positive-infinity timing violation margin to detect timing paths, it is possible to check as comprehensively as possible the number of timing paths. The detection result includes timing paths that do not have a timing convergence risk at the current stage, so as to predict whether such timing paths may have a timing convergence risk in subsequent stages.

[0050] In addition, it can also be to detect the timing violation margin of each timing path in the timing path set corresponding to the target classification from the gate-level netlist after filtering the functional units corresponding to the preset logic functions and classifying the timing paths, and then determine the target timing paths from the timing paths obtained by the detection of the timing violation margin.

[0051] S130, if both the starting functional unit and the ending functional unit of the target timing path are provided with gated clocks, and the logic level of the target timing path exceeds a preset threshold, then output a first prediction result.

[0052] After obtaining the target timing path, it is necessary to determine whether it may have a timing convergence risk.

[0053] The timing convergence risk usually occurs on a timing path where there are gated clock units on the clock paths of both the starting functional unit and the ending functional unit, that is, if there are gated clock units in both the starting functional unit and the ending functional unit of the timing path, this timing path may have a timing convergence risk. Also, the more logic levels there are on the data path, the more likely a risk is to occur. The logic level is the number of logic gate devices connected in the data path of the target timing path.

[0054] Therefore, in the embodiments of the present application, it can be determined that there are gating clock units in the starting functional unit and the ending functional unit of the timing path. If there are gating clock units on the clock paths of both of them, and the logic levels of the target timing path exceed a preset threshold, then a first prediction result is output, where the first prediction result indicates that the target timing path is a risk path that may have a timing convergence risk. If only one of them is provided with a gating clock, or neither of them is provided with a gating clock, then in some embodiments, a second prediction result may also be output, and the second prediction result may indicate that the target timing path is a risk path that does not have a timing convergence risk.

[0055] In addition, it should be noted that the first prediction result is obtained by prediction, and there may still be no timing convergence risk for this path, which needs to be confirmed by the designer or determined after clock tree synthesis. That is, the first prediction result is used to guide the designer to check for timing convergence risks, so that the designer can timely carry out other work of integrated circuit design.

[0056] In the embodiments of the application, if there are gating clock units on the respective clock paths of the starting functional unit and the ending functional unit of the timing path, there may be a timing convergence risk for this timing path, and the more the number of logic gate devices between the starting functional unit and the ending functional unit, the more likely this timing path is to have a timing convergence risk. For example, when the logic levels on the data path between the starting functional unit and the ending functional unit of the target timing path exceed a preset threshold, it can be determined that there is a greater possibility of a timing convergence risk for this risk path. Here, it should be distinguished that it is to judge whether there is a gating clock unit on the clock path of the timing path, and it is to judge the logic levels on the data path of the timing path.

[0057] The preset threshold can be determined according to the type, scale, etc. of the chip design. In one embodiment, after determining the risk path, for each risk path: the logic levels of the risk path can also be determined, and the risk level of the risk path can be determined based on the corresponding relationship between the preset logic levels and the risk levels and the logic levels of the risk path. Among them, the logic levels are the levels of the logic gate devices connected in the data path of the risk path.

[0058] The timing path includes a data path. The longer the data path, the more difficult it is to meet the preset requirements between the data path and the clock path, and the more likely this timing path is to have a timing convergence risk. Therefore, in the embodiments of the present application, the risk level of this timing path can also be estimated using the logic levels.

[0059] In the embodiments of the present application, the correspondence between the preset logic level and the risk level can be set according to actual needs. For example, high risk and low risk are set, and a threshold of the logic level is set. A timing path with a logic level greater than the threshold is predicted as high risk, and conversely, a timing path with a logic level less than the threshold is predicted as low risk. Multiple risk levels can also be set, and a range of logic levels is set for each risk level. If the logic level of a timing path falls within a certain range, the timing path is marked with the risk level corresponding to that range.

[0060] In some embodiments of the present application, the correspondence between the preset logic level and the risk level includes: the risk level corresponding to a logic level greater than the first threshold is high risk; high risk indicates that the risk path needs code modification; the risk level corresponding to a logic level greater than the second threshold and less than or equal to the first threshold is medium risk; the risk path of medium risk indicates that the risk path needs to wait for clock tree synthesis and then detect the timing convergence risk; the risk level corresponding to a logic level less than or equal to the second threshold is low risk.

[0061] Exemplarily, the first threshold is 26 and the second threshold is 18. If the logic level of a certain target timing path is greater than 26, the target timing path is marked as high risk. If the logic level of a certain target timing path is between 18 and 26, the target timing path is marked as medium risk; if the logic level of a certain target timing path is less than 18, the target timing path is marked as medium risk.

[0062] For a timing path with high risk, there is a greater possibility of timing convergence risk, so the designer can be reminded to adjust in time. For a timing path with medium risk, there is no timing convergence risk at the current stage, but there may be a timing convergence risk after later adjustment. Therefore, the designer can be prompted to pay attention and wait for clock tree synthesis before detecting again to determine whether modification is needed. For a timing path with low risk, the possibility of timing convergence risk is low, and no processing is required at the current stage.

[0063] In the embodiments of the present application, the gate-level netlist can record the connection relationships between functional units. Therefore, all timing paths can be determined using the gate-level netlist. If the data path and clock path of a timing path do not meet the preset conditions, there will be a timing convergence risk. When performing timing configuration for timing paths, multiple interacting timing paths are likely to not meet the preset conditions. Therefore, target timing paths with data interaction can be determined from the gate-level netlist. For a timing path with a timing convergence risk, its clock path from the starting functional unit to the ending functional unit usually has a gated clock unit. Therefore, it is possible to determine whether the starting functional unit and the ending functional unit have a gated clock to predict the risk paths that may have a timing convergence risk, and then provide the predicted result to the designer to assist the designer in troubleshooting the timing convergence risk, guiding the optimization of RTL code, and effectively predicting timing risks in the early stage of design, rather than having to wait until the later stage of physical design or the later stage of automatic placement and routing to discover this problem. Whether there is a timing convergence risk for the target timing path. Among them, the gate-level netlist can be obtained after the logic synthesis stage of integrated circuit design. Using the gate-level netlist to predict the timing convergence risk can eliminate the need to wait for the completion of clock tree synthesis in the placement and routing stage, predict the timing convergence risk in advance, and designers can reduce the waiting time for obtaining the timing convergence risk, without having to wait for the completion of clock tree synthesis, so as to make modifications in advance, reduce the workload that needs to be adjusted in the later stage, and reduce the iteration time required for integrated circuit design.

[0064] For ease of understanding, an example is provided here, which should not be construed as a limitation to the present application. Please refer to Figure 2 , Figure 2 which is a flowchart of an embodiment of a method for predicting timing convergence risk provided by the present application.

[0065] First, a timing constraint file and RTL code of the integrated circuit design can be obtained, and the timing constraint file and RTL code are logically synthesized to obtain a gate-level netlist.

[0066] Next, preliminary processing is performed on the gate-level netlist. For example, using the filtering function in the logic synthesis tool to filter out the functional units of the logic functions that are irrelevant to timing from the gate-level netlist. Then, according to the type of signal transmission, each timing path in the gate-level netlist is classified to obtain multiple classified timing path sets.

[0067] Furthermore, the timing paths in the gate-level netlist are classified to determine a set of timing paths that may have a timing convergence risk, and from the set of timing paths of the target classification that may have a timing convergence risk, detection is performed using a timing violation margin of positive infinity to determine all timing paths with a timing violation margin. Then, target timing paths with data interaction are determined from the timing paths with a timing violation margin.

[0068] Then, it is determined whether gated clocks are set for the clock paths of the starting functional unit and the ending functional unit of each target timing path. If both the starting functional unit and the ending functional unit have gated clocks, and the logical level count of the data path between the starting functional unit and the ending functional unit exceeds a preset threshold, it is determined as a high-risk path for timing convergence. Then, the target timing path is predicted as a risk path that may have a risk of timing convergence, and the first prediction result is output.

[0069] Finally, the risk level of the risk path can also be determined. According to the logical records, each risk path is divided into high risk, medium risk, and low risk, and the high-risk paths for timing convergence are fed back to the designer for RTL optimization.

[0070] Based on the same inventive concept, an embodiment of the present application also provides a timing convergence risk prediction device. Please refer to Figure 3 , Figure 3 which is a schematic diagram of a timing convergence risk prediction device 200 provided in an embodiment of the present application. The timing convergence risk prediction device 200 includes: a synthesis module 210, a detection module 220, and a prediction module 230.

[0071] The synthesis module 210 is configured to obtain a timing constraint file and a gate-level netlist of the RTL code; the gate-level netlist includes multiple timing paths, and each timing path includes multiple functional units.

[0072] The detection module 220 is configured to determine all target timing paths in the gate-level netlist; the target timing path is: a timing path that has data interaction with at least one other timing path.

[0073] The prediction module 230 is configured to output a first prediction result if gated clocks are set for both the starting functional unit and the ending functional unit of the target timing path, and the first prediction result indicates that the target timing path is a risk path that may have a risk of timing convergence.

[0074] In one embodiment, the detection module 220 is further configured to configure the detection condition of the timing path as the timing violation margin being positive infinity; determine all timing paths in the gate-level netlist based on the configured detection condition; and determine all target timing paths from all the timing paths.

[0075] In one embodiment, the synthesis module 210 is further configured to obtain a timing constraint file and the RTL code; perform logic synthesis on the timing constraint file and the RTL code to obtain a gate-level netlist.

[0076] In one embodiment, the synthesis module 210 is further configured to filter out the functional units corresponding to the target logic function from the gate-level netlist. The detection module 220 is further configured to determine all target timing paths in the gate-level netlist after filtering out the functional units corresponding to the target logic function.

[0077] In one embodiment, the synthesis module 210 is further configured to classify each timing path in the gate-level netlist based on the transmission direction of the clock signal in each timing path, so as to obtain a set of timing paths corresponding to each of the multiple classifications. The detection module 220 is further configured to determine all target timing paths from the set of timing paths corresponding to the target classification among the multiple classifications; the target classification is a preset classification type that may have a timing convergence risk.

[0078] In one embodiment, the prediction module 230 is further configured to, for each of the risk paths: determine the logic level of the risk path; the logic level is the level of the logic gate devices connected in the data path of the risk path; and determine the risk level of the risk path based on the corresponding relationship between the preset logic level and the risk level and the logic level of the risk path.

[0079] In one embodiment, the prediction module 230 is configured with the following preset corresponding relationship between the logic level and the risk level: the risk level corresponding to a logic level greater than the first threshold is a high risk; the high risk indicates that the risk path needs to be modified in code; the risk level corresponding to a logic level greater than the second threshold and less than or equal to the first threshold is a medium risk; the risk path with the medium risk indicates that the risk path needs to wait for clock tree synthesis and then detect the timing convergence risk; the risk level corresponding to a logic level less than or equal to the second threshold is a low risk.

[0080] It can be understood that the functions implemented by the timing convergence risk prediction device 200 are similar to those of the foregoing timing convergence risk prediction method. For specific content, reference can be made to the foregoing timing simulation method, which will not be elaborated here.

[0081] Please refer to Figure 4 , based on the same inventive concept, an embodiment of the present application further provides an electronic device 300, which can be used as the execution subject of the foregoing timing convergence risk prediction method, that is, it can be a server device, including: a processor 310 and a memory 320 communicatively connected to the processor 310, and multiple virtual systems can be arranged by using resources including the processor 310 and the memory 320.

[0082] In the embodiment of the present application, the memory 320 may store computer-readable instructions executable by the processor 310. The computer-readable instructions are executed by the processor 310, so that the processor 310 can execute the timing convergence risk prediction method in the foregoing embodiment.

[0083] The processor 310 and the memory 320 can be connected via a communication bus.

[0084] The processor 310 can be an integrated circuit chip with signal processing capabilities. The processor 310 can be a general-purpose processor, including a CPU, an NP (Network Processor), etc.; it can also be a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices, transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor, etc.

[0085] The memory 320 can include, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0086] It can be understood that the electronic device 300 can also include more general modules required by itself, which will not be introduced one by one in the embodiments of the present application.

[0087] Based on the same inventive concept, the embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, and the computer program, when run, executes the method provided in the above embodiments.

[0088] The storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that integrates one or more available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as an SSD (Solid State Disk)).

[0089] In the embodiments provided in the present application, it should be understood that the disclosed methods and devices can also be implemented in other ways. The device embodiments described above are only illustrative. In each embodiment of the present application, the various functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0090] If the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0091] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0092] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitations, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

Claims

1. A method for predicting timing convergence risk, characterized in that, it includes: Obtain the gate-level netlist of the RTL code; the gate-level netlist includes multiple timing paths, and each of the timing paths includes multiple functional units; Determine all target timing paths in the gate-level netlist; wherein, the target timing path is: a timing path that has data interaction with at least one other timing path; the timing path includes a clock path and a data path; If both the start functional unit and the end functional unit of the target timing path are set with gated clocks on their clock paths, and the logic level of the target timing path exceeds a preset threshold, then output a first prediction result, and the first prediction result indicates that the target timing path is a risk path that may have timing convergence risk; the logic level is the number of logic gate devices connected in the data path of the target timing path.

2. The method for predicting timing convergence risk according to claim 1, characterized in that, The gate-level netlist includes the timing violation margin of each timing path, and in the case that any one timing path has a timing convergence risk, the timing violation margin of this timing path is negative; The determining all target timing paths in the gate-level netlist includes: Configuring the detection condition of the timing path to be positive infinity for the timing violation margin; Determining all timing paths in the gate-level netlist based on the configured detection condition; Determining all target timing paths from all the timing paths.

3. The method for predicting timing convergence risk according to claim 1, characterized in that, The obtaining the gate-level netlist of the RTL code includes: Obtaining the RTL code and the timing constraint file corresponding to the RTL code; Performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist.

4. The method for predicting timing convergence risk according to claim 3, characterized in that, After performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist, the method further includes: Detecting the target logic function in the gate-level netlist, and the target logic is the logic function in the gate-level netlist that does not involve timing; Filtering out the functional units corresponding to the target logic function from the gate-level netlist; Correspondingly, determining all target timing paths in the gate-level netlist includes: determining all target timing paths in the gate-level netlist from the gate-level netlist after filtering out the functional units corresponding to the target logic function.

5. The method for predicting timing convergence risk according to claim 3, characterized in that, After performing logic synthesis on the timing constraint file and the RTL code to obtain the gate-level netlist, the method further includes: Classifying each timing path in the gate-level netlist according to the transmission direction of the clock signal in the timing path to obtain multiple sets of timing paths corresponding to each classification; The determining all target timing paths in the gate-level netlist includes: Determine all target timing paths from the set of timing paths corresponding to the target classification among the multiple classifications; the target classification is a preset classification type that may have timing convergence risks.

6. The timing convergence risk prediction method according to any one of claims 1-5, wherein, the method further includes: For each of the risk paths: Determine the logic level of the risk path; determine the risk level of the risk path based on the corresponding relationship between the preset logic level and the risk level and the logic level of the risk path.

7. The timing convergence risk prediction method according to claim 6, wherein, the corresponding relationship between the preset logic level and the risk level includes: The risk level corresponding to a logic level greater than the first threshold is a high risk; the high risk indicates that the risk path needs to be code-modified; The risk level corresponding to a logic level greater than the second threshold and less than or equal to the first threshold is a medium risk; the risk path of the medium risk indicates that the risk path needs to wait for clock tree synthesis and then detect the timing convergence risk; The risk level corresponding to a logic level less than or equal to the second threshold is a low risk.

8. A timing convergence risk prediction device, wherein, it includes: A synthesis module for obtaining the gate-level netlist of the RTL code; the gate-level netlist includes multiple timing paths, and each timing path includes multiple functional units; A detection module for determining all target timing paths in the gate-level netlist; the target timing path is: a timing path that has data interaction with at least one other timing path; the timing path includes a clock path and a data path; A prediction module for outputting a first prediction result if both the clock paths of the starting functional unit and the ending functional unit of the target timing path are set with gated clocks and the logic level of the target timing path exceeds a preset threshold, and the first prediction result indicates that the target timing path is a risk path that may have timing convergence risks; the logic level is the number of levels of logic gate devices connected in the data path of the target timing path.

9. An electronic device, wherein, it includes a memory and a processor, and the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes the timing convergence risk prediction method according to any one of claims 1-7.

10. A computer-readable storage medium, wherein, the readable storage medium stores a computer program. When the computer program runs on a computer, the computer executes the timing convergence risk prediction method according to any one of claims 1-7.

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