Flash memory chip testing methods

Abstract

This application discloses a flash memory chip testing method, which includes: providing multiple flash memory chips; performing dynamic power consumption testing on the multiple flash memory chips during a first erase operation before routine functional testing to obtain a first power consumption value for each flash memory chip; performing dynamic power consumption testing on the flash memory chips after passing routine functional testing during a second erase operation to obtain a second power consumption value for each flash memory chip; calculating the power consumption change value of each flash memory chip based on the first and second power consumption values; performing outlier statistics based on the power consumption change values ​​of the multiple flash memory chips to identify outlier flash memory chips; and removing outlier flash memory chips. Using this solution can effectively improve the reliability of flash memory chips and reduce the risk of flash memory chips with potential problems, especially charge pump leakage, entering the end-user market and causing end-user failures.

Description

Technical Field

[0001] This application relates to the field of flash memory testing technology, and specifically to a flash memory chip testing method. Background Technology

[0002] Flash memory, as an integrated circuit storage device, is widely used in electronic products such as portable computers, mobile phones, and digital music players because it has the function of electrically erasable and rewritable storage of information, and the stored information will not be lost after power is turned off.

[0003] In power supply design, flash memory chips typically incorporate multiple charge pumps to provide the appropriate voltage to each memory cell. When operating at high frequencies, certain process defects can cause some components within the charge pump to fail under frequent use, leading to device damage such as high-voltage NMOS burnout or leakage in the flash memory area. Current flash memory yield testing methods, such as routine trimming of the erase voltage (VEE) and programming voltage (VEP), are insufficient to simulate the frequent use of charge pumps in end-user applications. If chips with these defects are shipped as standard samples to the end-user market, continuous use by end users may cause the charge pumps to fail rapidly, resulting in a reliability failure event. Summary of the Invention

[0004] This application provides a flash memory chip testing method to eliminate flash memory chips with some process defects as much as possible during the yield testing stage, thereby ensuring the quality of flash memory that flows to end users.

[0005] Therefore, the embodiments of this application provide the following technical solutions:

[0006] This application provides a flash memory chip testing method, the method comprising:

[0007] Provides multiple flash memory chips;

[0008] Dynamic power consumption tests were performed on the multiple flash memory chips during the first erase operation before routine functional testing to obtain the first power consumption value of each flash memory chip.

[0009] Dynamic power consumption tests were performed on flash memory chips that had passed routine functional tests during the second erase operation to obtain the second power consumption value for each flash memory chip.

[0010] Calculate the power consumption change value of each flash memory chip based on the first power consumption value and the second power consumption value;

[0011] Outlier flash memory chips are identified by performing outlier statistics based on the power consumption variation values ​​of the multiple flash memory chips.

[0012] Remove the outlier flash memory chip.

[0013] Optionally, the method further includes:

[0014] DC characteristics and parameter tuning tests were performed on the multiple flash memory chips;

[0015] After the test is passed, a dynamic power consumption test is performed on the multiple flash memory chips when the first erase operation is performed before the regular functional test.

[0016] Optionally, the routine functional tests include any one or more of the following tests: read tests, write tests, erase tests, logic tests, performance tests, programming tests, and interference tests.

[0017] Optionally, dynamic power consumption testing is performed on the plurality of flash memory chips during the erase operation to obtain the power consumption value of each flash memory chip, including:

[0018] Connect the power supply terminal of the flash memory chip to the operating power supply, apply an erase voltage to all word lines for a certain period of time, and measure the current flowing through the power supply terminal.

[0019] The power consumption of the flash memory chip is calculated based on the voltage of the power supply and the measured current.

[0020] Optionally, the erase voltage is the same during the dynamic power consumption test for both erase operations.

[0021] Optionally, the step of performing outlier statistics based on the power consumption variation values ​​of the plurality of flash memory chips to determine outlier flash memory chips includes:

[0022] Calculate the mean and standard deviation of the power consumption variation values ​​of the plurality of flash memory chips;

[0023] Outlier flash memory chips are identified based on the mean and standard deviation.

[0024] Optionally, the method further includes:

[0025] Outlier flash memory chips are identified and removed based on the first power consumption value of the plurality of flash memory chips.

[0026] Perform routine functional tests on the remaining flash memory chips.

[0027] Optionally, the method further includes: performing outlier statistics based on the second power consumption value of the plurality of flash memory chips to determine outlier flash memory chips.

[0028] Optionally, the flash memory chip includes a memory cell array, which includes a plurality of memory cells arranged in a matrix. The memory cells are grid-type flash memory cells. Each memory cell includes a floating gate and a bit line. The memory cells in each column share the bit line.

[0029] Optionally, the gate-type flash memory cell includes two memory structures that share a source region and are symmetrically distributed; the memory structure includes a drain region and the source region located in the substrate, the drain region is connected to the bit line, the floating gate and word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate near the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0030] The flash memory chip testing method provided in this application embodiment, during the CP testing process, dynamically tests the power consumption of multiple flash memory chips during erase operations before and after the conventional functional testing. Based on the power consumption values ​​obtained from the two tests, the power consumption change value of each flash memory chip is calculated. Outlier statistics are performed based on the power consumption change value, and flash memory chips with outlier power consumption changes are screened out and removed during the yield testing stage. This effectively improves the reliability of flash memory chips and greatly reduces the risk of flash memory chips with potential problems, especially those with charge pump leakage, entering the end market and causing terminal failure.

[0031] Furthermore, outlier statistics can be performed by combining the power consumption values ​​of each flash memory chip obtained from one or two tests to identify outlier flash memory chips, thereby effectively eliminating potentially problematic outlier flash memory chips and ensuring the quality of flash memory chips entering the market. Attached Figure Description

[0032] Figure 1 This is a flowchart of a flash memory testing method provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of a flash memory structure in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the flash memory in the embodiments of this application;

[0035] Figure 4 This is another flowchart of the flash memory testing method provided in the embodiments of this application;

[0036] Figure 5 This is another flowchart of the flash memory testing method provided in the embodiments of this application. Detailed Implementation

[0037] To make the above-mentioned objectives, features and beneficial effects of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0038] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0039] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0040] Statistical analysis of terminal failure samples using flash memory chips reveals two common characteristics for terminal failures caused by process defects:

[0041] (1) The charge pump of the flash memory chip is malfunctioning;

[0042] (2) Some data exhibited during flash memory erasure and programming were significantly different from those of normal flash memory chips, and this phenomenon was more pronounced during flash memory erasure.

[0043] To address the aforementioned issues and based on statistical analysis of terminal failure samples, this application provides a flash memory testing method. During the CP (Chip Probing) testing phase, dynamic power consumption tests are performed on multiple flash memory chips before and after routine functional testing, during which erase operations are conducted. The power consumption change value of each flash memory chip is calculated based on the power consumption change values. Outlier statistical analysis is then performed based on these power consumption change values ​​to identify outlier samples. Although the anomalies of outlier samples are not always caused by charge pump failure, this method can, to a certain extent, screen out flash memory chips with potential risks due to various process defects, preventing them from being shipped as normal samples.

[0044] CP testing is performed on uncut wafers and requires probes to contact test pads on the wafer. It can test one or more dies at a time. CP testing generally includes three stages: CP1 tests basic memory read / write functions and writes certain data into the memory chip; then, after the wafer is baked at high temperature, CP2 tests are performed to check if the previously written data can be retained; finally, the logic function of the MCU (Microcontroller Unit) is tested.

[0045] The CP1 testing process mainly includes:

[0046] (1) DC parameters and trim test:

[0047] DC parameter testing mainly includes tests for short circuit, open circuit, maximum current, leakage current, output drive current, and turn-on level. For example, the open / short circuit test is mainly used to find out if there is a short circuit between the pins of the chip, and whether there is a lack of bonding wires during chip packaging; the leakage current test detects the leakage current of the chip's input pins when a voltage is applied.

[0048] Trimming is a process in chip testing that adjusts certain parameters within a circuit. These parameters can be reference voltage, bias current, bandgap voltage, and / or oscillation frequency, among others. Trimming tests measure the values ​​of these parameters, and if they deviate from target values, they can be corrected and adjusted to meet specifications. Adjusting parameters through trimming can significantly improve chip yield. Parameter adjustment in chip testing can be achieved by increasing or decreasing the resistance of the corresponding resistor network.

[0049] (2) Flash standard function test:

[0050] This mainly includes, but is not limited to: read tests, write tests, erase tests, logic tests, performance tests, programming tests, and interference tests. For example, erase / read tests are mainly used to filter out chips that cannot complete basic erase, programming, and read / write operations. During the test, the chip is erased and programmed at different operating voltages on a single sector or the entire flash memory array, and then read operations are performed on the chip to determine whether it passes the test.

[0051] (3) Write the flag to NVR1 and erase the chip.

[0052] During this process, all sectors will be erased.

[0053] CP2 testing primarily involves functional testing of the baked-out chip to check its data retention capability. The CP2 testing process typically includes the following steps:

[0054] (1) Open / short test and leakage test

[0055] Similar to the corresponding steps in the CP1 test, the open / short circuit test is mainly used to find out whether there is a short circuit between the pins of the chip, and whether there is a lack of bonding wires during chip packaging; the leakage current test is to detect the leakage current of the chip's input pins when voltage is applied.

[0056] (2) NVR1 verification

[0057] Used to verify that the flags written to NVR1 during the CP1 test are correct.

[0058] (3) Data retention capability and durability test

[0059] Data retention capability refers to the ability of a storage unit to maintain its programmed state for an acceptable period of time.

[0060] Durability testing is used to characterize the maximum number of program / erase (P / E) cycles a memory cell can withstand without failure.

[0061] The flash memory testing method provided in this application adds two dynamic power consumption tests during the CP1 testing phase, one before the regular functional test and one after the regular functional test. Based on the power consumption changes in the two tests, outlier flash memory chips are screened and eliminated. It should be noted that the specific items and methods of the regular functional tests may vary depending on the type and manufacturer of the flash memory chip, and this application embodiment does not limit them.

[0062] like Figure 1 The diagram shown is a flowchart of a flash memory testing method provided in an embodiment of this application, including the following steps:

[0063] Step 101: Provide multiple flash memory chips.

[0064] The flash memory chip includes a memory cell array, which comprises a plurality of memory cells arranged in a matrix. The memory cells can be grid-type flash memory cells or memory cells with other structures involving charge pumps; this embodiment of the application does not limit the specific type of memory cell. Each memory cell includes a floating gate and a bit line.

[0065] The flash memory chip can be NAND type (memory cells connected in series) or NOR type (memory cells connected in parallel, i.e., each column of memory cells is connected to the same bit line), and this application embodiment does not limit this.

[0066] The following section uses a grid-type flash memory cell as an example to briefly explain its structure and principle. (See also...) Figure 2 and Figure 3 ,in, Figure 2 This is a schematic diagram of a flash memory structure in one embodiment of this application. Figure 3 This is a schematic diagram of the flash memory in the embodiments of this application.

[0067] Flash memory includes a memory cell array, which comprises multiple memory cells A arranged in a matrix. Each memory cell is a grid-type flash memory cell; each memory cell includes a floating gate 11 and a bit line 13; each column of memory cells shares a bit line 13. Multiple grid-type flash memory cells are formed side-by-side on a semiconductor substrate. The semiconductor substrate material can be silicon, germanium, silicon-germanium, or silicon carbide, or it can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials such as gallium arsenide or other group III and V compounds.

[0068] In this embodiment, a gate-type flash memory cell includes two memory structures that share a source region 14 and are symmetrically distributed. Each gate-type flash memory cell includes a drain region 15, a source region 14, and a source line (not shown) formed on the semiconductor substrate connecting the source region 14, the source line being located above the source region 14. The drain region 15 is connected to a bit line 13, and a word line 21 is formed between the source region 14 and the drain region 15. Two word lines 21 of the same gate-type flash memory cell are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and sidewalls are formed on the semiconductor substrate between the source line and the word line 21. A tunneling oxide layer is formed between the floating gate 11 and the word line 21. The floating gate 11, word line 21, and source line can all be made of polysilicon. A floating gate tip is formed on the side of the floating gate 11 closest to the word line 21. The memory structures on the left and right are symmetrically distributed and share a source line. In this embodiment, the source region 14 and the drain region 15 are, for example, N-type doped.

[0069] During programming of this gate-type flash memory cell, word line 21 acts as a control gate. A high voltage is applied to the source region 14, a voltage that can open the channel is applied to word line 21, and a constant current is injected through the drain region 15. The source region 14 is at a high potential. Under the influence of the high potential, hot electrons are generated in the channel. On the other hand, the high potential is coupled to the floating gate 11, which generates a coupling voltage. Under the influence of the coupling voltage, electrons are injected from the channel into the floating gate 11, thereby realizing programming. Programming is also called the write "0" operation.

[0070] Step 102: Before the routine functional test, perform a dynamic power consumption test on the multiple flash memory chips during the first erase operation to obtain the first power consumption value of each flash memory chip.

[0071] It should be noted that the plurality of flash memory chips may be flash memory chips that have passed DC parameter and TRIM tests.

[0072] Specifically, the power supply terminals of each flash memory chip are connected to the operating power supply, an erase voltage is applied to all word lines for a certain period of time, and the current flowing through the power supply terminals is measured; based on the voltage of the operating power supply and the measured current, the power consumption value of each flash memory chip is calculated.

[0073] In a standard CP test, the normal erase voltage VEE applied to the word line is, for example, 12V.

[0074] Simultaneously refer to Figure 2 and Figure 3 When erasing the segmented gate flash memory cell, an erasure voltage VEE is applied to all word lines 21. The floating gate tip reduces the channel voltage of the tunneling effect through the tip discharge principle, enabling electrons to pass through the tunneling oxide layer from the tip of the floating gate 11 into the word line 21. After the memory cell is erased, the memory bit of the memory cell is in the "1" state, that is, all memory cells of the flash memory are erased and set to "1".

[0075] Since a complete erasure process lasts for a very short time, in order to obtain accurate current measurements, the erasure voltage can be held for a period of time (e.g., 5-10 ms) after it is applied to allow the current flowing through the power supply to stabilize.

[0076] Step 103: Perform dynamic power consumption test on the flash memory chip after passing the conventional function test during the second erase operation to obtain the second power consumption value of each flash memory chip.

[0077] It should be noted that the dynamic power consumption test during the first erase operation and the dynamic power consumption test during the second erase operation only represent dynamic power consumption tests during two different stages of the erase operation. The specific implementation methods of the two test processes are the same, and the erase voltage during the two erase operations can be the same.

[0078] In addition, the dynamic power consumption test during the second erase operation can be performed only on flash memory chips that have passed the regular functional test. In other words, flash memory chips that have not passed the regular functional test can be directly eliminated at this stage and will not be subject to the dynamic power consumption test during the second erase operation.

[0079] Step 104: Calculate the power consumption change value of each flash memory chip based on the first power consumption value and the second power consumption value.

[0080] It should be noted that since flash memory chips that failed the routine tests have been eliminated, the flash memory chips for which power consumption changes need to be calculated in step 104 are only those that passed the routine tests. The measured values, i.e., the first power consumption values, of the flash memory chips that failed the routine tests can be discarded directly.

[0081] Step 105: Perform outlier statistics based on the power consumption change values ​​of each flash memory chip to identify outlier flash memory chips.

[0082] In some embodiments, outlier statistics for power consumption variation values ​​can be performed using the n-sigma principle. The n-sigma principle is based on the assumption of normal distribution, calculates the deviation of data points from the mean, and classifies data points into outliers and normal values ​​according to the magnitude of the deviation.

[0083] The process for identifying outlier flash memory chips is as follows: First, calculate the mean and standard deviation of the power consumption variation values ​​of the multiple flash memory chips; then, determine the outlier flash memory chips based on the mean and standard deviation. Specifically, calculate the deviation of each power consumption variation value from the mean. For power consumption variation values ​​with a deviation value greater than n (n can be 3, 5, 9, etc.) times the standard deviation, they are identified as outliers, and the flash memory chip corresponding to the outlier is the outlier flash memory chip.

[0084] In some embodiments, other outlier statistical algorithms may also be used to determine outlier flash memory chips, such as: Dixon algorithm, Glubbs algorithm, box plot, Mahalanobis distance, Local Outlier Factor (LOF) algorithm, etc., which are not limited in this application embodiment.

[0085] Step 106: Remove the outlier flash memory chip.

[0086] The flash memory chip testing method provided in this application simulates the use of flash memory chips in terminal products by performing dynamic power consumption tests on multiple flash memory chips during erase operations before and after conventional functional testing. Based on the power consumption values ​​obtained from the two tests, the power consumption change value of each flash memory chip is calculated. Outlier statistics are performed based on the power consumption change value, and flash memory chips with outlier power consumption changes are screened out and removed during the yield testing stage. This effectively improves the reliability of flash memory chips and greatly reduces the risk of flash memory chips with potential problems, especially those with charge pump leakage, entering the terminal market and causing terminal failure.

[0087] like Figure 4 The diagram shown is another flowchart of a flash memory testing method provided in this application, including the following steps:

[0088] Step 401: Provide multiple flash memory chips.

[0089] The plurality of flash memory chips may be flash memory chips that have passed DC parameter and trim tests.

[0090] Step 402: Perform dynamic power consumption test on the plurality of flash memory chips during the first erase operation to obtain the first power consumption value of each flash memory chip.

[0091] Step 403: Perform outlier statistics based on the first power consumption value of the plurality of flash memory chips to identify and remove outlier flash memory chips.

[0092] In some embodiments, outlier statistics for power consumption values ​​can be performed using the 3sigma principle. The 3sigma principle is based on the assumption of normal distribution, calculates the deviation of data points from the mean, and classifies data points into outliers and normal values ​​according to the magnitude of the deviation.

[0093] The process for identifying outlier flash memory chips is as follows: First, calculate the mean and standard deviation of the power consumption values ​​of the multiple flash memory chips; then, identify outlier flash memory chips based on the mean and standard deviation. Specifically, calculate the deviation of each power consumption value from the mean. For power consumption values ​​with a deviation greater than 3 times the standard deviation, they are identified as outliers, and the flash memory chip corresponding to that power consumption value is an outlier flash memory chip.

[0094] In some embodiments, other outlier statistical algorithms may also be used to determine outlier flash memory chips, such as: Dixon algorithm, Glubbs algorithm, box plot, Mahalanobis distance, Local Outlier Factor (LOF) algorithm, etc., which are not limited in this application embodiment.

[0095] Step 404: Perform routine functional tests on the remaining flash memory chips.

[0096] Step 405: Perform dynamic power consumption test on the flash memory chip during the second erase operation after passing the conventional function test to obtain the second power consumption value of each flash memory chip.

[0097] Step 406: Calculate the power consumption change value of each flash memory chip based on the first power consumption value and the second power consumption value.

[0098] Similarly, since outlier flash memory chips determined by the first power consumption value and flash memory chips that failed the regular test have been eliminated, the flash memory chips whose power consumption change value needs to be calculated in step 406 are only the remaining flash memory chips after screening. The number of remaining flash memory chips after screening is less than or equal to the number of flash memory chips provided in step 401.

[0099] Step 407: Perform outlier statistics based on the power consumption change values ​​of the multiple flash memory chips to identify outlier flash memory chips.

[0100] For specific methods on determining outlier flash memory chips based on power consumption variations, please refer to the previous section on... Figure 1 The description of step 105 in the illustrated embodiment will not be repeated here.

[0101] Step 408: Remove the outlier flash memory chip.

[0102] In some embodiments, outlier flash memory chips can be determined based on the first power consumption value of each flash memory chip and the power consumption change value between the two consecutive tests, resulting in a set of outlier flash memory chips for each chip. Then, the union of the two sets of outlier flash memory chips is taken to obtain the final outlier flash memory chips. These final outlier flash memory chips are then removed to avoid misjudgment due to test errors.

[0103] like Figure 5 The diagram shown is another flowchart of a flash memory testing method provided in this application, including the following steps:

[0104] Step 501: Provide multiple flash memory chips.

[0105] The plurality of flash memory chips may be flash memory chips that have passed DC parameter and trim tests.

[0106] Step 502: Perform dynamic power consumption test on the plurality of flash memory chips during the first erase operation to obtain the first power consumption value of each flash memory chip.

[0107] Step 503: Perform routine functional tests on the plurality of flash memory chips.

[0108] Step 504: Perform dynamic power consumption test on the flash memory chip after passing the conventional function test during the second erase operation to obtain the second power consumption value of each flash memory chip.

[0109] Step 505: Perform outlier statistics based on the second power consumption values ​​of the plurality of flash memory chips to determine outlier flash memory chips.

[0110] In some embodiments, outlier statistics for power consumption values ​​can be performed using the 3sigma principle. The 3sigma principle is based on the assumption of normal distribution, calculates the deviation of data points from the mean, and classifies data points into outliers and normal values ​​according to the magnitude of the deviation.

[0111] The process for identifying outlier flash memory chips is as follows: First, calculate the mean and standard deviation of the power consumption values ​​of the multiple flash memory chips; then, identify outlier flash memory chips based on the mean and standard deviation. Specifically, calculate the deviation of each power consumption value from the mean. For power consumption values ​​with a deviation greater than 3 times the standard deviation, they are identified as outliers, and the flash memory chip corresponding to that power consumption value is an outlier flash memory chip.

[0112] In some embodiments, other outlier statistical algorithms may also be used to determine outlier flash memory chips, such as: Dixon algorithm, Glubbs algorithm, box plot, Mahalanobis distance, Local Outlier Factor (LOF) algorithm, etc., which are not limited in this application embodiment.

[0113] Step 506: Calculate the power consumption change value of each flash memory chip based on the first power consumption value and the second power consumption value.

[0114] Step 507: Perform outlier statistics based on the power consumption change values ​​of the multiple flash memory chips to identify outlier flash memory chips.

[0115] For specific methods on determining outlier flash memory chips based on power consumption variations, please refer to the previous section on... Figure 1 The description of step 105 in the illustrated embodiment will not be repeated here.

[0116] Step 508: Remove the outlier flash memory chip.

[0117] In some embodiments, outlier flash memory chips can be determined based on the second power consumption value of each flash memory chip and the power consumption change value between two consecutive tests, resulting in a set of outlier flash memory chips for each chip. Then, the union of the two sets of outlier flash memory chips is taken to obtain the final outlier flash memory chips. These final outlier flash memory chips are then removed to avoid misjudgment due to test errors.

[0118] In other embodiments, outlier flash memory chips can be determined and eliminated first based on a second power consumption value, and then determined and eliminated based on the power consumption change values ​​before and after the two instances.

[0119] In other embodiments, outlier flash memory chips can be determined and eliminated sequentially based on a first power consumption value, a second power consumption value, and a power consumption change value.

[0120] In other embodiments, the corresponding set of outlier flash memory chips can be determined based on the first power consumption value, the second power consumption value, and the power consumption change value, respectively. The set of outlier flash memory chips determined by these three methods is then combined to obtain the final set of outlier flash memory chips. These final determined outlier flash memory chips are then removed to avoid misjudgment due to testing errors.

[0121] Of course, the flash memory chip testing method of this application embodiment can also have other variations, which will not be described in detail here.

[0122] The flash memory chip testing method of this application embodiment can eliminate outlier flash memory chips with potential problems by testing the power consumption of flash memory chips during the yield testing stage, thereby improving the reliability of flash memory chips and effectively ensuring the quality of flash memory chips entering the market.

[0123] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0124] In the embodiments of this application, "multiple" refers to two or more.

[0125] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0126] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above method embodiments. The aforementioned storage medium can include various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0127] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

Claims

1. A method for testing flash memory chips, characterized in that, The method includes: Provides multiple flash memory chips; Dynamic power consumption tests were performed on the multiple flash memory chips during the first erase operation before routine functional testing to obtain the first power consumption value of each flash memory chip. Dynamic power consumption tests were performed on flash memory chips that had passed routine functional tests during the second erase operation to obtain the second power consumption value for each flash memory chip. Calculate the power consumption change value of each flash memory chip based on the first power consumption value and the second power consumption value; Outlier flash memory chips are identified by performing outlier statistics based on the power consumption variation values ​​of the multiple flash memory chips. Remove the outlier flash memory chip.

2. The flash memory chip testing method according to claim 1, characterized in that, The method further includes: DC characteristics and parameter tuning tests were performed on the multiple flash memory chips; After the test is passed, a dynamic power consumption test is performed on the multiple flash memory chips when the first erase operation is performed before the regular functional test.

3. The flash memory chip testing method according to claim 1, characterized in that, The routine functional tests include any one or more of the following tests: read test, write test, erase test, logic test, performance test, programming test, and interference test.

4. The flash memory chip testing method according to claim 1, characterized in that, Dynamic power consumption tests were performed on the multiple flash memory chips during erase operations to obtain the power consumption values ​​for each flash memory chip, including: Connect the power supply terminal of the flash memory chip to the operating power supply, apply an erase voltage to all word lines for a certain period of time, and measure the current flowing through the power supply terminal. The power consumption of the flash memory chip is calculated based on the voltage of the power supply and the measured current.

5. The flash memory chip testing method according to claim 1, characterized in that, The erase voltage was the same during the dynamic power consumption test for both erase operations.

6. The flash memory chip testing method according to claim 1, characterized in that, The step of performing outlier statistics based on the power consumption changes of the plurality of flash memory chips to determine outlier flash memory chips includes: Calculate the mean and standard deviation of the power consumption variation values ​​of the plurality of flash memory chips; Outlier flash memory chips are identified based on the mean and standard deviation.

7. The flash memory chip testing method according to claim 1, characterized in that, The method further includes: Outlier flash memory chips are identified and removed based on the first power consumption value of the plurality of flash memory chips. Perform routine functional tests on the remaining flash memory chips.

8. The flash memory chip testing method according to claim 1, characterized in that, The method further includes: Outlier flash memory chips are identified by performing outlier statistics based on the second power consumption values ​​of the plurality of flash memory chips.

9. The flash memory chip testing method according to any one of claims 1 to 8, characterized in that, The flash memory chip includes a memory cell array, which comprises a plurality of memory cells arranged in a matrix. The memory cells are grid-type flash memory cells. Each memory cell includes a floating gate and a bit line. The memory cells in each column share the bit line.

10. The flash memory chip testing method according to claim 9, characterized in that, The gate-type flash memory cell includes two memory structures that share a source region and are symmetrically distributed. The memory structure includes a drain region and a source region located in the substrate. The drain region is connected to the bit line. The floating gate and word line are formed on the substrate between the source region and the drain region. A floating gate tip is formed on the side of the floating gate near the word line. A tunneling oxide layer is formed between the floating gate and the word line.

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