Re-packaging method and re-packaging structure of packaged chip

Abstract

The invention discloses a repackaging method and repackaging structure of a packaged chip, and the repackaging method comprises the steps: providing the packaged chip, the packaged chip comprises a target chip which is located in a packaging body and is provided with a test PAD, and the surface of the packaging body is provided with a first region which at least corresponds to the test PAD of the target chip; etching the packaging body in the first area until the test PAD of the target chip is displayed; corroding the packaging body in the first area until the test PAD of the target chip is exposed; arranging a test patch on a second area on the surface of the packaging body, wherein the second area is different from the first area; forming a bonding wire between the test PAD of the target chip and the test patch; and filling a packaging material in the first region. According to the repackaging method and the repackaging structure of the packaged chip, the testing efficiency and the success rate of the packaged chip can be greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a repackaging method and a repackaging structure of a packaged chip. Background Art

[0002] With the development of integrated circuits, packaging forms are also changing with each passing day, extending from single die (chip / die) packaging to multi-die packaging, but with it comes the problem of multi-die compatibility. In the multi-die packaging process, from the engineering batch stage to the mass production stage and then to the later use stage, compatibility issues always exist.

[0003] In the existing multi-die packaging structure, the test PADs of some dies are not wired after packaging. After a problem occurs in the packaging structure, it is impossible to directly perform functional testing, and the only way is to remove the die and repackage it for functional testing. However, removing the die is a destructive experiment, which may cause irreversible damage to the die during the operation, thereby causing the abnormal phenomenon to disappear or change.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a repackaging method and a repackaging structure for a packaged chip, which can greatly improve the testing efficiency and success rate of the packaged chip.

[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows: A repackaging method for a packaged chip, suitable for functional testing, the repackaging method comprising: Providing a packaged chip, the packaged chip comprising a target chip located in a package body and having a test PAD, wherein a surface of the package body has at least a first area corresponding to the test PAD of the target chip; Etching the package body located in the first area until a test PAD of the target chip is displayed; Corroding the package located in the first area until the test PAD of the target chip is exposed; Disposing the test patch in a second area on the surface of the package body, the second area being different from the first area; forming a bonding wire between the test PAD of the target chip and the test patch; The first region is filled with a packaging material and then cured.

[0007] In one or more embodiments of the present invention, etching the package located in the first region until the test PAD of the target chip is exposed, includes: Using a laser etching process to perform partial etching on the package located in the first region in the thickness direction until the test PAD of the target chip located below can be observed by the naked eye, and the package above the test PAD of the target chip is not etched through during the etching process.

[0008] In one or more embodiments of the present invention, the laser power in the laser etching process is 4W - 6W.

[0009] In one or more embodiments of the present invention, etching the package located in the first region until the test PAD of the target chip is exposed, includes: Using a de-encapsulation solvent to etch the remaining package above the test PAD of the target chip corresponding to the first region until the package above the test PAD of the target chip is completely etched away, and the test PAD of the target chip is exposed.

[0010] In one or more embodiments of the present invention, a dropper is used to suck the de-encapsulation solvent and drop it onto the package above the test PAD of the target chip corresponding to the first region.

[0011] In one or more embodiments of the present invention, setting a test patch on the second region of the package surface, includes: Using an insulating adhesive to paste the test patch on the second region of the package surface; Curing the insulating adhesive to fix the test patch.

[0012] In one or more embodiments of the present invention, the curing temperature is 140°C - 150°C, and the curing time is 20min - 30min.

[0013] In one or more embodiments of the present invention, during the etching process, the temperature of the packaged chip is maintained at 120°C - 180°C; and / or, The distance between the second region and the first region is 1mm - 2mm.

[0014] In one or more embodiments of the present invention, during the process of forming a bonding wire between the test PAD of the target chip and the test patch, the bonding wire diameter is controlled to be 0.6mil - 0.8mil, the bonding ultrasonic current is 120mAmps - 130mAmps, and the arc height is 7mil - 8mil.

[0015] In one or more embodiments of the present invention, after the step of forming a bonding wire between the test PAD of the target chip and the test patch, it further includes: Steps of observing with an optical microscope to confirm that the bonding wires are successfully bonded to the test PADs and test patches of the target chip and the sample is intact.

[0016] In one or more embodiments of the present invention, filling the encapsulation material in the first region includes: Dropping the encapsulation material into the first region by dispensing or filling; The encapsulation material covers the bonding wires; and / or, the encapsulation material is 0.5 mm - 2 mm higher than the highest point of the bonding wires; Curing the encapsulation material.

[0017] In one or more embodiments of the present invention, the curing time is 25 min - 30 min.

[0018] A repackaging structure of an encapsulated chip, which is encapsulated by the above-mentioned repackaging method of an encapsulated chip.

[0019] Compared with the prior art, the repackaging method of an encapsulated chip of the present invention repackages the encapsulated chip by opening a part of the region of the encapsulated chip to expose the test PADs of the target chip and wire-bonding them to the test patches arranged on the surface of the encapsulated chip, so that the repackaged encapsulated chip is suitable for functional testing, with safe, efficient and cost-saving testing, and can greatly improve the testing efficiency and success rate.

[0020] The repackaging method of an encapsulated chip of the present invention leads out the test PADs of the target chip by wire-bonding for functional testing. First, the test PADs of the target chip are exposed by laser etching and chemical reagent corrosion; then, the test patches are fixed on the surface of the encapsulated chip; then, wire-bonding is carried out between the test PADs and the test patches; finally, the exposed area is backfilled to repackage the encapsulated chip. The repackaging structure can be used for subsequent testing.

[0021] The repackaging method of an encapsulated chip of the present invention has a wide range of applications, can be applied to all encapsulated chips in the form of stacked dies or single dies, and has simple steps, is easy to operate, has a high success rate and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1This is a process flow diagram of the repackaging method for a packaged chip in an embodiment of the present invention. Detailed implementation manners

[0024] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0025] As Figure 1 shown, the repackaging method for a packaged chip in an embodiment of the present invention includes the following steps: S1. Provide a packaged chip, where the packaged chip includes a target chip located in a package body and having test PADs, and at least a first area corresponding to the test PADs of the target chip is provided on the surface of the package body.

[0026] S2. Etch the package body located in the first area until the test PADs of the target chip are shown.

[0027] S3. Corrode the package body located in the first area until the test PADs of the target chip are exposed.

[0028] S4. Set test patches on a second area on the surface of the package body, and the second area is different from the first area.

[0029] S5. Form bonding wires between the test PADs of the target chip and the test patches.

[0030] S6. Fill the package material in the first area and cure it.

[0031] It can be understood that if the packaged chip is a packaged structure in the form of stacked dies (chips / grains), the target chip having test PADs is usually located at the top layer of multiple stacked chips. If the packaged chip is a packaged structure in the form of a single die package, the chip therein is the target chip having test PADs.

[0032] In step S1, the position of the test PADs of the target chip in the packaged chip can be located by X-ray, and the first area corresponding to the test PADs of the target chip on the surface of the package body above the test PADs of the target chip can be defined according to the located position. The equipment for positioning the position can include X-ray non-destructive testing equipment.

[0033] It is understandable that X-Ray Positioning refers to a technology that uses the penetrability and imaging characteristics of X-rays to accurately determine the position of an object or an internal target of the human body. Currently, it is widely used in medical, industrial inspection, security inspection and other fields. The core of X-ray positioning is to achieve accurate mapping of spatial coordinates through imaging and geometric calculations, and its accuracy depends on the equipment (such as CT vs. ordinary X-ray machines) and algorithm support. X-ray positioning is already a mature technology, and this application will not elaborate on it in detail.

[0034] In step S1, the range of the first area should be smaller than the range of the surface of the encapsulation chip to which it belongs, and there should be a spacing of 4 mm - 5 mm between the edge of the first area and any edge of the surface of the encapsulation chip to which it belongs, which is convenient for subsequently setting test patches on the surface of the encapsulation chip. In the thickness direction of the encapsulation chip, the range where the first area is located covers the test PAD of the target chip.

[0035] In step S2, a laser etching process can be used to perform partial etching on the encapsulation body located in the first area in the thickness direction. The laser etching process does not need to etch through the encapsulation body above the test PAD of the target chip, and the initial etching is stopped until the test PAD of the target chip located below can be observed by the naked eye. That is, after the laser etching is completed, a thin layer of encapsulation body still remains above the test PAD of the target chip. This design can protect the test PAD of the target chip and prevent the laser from damaging the test PAD of the target chip during the laser etching process. Preferably, the laser power in the laser etching process is 20% - 30% of the maximum power of the laser device; for example, if the maximum power of the laser device is about 20 W, then the laser power in the laser etching process is 4 W - 6 W.

[0036] The encapsulation body on the encapsulation chip can be epoxy resin, silica gel, etc.

[0037] In step S3, a dropper is used to suck up the de-encapsulation solvent and drop it onto the remaining encapsulation body above the test PAD of the target chip corresponding to the first area that has been laser-etched, to corrode the remaining encapsulation body above the test PAD of the target chip corresponding to the first area until the encapsulation body above the test PAD of the target chip is completely corroded away, exposing the test PAD of the target chip. During the corrosion process, by heating, the temperature of the encapsulation chip is always maintained at 120°C - 180°C. For example, it can be 120°C, 130°C, 140°C, 150°C, 160°C, 170°C or 180°C, etc., and preferably 150°C.

[0038] It is understandable that the de-encapsulation solvent is a chemical reagent used to dissolve or soften the encapsulation body of electronic components (such as epoxy resin, silicone rubber, etc.) to expose the internal structure of the encapsulated chip. If the material of the encapsulation body is epoxy resin, typical de-encapsulation solvents include: fuming nitric acid (HNO 3 ), and concentrated sulfuric acid (H 2 SO 4 ). Fuming nitric acid will rapidly corrode epoxy resin at high temperature (~180°C). Concentrated sulfuric acid can corrode epoxy resin above 200°C. If the material of the encapsulation body is silicone rubber or soft encapsulation glue, typical de-encapsulation solvents include: dimethyl sulfoxide (DMSO) and N-methylpyrrolidone (NMP). Dimethyl sulfoxide (DMSO) can gently dissolve silicone rubber under heating (~150°C). N-methylpyrrolidone (NMP) selectively dissolves epoxy resin.

[0039] The de-encapsulation solvent in this embodiment is a reagent proportioned according to the material of the bonding wire. This de-encapsulation solvent has no corrosive effect on the target chip, the test PADs thereon, and the bonding wire, and will not cause damage to the target chip, the test PADs thereon, and the bonding wire.

[0040] In step S4, an insulating adhesive can be used to paste the test patch on the second area on the surface of the encapsulation body. The second area should be different from the first area, and preferably, the distance between the edge of the second area and the edge of the first area is 1 mm - 2 mm. After pasting, heat the insulating adhesive through a heating table and cure it to fix the test patch. Among them, the heating temperature is 140°C - 150°C. For example, it can be 140°C, 142°C, 144°C, 145°C, 147°C, or 150°C, etc. The heating time is 20 min - 30 min. For example, it can be 20 min, 22 min, 24 min, 25 min, 27 min, or 30 min, etc.

[0041] The test patch is preferably a conductive metal sheet, such as copper foil, aluminum foil, gold foil, silver foil, nickel foil, or stainless steel foil, etc., and preferably gold foil. The test patch is used to electrically lead out the test PADs of the target chip, so as to facilitate the testing of the functions of the target chip on the testing machine for the re-encapsulation structure. That is, the part of the test patch that is wire-bonded to the test PADs of the target chip will be re-encapsulated into the re-encapsulation structure in subsequent steps, while the rest of the test patch will be exposed outside the re-encapsulation structure. When the re-encapsulation structure is placed on the testing machine for testing the functions of the encapsulated chip, only the probing needle needs to contact the exposed test patch or wire-bond the exposed test patch to the test PCB board of the testing machine to complete the function testing of the target chip on the testing machine.

[0042] The insulating adhesive in this embodiment is a colloid that needs to be thermally cured. In other embodiments, the insulating adhesive can also use a colloid that does not need to be thermally cured.

[0043] It can be understood that in other embodiments, the test patch can also be set in the second area on the surface of the package body in other ways. For example, it can be welded, or fixed with insulating curing glue, or directly placed on the surface of the package body, and then fixed by partially covering with encapsulation material in the later stage. Among them, the present invention does not have special limitations on the model and specific composition of the insulating curing glue, and any curing glue well-known to those skilled in the art that can be used to fix the test patch and has insulating properties can be adopted. The components of the insulating curing glue can include base material, filler, curing agent and additives. The present invention does not have special limitations on the base material, filler, curing agent and additives in the insulating curing glue, and any base material, filler, curing agent and additives well-known to those skilled in the art that can be used in the insulating curing glue can be adopted.

[0044] In step S5, the bonding wire diameter is set to 0.6 mil - 0.8 mil, the bonding ultrasonic current is 120 mAmps - 130 mAmps, and the arc height is 7 mil - 8 mil, and wire bonding is performed between the test PAD of the target chip and the test patch. It can be understood that the parameters required in the bonding process and the specific wire bonding method can be adjusted according to actual needs. After the bonding is completed, it is also necessary to observe with an optical microscope to check whether there is any cracking or poor soldering around the test PAD, and confirm that the bonding wire is successfully bonded to the test PAD of the target chip and the test patch and the sample is intact.

[0045] In step S6, the packaged chip after wire bonding is placed on a heating stage, and the heating temperature is set to 100°C - 150°C. For example, it can be 100°C, 110°C, 120°C, 130°C, 140°C or 150°C, etc. Preferably, it is 125°C, and the heating time is 1 min - 2 min. For example, it can be 1 min, 1.2 min, 1.4 min, 1.5 min, 1.7 min or 2 min, etc. Then, encapsulation material is dropped into the opened first area by means of dispensing or filling, etc., and the encapsulation material is cured to complete the re-packaging of the packaged chip. Among them, the encapsulation material can be epoxy resin, silicone (silica gel), polyurethane (PU) or acrylic resin, etc. The curing time is 25 min - 30 min. For example, it can be 25 min, 26 min, 27 min, 28 min, 29 min or 30 min, etc. The encapsulation material should cover the bonding wire, and / or the encapsulation material is 0.5 mm - 2 mm higher than the highest point of the bonding wire.

[0046] An embodiment of the present invention also provides a re-packaged structure packaged by the above re-packaging method of the packaged chip.

[0047] The following further illustrates the present invention with specific embodiments.

[0048] Example 1: 1. Open the lid of the package part of the encapsulated chip.

[0049] Take the encapsulated chip that needs to have its lid opened and place it on the laser machine. Use X-ray to locate the test PAD position of the target chip inside the encapsulated chip and perform laser etching on the package body until the test PAD of the target chip is visible. The laser power is 20% - 30% of the laser machine.

[0050] Drop the prepared de-encapsulation solvent (reagent ratio according to the material of the bonding wire) onto the laser opening position with a dropper and heat the encapsulated chip to 150°C. Continue to corrode the remaining package body inside the laser opening until the test PAD of the target chip is completely exposed, ensuring that the surface of the target chip is clean and undamaged.

[0051] 2. Curing.

[0052] Paste the metal sheet on the package body with insulating glue. The bonding position of the metal sheet is about 1 mm - 2 mm away from the laser opening position. Place the whole on the heating table, set the heating temperature to about 140°C - 150°C, and heat for 20 min - 30 min to cure the insulating glue and fix the metal sheet.

[0053] 3. Wire bonding.

[0054] Place the encapsulated chip with the metal sheet on the packaging machine table, set the parameters of the packaging machine table: wire diameter: 0.6 mil - 0.8 mil; bonding ultrasonic current (USG Current): 120 mAmps - 130 mAmps; arc height: 7 mil - 8 mil. After setting the parameters, perform wire bonding according to the requirements.

[0055] 4. Observation.

[0056] Use an optical microscope to observe whether the wire bonding is intact for the sample after wire bonding, and whether there is cracking or poor soldering around the test PAD. After observing that the sample is intact, proceed to the next step of dispensing glue.

[0057] 5. Dispensing glue and curing.

[0058] Place the sample on the heating machine table, set the heating temperature to 125°C. After waiting for 1 min - 2 min, drop the encapsulation material into the laser opening position until the encapsulation material covers the wire bonding position and is about 1 mm higher. Finally, place it on the heating table for 25 min - 30 min to cure and complete the re-encapsulation of the encapsulated chip.

[0059] Compared with the prior art, the method for re-packaging a packaged chip of the present invention re-packages the packaged chip by opening a partial area of the packaged chip to expose the test PAD of the target chip and wire-bonding it to a test patch provided on the surface of the packaged chip, so that the re-packaged chip is suitable for functional testing, with safe, efficient and cost-saving testing, and can greatly improve the testing efficiency and success rate.

[0060] The method for re-packaging a packaged chip of the present invention leads out the test PAD of the target chip by wire-bonding for functional testing. First, the test PAD of the target chip is exposed by means of laser etching and chemical reagent corrosion; then, the test patch is fixed on the surface of the packaged chip; then, wire-bonding is carried out between the test PAD and the test patch; finally, the exposed area is backfilled to re-package the packaged chip. The re-packaged structure can be used for subsequent testing.

[0061] The method for re-packaging a packaged chip of the present invention has a wide range of applications and can be applied to all packaged chips in the form of stacked dies or single dies. Moreover, the steps are simple, easy to operate, with a high success rate and low cost.

[0062] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0063] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for repackaging a packaged chip, suitable for functional testing, characterized in that: The repackaging method comprises: Providing a packaged chip, the packaged chip comprising a target chip located in a package body and having a test PAD, wherein a surface of the package body has at least a first area corresponding to the test PAD of the target chip; Etching the package body located in the first area until a test PAD of the target chip is displayed; Corroding the package located in the first area until the test PAD of the target chip is exposed; Disposing the test patch in a second area on the surface of the package body, the second area being different from the first area; forming a bonding wire between the test PAD of the target chip and the test patch; The first region is filled with a packaging material and cured.

2. The method for repackaging a packaged chip according to claim 1, characterized in that: Etching the package body located in the first area to a test PAD showing the target chip, comprising: The package body located in the first area is partially etched in the thickness direction by a laser etching process until the test PAD of the target chip located below can be observed by naked eyes, and the package body located above the test PAD of the target chip is not etched through during the etching process.

3. The method for repackaging a packaged chip according to claim 2, characterized in that: The laser power in the laser etching process is 4W-6W.

4. The method for repackaging a packaged chip according to claim 1, characterized in that: The step of corroding the package body located in the first region until the test PAD of the target chip is exposed comprises: The remaining packaging body above the test PAD of the target chip corresponding to the first region is corroded by using a de-packaging solvent until the packaging body above the test PAD of the target chip is completely corroded to expose the test PAD of the target chip.

5. The method for repackaging a packaged chip according to claim 4, characterized in that: The depackaging solvent is sucked by a dropper and dropped onto the packaging body located above the test PAD of the target chip corresponding to the first area.

6. The method for repackaging a packaged chip according to claim 1, characterized in that: The test patch is arranged in a second area on the surface of the package body, comprising: Adhere the test patch to the second area on the surface of the package body using insulating glue; The insulating adhesive is cured to fix the test patch.

7. The method for repackaging a packaged chip according to claim 6, characterized in that: The curing temperature is 140℃-150℃, and the curing time is 20min-30min.

8. The method for repackaging a packaged chip according to claim 1, characterized in that: During the etching process, the temperature of the packaged chip is maintained at 120°C-180°C; and / or, The distance between the second area and the first area is 1 mm-2 mm.

9. The method for repackaging a packaged chip according to claim 1, characterized in that: In the process of forming a bonding wire between the test PAD of the target chip and the test patch, the bonding wire diameter is controlled to be 0.6mil-0.8mil, the bonding ultrasonic current is controlled to be 120mAmps-130mAmps, and the arc height is controlled to be 7mil-8mil.

10. The method for repackaging a packaged chip according to claim 1, characterized in that: After the step of forming a bonding wire between the test PAD of the target chip and the test patch, the step further includes: The step of using an optical microscope to observe and confirm that the bonding wires are successfully bonded to the test PAD and test patch of the target chip and that the sample is intact.

11. The method for repackaging a packaged chip according to claim 1, characterized in that: Filling the first region with packaging material comprises: dripping packaging material into the first area by dispensing or filling; The packaging material covers the bonding wire, and / or the packaging material is 0.5 mm to 2 mm higher than the highest point of the bonding wire; The encapsulation material is cured.

12. A repackaging structure for a packaged chip, characterized in that: The chip is packaged by the repackaging method of the packaged chip as described in any one of claims 1 to 11.

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