Voltage conversion circuit, circuit system and voltage conversion method

Abstract

The invention provides a voltage conversion circuit, a circuit system and a voltage conversion method, and the voltage conversion circuit comprises an enabling module which provides a group of enabling signals which are opposite in phase based on a first mode and a second mode; and the conversion module is connected with the enabling module, receives the first voltage, directly outputs the first voltage in the first mode, and reduces and outputs the first voltage in the second mode. According to the voltage conversion circuit, the circuit system and the voltage conversion method provided by the invention, the problem of high power consumption of an existing storage chip in a standby mode is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a voltage conversion circuit, a circuit system and a voltage conversion method. Background Art

[0002] With the continuous increase in the capacity of storage chips, in the storage chips, the N-well capacitance in the direction of the row decoding circuit is getting larger and larger, resulting in a longer charging time for the capacitance, thereby affecting the reading speed of the storage chips.

[0003] In order to ensure the chip reading speed, currently, the common practice in the industry is: after the storage chip is powered on, a high voltage generated by a charge pump is connected in the direction of the row decoding circuit; although this approach can solve the problem of the chip reading speed, it also brings the problem of high standby power consumption due to leakage current.

[0004] The specific analysis is as follows: The high voltage provided by the charge pump is connected to the row decoding circuit direction after the chip is powered on. Even when the chip is in the standby mode, the high voltage is still connected to the row decoding circuit direction; although the row decoding circuit does not work in the standby mode, there is a certain leakage current in the PMOS transistors in the circuit because their substrates are connected to the high voltage, resulting in an increase in the load current of the charge pump, and ultimately an increase in the power consumption of the charge pump, making the standby power consumption at the product level not meet the index requirements, as specifically Figure 1 shown.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a voltage conversion circuit, a circuit system and a voltage conversion method, which are used to solve the problem of high product power consumption in the standby mode of existing storage chips.

[0007] To achieve the above object and other related objects, the present invention provides a voltage conversion circuit, including:

[0008] An enable module that provides a set of mutually inverted enable signals based on a first mode and a second mode;

[0009] A conversion module, connected to the enable module, receiving a first voltage, and directly outputting the first voltage in the first mode and stepping down the first voltage for output in the second mode.

[0010] Optionally, in the enabling module, a set of mutually inverted enabling signals includes a first enabling signal and a second enabling signal; in the first mode, the first enabling signal is at a high level and the second enabling signal is at a low level; in the second mode, the first enabling signal is at a low level and the second enabling signal is at a high level.

[0011] Optionally, the conversion module includes:

[0012] A conversion control unit, connected to the enabling module, controlled by a set of mutually inverted enabling signals, generating a first channel opening signal in the first mode and a second channel opening signal in the second mode;

[0013] A voltage output unit, connected to the conversion control unit, including a first output channel and a second output channel, wherein the first output channel is opened under the control of the first channel opening signal and directly outputs the first voltage, and the second output channel is opened under the control of the second channel opening signal and outputs the first voltage after voltage reduction.

[0014] Optionally, the conversion control unit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and an inverter logic device, wherein: the gates of the first NMOS transistor and the first PMOS transistor are connected to the first enabling signal, the gates of the second NMOS transistor and the second PMOS transistor are connected to the second enabling signal, the sources of the first NMOS transistor and the second NMOS transistor are connected to the reference ground, the drains of the first NMOS transistor and the second NMOS transistor are correspondingly connected to the drains of the first PMOS transistor and the second PMOS transistor, the sources of the first PMOS transistor and the second PMOS transistor are correspondingly connected to the drains of the third PMOS transistor and the fourth PMOS transistor, the gate of the third PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the first NMOS transistor and serves as the first output terminal of the conversion control unit, the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the first voltage, the input terminal of the inverter logic device is connected to the drain of the second NMOS transistor, and the output terminal of the inverter logic device serves as the second output terminal of the conversion control unit.

[0015] Optionally, the inverter logic device includes a third NMOS transistor and a fifth PMOS transistor, where: the gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor and serves as the input terminal of the inverter logic device, the source of the third NMOS transistor is connected to the reference ground, the drain of the third NMOS transistor is connected to the drain of the fifth PMOS transistor and serves as the output terminal of the inverter logic device, and the source of the fifth PMOS transistor is connected to the first voltage.

[0016] Optionally, the first output channel includes a sixth PMOS transistor, where: the gate of the sixth PMOS transistor is connected to the first output terminal of the conversion control unit, the source of the sixth PMOS transistor is connected to the first voltage, and the drain of the sixth PMOS transistor serves as the output terminal of the first output channel.

[0017] Optionally, the second output channel includes a fourth NMOS transistor, where: the gate of the fourth NMOS transistor is connected to the second output terminal of the conversion control unit, the source of the fourth NMOS transistor serves as the output terminal of the second output channel, and the drain of the fourth NMOS transistor is connected to the first voltage.

[0018] The present invention also provides a circuit system, including: the voltage conversion circuit described in any one of the above.

[0019] Optionally, the voltage obtained by stepping down the first voltage is denoted as the second voltage, and the circuit system further includes:

[0020] A charge pump circuit for providing the first voltage;

[0021] A memory circuit connected to the voltage conversion circuit, which charges the N-well capacitor based on the first voltage in the first mode; and charges the N-well capacitor based on the second voltage in the second mode.

[0022] The present invention also provides a voltage conversion method, including:

[0023] In the first mode, receive the first voltage and directly output the first voltage;

[0024] In the second mode, receive the first voltage and step down the first voltage for output;

[0025] Wherein, the voltage obtained by stepping down the first voltage is denoted as the second voltage, and the difference between the first voltage and the second voltage is the threshold voltage of the NMOS transistor.

[0026] As described above, the voltage conversion circuit, circuit system and voltage conversion method of the present invention propose a brand-new voltage conversion scheme through the design of the enabling module and the conversion module. The first voltage is directly output in the first mode, and the first voltage is stepped down and output in the second mode, realizing different voltages output in different modes. When this voltage conversion scheme is applied to a semiconductor memory, the standby power consumption can be reduced by stepping down and outputting the first voltage in the standby mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It shows a schematic diagram of the power consumption of an existing charge pump.

[0028] Figure 2 It shows a schematic diagram of the voltage conversion circuit in an embodiment of the present invention.

[0029] Figure 3 It shows a schematic diagram of the circuit system in an embodiment of the present invention.

[0030] Figure 4 It shows a schematic diagram of the power consumption of the charge pump in an embodiment of the present invention.

[0031] DESCRIPTION OF REFERENCE NUMERALS

[0032] 10 Circuit system

[0033] 100 Voltage conversion circuit

[0034] 110 Enabling module

[0035] 120 Conversion module

[0036] 121 Conversion control unit

[0037] 121a Inverting logic device

[0038] 122 Voltage output unit

[0039] 121a First output channel

[0040] 121b Second output channel

[0041] 200 Charge pump circuit

[0042] 300 Memory circuit DETAILED DESCRIPTION OF THE INVENTION

[0043] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Please refer to Figures 2 to 4 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout form of its components may also be more complex.

[0045] As Figure 2 shown, this embodiment provides a voltage conversion circuit 100, which includes an enable module 110 and a conversion module 120.

[0046] Wherein:

[0047] The enable module 110 provides a set of mutually inverted enable signals based on the first mode and the second mode, including the first enable signal EN and the second enable signal ENB. In one example, in the first mode, the first enable signal EN is at a high level, and the second enable signal ENB is at a low level; in the second mode, the first enable signal EN is at a low level, and the second enable signal ENB is at a high level. In one implementation manner, the enable module 110 is implemented by an inverter INV. Among them, the input terminal of the inverter INV is connected to the first enable signal EN, and the output terminal of the inverter INV generates the second enable signal ENB. In practical applications, the first mode is usually the working mode, and the second mode is usually the standby mode. Of course, it is also feasible that the first mode and the second mode are other mode states, which has no substantial impact on the implementation of the solution of this embodiment.

[0048] The conversion module 120 is connected to the enable module 110, receives the first voltage V1, and directly outputs the first voltage V1 in the first mode, and steps down the first voltage V1 in the second mode. In one example, the conversion module 120 includes a conversion control unit 121 and a voltage output unit 122.

[0049] The conversion control unit 121 is connected to the enable module 110 and is controlled by a set of mutually inverted enable signals, that is, the first enable signal EN and the second enable signal ENB. It generates a first channel opening signal in the first mode and a second channel opening signal in the second mode. In one implementation manner, the conversion control unit 121 includes a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, and an inverter logic device 121a; wherein:

[0050] The gate of the first NMOS transistor N1 is connected to the first enable signal EN, the source of the first NMOS transistor N1 is connected to the reference ground AGND, the drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and the substrate of the first NMOS transistor N1 is connected to its source; the gate of the second NMOS transistor N2 is connected to the second enable signal ENB, the source of the second NMOS transistor N2 is connected to the reference ground AGND, the drain of the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2, and the substrate of the second NMOS transistor N2 is connected to its source; the gate of the first PMOS transistor P1 is connected to the first enable signal EN, the source of the first PMOS transistor P1 is connected to the drain of the third PMOS transistor P3, and the substrate of the first PMOS transistor P1 is connected to the first voltage V1; the gate of the second PMOS transistor P2 is connected to the second enable signal ENB, the source of the second PMOS transistor P2 is connected to the drain of the fourth PMOS transistor P4, and the substrate of the second PMOS transistor P2 is connected to the first voltage V1; the gate of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2, the source of the third PMOS transistor P3 is connected to the first voltage V1, and the substrate of the third PMOS transistor P3 is connected to its source; the gate of the fourth PMOS transistor P4 is connected to the drain of the first NMOS transistor N1 and serves as the first output terminal of the conversion control unit 121 for outputting the first channel enable signal, the source of the fourth PMOS transistor P4 is connected to the first voltage V1, and the substrate of the fourth PMOS transistor P4 is connected to its source; the input terminal of the inverter logic device 121a is connected to the drain of the second NMOS transistor N2, and the output terminal of the inverter logic device 121a serves as the second output terminal of the conversion control unit 121 for outputting the second channel enable signal.

[0051] In this embodiment, the inverter logic device 121a can be any circuit structure with an inverter logic function. As an alternative, the inverter logic device 121a includes a third NMOS transistor N3 and a fifth PMOS transistor P5; where: the gate of the third NMOS transistor N3 is connected to the gate of the fifth PMOS transistor P5 and serves as the input terminal of the inverter logic device 121a, the source of the third NMOS transistor N3 is connected to the reference ground AGND, the drain of the third NMOS transistor N3 is connected to the drain of the fifth PMOS transistor P5 and serves as the output terminal of the inverter logic device 121a, and the substrate of the third NMOS transistor N3 is connected to its source; the source of the fifth PMOS transistor P5 is connected to the first voltage V1, and the substrate of the fifth PMOS transistor P5 is connected to its source.

[0052] In the above conversion control unit 121:

[0053] In the first mode, the first enable signal EN is at a high level and the second enable signal ENB is at a low level. At this time, the first NMOS transistor N1 is turned on and the first PMOS transistor P1 is turned off, the second PMOS transistor P2 is turned on and the second NMOS transistor N2 is turned off. In this way, the gate of the fourth PMOS transistor P4 is pulled low, which is equivalent to generating a first channel opening signal. The fourth PMOS transistor P4 is turned on, making the input terminal of the inverter logic device 121a at a high level and the output terminal of the inverter logic device 121a at a low level, which is equivalent to not generating a second channel opening signal.

[0054] In the second mode, the first enable signal EN is at a low level and the second enable signal ENB is at a high level. At this time, the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off, the second NMOS transistor N2 is turned on and the second PMOS transistor P2 is turned off. In this way, the gate of the third PMOS transistor P3 is pulled low and the third PMOS transistor P3 is turned on, thereby pulling the gate of the fourth PMOS transistor P4 high, which is equivalent to not generating a first channel opening signal. At the same time, the input terminal of the inverter logic device 121a is at a low level and the output terminal of the inverter logic device 121a is at a high level, which is equivalent to generating a second channel opening signal.

[0055] The voltage output unit 122 is connected to the conversion control unit 121 and includes a first output channel 122a and a second output channel 122b; among them, the first output channel 122a is controlled by the first channel opening signal to be turned on and directly outputs the first voltage V1, and the second output channel 122b is controlled by the second channel opening signal to be turned on and outputs the first voltage V1 after voltage reduction. In one embodiment, the first output channel 122a includes a sixth PMOS transistor P6, and the second output channel 122b includes a fourth NMOS transistor N4; among them:

[0056] The gate of the sixth PMOS transistor P6 is connected to the first output terminal of the conversion control unit 121 to facilitate access to the first channel opening signal. The source of the sixth PMOS transistor P6 is connected to the first voltage V1. The drain of the sixth PMOS transistor P6 is used as the output terminal of the first output channel 122a, and the substrate of the sixth PMOS transistor P6 is connected to its source. The gate of the fourth NMOS transistor N4 is connected to the second output terminal of the conversion control unit 121 to facilitate access to the second channel opening signal. The source of the fourth NMOS transistor N4 is used as the output terminal of the second output channel 122b. The drain of the fourth NMOS transistor N4 is connected to the first voltage V1, and the substrate of the fourth NMOS transistor is connected to the reference ground AGND.

[0057] In the above voltage output unit 122:

[0058] In the first mode, the conversion control unit 121 generates a first channel enable signal but does not generate a second channel enable signal. At this time, the gate of the sixth PMOS transistor P6 is connected to a low level, the gate of the fourth NMOS transistor N4 is connected to a low level, the sixth PMOS transistor P6 is turned on, the fourth NMOS transistor N4 is turned off, and the first voltage V1 is directly output through the sixth PMOS transistor P6. That is, the output voltage is V1.

[0059] In the second mode, the conversion control unit 121 generates a second channel enable signal but does not generate a first channel enable signal. At this time, the gate of the fourth NMOS transistor N4 is connected to a high level, the gate of the sixth PMOS transistor P6 is connected to a high level, the fourth NMOS transistor N4 is turned on, the sixth PMOS transistor P6 is turned off, and the first voltage V1 is output through the fourth NMOS transistor N4; if the output voltage is denoted as V2, then: V2 = V1 - VTH_N4, where VTH_N4 is the threshold voltage of the fourth NMOS transistor N4.

[0060] As Figure 3 shown, this embodiment also provides a circuit system 10, including a voltage conversion circuit 100; further, it further includes a charge pump circuit 200 and a memory circuit 300.

[0061] The voltage conversion circuit 100 receives the first voltage V1, and directly outputs the first voltage V1 in the first mode, and outputs the first voltage V1 after voltage reduction in the second mode (the voltage after voltage reduction is denoted as the second voltage V2). Among them, the voltage conversion circuit 100 is implemented by the circuit structure described above, and the relevant content can be seen in the above, which will not be elaborated here.

[0062] The charge pump circuit 200 is connected to the voltage conversion circuit 100 and is used to provide the first voltage V1 to the voltage conversion circuit 100. In one example, the charge pump circuit 200 is implemented by a charge pump boost structure. It should be noted that the specific value of the first voltage V1 should be determined by actual requirements and is not limited thereto.

[0063] The memory circuit 300 is connected to the voltage conversion circuit 100. In practical applications, the memory circuit 300 is usually a NOR FLASH (non-volatile flash) memory circuit, including a row decoder and an N-well capacitor disposed in the direction of the row decoder. Of course, it also includes other parts such as a memory array. In the first mode, for example, in the working mode, the memory circuit 300 charges the N-well capacitor based on the first voltage V1 to ensure the read speed of the memory circuit 300. In the second mode, for example, in the standby mode, the memory circuit 300 charges the N-well capacitor based on the second voltage V2, which can reduce the standby power consumption on the basis of ensuring that there is no waiting time when switching from the standby mode to the working mode. The specific analysis is as follows: In the standby mode, the second voltage V2 input to the memory circuit 300 is smaller than the first voltage V1 (specifically, it is reduced by the threshold voltage of an NMOS transistor), which reduces the leakage current generated by the memory circuit 300, thereby reducing the load current of the charge pump circuit 200, increasing the discharge time of the charge pump circuit 200, and reducing the number of boost operations, thus reducing the power consumption of the charge pump circuit 200 in the standby mode, as specifically shown in Figure 4 shown.

[0064] This embodiment also provides a voltage conversion method, including the following steps; wherein, this voltage conversion method can be implemented by using the circuit structure described above. In practical applications, the method of this embodiment is usually applied to a semiconductor memory, for example, a NOR FLASH (non-volatile flash) memory.

[0065] In the first mode, receive the first voltage V1 and directly output the first voltage V1. Taking the NOR FLASH memory as an example, and the first mode is the working mode; directly outputting the first voltage V1 to the subsequent memory circuit in the working mode can ensure the normal operation of the memory circuit in the working mode and avoid affecting the read speed due to the long charging time of the N-well capacitor.

[0066] In the second mode, receive the first voltage V1 and step down the first voltage V1 for output; wherein, the stepped-down voltage is denoted as the second voltage V2, then: the difference between the second voltage V2 and the first voltage V1 is the threshold voltage of the NMOS transistor, satisfying the formula V2 = V1 - VTH_N4. Taking the NOR FLASH memory as an example, and the second mode is the standby mode; stepping down the first voltage V1 and outputting it to the subsequent memory circuit in the standby mode can reduce the leakage current generated by the memory circuit, thereby achieving the purpose of reducing the standby power consumption.

[0067] In summary, a voltage conversion circuit, a circuit system, and a voltage conversion method according to the present invention propose a brand-new voltage conversion solution through the design of an enabling module and a conversion module. The first voltage is directly output in the first mode, and the first voltage is stepped down and output in the second mode, realizing different voltages output in different modes. When this voltage conversion solution is applied to a semiconductor memory, the standby power consumption can be reduced by stepping down the first voltage in the standby mode. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0068] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A voltage conversion circuit, characterized in that: The voltage conversion circuit comprises: An enabling module, providing a set of mutually inverted enabling signals based on the first mode and the second mode; The conversion module is connected to the enabling module, receives a first voltage, and directly outputs the first voltage in the first mode, and outputs the first voltage in a stepped-down manner in the second mode.

2. The voltage conversion circuit according to claim 1, characterized in that: In the enable module, a set of mutually inverted enable signals includes a first enable signal and a second enable signal; in the first mode, the first enable signal is a high level and the second enable signal is a low level; in the second mode, the first enable signal is a low level and the second enable signal is a high level.

3. The voltage conversion circuit according to claim 1, characterized in that: The conversion module comprises: A conversion control unit, connected to the enabling module, controlled by a set of mutually inverted enabling signals, generating a first channel start signal in the first mode, and generating a second channel start signal in the second mode; A voltage output unit is connected to the conversion control unit, and includes a first output channel and a second output channel, wherein the first output channel is controlled by the first channel start signal to be turned on and directly output the first voltage, and the second output channel is controlled by the second channel start signal to be turned on and output the first voltage at a reduced voltage.

4. The voltage conversion circuit according to claim 3, characterized in that: The conversion control unit includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and an inverting logic device, wherein: the gate of the first NMOS tube and the gate of the first PMOS tube are connected to a first enable signal, the gate of the second NMOS tube and the gate of the second PMOS tube are connected to a second enable signal, the source of the first NMOS tube and the source of the second NMOS tube are connected to a reference ground, the drain of the first NMOS tube and the drain of the second NMOS tube are connected to the drain of the first PMOS tube and the drain of the second PMOS tube respectively. The source of the first PMOS tube and the source of the second PMOS tube are connected to the drain of the third PMOS tube and the drain of the fourth PMOS tube respectively, the gate of the third PMOS tube is connected to the drain of the second NMOS tube, the gate of the fourth PMOS tube is connected to the drain of the first NMOS tube and serves as the first output end of the conversion control unit, the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the first voltage, the input end of the inverting logic device is connected to the drain of the second NMOS tube, and the output end of the inverting logic device serves as the second output end of the conversion control unit.

5. The voltage conversion circuit according to claim 4, characterized in that: The inverting logic device includes a third NMOS tube and a fifth PMOS tube, wherein: the gate of the third NMOS tube is connected to the gate of the fifth PMOS tube and serves as the input end of the inverting logic device, the source of the third NMOS tube is connected to the reference ground, the drain of the third NMOS tube is connected to the drain of the fifth PMOS tube and serves as the output end of the inverting logic device, and the source of the fifth PMOS tube is connected to the first voltage.

6. The voltage conversion circuit according to claim 3, characterized in that: The first output channel includes a sixth PMOS tube, wherein: the gate of the sixth PMOS tube is connected to the first output end of the conversion control unit, the source of the sixth PMOS tube is connected to the first voltage, and the drain of the sixth PMOS tube serves as the output end of the first output channel.

7. The voltage conversion circuit according to claim 3, characterized in that: The second output channel includes a fourth NMOS tube, wherein: the gate of the fourth NMOS tube is connected to the second output end of the conversion control unit, the source of the fourth NMOS tube serves as the output end of the second output channel, and the drain of the fourth NMOS tube is connected to the first voltage.

8. A circuit system, characterized in that: The circuit system comprises: a voltage conversion circuit as claimed in any one of claims 1 to 7.

9. The circuit system according to claim 8, characterized in that: A voltage obtained by reducing the first voltage is recorded as a second voltage, and the circuit system further includes: A charge pump circuit, used for providing the first voltage; A memory circuit is connected to the voltage conversion circuit, and in the first mode, the N-well capacitor is charged based on the first voltage; in the second mode, the N-well capacitor is charged based on the second voltage.

10. A voltage conversion method, characterized in that: The voltage conversion method comprises: In the first mode, a first voltage is received and the first voltage is directly outputted; In the second mode, a first voltage is received and the first voltage is stepped down and outputted; The voltage obtained by reducing the first voltage is recorded as the second voltage, and the difference between the first voltage and the second voltage is the threshold voltage of the NMOS tube.

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