A high-efficiency tripler based on transformer-tap inductance optimized common-mode impedance

Abstract

The application provides a high-efficiency tripler based on transformer tap inductance optimized common mode impedance, and belongs to the field of radio frequency integrated circuits, comprising an input matching network, a tripling unit, an inter-stage matching network, a buffer amplification unit and an output matching network. The inter-stage matching network is connected in series with an 8-shaped inductor at the center tap of the primary coil, can adjust and optimize the common mode impedance without obviously affecting the differential mode impedance, improve the efficiency of the tripler, and suppress the sensitivity of the tripling unit to the common mode impedance. In addition, since the inductor connected in series with the center tap adopts the form of 8-shaped symmetrical winding, the additional area is not needed when the tap inductor is added.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuits, and specifically relates to a high-efficiency tripler based on transformer tap inductance optimization of common-mode impedance. Background Technology

[0002] With the development of communication technology, the millimeter-wave band (30 GHz ~ 300 GHz) has become crucial for achieving high-speed wireless communication data transmission due to its high frequency and ample bandwidth resources. As the core component of a high-speed wireless transceiver, the performance of the millimeter-wave frequency source, including its power consumption, output power, and phase noise, plays a vital role in the entire system. Furthermore, there is a widespread demand for high-performance millimeter-wave frequency sources in the fields of high-precision radar and high-precision imaging.

[0003] In the millimeter-wave band, there are two main approaches to generating frequency sources. One approach involves directly generating the millimeter-wave signal using an oscillator. However, as the frequency increases, the directly generated frequency suffers from poor noise performance. The other approach is to first generate the fundamental frequency using a low-frequency oscillator, and then use a frequency multiplier to provide the local oscillator output at the target frequency. This approach avoids directly designing an oscillator in the millimeter-wave band, reducing design complexity and becoming a common frequency source approach.

[0004] The introduction of frequency multipliers increases the overhead of area and power consumption. Common triple multipliers implemented using transistor differential pairs have the problem of low efficiency. Improving the conversion efficiency of frequency multipliers has become a hot issue in frequency multiplier design. Summary of the Invention

[0005] The purpose of this invention is to propose a high-efficiency tripler circuit based on transformer tap inductance optimization of common-mode impedance, thereby improving the efficiency of the tripler.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A high-efficiency tripler based on transformer tap inductance optimization of common-mode impedance is characterized by comprising: an input matching network, a tripler unit, an interstage matching network, a buffer amplification unit, and an output matching network; wherein the tripler unit generates the third harmonic, and the buffer amplification unit amplifies the third harmonic.

[0008] Furthermore, the input matching network consists of a first transformer, a first capacitor, a second capacitor, a first inductor, a second inductor, and a first resistor; one end of the primary coil of the first transformer is connected to the input terminal of the tripler, and the other end is grounded; the first capacitor is connected in parallel across the primary coil of the first transformer; one end of the first resistor is connected to the center tap of the secondary coil of the first transformer, and the other end is connected to the first bias voltage; the second capacitor is connected in parallel across the secondary coil of the first transformer; one end of the first inductor and the second inductor are respectively connected to the two ends of the secondary coil of the first transformer, the other end of the first inductor is connected to the gate of the first transistor, and the other end of the second inductor is connected to the gate of the second transistor.

[0009] Furthermore, the tripler unit consists of a first transistor, a second transistor, a first neutralizing capacitor, and a second neutralizing capacitor; the sources of the first transistor and the second transistor are grounded, and the drains of the first transistor and the second transistor are respectively connected to the two ends of the primary coil of the second transformer; one end of the first neutralizing capacitor is connected to the gate of the first transistor, and the other end is connected to the drain of the second transistor; one end of the second neutralizing capacitor is connected to the gate of the second transistor, and the other end is connected to the drain of the first transistor.

[0010] Furthermore, the interstage matching network consists of a second transformer, a second resistor, and a tapped inductor; the two ends of the secondary coil of the second transformer are respectively connected to the third transistor and the fourth transistor; one end of the tapped inductor is connected to the center tap of the primary coil of the second transformer, and the other end is connected to the power supply; one end of the second resistor is connected to the center tap of the secondary coil of the second transformer, and the other end is connected to the second bias voltage.

[0011] Furthermore, the buffer amplification unit consists of a third transistor, a fourth transistor, a third neutralizing capacitor, and a fourth neutralizing capacitor; the sources of the third transistor and the fourth transistor are grounded, and the drains of the third transistor and the fourth transistor are respectively connected to the two ends of the primary coil of the third transformer; one end of the third neutralizing capacitor is connected to the gate of the third transistor, and the other end is connected to the drain of the fourth transistor; one end of the fourth neutralizing capacitor is connected to the gate of the fourth transistor, and the other end is connected to the drain of the third transistor.

[0012] Furthermore, the output matching network consists of a third transformer, a third capacitor, and a fourth capacitor; the third capacitor is connected in parallel across the primary coil of the third transformer, the center tap of the primary coil of the third transformer is connected to the power supply, the fourth capacitor is connected in parallel across the secondary coil of the third transformer, one end of the secondary coil of the third transformer is connected to the output terminal of the tripler, and the other end is grounded.

[0013] Furthermore, one end of the tapped inductor is connected to the center tap of the primary coil of the second transformer, and the other end is connected to the power supply. The tapped inductor can adjust the common-mode impedance of the interstage matching network without significantly affecting the differential-mode impedance of the interstage matching network.

[0014] Furthermore, the tapped inductor can be implemented by starting from the center tap of the primary coil of the second transformer and winding symmetrically around the second transformer before being connected to the power supply (Vsupply).

[0015] Furthermore, the first bias voltage is connected to the center tap of the secondary coil of the first transformer via the first resistor, and directly provides DC bias to the gates of the first transistor and the second transistor through the first inductor and the second inductor. The first bias voltage is selected as the DC voltage that maximizes the third harmonic current output by the third harmonic unit under the corresponding input signal amplitude.

[0016] Furthermore, the second bias voltage is connected to the center tap of the secondary coil of the second transformer via the second resistor, directly providing DC bias to the gates of the third and fourth transistors. The second bias voltage is selected to maximize the DC voltage at which the buffer amplifier unit gain is maximized.

[0017] Furthermore, the first neutralizing capacitor (Cn1) and the second neutralizing capacitor (Cn2) are selected based on the capacitance values ​​that maximize the stability of the third harmonic unit.

[0018] Furthermore, the third neutralizing capacitor (Cn3) and the fourth neutralizing capacitor (Cn4) are selected based on the capacitance values ​​at which the stability of the buffer amplification unit is highest.

[0019] The beneficial effects of this invention are as follows:

[0020] This invention differs from traditional transistor differential pair third harmonics by considering the adjustment of the common-mode impedance of the third harmonic unit to improve its efficiency and suppress its sensitivity to common-mode impedance. A tapped inductor is added between the center tap of the primary coil of the load transformer of the third harmonic unit and the power supply. This minimizes the impact of common-mode impedance adjustment on the differential-mode impedance, allowing for independent design and optimization of the load differential-mode and common-mode impedances of the third harmonic unit. The tapped inductor is implemented with symmetrical windings near the transformer, thereby improving the efficiency of the third harmonic unit while avoiding additional area requirements. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the tripler and the layout of the interstage matching network in this invention.

[0022] Figure 2 This is a schematic diagram of the interstage matching network for a traditional tripler without tapped inductors.

[0023] Figure 3 This is a comparison chart of the efficiency of the frequency tripler of this invention and a traditional frequency tripler.

[0024] Figure 4This is a schematic diagram of a traditional layout for tapped inductors. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in conjunction with the following specific embodiments and with reference to the accompanying drawings.

[0026] The following non-limiting embodiments are intended to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0027] Example 1

[0028] In this embodiment, see the tripler. Figure 1 The structural diagram shows that it consists of an input matching network, a third harmonic unit, an interstage matching network, a buffer amplifier unit, and an output matching network.

[0029] The input matching network consists of a first transformer XFMR1, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2, and a first resistor R1. One end of the primary coil of the first transformer XFMR1 is connected to the input terminal Input of the tripler, and the other end is grounded. The first capacitor C1 is connected in parallel across the primary coil of the first transformer XFMR1. One end of the first resistor R1 is connected to the center tap of the secondary coil of the first transformer XFMR1, and the other end is connected to the first bias voltage Vbias1. The second capacitor C2 is connected in parallel across the secondary coil of the first transformer XFMR1. One end of the first inductor L1 and the second inductor L2 are respectively connected to the two ends of the secondary coil of the first transformer XFMR1. The other end of the first inductor L1 is connected to the gate of the first transistor M1, and the other end of the second inductor L2 is connected to the gate of the second transistor M2.

[0030] The tripler unit consists of a first transistor M1, a second transistor M2, a first neutralizing capacitor Cn1, and a second neutralizing capacitor Cn2. The sources of the first transistor M1 and the second transistor M2 are grounded, and the drains of the first transistor M1 and the second transistor M2 are respectively connected to the two ends of the primary coil of the second transformer XFMR2. One end of the first neutralizing capacitor Cn1 is connected to the gate of the first transistor M1, and the other end is connected to the drain of the second transistor M2. One end of the second neutralizing capacitor Cn2 is connected to the gate of the second transistor M2, and the other end is connected to the drain of the first transistor M1.

[0031] The interstage matching network consists of a second transformer XFMR2, a second resistor R2, and a tapped inductor Lt. The two ends of the secondary coil of the second transformer XFMR2 are connected to the third transistor M3 and the fourth transistor M4, respectively. One end of the tapped inductor Lt is connected to the center tap of the primary coil of the second transformer XFMR2, and the other end is connected to the power supply Vsupply. One end of the second resistor R2 is connected to the center tap of the secondary coil of the second transformer XFMR2, and the other end is connected to the second bias voltage Vbias2.

[0032] The buffer amplification unit consists of a third transistor M3, a fourth transistor M4, a third neutralizing capacitor Cn3, and a fourth neutralizing capacitor Cn4. The sources of the third transistor M3 and the fourth transistor M4 are grounded, and the drains of the third transistor M3 and the fourth transistor M4 are respectively connected to the two ends of the primary coil of the third transformer XFMR3. One end of the third neutralizing capacitor Cn3 is connected to the gate of the third transistor M3, and the other end is connected to the drain of the fourth transistor M4. One end of the fourth neutralizing capacitor Cn4 is connected to the gate of the fourth transistor M4, and the other end is connected to the drain of the third transistor M3.

[0033] The output matching network consists of a third transformer XFMR3, a third capacitor C3, and a fourth capacitor C4. The third capacitor C3 is connected in parallel across the primary coil of the third transformer XFMR3. The center tap of the primary coil of the third transformer XFMR3 is connected to the power supply Vsupply. The fourth capacitor C4 is connected in parallel across the secondary coil of the third transformer XFMR3. One end of the secondary coil of the third transformer XFMR3 is connected to the output terminal Output of the tripler, and the other end is grounded.

[0034] Among them, such as Figure 1 As shown in the schematic diagram, the tapped inductance of the interstage matching network starts from the center tap of the primary coil of the second transformer and is implemented in a symmetrical winding form near the second transformer, then leads out from one side and connects to the power supply. Since the current directions and the resulting magnetic flux directions of the two windings are opposite, the coupling between the tapped inductance and the primary and secondary coils of the second transformer is very small. This allows adjustment of the common-mode impedance of the interstage matching network without significantly affecting its differential-mode impedance. By adjusting and optimizing the common-mode impedance of the interstage matching network, the efficiency of the tripler is improved.

[0035] Based on the above working principle, this embodiment presents the design and simulation of a third frequency multiplier, verifying the practicality of the present invention.

[0036] Figure 3 A tapless inductor is given (i.e.) Figure 2 The conventional tripler (as shown) and the tapped inductor proposed in this invention (i.e., Figure 1The comparison of the conversion efficiency of the tripler (as shown in the figure) shows that adding a certain tap inductance between the center tap of the primary coil of the second transformer and the power supply can improve the efficiency of the tripler.

[0037] Figure 4 An interstage matching network using a traditional tapped inductor layout is presented. (Comparison) Figure 1 and Figure 4 As can be seen, by adopting a symmetrical winding form, tapped inductors can be implemented without requiring additional area, saving more than 40% of the area of ​​the interstage matching network.

[0038] The above description is merely a specific embodiment of the present invention. For those skilled in the art, any modifications and variations made without departing from the principle of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A high-efficiency third frequency multiplier based on transformer tap inductance-optimized common-mode impedance, characterized in that, include: Input matching network, third harmonic unit, interstage matching network, buffer amplifier unit, and output matching network; The input matching network consists of a first transformer (XFMR1), a first capacitor (C1), a second capacitor (C2), a first inductor (L1), a second inductor (L2), and a first resistor (R1). One end of the primary coil of the first transformer (XFMR1) is connected to the input terminal of the tripler, and the other end is grounded. The first capacitor (C1) is connected in parallel across the primary coil of the first transformer (XFMR1). One end of the first resistor (R1) is connected to the center tap of the secondary coil of the first transformer (XFMR1), and the other end is connected to the first bias voltage (Vbias1). The second capacitor (C2) is connected in parallel across the secondary coil of the first transformer (XFMR1). One end of the first inductor (L1) and the second inductor (L2) are respectively connected to the two ends of the secondary coil of the first transformer (XFMR1). The other end of the first inductor (L1) is connected to the gate of the first transistor (M1), and the other end of the second inductor (L2) is connected to the gate of the second transistor (M2). The tripler unit consists of a first transistor (M1), a second transistor (M2), a first neutralizing capacitor (Cn1), and a second neutralizing capacitor (Cn2). The sources of the first transistor (M1) and the second transistor (M2) are grounded, and the drains of the first transistor (M1) and the second transistor (M2) are respectively connected to the two ends of the primary coil of the second transformer (XFMR2). One end of the first neutralizing capacitor (Cn1) is connected to the gate of the first transistor (M1), and the other end is connected to the drain of the second transistor (M2). One end of the second neutralizing capacitor (Cn2) is connected to the gate of the second transistor (M2), and the other end is connected to the drain of the first transistor (M1). The interstage matching network consists of a second transformer (XFMR2), a second resistor (R2), and a tapped inductor (Lt). The two ends of the secondary coil of the second transformer (XFMR2) are connected to the third transistor (M3) and the fourth transistor (M4) respectively. One end of the tapped inductor (Lt) is connected to the center tap of the primary coil of the second transformer (XFMR2), and the other end is connected to the power supply (Vsupply). One end of the second resistor (R2) is connected to the center tap of the secondary coil of the second transformer (XFMR2), and the other end is connected to the second bias voltage (Vbias2). The buffer amplification unit consists of a third transistor (M3), a fourth transistor (M4), a third neutralizing capacitor (Cn3), and a fourth neutralizing capacitor (Cn4). The sources of the third transistor (M3) and the fourth transistor (M4) are grounded, and the drains of the third transistor (M3) and the fourth transistor (M4) are respectively connected to the two ends of the primary coil of the third transformer (XFMR3). One end of the third neutralizing capacitor (Cn3) is connected to the gate of the third transistor (M3), and the other end is connected to the drain of the fourth transistor (M4). One end of the fourth neutralizing capacitor (Cn4) is connected to the gate of the fourth transistor (M4), and the other end is connected to the drain of the third transistor (M3). The output matching network consists of a third transformer (XFMR3), a third capacitor (C3), and a fourth capacitor (C4). The third capacitor (C3) is connected in parallel across the primary coil of the third transformer (XFMR3). The center tap of the primary coil of the third transformer (XFMR3) is connected to the power supply (Vsupply). The fourth capacitor (C4) is connected in parallel across the secondary coil of the third transformer (XFMR3). One end of the secondary coil of the third transformer (XFMR3) is connected to the output terminal of the tripler, and the other end is grounded.

2. The high-efficiency third frequency harmonic according to claim 1, characterized in that, One end of the tapped inductor (Lt) is connected to the center tap of the primary coil of the second transformer (XFMR2), and the other end is connected to the power supply (Vsupply). The tapped inductor (Lt) can adjust the common-mode impedance of the interstage matching network without significantly affecting the differential-mode impedance of the interstage matching network.

3. The high-efficiency third frequency harmonic according to claim 1, characterized in that, The tapped inductor (Lt) starts from the center tap of the primary coil of the second transformer (XFMR2) and is implemented in a symmetrical figure-eight shape near the second transformer (XFMR2) before being connected to the power supply (Vsupply).

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