High-efficiency and high-linearity power amplifier with self-adaptive biasing circuit

Abstract

The invention discloses a high-efficiency and high-linearity power amplifier with a self-adaptive biasing circuit. According to the technical scheme, the high-efficiency and high-linearity power amplifier with the self-adaptive bias circuit comprises a voltage reference source circuit, the self-adaptive bias circuit and a power amplifier body. The self-adaptive bias circuit is adopted to provide a bias voltage which is dynamically adjusted along with the change of an input signal for the power amplifier, so that the power amplifier is ensured to realize relatively constant gain under different power supply voltages, and the problem of gain compression of the power amplifier when the input power is increased under the low-power-consumption bias voltage is solved; and the linearity and the power additional efficiency of the low-power-consumption power amplifier are greatly improved. The invention relates to a power amplifier in a radio frequency receiver in the field of wireless communication, in particular to a high-efficiency and high-linearity power amplifier with a self-adaptive biasing circuit based on a CMOS (complementary metal oxide semiconductor) process.

Description

Technical Field

[0001] The present invention relates to a power amplifier in a radio frequency receiver in the field of wireless communication, and particularly to a high-efficiency and high-linearity power amplifier with an adaptive bias circuit based on CMOS technology. Background Art

[0002] Radio frequency, abbreviated as RF, represents the electromagnetic frequency that can be radiated into space, with a frequency range from 300 KHz to 30 GHz. Radio frequency is radio frequency electromagnetic wave, which is a short form of a high-frequency alternating current changing electromagnetic wave. The radio frequency signal is the same as the radio frequency concept, that is, an electromagnetic wave that has been modulated and has a certain transmission frequency. The radio frequency power amplifier is a core component in a wireless communication system, responsible for amplifying the radio frequency signal to a sufficient power level to ensure that the signal can be transmitted over a long distance and with high quality. It plays a crucial role in devices such as base stations, radars, satellite communications, and radio transmitters. The radio frequency power amplifier enhances the weak radio frequency signal to a level that can penetrate the atmosphere and overcome path loss by precisely controlling the gain and phase of the signal. In design, these amplifiers need to balance high efficiency, linearity, and stability to maintain excellent performance in a complex and changing communication environment. In short, the radio frequency power amplifier is the key to realizing long-distance, high-rate, and high-quality communication in a wireless communication system. Its technological progress continuously pushes the boundaries of wireless technology and provides strong support for the informatization process of modern society.

[0003] The 1dB compression point is an important parameter to describe the non-linear characteristics of an amplifier. Before the amplifier operates normally and enters the saturation state, its output power increases linearly with the input power. However, when the input power increases to a certain level, due to the non-linear effect of the amplifier, the increasing speed of the output power begins to slow down, that is, the gain begins to decrease. When the input power changes by 2dB while the output power only changes by 1dB, the corresponding input and output power points are the 1dB compression point. This point marks the start of the amplifier entering the non-linear region and is a key indicator for evaluating the linearity and dynamic range of the amplifier.

[0004] PAE, namely Power Added Efficiency, is defined as the difference between the RF power output by the power amplifier and the input DC power, divided by the input DC power, usually expressed as a percentage. PAE reflects the ability of the power amplifier to convert the input DC power into RF power. In an ideal situation, all the DC power supplied to the amplifier should be converted into RF output power. However, in reality, due to factors such as the internal resistance of the amplifier and the non-linear effects of transistors, a part of the DC power will be lost in the form of heat. Therefore, PAE is one of the important indicators to measure the performance of the amplifier.

[0005] CMOS process, whose full name is Complementary Metal Oxide Semiconductor process. It combines N-type MOS transistors (NMOS) and P-type MOS (PMOS) transistors on the same silicon substrate and is the mainstream integrated circuit manufacturing process developed on the basis of PMOS and NMOS processes. The CMOS process has the advantages of high integration and flexible design, and is widely used in fields such as portable electronic devices, high-performance computing, communication technologies, and the Internet of Things. Devices such as MOS transistors, bipolar junction transistors (BJT transistors), polysilicon resistors, metal capacitors, and metal inductors can be integrated on the CMOS process.

[0006] In the design of traditional CMOS power amplifiers, there are mainly three ways to implement the bias circuit. The first way is that an off-chip circuit provides the bias voltage for the gates of each stage of amplifying transistors. One of its disadvantages is that the off-chip circuit needs to provide an accurate bias voltage additionally, which will increase the product cost and reduce the product integration. Second, under the condition of a constant bias voltage, the threshold voltage and mobility of the amplifying transistors will change with temperature, resulting in the deterioration of the amplifier gain and linearity performance. Third, the bias voltage provided for the gates of each stage of amplifying transistors cannot be dynamically adjusted according to the change of the input signal. The second way is to provide the bias voltage for the gates of each stage of amplifying transistors by dividing the power supply voltage with a resistor or the current mirror of a resistive load. One of its disadvantages is that in order to obtain an accurate bias voltage, an accurate power supply voltage needs to be provided off-chip. Second, under the condition of a constant power supply voltage, the threshold voltage and mobility of the amplifying transistors change with temperature, resulting in the deterioration of the amplifier gain and linearity performance. Third, the bias voltage provided for the gates of each stage of amplifying transistors cannot be dynamically adjusted according to the change of the input signal. The third way is that an on-chip reference circuit provides a reference voltage to provide a bias voltage independent of the power supply voltage for the gates of CMOS amplifying transistors, without the need to provide an accurate power supply voltage off-chip. Its disadvantage is that the bias voltage provided for the gates of the amplifying transistors cannot be dynamically adjusted according to the change of the input signal. Especially when the CMOS amplifying transistor biases the gate at a low bias voltage to improve efficiency, as the input signal increases, the gain of the amplifier will show a slow compression.

[0007] To avoid the slow compression of the amplifier gain when the input signal continuously increases, the traditional approach is to directly increase the bias voltage of the CMOS transistor. However, this will significantly increase the power consumption of the amplifier and reduce the PAE efficiency of the amplifier. Therefore, for applications where the input signal power varies significantly, how to design an adaptive bias circuit for a high-linearity power amplifier is a major challenge in the field of radio frequency integrated circuit design. Summary of the Invention

[0008] The objective of the present invention is to address the deficiencies of the existing technology and provide an on-chip fully integrated adaptive bias circuit for a high-efficiency and high-linearity power amplifier, which can provide a bias voltage independent of the power supply voltage and dynamically adjusted with the input signal for the gate of the power amplifier.

[0009] To achieve the above objective, the present invention adopts the following technical solution: A high-efficiency and high-linearity power amplifier with an adaptive bias circuit, comprising: a voltage reference source circuit 1, an adaptive bias circuit 1, and a power amplifier 1. The bias voltage reference source circuit 1 provides a reference voltage Vref1 independent of the power supply voltage for the adaptive bias circuit 1; the adaptive bias circuit 1 generates a bias voltage Vb1 that dynamically adjusts with the change of the input signal amplitude by sensing the change of the input signal amplitude.

[0010] The present invention has the following advantages compared with the existing technology: All circuits and devices involved in the present invention can be implemented on a CMOS process chip, with small size, light weight, and low cost. By adopting a bias voltage reference source circuit to provide a reference voltage independent of the power supply voltage for the gate of the amplifying transistor, when the input signal amplitude is relatively low, it can ensure that the NMOS amplifying transistor of the power amplifier maintains a relatively constant transconductance and realizes a power amplifier with a relatively constant gain. By adopting an adaptive bias circuit to provide a bias voltage that dynamically adjusts with the input signal for the power amplifier, it alleviates the problem of gain compression of the power amplifier when the input power increases under a low-power bias voltage, and significantly improves the linearity and power added efficiency of the low-power power amplifier. Description of the Drawings

[0011] Figure 1 is a schematic diagram of the principle of a traditional power amplifier with a constant transconductance voltage reference source.

[0012] Figure 2 is a system block diagram of a high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to the present invention.

[0013] Figure 3 is a schematic diagram of the principle of a high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to the present invention.

[0014] Figure 4 isFigure 3 Schematic diagram of the principle of the voltage reference source circuit 2.

[0015] Figure 5 is Figure 3 Schematic diagram of the principle of the voltage reference source circuit 3.

[0016] Figure 6 is Figure 3 Schematic diagram of the principle of the operational transconductance amplifier OTA1.

[0017] Figure 7 is a comparison of the simulation results of the DC bias voltage of the gate of the amplifying tube of the present invention and Figure 1 the power amplifier 1a in [reference] under the condition that the input RF signal gradually increases.

[0018] Figure 8 is a comparison of the simulation results of the gain compression characteristics of the present invention and Figure 1 the RF amplifier 1a in [reference] under the condition that the input RF signal gradually increases.

[0019] Figure 9 is a comparison of the simulation results of the power added efficiency of the present invention and Figure 1 the RF amplifier 1a in [reference] under the condition that the input RF signal gradually increases. Detailed implementation manners

[0020] Refer to Figure 2 . In an optimal embodiment described in the following embodiments, a high-efficiency and high-linearity power amplifier with an adaptive bias circuit includes: a voltage reference source circuit 1, an adaptive bias circuit 1, and a power amplifier 1 connected in parallel between the common terminal GND and the power supply terminal VDD. The reference voltage Vref1 output terminal of the voltage reference source circuit 1 is connected to the reference voltage Vref1 input terminal of the adaptive bias circuit 1; the bias voltage Vb1 output terminal of the adaptive bias circuit 1 is connected to the bias voltage Vb1 input terminal of the power amplifier 1; the induced signal AC voltage Va1 input terminal of the adaptive bias circuit 1 is connected to the induced signal AC voltage Va1 output terminal of the power amplifier 1.

[0021] Refer to Figure 3。The voltage reference source circuit 1 includes an NMOS transistor NM3, an NMOS transistor NM4, an NMOS transistor NM5, a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, a resistor R2, and a reference voltage Vref1 output terminal of the voltage reference source circuit 1. Among them, the gate of the PMOS transistor PM1 is connected to the gates of the PMOS transistor PM2, the drain of the PMOS transistor PM2, the gate of the PMOS transistor PM3, and the drain of the NMOS transistor NM4. The drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM3. The source of the PMOS transistor PM1 is connected to the power supply terminal VDD. The gate of the PMOS transistor PM2 is connected to the gates of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and the gate of the PMOS transistor PM3. The source of the PMOS transistor PM2 is connected to the power supply terminal VDD. The gate of the PMOS transistor PM3 is connected to the gates of the PMOS transistor PM2, the drain of the PMOS transistor PM2, and the gate of the PMOS transistor PM1. The drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, the gate of the NMOS transistor NM5, and the reference voltage Vref1 output terminal of the voltage reference source circuit 1. The source of the PMOS transistor PM3 is connected to the power supply terminal VDD. The gate of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM3, the drain of the PMOS transistor PM1, and the gate of the NMOS transistor NM4. The source of the NMOS transistor NM3 is connected to the common terminal GND. The gate of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM3, the drain of the PMOS transistor PM1, and the gate of the NMOS transistor NM4. The gate of the PMOS transistor PM2 is connected to the gates of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and the gate of the PMOS transistor PM3. The drain of the NMOS transistor NM4 is connected to the gates of the PMOS transistor PM2, the drain of the PMOS transistor PM2, the gate of the PMOS transistor PM3, and the gate of the PMOS transistor PM1. The source of the NMOS transistor NM4 is connected to one end of the resistor R2. One end of the resistor R2 is connected to the source of the NMOS transistor NM4, and the other end of the resistor R2 is connected to the common terminal GND. The gate of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM5, the drain of the PMOS transistor PM3, and the reference voltage Vref1 output terminal of the voltage reference source circuit 1. The source of the NMOS transistor NM5 is connected to the common terminal GND.

[0022] For the voltage reference source circuit 1, the PMOS transistors PM1, PM2, and PM3 with their gates connected back-to-back have their sources connected to the power supply terminal VDD. The transistors PM1, PM2, and PM3 with the same size form a current mirror to force the currents flowing through the drains of the NMOS transistors NM3, NM4, and NM5 to be equal.

[0023] Refer to Figure 3Power amplifier, including NMOS transistor NM1, NMOS transistor NM2, inductor L1, capacitor C1, capacitor C2, capacitor C3, resistor R1, radio frequency signal input terminal RFin1, radio frequency signal output terminal RFout1, bias voltage Vb1 input terminal of the power amplifier, and induced signal AC voltage Va1 output terminal of the power amplifier. Among them, the drain of NMOS transistor NM1 is connected to the source of NMOS transistor NM2. The gate of NMOS transistor NM1 is connected to one end of resistor R1, one end of capacitor C1, and one end of capacitor C3. The source of NMOS transistor NM1 is connected to the common terminal GND. The drain of NMOS transistor NM2 is connected to one end of inductor L1 and one end of capacitor C2. The gate of NMOS transistor NM1 is connected to the power supply terminal VDD. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM1. One end of inductor L1 is connected to the drain of NMOS transistor NM2, and the other end of inductor L1 is connected to the power supply terminal VDD. One end of capacitor C2 is connected to the drain of NMOS transistor NM2 and one end of inductor L1, and the other end of capacitor C2 is connected to the radio frequency signal output terminal RFout1 through output stage matching network 1. One end of capacitor C1 is connected to the gate of NMOS transistor NM1, one end of resistor R1, and one end of capacitor C3, and the other end of capacitor C1 is connected to the radio frequency signal input terminal RFin1 through input stage matching network 1. One end of resistor R1 is connected to the gate of NMOS transistor NM1, one end of capacitor C1, and one end of capacitor C3, and the other end of resistor R1 is connected to the bias voltage Vb1 input terminal of the power amplifier. One end of capacitor C3 is connected to the gate of NMOS transistor NM1, one end of capacitor C1, and one end of resistor R1, and the other end of capacitor C3 is connected to the induced signal AC voltage Va1 output terminal of the power amplifier.

[0024] Refer to Figure 4。The voltage reference source circuit 2 includes a BJT transistor Q1, a PMOS transistor PM4, a resistor R7, a resistor R8, an input terminal for the induced signal AC voltage Va2 of the voltage reference source circuit 2, and an output terminal for the reference voltage Vref2 of the voltage reference source circuit 2. Among them, the collector of the BJT transistor Q1 is connected to the base of the BJT transistor Q1, the gate of the PMOS transistor PM4, one end of the resistor R8, and the input terminal for the induced signal AC voltage Va2 of the voltage reference source circuit 2. The emitter of the BJT transistor Q1 is connected to the common terminal GND; the gate of the PMOS transistor PM4 is connected to the base of the BJT transistor Q1, the collector of the BJT transistor Q1, one end of the resistor R8, and the input terminal for the induced signal AC voltage Va2 of the voltage reference source circuit 2. The source of the PMOS transistor PM4 is connected to the power supply terminal VDD, and the drain of the PMOS transistor PM4 is connected to one end of the resistor R7 and the output terminal for the reference voltage Vref2 of the voltage reference source circuit 2; one end of the resistor R8 is connected to the base of the BJT transistor Q1, the gate of the PMOS transistor PM4, the collector of the BJT transistor Q1, and the input terminal for the induced signal AC voltage Va2 of the voltage reference source circuit 2, and the other end of the resistor R8 is connected to the power supply terminal VDD; one end of the resistor R7 is connected to the drain of the PMOS transistor PM4 and the output terminal for the reference voltage Vref2 of the voltage reference source circuit 2, and the other end of the resistor R7 is connected to the common terminal GND.

[0025] For the voltage reference source circuit 2, its input terminal for the induced signal AC voltage Va2 is connected to the input terminal for the induced signal AC voltage Va1 of the adaptive bias circuit, and it can receive the RF AC signal coupled by the capacitor C1 from the input terminal of the power amplifier. The Va2 input terminal is connected to the BJT transistor Q1 connected in the diode connection method (the base and the collector are short-circuited). When the RF AC signal gradually increases, the DC voltage of Va2 will decrease, and the DC gate-source voltage of the PMOS transistor PM4 will increase, which will further cause the drain-source current of the PMOS transistor PM4 to increase, the current flowing through the resistor R7 to increase, and finally prompt the DC voltage of Vref2 to increase.

[0026] Refer to Figure 5The voltage reference source circuit 3 includes a BJT transistor Q2, a PMOS transistor PM5, a resistor R9, a resistor R10, and a reference voltage Vref3 output terminal of the voltage reference source circuit 3. Among them, the collector of the BJT transistor Q2 is connected to the base of the BJT transistor Q2, the gate of the PMOS transistor PM5, and one end of the resistor R10. The emitter of the BJT transistor Q2 is connected to the common terminal GND; the gate of the PMOS transistor PM5 is connected to the base of the BJT transistor Q2, the collector of the BJT transistor Q2, and one end of the resistor R10. The source of the PMOS transistor PM5 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM5 is connected to one end of the resistor R9 and the reference voltage Vref3 output terminal of the voltage reference source circuit 3; one end of the resistor R10 is connected to the base of the BJT transistor Q2, the gate of the PMOS transistor PM5, and the collector of the BJT transistor Q2. The other end of the resistor R10 is connected to the power supply terminal VDD; one end of the resistor R9 is connected to the drain of the PMOS transistor PM5 and the reference voltage Vref3 output terminal of the voltage reference source circuit 3. The other end of the resistor R9 is connected to the common terminal GND.

[0027] For the voltage reference source circuit 3, the BJT transistor Q2 has the same size as the BJT transistor Q1 in the voltage reference source circuit 2, the PMOS transistor PM5 has the same size as the PMOS transistor PM4 in the voltage reference source circuit 2, the resistor R9 has the same size as the resistor R7 in the voltage reference source circuit 2, and the resistor R10 has the same size as the resistor R8 in the voltage reference source circuit 2. The value of the output reference voltage Vref3 is the same as the value of the reference voltage Vref2 output by the voltage reference source circuit 2 when the RF AC signal is weak.

[0028] Refer to Figure 6. The operational transconductance amplifier OTA1 includes NMOS transistors NM8, NM9, NM10, NM11, NM12, NM13, NM14, PMOS transistors PM6, PM7, PM8, PM9, PM10, PM11, PM12, PM13, PM14, PM15, PM16, PM17, PM18, PM19, resistor R11, the positive input terminal IN1+ of the operational transconductance amplifier OTA1, the negative input terminal IN1- of the operational transconductance amplifier OTA1, and the output terminal OUT1 of the operational transconductance amplifier OTA1. Among them, the drain of NMOS transistor NM8 is connected to the source of NMOS transistor NM10 and the drain of PMOS transistor PM19. The gate of NMOS transistor NM8 is connected to the gates of NMOS transistors NM9, NM13, the source of NMOS transistor NM12, the gate of NMOS transistor NM14, and the drain of NMOS transistor NM14. The source of NMOS transistor NM8 is connected to the common terminal GND; the drain of NMOS transistor NM9 is connected to the source of NMOS transistor NM11 and the drain of PMOS transistor PM18. The gate of NMOS transistor NM9 is connected to the gates of NMOS transistors NM8, NM13, the source of NMOS transistor NM12, the gate of NMOS transistor NM14, and the drain of NMOS transistor NM14. The source of NMOS transistor NM9 is connected to the common terminal GND; the drain of NMOS transistor NM10 is connected to the drain of PMOS transistor PM8, the gates of PMOS transistors PM6 and PM7. The gate of NMOS transistor NM10 is connected to the gates of NMOS transistors NM11, NM12, and the drain of NMOS transistor NM12. The source of NMOS transistor NM10 is connected to the drain of NMOS transistor NM8 and the drain of PMOS transistor PM19; the drain of NMOS transistor NM11 is connected to the drain of PMOS transistor PM9 and the output terminal OUT1 of the operational transconductance amplifier OTA1. The gate of NMOS transistor NM11 is connected to the gates of NMOS transistors NM10, NM12, and the drain of NMOS transistor NM12. The source of NMOS transistor NM11 is connected to the drain of NMOS transistor NM9 and the drain of PMOS transistor PM18;The drain of NMOS transistor NM12 is connected to the gate of NMOS transistor NM12, the gate of NMOS transistor NM10, the drain of PMOS transistor PM11, and the gate of NMOS transistor NM11. The source of NMOS transistor NM12 is connected to the gate of NMOS transistor NM8, the gate of NMOS transistor NM13, the gate of NMOS transistor NM9, the gate of NMOS transistor NM14, and the drain of NMOS transistor NM14. The drain of NMOS transistor NM13 is connected to the gate of PMOS transistor PM15, the drain of PMOS transistor PM15, and the gate of PMOS transistor PM17. The gate of NMOS transistor NM13 is connected to the gate of NMOS transistor NM8, the source of NMOS transistor NM12, the gate of NMOS transistor NM9, the gate of NMOS transistor NM14, and the drain of NMOS transistor NM14. The source of NMOS transistor NM13 is connected to the common terminal GND. The drain of NMOS transistor NM14 is connected to the gate of NMOS transistor NM14, the gate of NMOS transistor NM8, the source of NMOS transistor NM12, the gate of NMOS transistor NM9, and the gate of NMOS transistor NM13. The source of NMOS transistor NM14 is connected to the common terminal GND. The drain of PMOS transistor PM6 is connected to the source of PMOS transistor PM8. The gate of PMOS transistor PM6 is connected to the drain of PMOS transistor PM8, the drain of NMOS transistor NM10, and the gate of PMOS transistor PM7. The source of PMOS transistor PM6 is connected to the power supply terminal VDD. The drain of PMOS transistor PM7 is connected to the source of PMOS transistor PM9. The gate of PMOS transistor PM7 is connected to the drain of PMOS transistor PM8, the drain of NMOS transistor NM10, and the gate of PMOS transistor PM6. The source of PMOS transistor PM7 is connected to the power supply terminal VDD. The drain of PMOS transistor PM8 is connected to the gate of PMOS transistor PM7, the drain of NMOS transistor NM10, and the gate of PMOS transistor PM6. The gate of PMOS transistor PM8 is connected to the gate of PMOS transistor PM9, the drain of PMOS transistor PM16, and the source of PMOS transistor PM17. The source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM6. The drain of PMOS transistor PM9 is connected to the drain of NMOS transistor NM11 and the gate of PMOS transistor PM6. The gate of PMOS transistor PM9 is connected to the gate of PMOS transistor PM8, the drain of PMOS transistor PM16, and the source of PMOS transistor PM17. The source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM6.The drain of PMOS transistor PM10 is connected to the source of PMOS transistor PM18 and the source of PMOS transistor PM19. The gate of PMOS transistor PM10 is connected to the gate of PMOS transistor PM11, the source of PMOS transistor PM13, the gate of PMOS transistor PM12, and the drain of PMOS transistor PM12. The source of PMOS transistor PM10 is connected to the power supply terminal VDD. The drain of PMOS transistor PM11 is connected to the gate of NMOS transistor NM12, the gate of NMOS transistor NM10, the drain of NMOS transistor NM12, and the gate of NMOS transistor NM11. The gate of PMOS transistor PM11 is connected to the gate of PMOS transistor PM10, the source of PMOS transistor PM13, the gate of PMOS transistor PM12, and the drain of PMOS transistor PM12. The source of PMOS transistor PM11 is connected to the power supply terminal VDD. The drain of PMOS transistor PM12 is connected to the gate of PMOS transistor PM12, the source of PMOS transistor PM13, the gate of PMOS transistor PM10, and the gate of PMOS transistor PM11. The source of PMOS transistor PM12 is connected to the power supply terminal VDD. The drain of PMOS transistor PM13 is connected to the gate of PMOS transistor PM13 and one end of resistor R11. The source of PMOS transistor PM13 is connected to the gate of PMOS transistor PM12, the drain of PMOS transistor PM12, the gate of PMOS transistor PM10, and the gate of PMOS transistor PM11. The drain of PMOS transistor PM14 is connected to the gate of PMOS transistor PM14, the source of PMOS transistor PM15, and the gate of PMOS transistor PM16. The source of PMOS transistor PM14 is connected to the power supply terminal VDD. The drain of PMOS transistor PM15 is connected to the gate of PMOS transistor PM15, the gate of PMOS transistor PM17, and the drain of NMOS transistor NM13. The source of PMOS transistor PM15 is connected to the gate of PMOS transistor PM14, the drain of PMOS transistor PM14, and the gate of PMOS transistor PM16. The drain of PMOS transistor PM16 is connected to the gate of PMOS transistor PM9, the gate of PMOS transistor PM8, and the source of PMOS transistor PM17. The gate of PMOS transistor PM16 is connected to the gate of PMOS transistor PM14, the source of PMOS transistor PM15, and the drain of PMOS transistor PM14. The source of PMOS transistor PM16 is connected to the power supply terminal VDD. The drain of PMOS transistor PM17 is connected to the common terminal GND. The gate of PMOS transistor PM17 is connected to the gate of PMOS transistor PM15, the drain of PMOS transistor PM15, and the drain of NMOS transistor NM13. The source of PMOS transistor PM17 is connected to the gate of PMOS transistor PM9, the gate of PMOS transistor PM8, and the drain of PMOS transistor PM16.The drain of PMOS transistor PM18 is connected to the drain of NMOS transistor NM9 and the source of NMOS transistor NM11. The gate of PMOS transistor PM18 is connected to the negative input terminal IN1- of operational transconductance amplifier OTA1. The source of PMOS transistor PM18 is connected to the drain of PMOS transistor PM10 and the source of PMOS transistor PM19. The drain of PMOS transistor PM19 is connected to the drain of NMOS transistor NM8 and the source of NMOS transistor NM10. The gate of PMOS transistor PM19 is connected to the positive input terminal IN1+ of operational transconductance amplifier OTA1. The source of PMOS transistor PM19 is connected to the drain of PMOS transistor PM10 and the source of PMOS transistor PM18. One end of resistor R11 is connected to the gate and the drain of PMOS transistor PM13, and the other end of resistor R11 is connected to the common terminal GND.;

[0029] Refer to Figure 3 The adaptive bias circuit 1 includes a voltage reference source circuit 2, a voltage reference source circuit 3, an operational transconductance amplifier OTA1, an NMOS transistor NM6, a resistor R3, a resistor R4, a resistor R5, a resistor R6, an input terminal Va1 of the induced signal AC voltage of the adaptive bias circuit 1, and an output terminal Vb1 of the bias voltage of the adaptive bias circuit 1, which are connected in parallel between the common terminal GND and the power supply terminal VDD. Among them, the gate of NMOS transistor NM6 is connected to the output terminal OUT1 of operational transconductance amplifier OTA1. The drain of NMOS transistor NM6 is connected to the power supply terminal VDD. The source of NMOS transistor NM6 is connected to one end of resistor R5 and the output terminal Vb1 of the bias voltage of the adaptive bias circuit 1. One end of resistor R5 is connected to the source of NMOS transistor NM6 and the output terminal Vb1 of the bias voltage of the adaptive bias circuit 1. The other end of resistor R5 is connected to one end of resistor R6 and the negative input terminal IN1- of operational transconductance amplifier OTA1. One end of resistor R6 is connected to the other end of resistor R5 and the negative input terminal IN1- of operational transconductance amplifier OTA1. The other end of resistor R6 is connected to the output terminal Vref3 of the reference voltage of voltage reference source circuit 3. One end of resistor R3 is connected to the positive input terminal IN1+ of operational transconductance amplifier OTA1 and one end of resistor R4. The other end of resistor R3 is connected to the output terminal Vref2 of the reference voltage of voltage reference source circuit 2. One end of resistor R4 is connected to the positive input terminal IN1+ of operational transconductance amplifier OTA1 and one end of resistor R3. The other end of resistor R4 is connected to the output terminal Vref1 of the reference voltage of voltage reference source circuit 1. The input terminal Va2 of the induced signal AC voltage of voltage reference source circuit 2 is connected to the input terminal Va1 of the induced signal AC voltage of the adaptive bias circuit 1.

[0030] For the adaptive bias circuit 1, the resistance values of R3 and R4 are equal, and the resistance values of R5 and R6 are equal. Through the feedback loop formed by operational transconductance amplifier OTA1, NMOS transistor NM6, and resistors R3, R4, R5, and R6, the following relationship exists among the bias voltage Vb1, the induced signal AC voltage Va1, the reference voltage Vref2, and the reference voltage Vref3: Vb1 = Va1 + Vref2 - Vref3.

[0031] The working mechanism of the adaptive bias circuit 1 is as follows: when the RF input signal is small, the bias voltage Vb1 is equivalent to the reference voltage Vref1 provided by the voltage reference source circuit 1; as the RF input signal gradually increases, the reference voltage Vref2 output by the reference source circuit 2 will increase accordingly, while the reference voltage Vref3 output by the reference source circuit 3 remains at the level before the increase of Vref2; by using an operational amplifier to achieve Vref2 - Vref3, a voltage positively correlated with the RF input signal can be obtained; when the RF input signal is at a low level, Vref2 - Vref3 = 0; finally, through an operational amplifier, (Vref2 - Vref3) is superimposed on the reference voltage Vref1 provided by the voltage reference source circuit 1.

[0032] Based on the above circuit structure, the working mechanism of the high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to the present invention is as follows: when the RF input signal is small, the bias voltage Vb1 provided by the adaptive bias circuit for the gate of the NMOS amplifier transistor NM1 of the power amplifier 1 is equal to the reference voltage Vref1, which can ensure that the NMOS amplifier transistor NM1 of the power amplifier maintains a relatively constant transconductance when the power supply voltage fluctuates, realizing a power amplifier with a relatively constant gain; when the RF input signal gradually increases, the bias voltage Vb1 provided by the adaptive bias circuit for the gate of the NMOS amplifier transistor NM1 of the power amplifier 1 will gradually increase, increasing the gate-source voltage and drain-source current of the NMOS amplifier transistor NM1, alleviating the gain compression of the power amplifier under a low-power bias voltage when the input power increases, and improving the 1dB compression point of the power amplifier.

[0033] Refer to Figure 7 . To verify the above mechanism, the present invention is compared with Figure 1 in terms of the bias voltage simulation of the power amplifier 1a. When the input RF signal gradually increases, the DC bias voltage Vb1 gradually increases, while the DC bias voltage Vb1a slightly decreases.

[0034] Refer to Figure 8 . To verify the improvement of the linearity performance of the present invention, the present invention is compared with Figure 1The medium-power amplifier 1a was subject to simulation comparison of gain compression. The gain Gain1 of the power amplifier 1a started to exhibit compression when the input RF signal was greater than -30 dBm. The input 1 dB compression point = -15 dBm, and the output 1 dB compression point = 5 dBm. For the RF amplifier 1 of the present invention, the gain Gain2 started to exhibit compression when the input RF signal was greater than -10 dBm. The input 1 dB compression point = -8 dBm, and the output 1 dB compression point = 12 dBm.

[0035] Refer to Figure 9 ... To verify the improvement of the power added efficiency by the present invention, the present invention was compared with Figure 1 the medium-power amplifier 1a in terms of power added efficiency through simulation. The power added efficiency PAE1 of the power amplifier 1a at its input 1 dB compression point (-15 dBm) was 11.6%. The power added efficiency PAE2 of the RF amplifier 1 of the present invention at its input 1 dB compression point (-8 dBm) was 22.1%. The power added efficiency PAE2 of the RF amplifier 1 of the present invention at the input power back-off to -15 dBm was 12.2%, which was still greater than the power added efficiency PAE1 (11.6%) of the power amplifier 1a at the same input power.

[0036] In summary, by using an adaptive bias circuit to provide a bias voltage for the power amplifier that dynamically adjusts with the input signal, it ensures that the power amplifier achieves a relatively constant gain under different supply voltages, alleviates the problem of gain compression in the power amplifier under a low-power bias voltage when the input power increases, and significantly improves the linearity and power added efficiency of the low-power power amplifier.

[0037] Various modifications to these embodiments will be apparent to those skilled in the art. The general principles defined by the present invention can be implemented in other embodiments without departing from the spirit or scope of the present invention. The scope of the present invention is not limited to the specific technical solutions described. Any technical solution obtained by making the same or equivalent substitutions for the technical elements in the described specific technical solutions or any technical solution that can be obtained by those skilled in the art without creative efforts based on the described specific technical solutions shall be considered as falling within the protection scope of the present invention.

Claims

1. A high efficiency and high linearity power amplifier with an adaptive bias circuit, characterized in that: It includes a voltage reference source circuit 1, an adaptive bias circuit 1 and a power amplifier 1 connected in parallel between a common terminal GND and a power terminal VDD; The reference voltage Vref1 output terminal of the voltage reference source circuit 1 is connected to the reference voltage Vref1 input terminal of the adaptive bias circuit 1; The bias voltage Vb1 output terminal of the adaptive bias circuit 1 is connected to the bias voltage Vb1 input terminal of the power amplifier 1; The induction signal AC voltage Va1 input terminal of the adaptive bias circuit 1 is connected to the induction signal AC voltage Va1 output terminal of the power amplifier 1 .

2. The voltage reference source circuit 1 according to claim 1, characterized in that: It includes an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a resistor R2, and a reference voltage Vref1 output end of a voltage reference source circuit 1; The gate of the PMOS tube PM1 is connected to the gate of the PMOS tube PM2, the drain of the PMOS tube PM2, the gate of the PMOS tube PM3, and the drain of the NMOS tube NM4; the drain of the PMOS tube PM1 is connected to the drain of the NMOS tube NM3 and the gate of the NMOS tube NM3; the source of the PMOS tube PM1 is connected to the power supply terminal VDD; The gate of the PMOS tube PM2 is connected to the drain of the PMOS tube PM2, the gate of the PMOS tube PM1, and the gate of the PMOS tube PM3, and the source of the PMOS tube PM2 is connected to the power supply terminal VDD; The gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM2, the drain of the PMOS tube PM2, and the gate of the PMOS tube PM1, the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM5, the gate of the NMOS tube NM5, and the reference voltage Vref1 output terminal of the voltage reference source circuit 1, and the source of the PMOS tube PM3 is connected to the power supply terminal VDD; The gate of the NMOS tube NM3 is connected to the drain of the NMOS tube NM3, the drain of the PMOS tube PM1, and the gate of the NMOS tube NM4, and the source of the NMOS tube NM3 is connected to the common terminal GND; The gate of the NMOS tube NM4 is connected to the drain of the NMOS tube NM3, the drain of the PMOS tube PM1, and the gate of the NMOS tube NM4; the gate of the PMOS tube PM2 is connected to the drain of the PMOS tube PM2, the gate of the PMOS tube PM1, and the gate of the PMOS tube PM3; the drain of the NMOS tube NM4 is connected to the gate of the PMOS tube PM2, the drain of the PMOS tube PM2, the gate of the PMOS tube PM3, and the gate of the PMOS tube PM1; the source of the NMOS tube NM4 is connected to one end of the resistor R2; One end of the resistor R2 is connected to the source of the NMOS tube NM4, and the other end of the resistor R2 is connected to the common terminal GND; The gate of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM5, the drain of the PMOS transistor PM3, and the reference voltage Vref1 output terminal of the voltage reference source circuit 1, and the source of the NMOS transistor NM5 is connected to the common terminal GND.

3. The power amplifier 1 according to claim 1, characterized in that: It includes an NMOS tube NM1, an NMOS tube NM2, an inductor L1, a capacitor C1, a capacitor C2, a capacitor C3, a resistor R1, a radio frequency signal input terminal RFin1, a radio frequency signal output terminal RFout1, a bias voltage Vb1 input terminal of a power amplifier, and an induction signal AC voltage Va1 output terminal of the power amplifier; The drain of the NMOS tube NM1 is connected to the source of the NMOS tube NM2, the gate of the NMOS tube NM1 is connected to one end of the resistor R1, one end of the capacitor C1, and one end of the capacitor C3, and the source of the NMOS tube NM1 is connected to the common terminal GND; The drain of the NMOS tube NM2 is connected to one end of the inductor L1 and one end of the capacitor C2, the gate of the NMOS tube NM1 is connected to the power supply terminal VDD, and the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM1; One end of the inductor L1 is connected to the drain of the NMOS tube NM2, and the other end of the inductor L1 is connected to the power supply terminal VDD; One end of the capacitor C2 is connected to the drain of the NMOS tube NM2 and one end of the inductor L1, and the other end of the capacitor C2 is connected to the RF signal output terminal RFout1 through the output stage matching network 1; One end of the capacitor C1 is connected to the gate of the NMOS transistor NM1, one end of the resistor R1, and one end of the capacitor C3, and the other end of the capacitor C1 is connected to the RF signal input terminal RFin1 through the input stage matching network 1; One end of the resistor R1 is connected to the gate of the NMOS transistor NM1, one end of the capacitor C1, and one end of the capacitor C3, and the other end of the resistor R1 is connected to the bias voltage Vb1 input end of the power amplifier; One end of the capacitor C3 is connected to the gate of the NMOS transistor NM1, one end of the capacitor C1, and one end of the resistor R1, and the other end of the capacitor C3 is connected to the output end of the induction signal AC voltage Va1 of the power amplifier.

4. The adaptive bias circuit 1 according to claim 1, characterized in that: It includes a voltage reference source circuit 2 connected in parallel between a common terminal GND and a power supply terminal VDD, a voltage reference source circuit 3, an operational transconductance amplifier OTA1, an NMOS tube NM6, a resistor R3, a resistor R4, a resistor R5, a resistor R6, an input terminal of an induced signal AC voltage Va1 of an adaptive bias circuit 1, and an output terminal of a bias voltage Vb1 of the adaptive bias circuit 1; The gate of the NMOS tube NM6 is connected to the output terminal OUT1 of the operational transconductance amplifier OTA1, the drain of the NMOS tube NM6 is connected to the power supply terminal VDD, and the source of the NMOS tube NM6 is connected to one end of the resistor R5 and the bias voltage Vb1 output terminal of the adaptive bias circuit 1; One end of the resistor R5 is connected to the source of the NMOS tube NM6 and the output end of the bias voltage Vb1 of the adaptive bias circuit 1, and the other end of the resistor R5 is connected to one end of the resistor R6 and the negative input end IN1- of the operational transconductance amplifier OTA1; One end of the resistor R6 is connected to the other end of the resistor R5 and the negative input terminal IN1- of the operational transconductance amplifier OTA1, and the other end of the resistor R6 is connected to the reference voltage Vref3 output terminal of the voltage reference source circuit 3; One end of the resistor R3 is connected to the positive input terminal IN1+ of the operational transconductance amplifier OTA1 and one end of the resistor R4, and the other end of the resistor R3 is connected to the reference voltage Vref2 output terminal of the voltage reference source circuit 2; One end of the resistor R4 is connected to the positive input terminal IN1+ of the operational transconductance amplifier OTA1 and one end of the resistor R3, and the other end of the resistor R4 is connected to the reference voltage Vref1 output terminal of the voltage reference source circuit 1; The induction signal AC voltage Va2 input terminal of the voltage reference source circuit 2 is connected to the induction signal AC voltage Va1 input terminal of the adaptive bias circuit 1 .

5. The voltage reference source circuit 2 according to claim 4, characterized in that: It includes a BJT tube Q1, a PMOS tube PM4, a resistor R7, a resistor R8, an input terminal of an induced signal AC voltage Va2 of a voltage reference source circuit 2, and an output terminal of a reference voltage Vref2 of the voltage reference source circuit 2; The collector of the BJT tube Q1 is connected to the base of the BJT tube Q1, the gate of the PMOS tube PM4, one end of the resistor R8, and the input end of the induced signal AC voltage Va2 of the voltage reference source circuit 2, and the emitter of the BJT tube Q1 is connected to the common end GND; The gate of the PMOS tube PM4 is connected to the base of the BJT tube Q1, the collector of the BJT tube Q1, one end of the resistor R8, and the input end of the induced signal AC voltage Va2 of the voltage reference source circuit 2, the source of the PMOS tube PM4 is connected to the power supply terminal VDD, and the drain of the PMOS tube PM4 is connected to one end of the resistor R7 and the output end of the reference voltage Vref2 of the voltage reference source circuit 2.

6. One end of the resistor R8 is connected to the base of the BJT tube Q1, the gate of the PMOS tube PM4, the collector of the BJT tube Q1, and the input end of the induced signal AC voltage Va2 of the voltage reference source circuit 2, and the other end of the resistor R8 is connected to the power supply terminal VDD; One end of the resistor R7 is connected to the drain of the PMOS transistor PM4 and the reference voltage Vref2 output end of the voltage reference source circuit 2 , and the other end of the resistor R7 is connected to the common end GND.

7. The voltage reference source circuit 3 according to claim 4, characterized in that: A reference voltage Vref3 output terminal 1 including a BJT tube Q2, a PMOS tube PM5, a resistor R9, a resistor R10, and a voltage reference source circuit 3; The collector of the BJT tube Q2 is connected to the base of the BJT tube Q2, the gate of the PMOS tube PM5, and one end of the resistor R10, and the emitter of the BJT tube Q2 is connected to the common terminal GND; The gate of the PMOS tube PM5 is connected to the base of the BJT tube Q2, the collector of the BJT tube Q2, and one end of the resistor R10, the source of the PMOS tube PM5 is connected to the power supply terminal VDD, and the drain of the PMOS tube PM5 is connected to one end of the resistor R9 and the reference voltage Vref3 output end of the voltage reference source circuit 3; One end of the resistor R10 is connected to the base of the BJT tube Q2, the gate of the PMOS tube PM5, and the collector of the BJT tube Q2, and the other end of the resistor R10 is connected to the power supply terminal VDD; One end of the resistor R9 is connected to the drain of the PMOS transistor PM5 and the output end of the reference voltage Vref3 of the voltage reference source circuit 3 , and the other end of the resistor R9 is connected to the common end GND.

8. The operational transconductance amplifier OTA1 according to claim 4, characterized in that: Including NMOS tube NM8, NMOS tube NM9, NMOS tube NM10, NMOS tube NM11, NMOS tube NM12, NMOS tube NM13, NMOS tube NM14, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, PMOS tube PM9, PMOS tube PM10, PMOS tube PM11, PMOS tube PM12, PMOS tube PM13, PMOS tube PM14, PMOS tube PM15, PMOS tube PM16, PMOS tube PM17, PMOS tube PM18, PMOS tube PM19, resistor R11, input positive terminal IN1+ of operational transconductance amplifier OTA1, input negative terminal IN1- of operational transconductance amplifier OTA1, and output terminal OUT1 of operational transconductance amplifier OTA1; The drain of the NMOS tube NM8 is connected to the source of the NMOS tube NM10 and the drain of the PMOS tube PM19, the gate of the NMOS tube NM8 is connected to the gate of the NMOS tube NM9, the gate of the NMOS tube NM13, the source of the NMOS tube NM12, the gate of the NMOS tube NM14, and the drain of the NMOS tube NM14, and the source of the NMOS tube NM8 is connected to the common terminal GND; The drain of the NMOS tube NM9 is connected to the source of the NMOS tube NM11 and the drain of the PMOS tube PM18, the gate of the NMOS tube NM9 is connected to the gate of the NMOS tube NM8, the gate of the NMOS tube NM13, the source of the NMOS tube NM12, the gate of the NMOS tube NM14, and the drain of the NMOS tube NM14, and the source of the NMOS tube NM9 is connected to the common terminal GND; The drain of the NMOS tube NM10 is connected to the drain of the PMOS tube PM8, the gate of the PMOS tube PM6, and the gate of the PMOS tube PM7; the gate of the NMOS tube NM10 is connected to the gate of the NMOS tube NM11, the gate of the NMOS tube NM12, and the drain of the NMOS tube NM12; the source of the NMOS tube NM10 is connected to the drain of the NMOS tube NM8 and the drain of the PMOS tube PM19; The drain of the NMOS tube NM11 is connected to the drain of the PMOS tube PM9 and the output terminal OUT1 of the operational transconductance amplifier OTA1, the gate of the NMOS tube NM11 is connected to the gate of the NMOS tube NM10, the gate of the NMOS tube NM12, and the drain of the NMOS tube NM12, and the source of the NMOS tube NM11 is connected to the drain of the NMOS tube NM9 and the drain of the PMOS tube PM18; The drain of the NMOS tube NM12 is connected to the gate of the NMOS tube NM12, the gate of the NMOS tube NM10, the drain of the PMOS tube PM11, and the gate of the NMOS tube NM11, and the source of the NMOS tube NM12 is connected to the gate of the NMOS tube NM8, the gate of the NMOS tube NM13, the gate of the NMOS tube NM9, the gate of the NMOS tube NM14, and the drain of the NMOS tube NM14; The drain of the NMOS tube NM13 is connected to the gate of the PMOS tube PM15, the drain of the PMOS tube PM15, and the gate of the PMOS tube PM17, the gate of the NMOS tube NM13 is connected to the gate of the NMOS tube NM8, the source of the NMOS tube NM12, the gate of the NMOS tube NM9, the gate of the NMOS tube NM14, and the drain of the NMOS tube NM14, and the source of the NMOS tube NM13 is connected to the common terminal GND; The drain of the NMOS tube NM14 is connected to the gate of the NMOS tube NM14, the gate of the NMOS tube NM8, the source of the NMOS tube NM12, the gate of the NMOS tube NM9, and the gate of the NMOS tube NM13, and the source of the NMOS tube NM14 is connected to the common terminal GND; The drain of the PMOS tube PM6 is connected to the source of the PMOS tube PM8, the gate of the PMOS tube PM6 is connected to the drain of the PMOS tube PM8, the drain of the NMOS tube NM10, and the gate of the PMOS tube PM7, and the source of the PMOS tube PM6 is connected to the power supply terminal VDD; The drain of the PMOS tube PM7 is connected to the source of the PMOS tube PM9, the gate of the PMOS tube PM7 is connected to the drain of the PMOS tube PM8, the drain of the NMOS tube NM10, and the gate of the PMOS tube PM6, and the source of the PMOS tube PM7 is connected to the power supply terminal VDD; The drain of the PMOS tube PM8 is connected to the gate of the PMOS tube PM7, the drain of the NMOS tube NM10, and the gate of the PMOS tube PM6; the gate of the PMOS tube PM8 is connected to the gate of the PMOS tube PM9, the drain of the PMOS tube PM16, and the source of the PMOS tube PM17; the source of the PMOS tube PM8 is connected to the drain of the PMOS tube PM6; The drain of the PMOS tube PM9 is connected to the drain of the NMOS tube NM11 and the gate of the PMOS tube PM6, the gate of the PMOS tube PM9 is connected to the gate of the PMOS tube PM8, the drain of the PMOS tube PM16, and the source of the PMOS tube PM17, and the source of the PMOS tube PM8 is connected to the drain of the PMOS tube PM6; The drain of the PMOS tube PM10 is connected to the source of the PMOS tube PM18 and the source of the PMOS tube PM19, the gate of the PMOS tube PM10 is connected to the gate of the PMOS tube PM11, the source of the PMOS tube PM13, the gate of the PMOS tube PM12, and the drain of the PMOS tube PM12, and the source of the PMOS tube PM10 is connected to the power supply terminal VDD; The drain of the PMOS tube PM11 is connected to the gate of the NMOS tube NM12, the gate of the NMOS tube NM10, the drain of the NMOS tube NM12, and the gate of the NMOS tube NM11; the gate of the PMOS tube PM11 is connected to the gate of the PMOS tube PM10, the source of the PMOS tube PM13, the gate of the PMOS tube PM12, and the drain of the PMOS tube PM12; the source of the PMOS tube PM11 is connected to the power supply terminal VDD; The drain of the PMOS tube PM12 is connected to the gate of the PMOS tube PM12, the source of the PMOS tube PM13, the gate of the PMOS tube PM10, and the gate of the PMOS tube PM11, and the source of the PMOS tube PM12 is connected to the power supply terminal VDD; The drain of the PMOS tube PM13 is connected to the gate of the PMOS tube PM13 and one end of the resistor R11, and the source of the PMOS tube PM13 is connected to the gate of the PMOS tube PM12, the drain of the PMOS tube PM12, the gate of the PMOS tube PM10, and the gate of the PMOS tube PM11; The drain of the PMOS tube PM14 is connected to the gate of the PMOS tube PM14, the source of the PMOS tube PM15, and the gate of the PMOS tube PM16, and the source of the PMOS tube PM14 is connected to the power supply terminal VDD; The drain of the PMOS tube PM15 is connected to the gate of the PMOS tube PM15, the gate of the PMOS tube PM17, and the drain of the NMOS tube NM13, and the source of the PMOS tube PM15 is connected to the gate of the PMOS tube PM14, the drain of the PMOS tube PM14, and the gate of the PMOS tube PM16; The drain of the PMOS tube PM16 is connected to the gate of the PMOS tube PM9, the gate of the PMOS tube PM8, and the source of the PMOS tube PM17, the gate of the PMOS tube PM16 is connected to the gate of the PMOS tube PM14, the source of the PMOS tube PM15, and the drain of the PMOS tube PM14, and the source of the PMOS tube PM16 is connected to the power supply terminal VDD; The drain of the PMOS tube PM17 is connected to the common terminal GND, the gate of the PMOS tube PM17 is connected to the gate of the PMOS tube PM15, the drain of the PMOS tube PM15, and the drain of the NMOS tube NM13, and the source of the PMOS tube PM17 is connected to the gate of the PMOS tube PM9, the gate of the PMOS tube PM8, and the drain of the PMOS tube PM16; The drain of the PMOS tube PM18 is connected to the drain of the NMOS tube NM9 and the source of the NMOS tube NM11, the gate of the PMOS tube PM18 is connected to the negative input terminal IN1- of the operational transconductance amplifier OTA1, and the source of the PMOS tube PM18 is connected to the drain of the PMOS tube PM10 and the source of the PMOS tube PM19; The drain of the PMOS tube PM19 is connected to the drain of the NMOS tube NM8 and the source of the NMOS tube NM10, the gate of the PMOS tube PM19 is connected to the positive input terminal IN1+ of the operational transconductance amplifier OTA1, and the source of the PMOS tube PM19 is connected to the drain of the PMOS tube PM10 and the source of the PMOS tube PM18; One end of the resistor R11 is connected to the gate of the PMOS transistor PM13 and the drain of the PMOS transistor PM13 , and the other end of the resistor R11 is connected to the common terminal GND.

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