Analog-to-digital conversion method and device, two-stage analog-to-digital converter and storage medium

Abstract

The invention provides an analog-to-digital conversion method and device, a two-stage analog-to-digital converter and a storage medium, and relates to the technical field of analog-to-digital conversion. The method comprises the following steps: sampling a first to-be-converted voltage signal based on a first-stage analog-to-digital converter, and controlling a lower pole plate of a low-level capacitor array in the first-stage analog-to-digital converter to keep a conversion code value of a previous period; converting the second to-be-converted voltage signal based on a first-stage analog-to-digital converter to obtain a first conversion code value, amplifying the converted voltage margin, transmitting the amplified voltage margin to an upper pole plate of a second capacitor array in a second-stage analog-to-digital converter, and controlling a lower pole plate of the second capacitor array to retain the conversion code value of the previous period in the sampling process; resetting a lower-stage plate of the second capacitor array to obtain a third to-be-converted voltage signal; and converting the third to-be-converted voltage signal based on a second-stage analog-to-digital converter to obtain a second conversion code value, and determining a converted digital signal based on the first conversion code value and the second conversion code value.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and particularly to an analog-to-digital conversion method, device, two-stage analog-to-digital converter, and storage medium. Background Art

[0002] In high-precision analog-to-digital converters, the pipelined successive approximation register (Pipelined-SAR) architecture is a very commonly used architecture, but its accuracy is often affected by capacitor mismatch and inter-stage gain error. To solve the mismatch problem of the capacitor array, an off-chip calibration method based on the least mean square (LMS) algorithm has been proposed in the prior art. However, this method requires additional off-chip processing, which will introduce additional cost for mass production. The on-chip solution mainly relies on dynamic element matching (DEM). A binary array is composed of exactly the same unit elements, and the mismatch error between each unit is scattered in a dynamic and random manner. In addition, there is also the mismatch error shaping (MES) technology. By retaining the digital code value obtained from the conversion in the previous cycle during sampling, the mismatch error in the reverse direction of the previous cycle is injected to form a first-order shaping of the mismatch error, thereby reducing the influence of the mismatch error.

[0003] In addition to the mismatch error, the gain error is also one of the bottlenecks that limit the accuracy of the pipelined architecture. To solve the problem of the gain error, an off-chip calibration method can also be used. The on-chip solution is a calibration method based on random dither injection. By injecting a known random dither, a signal component related to the random dither will be reflected in the output after amplification, and the actual inter-stage gain value can be obtained by using the autocorrelation algorithm.

[0004] However, the existing technologies only target one of the mismatch error and the gain error, and cannot eliminate both the mismatch error and the gain error simultaneously. Summary of the Invention

[0005] Embodiments of the present invention provide an analog-to-digital conversion method, device, two-stage analog-to-digital converter, and storage medium, so as to realize the collaborative processing of mismatch error and gain error in the analog-to-digital converter.

[0006] In a first aspect, an embodiment of the present invention provides an analog-to-digital conversion method, which is applied to a two-stage analog-to-digital converter. The two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. The method includes: sampling a first voltage signal to be converted based on the first-stage analog-to-digital converter, and during the sampling process, controlling the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle; resetting the lower plates of the first capacitor array in the first-stage analog-to-digital converter, and adding the low-order voltage signal corresponding to the previous cycle to the upper plates of the first capacitor array to obtain a second voltage signal to be converted; converting the second voltage signal to be converted based on the first-stage analog-to-digital converter to obtain a first conversion code value, and transmitting the converted voltage residue to the upper plates of the second capacitor array in the second-stage analog-to-digital converter after amplification. During the sampling process, controlling the lower plates of the second capacitor array to retain the conversion code value of the previous cycle; resetting the lower plates of the second capacitor array, and adding the voltage signal corresponding to the previous cycle to the upper plates of the second capacitor array to obtain a third voltage signal to be converted; converting the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and determining the converted digital signal based on the first conversion code value and the second conversion code value.

[0007] In some embodiments, the first capacitor array further includes a feedback capacitor; transferring the highest-bit conversion code value of the second analog-to-digital converter in the previous cycle to the lower plate of the feedback capacitor based on a latch; switching the feedback capacitor according to the high-bit conversion code value, and after all the first capacitor arrays are switched, obtaining the converted voltage residue.

[0008] As a possible implementation, controlling the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle includes: controlling the lower plates of the low-order capacitor array and the lower plates of the feedback capacitor to both retain their respective conversion code values of the previous cycle; wherein, adding the low-order voltage signal corresponding to the previous cycle to the upper plates of the first capacitor array to obtain a second voltage signal to be converted includes: adding the low-order voltage signal corresponding to the previous cycle and the voltage signal of the feedback capacitor in the previous cycle to the upper plates of the first capacitor array to obtain the second voltage signal to be converted.

[0009] In some embodiments, during the sampling process of the first voltage signal to be converted, it further includes: determining the polarity of the first voltage signal to be converted; switching the lower plates of the high-order capacitor array in the first-stage analog-to-digital converter based on the polarity of the first voltage signal to be converted.

[0010] As a possible implementation, switching the lower plates of the highest-order capacitor array in the first-stage analog-to-digital converter based on the polarity of the first voltage signal to be converted includes: if the first voltage signal to be converted is greater than 0, setting the lower plates of the highest-order capacitor array to 1; if the first voltage signal to be converted is less than 0, setting the lower plates of the highest-order capacitor array to -1.

[0011] In some embodiments, the first-stage analog-to-digital converter is connected to the second-stage analog-to-digital converter through an inter-stage integrator; during the process of receiving the amplified voltage margin by the upper plates of the second capacitor array, it further includes: controlling the upper plates of the second capacitor array to retain the voltage margin converted in the previous cycle.

[0012] In a second aspect, an embodiment of the present invention provides an analog-to-digital conversion device configured in a two-stage analog-to-digital converter, where the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter; the device includes: a sampling module, configured to sample a first voltage signal to be converted based on the first-stage analog-to-digital converter, and during the sampling process, control the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle; a first reset module, configured to reset the lower plates of the first capacitor array in the first-stage analog-to-digital converter, and add the corresponding low-order voltage signal of the previous cycle to the upper plates of the first capacitor array to obtain a second voltage signal to be converted; a first conversion module, configured to convert the second voltage signal to be converted based on the first-stage analog-to-digital converter to obtain a first conversion code value, and transmit the amplified voltage margin after conversion to the upper plates of the second capacitor array in the second-stage analog-to-digital converter, and control the lower plates of the second capacitor array to retain the conversion code value of the previous cycle during the sampling process; a second reset module, configured to reset the lower plates of the second capacitor array, and add the corresponding voltage signal of the previous cycle to the upper plates of the second capacitor array to obtain a third voltage signal to be converted; a second conversion module, configured to convert the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and determine the converted digital signal based on the first conversion code value and the second conversion code value.

[0013] In a third aspect, an embodiment of the present invention provides a two-stage analog-to-digital converter, including a processor and a memory storing a computer program, where when the processor executes the computer program, the analog-to-digital conversion method described in the first aspect above is implemented.

[0014] In a fourth aspect, an embodiment of the present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the analog-to-digital conversion method described in the first aspect above is implemented.

[0015] Fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, it implements the analog-to-digital conversion method described in the first aspect above.

[0016] The analog-to-digital conversion method, device, two-stage analog-to-digital converter and storage medium according to the embodiment of the present invention are applied to a second analog-to-digital converter. Based on the first-stage analog-to-digital converter sampling a first voltage signal to be converted, and during the sampling process, controlling the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle; resetting the lower plates of the first capacitor array in the first-stage analog-to-digital converter, and adding the corresponding low-order voltage signal of the previous cycle to the upper plates of the first capacitor array to obtain a second voltage signal to be converted; based on the first-stage analog-to-digital converter converting the second voltage signal to be converted to obtain a first conversion code value, and transmitting the converted voltage residue to the upper plates of the second capacitor array in the second-stage analog-to-digital converter after amplification, and controlling the lower plates of the second capacitor array to retain the conversion code value of the previous cycle during the sampling process; resetting the lower plates of the second capacitor array, and adding the corresponding voltage signal of the previous cycle to the upper plates of the second capacitor array to obtain a third voltage signal to be converted; based on the second-stage analog-to-digital converter converting the third voltage signal to be converted to obtain a second conversion code value, and determining the converted digital signal based on the first conversion code value and the second conversion code value. The present invention combines the gain error with the weight of the second capacitor array in the second-stage analog-to-digital converter, that is, treats the gain error as a mismatch error to eliminate it, realizes the simultaneous shaping of the mismatch error and the gain error, and improves the conversion accuracy of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is one of the flow diagrams of the analog-to-digital conversion method provided by the embodiment of the present invention; Figure 2 It is another flow diagram of the analog-to-digital conversion method provided by the embodiment of the present invention; Figure 3 It is a third flow diagram of the analog-to-digital conversion method provided by the embodiment of the present invention; Figure 4 It is a fourth flow diagram of the analog-to-digital conversion method provided by the embodiment of the present invention; Figure 5Schematic diagram of the two-stage analog-to-digital converter in the embodiment of the present invention; Figure 6 Schematic diagram of the structure of the analog-to-digital conversion device provided by the embodiment of the present invention; Figure 7 Schematic diagram of the structure of the two-stage analog-to-digital converter provided by the embodiment of the present invention. Detailed implementation manners

[0019] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] In high-precision analog-to-digital converters, the pipelined successive approximation register (Pipelined-SAR) architecture is a very commonly used architecture, but its accuracy is often affected by capacitor mismatch and inter-stage gain error. To solve the mismatch problem of the capacitor array, an off-chip calibration method based on the least mean square (LMS) algorithm has been proposed in the prior art. However, this method requires additional off-chip processing, which will introduce additional cost for large-scale mass production. The in-chip solution mainly relies on dynamic element matching (DEM). A binary array is composed of completely identical unit elements, and the mismatch error between each unit is scattered in a dynamic random manner. In addition, there is also the mismatch error shaping (MES) technology. By retaining the digital code value obtained in the previous cycle during sampling to inject the mismatch error in the reverse direction of the previous cycle, a first-order shaping of the mismatch error is formed, thereby reducing the influence of the mismatch error.

[0021] In addition to the mismatch error, the gain error is also one of the bottlenecks that limit the accuracy of the pipelined architecture. To solve the problem of the gain error, an off-chip calibration method can also be used. The in-chip solution is a calibration method based on random dither injection. By injecting a known random dither, a signal component related to the random dither will be reflected in the output after amplification. Then, the actual inter-stage gain value can be obtained by using the autocorrelation algorithm. In recent years, there has also been a proposal for gain error shaping technology, which reduces the requirement for the accuracy of the inter-stage gain by predicting or shaping the input of the inter-stage amplifier in advance.

[0022] The dynamic element matching for eliminating mismatch errors can well disperse the harmonics caused by mismatch. However, since units are required to form an array, as the number of bits of the array increases, the additional cost required by this technology will increase exponentially, resulting in area and power consumption losses.

[0023] In addition, the previously proposed mismatch error shaping technology can only be limited to a single-stage SAR (Successive Approximation Register) architecture and cannot be used in a multi-stage architecture. The inter-stage mismatch existing in a multi-stage pipelined architecture cannot be shaped or eliminated, resulting in accuracy loss.

[0024] Regarding the elimination of gain errors, the method of randomly injecting jitter can effectively perform background calibration of the gain. However, since it is an algorithm calibration based on autocorrelation, there is a certain convergence time, and additional digital circuits are required for digital arithmetic processing, bringing power consumption and area costs.

[0025] The existing gain error shaping means can effectively reduce the influence of gain errors, but there are certain accuracy requirements for the early prediction of the first-stage quantization margin. Therefore, it is necessary to additionally introduce a noise shaping ADC (Analog to Digital Converter) for coarse quantization; and the method of shaping the margin in advance requires multi-bit feedback. Restricted by the capacitor layout, it will instead bring truncation errors. At the same time, both of these methods will bring additional mismatch capacitor arrays that require off-chip calibration.

[0026] However, the existing technologies currently only target one of the mismatch errors or gain errors and cannot eliminate both mismatch errors and gain errors simultaneously.

[0027] To solve the above problems, embodiments of the present invention provide an analog-to-digital conversion method, device, two-stage analog-to-digital converter, and storage medium.

[0028] Figure 1 It is one of the flow diagrams of the analog-to-digital conversion method provided by embodiments of the present invention. The analog-to-digital conversion method of embodiments of the present invention is applied to a two-stage analog-to-digital converter, and the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. As Figure 1 shown, the method may include the following steps.

[0029] Step 101: Sample a first voltage signal to be converted based on the first-stage analog-to-digital converter, and during the sampling process, control the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle.

[0030] That is to say, the analog-to-digital conversion method of the embodiment of the present invention adopts the method of mismatch error shaping to solve the mismatch problem of the capacitor array. Therefore, in the current cycle sampling stage, the lower plates of the low-order capacitor arrays in the first-stage simulator retain the conversion code values of the previous cycle.

[0031] Among them, the first voltage signal to be converted refers to the input signal connected to the upper plate of the first-stage analog-to-digital converter.

[0032] Step 102: Reset the lower plates of the first capacitor array in the first-stage analog-to-digital converter, and add the low-order voltage signal corresponding to the previous cycle to the upper plates of the first capacitor array to obtain the second voltage signal to be converted.

[0033] In some embodiments, after sampling is completed, the sampling switch ports in the first-stage analog-to-digital converter reset the lower plates of all capacitors to return to the VCM common-mode voltage. Among them, the first capacitor array refers to all capacitors in the first-stage analog-to-digital converter. Since the lower plates of the low-order capacitor arrays retain the conversion code values of the previous cycle during the sampling stage, after reset, the low-order voltage signal converted in the previous cycle needs to be added back to the upper plates of the first capacitor array, which is equivalent to adding the mismatch error of the previous cycle back to the signal.

[0034] In some embodiments, the second voltage signal to be converted is the voltage signal received by the upper plates of the first capacitor array, that is, the voltage signal after adding the first voltage signal to be converted input during the sampling stage and the low-order voltage signal of the previous cycle. That is to say, in the reset stage, the expression of the voltage signal on the upper plates of the first capacitor array is as shown in the following formula (1).

[0035] (1); Among them, is the voltage signal on the upper plates of the first capacitor array in the reset stage; is the first voltage signal to be converted in the current cycle; is the low-order voltage signal of the previous cycle of the first-stage analog-to-digital converter.

[0036] Step 103: Based on the first-stage analog-to-digital converter, convert the second voltage signal to be converted to obtain the first conversion code value, and transmit the amplified voltage margin after conversion to the upper plates of the second capacitor array in the second-stage analog-to-digital converter, and control the lower plates of the second capacitor array to retain the conversion code values of the previous cycle during the sampling process.

[0037] In some embodiments, the second voltage signal to be converted is normally converted by the first-stage analog-to-digital converter to obtain a converted digital code value, i.e., the first conversion code value. That is to say, after conversion, the lower plate of the highest-order capacitor array in the first capacitor array is the highest-order conversion code value, and the lower plate of the lower-order capacitor array is the lower-order conversion code value. Based on the conversion code value, all capacitors are switched respectively, and the voltage signal converted in the current cycle is removed from the upper plate of the first capacitor array. At this time, the voltage signal on the upper plate of the first capacitor array is the converted voltage margin. Specifically, the voltage signal on the upper plate of the first capacitor array after conversion is shown in the following formula (2).

[0038] (2); Wherein, is the voltage signal converted in the current cycle by the first-stage analog-to-digital converter. Since the addition of is equivalent to adding the mismatch error of the previous cycle back to the signal, and also contains the mismatch error of the current cycle.

[0039] In addition, during the conversion process, the mismatch error introduced in the current cycle and the mismatch error of the previous cycle added back will form a first-order shaping to eliminate the mismatch error.

[0040] In some embodiments, the voltage margin can be amplified based on an amplifier, and the amplified voltage margin is transmitted to the upper plate of the second capacitor array in the second-stage analog-to-digital converter to enter the sampling stage of the second-stage analog-to-digital converter.

[0041] Since the second-stage analog-to-digital converter involves gain error and mismatch error, in order to simultaneously shape the mismatch error and gain error, the present invention combines the inter-stage gain with the weight of the second capacitor array, that is, regards the weight of the second capacitor array as and eliminates the gain error as a mismatch error.

[0042] In some embodiments, in the second-stage analog-to-digital converter, the mismatch error shaping method is adopted to simultaneously eliminate the gain error and mismatch error. In the sampling stage of the second-stage analog-to-digital converter, the sampling switch is closed to control all the lower plates of the capacitors to retain the code value converted in the previous cycle. Among them, the second capacitor array refers to all the capacitors in the second-stage analog-to-digital converter.

[0043] Step 104, reset the lower plate of the second capacitor array, and add the voltage signal corresponding to the previous cycle to the upper plate of the second capacitor array to obtain the third voltage signal to be converted.

[0044] In some embodiments, after sampling is completed, the sampling switch is disconnected, and the lower plates of all capacitors are reset to return to the VCM common-mode voltage. Therefore, the voltage signal corresponding to the previous cycle needs to be added back to the upper plates of the second capacitor array, thereby adding the mismatch error of the previous cycle of the second analog-to-digital converter back to the signal. Since all bits participate in the shaping operation in the second-stage analog-to-digital converter, the gain error is also added back to the signal as part of the mismatch error. In the reset stage, the voltage signal of the upper plates of the second capacitor array can be expressed by the following formula (3).

[0045] (3); Wherein, is the voltage signal of the upper plates of the second capacitor array; is the inter-stage gain; is the voltage margin transferred from the first-stage analog-to-digital converter to the second analog-to-digital converter in the current cycle; is the voltage signal converted by the second analog-to-digital converter in the previous cycle.

[0046] Wherein, the third voltage signal to be converted is the voltage signal of the upper plates of the second capacitor array after the reset is completed.

[0047] Step 105: Based on the second-stage analog-to-digital converter, convert the third voltage signal to be converted to obtain a second conversion code value, and determine the converted digital signal based on the first conversion code value and the second conversion code value.

[0048] In some embodiments, after the reset is completed, the second-stage analog-to-digital converter converts the third voltage signal to be converted to obtain a second conversion code value.

[0049] During the conversion process, the mismatch error and inter-stage error introduced in the current cycle will form a first-order shaping with the error signal added back from the previous cycle. When determining the finally converted digital signal, based on the first conversion code value and the second conversion code value, ideal weights and inter-stage gain can be used for splicing and restoration, and then the signal of the previous cycle that is additionally converted is compensated, so that the magnitude of the actual input voltage can be obtained, realizing the collaborative shaping of the gain error and the mismatch error.

[0050] According to the analog-to-digital conversion method of an embodiment of the present invention, a first analog voltage signal to be converted is sampled based on a first-stage analog-to-digital converter, and during the sampling process, the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter are controlled to retain the conversion code value of the previous cycle; the lower plates of the first capacitor array in the first-stage analog-to-digital converter are reset, and the low-order voltage signal corresponding to the previous cycle is added to the upper plates of the first capacitor array to obtain a second analog voltage signal to be converted; the second analog voltage signal to be converted is converted based on the first-stage analog-to-digital converter to obtain a first conversion code value, and the converted voltage residue is amplified and transmitted to the upper plates of the second capacitor array in the second-stage analog-to-digital converter. During the sampling process, the lower plates of the second capacitor array are controlled to retain the conversion code value of the previous cycle; the lower plates of the second capacitor array are reset, and the voltage signal corresponding to the previous cycle is added to the upper plates of the second capacitor array to obtain a third analog voltage signal to be converted; the third analog voltage signal to be converted is converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and the converted digital signal is determined based on the first conversion code value and the second conversion code value. The present invention combines the gain error with the weight of the second capacitor array in the second-stage analog-to-digital converter, that is, the gain error is also regarded as a mismatch error and eliminated, realizing the simultaneous shaping of the mismatch error and the gain error in the two-stage analog-to-digital converter, and improving the conversion accuracy of the analog-to-digital converter.

[0051] It can be understood that since the voltage signal converted in the previous cycle is added to the upper plates of the second capacitor array during the reset stage of each cycle, the second-stage analog-to-digital converter will be saturated. To solve this problem, another embodiment of the present invention is proposed.

[0052] Figure 2 It is a second flow diagram of the analog-to-digital conversion method provided by an embodiment of the present invention. In the embodiment of the present invention, a feedback capacitor is introduced into the first capacitor array of the first-stage analog-to-digital converter. That is, the first capacitor array of the first-stage analog-to-digital converter includes a highest-order capacitor array, a low-order capacitor array, and a feedback capacitor. The feedback capacitor is used to receive the highest-order conversion code value of the previous cycle of the second-stage analog-to-digital converter, thereby associating the first-stage analog-to-digital converter and the second-stage analog-to-digital converter to solve the saturation problem faced by the second-stage analog-to-digital converter. As Figure 2 shown, based on the above embodiment, after converting the second analog voltage to be converted based on the first-stage analog-to-digital converter, the following steps are further included.

[0053] Step 201, transferring the highest-order conversion code value of the previous cycle of the second analog-to-digital converter to the lower plate of the feedback capacitor based on a latch.

[0054] In some embodiments, after the most significant bit conversion code value is obtained by the second analog-to-digital converter in the previous cycle, the most significant bit conversion code value of the previous cycle is transmitted to a latch for storage. Based on the latch, after the first-stage analog-to-digital converter completes conversion in the current cycle, the most significant bit conversion code value of the second analog-to-digital converter in the previous cycle is passed to the lower plate of the feedback capacitor.

[0055] Step 202: Switch the feedback capacitor according to the high-order conversion code value. After all the first capacitor arrays are switched, the converted voltage margin is obtained.

[0056] In some embodiments, the feedback capacitor is switched based on the high-order conversion code value of the lower plate of the feedback capacitor. The high-order conversion code value of the lower plate of the feedback capacitor is multiplied by the weight of the feedback capacitor to obtain the voltage signal of the feedback capacitor in the current cycle, and this voltage signal is subtracted from the upper plate of the first capacitor array. At this stage, the relevant information of the second-stage mismatch is transmitted to the first stage to realize the association between the two stages. After subtracting the voltage signal of the feedback capacitor in the current cycle from the upper plate of the first capacitor array, the obtained voltage margin is greatly reduced, thereby solving the saturation problem faced by the second-stage analog-to-digital converter.

[0057] Since the feedback capacitor is introduced, the mismatch problem of the feedback capacitor also needs to be considered. The mismatch error shaping method is adopted in both stages of the analog-to-digital converter. Therefore, in the sampling stage of the first-stage analog-to-digital converter, it is necessary to control the lower plates of the low-order capacitor arrays and the lower plate of the feedback capacitor to retain their respective conversion code values of the previous cycle. Since after each cycle of conversion ends and enters the feedback stage, the feedback capacitor receives the most significant bit conversion code value of the previous cycle of the second-stage analog-to-digital converter, the conversion code value of the lower plate of the feedback capacitor retained in the sampling stage of the current cycle (n), which is the conversion code value of the previous cycle (n - 1), is equivalent to the most significant bit conversion code value of the previous cycle (n - 2) of the second-stage analog-to-digital converter.

[0058] Therefore, in the reset stage of the first-stage analog-to-digital converter in the current cycle, the lower plate of the feedback capacitor is also reset to the VCM common-mode voltage. In the process of adding the corresponding low-order voltage signal of the previous cycle to the upper plate of the first capacitor array to obtain the second voltage signal to be converted, the implementation process includes: adding the corresponding low-order voltage signal of the previous cycle and the voltage signal of the feedback capacitor in the previous cycle to the upper plate of the first capacitor array to obtain the second voltage signal to be converted. Adding the voltage signal of the feedback capacitor in the previous cycle to the upper plate of the first capacitor array is equivalent to adding the mismatch error of the feedback capacitor in the previous cycle back to the signal. After conversion, removing the voltage signal of the feedback capacitor in the current cycle from the signal is equivalent to eliminating the mismatch errors of all capacitors in the first-stage analog-to-digital converter in the obtained voltage margin.

[0059] Specifically, after introducing the feedback capacitor, in the reset stage, the voltage signal of the upper plate of the first capacitor array is as shown in the following formula (4). In the feedback stage, the voltage signal of the upper plate of the first capacitor array is as shown in the following formula (5).

[0060] (4); (5); Wherein, is the voltage signal of the feedback capacitor in the previous period; is the voltage signal of the feedback capacitor in the current period.

[0061] According to the analog-to-digital conversion method of the embodiment of the present invention, by introducing a feedback capacitor into the first capacitor array and based on the feedback capacitor receiving the highest-bit conversion code value of the second-stage analog-to-digital converter in the previous period, the saturation problem of the second analog-to-digital converter can be solved, and at the same time, the first-stage analog-to-digital converter and the second-stage analog-to-digital converter can be associated. That is to say, the present invention can shape all capacitor mismatch errors and inter-stage gain errors outside the effective bandwidth at the same time, so that the entire circuit architecture can achieve the target accuracy without additional calibration.

[0062] In the above embodiment, the actually converted voltage value of the first-stage analog-to-digital converter is the input voltage plus the voltage value corresponding to the lower bits in the previous period. Therefore, under extreme conditions, it may reach nearly 1.5 times the input swing, resulting in saturation of the two-stage analog-to-digital converter and thus impaired accuracy. To avoid input swing loss, the present invention provides another embodiment.

[0063] Figure 3 is the third schematic flow chart of the analog-to-digital conversion method provided by the embodiment of the present invention. As Figure 3 shown, based on the above embodiment, in the process of sampling the first voltage signal to be converted, the following steps are further included: Step 301, determine the polarity of the first voltage signal to be converted.

[0064] Step 302, based on the polarity of the first voltage signal to be converted, switch the lower plate of the highest-bit capacitor array in the first-stage analog-to-digital converter.

[0065] That is to say, in the process of sampling the input signal (the first voltage signal to be converted), the highest-bit conversion code value corresponding to the first voltage signal to be converted is predicted.

[0066] In some embodiments, the polarity of the first voltage signal to be converted refers to whether the first voltage signal to be converted is greater than 0 or less than 0. In this process, pre-comparison can be performed based on a comparator to obtain the approximate range of the first voltage signal to be converted and acquire the polarity of the first voltage signal to be converted.

[0067] In some embodiments, the implementation process of switching the lower plate of the highest-order capacitor array in the first-stage analog-to-digital converter based on the polarity of the first voltage signal to be converted may include: if the first voltage signal to be converted is greater than 0, setting the lower plate of the highest-order capacitor array to 1; if the first voltage signal to be converted is less than 0, setting the lower plate of the highest-order capacitor array to -1. That is to say, in the sampling stage, by predicting the highest-order conversion code value, a reverse fixed voltage value is compensated in advance to ensure that the signal is within the convertible range.

[0068] In the sampling stage, if the lower plate of the highest-order capacitor array is set to 1, it is equivalent to the voltage of the lower plate of the highest-order capacitor array being the reference voltage V ref ; if the lower plate of the highest-order capacitor array is set to -1, it is equivalent to the voltage of the lower plate of the highest-order capacitor array being the reference voltage -V ref . Therefore, in the reset stage, the voltage change value of the lower plate needs to be removed from the voltage signal of the upper plate. Specifically, if the lower plate of the highest-order capacitor array is set to 1 in the sampling stage, in the reset stage, the lower plate of the highest-order capacitor array is restored to the VCM common-mode voltage, so V ref / 2 needs to be subtracted from the voltage signal of the upper plate of the first capacitor array. If the lower plate of the highest-order capacitor array is set to -1 in the sampling stage, in the reset stage, -V ref / 2 needs to be added to the voltage signal of the upper plate of the first capacitor array.

[0069] According to the analog-to-digital conversion method of the embodiments of the present invention, in the sampling stage of the first-stage analog-to-digital converter, the polarity of the first voltage signal to be converted is determined; based on the polarity of the first voltage signal to be converted, the lower plate of the highest-order capacitor array in the first-stage analog-to-digital converter is switched to extract and compensate a reverse voltage to ensure that the signal of the first capacitor array is within the convertible range and avoid the problem of analog-to-digital converter saturation.

[0070] In some embodiments, the first-stage analog-to-digital converter is connected to the second-stage analog-to-digital converter through an inter-stage integrator; during the process of receiving the amplified voltage margin at the upper plate of the second capacitor array, it further includes: controlling the upper plate of the second capacitor array to retain the voltage margin after conversion in the previous cycle. By using an inter-stage integrator to connect the two-stage analog-to-digital converter, while retaining its own margin, the amplified margin information transmitted from the previous stage can be obtained, and noise shaping can be achieved to obtain higher quantization accuracy.

[0071] For the convenience of understanding the above embodiments, the analog-to-digital conversion processes of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter will be introduced below by means of the changes in the voltage signals of the upper and lower plates of the capacitor in different stages. Figure 5 It is the circuit diagram of the two-stage analog-to-digital converter involved in the embodiments of the present invention.

[0072] As Figure 4 shown, the first analog-to-digital converter and the second analog-to-digital converter operate in parallel. The execution of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter differs by one cycle. That is, when the current first analog-to-digital converter is in the nth cycle, the second analog-to-digital converter is in the (n - 1)th cycle. The working process of the first-stage analog-to-digital converter is as follows; (1) Sampling stage: Judge the polarity of the first voltage signal to be converted (input signal Vi(n)). For example, , set the lower plate of the most significant bit capacitor array (MSB1) to 1; the lower plates of the lower bit capacitor arrays retain the conversion code values of the previous cycle , and the lower plate of the feedback capacitor also retains the conversion code values of the previous cycle , that is, the most significant bit conversion code value of the second-stage analog-to-digital converter in the (n - 2)th cycle. The voltage signal of the upper plate of the first capacitor array ; (2) Reset stage: Reset the lower plates of all capacitors to return to the VCM common-mode voltage. In this stage, the voltage signal of the upper plate of the first capacitor array is . Among them, is the voltage signal of the feedback capacitor in the previous cycle; among them, , are added back to the signal, which is equivalent to introducing the reverse mismatch error of the previous cycle into the signal; (3) Conversion stage: Through voltage conversion, obtain the most significant bit conversion code value and the lower bit conversion code value . At this time, the voltage signal of the upper plate of the first capacitor array is . Among them, being removed is equivalent to the first-order shaping of the mismatch error of the lower bit capacitor array in the current cycle and the reverse mismatch error of the previous cycle; (4) Feedback stage: The feedback capacitor receives the most significant bit conversion code value of the second-stage analog-to-digital converter in the previous cycle, and switches the capacitor according to this code value. At this time, the voltage signal of the upper plate of the first capacitor array is . Among them, being removed is equivalent to the first-order shaping of the mismatch error of the feedback voltage in the current cycle and the reverse mismatch error of the previous cycle; In the inter-stage amplification stage, the voltage margin is amplified based on an inter-stage integrator and transmitted to the second-stage analog-to-digital converter for subsequent conversion.

[0073] For the current nth cycle, the second-stage analog-to-digital converter is performing the conversion work of the (n - 1)th cycle. The specific process is as follows: (1) Sampling stage: All lower levels of the second capacitor array retain the conversion code value of the previous cycle. At this time, the voltage signal on the upper plate of the second capacitor array is . Among them, is the voltage margin output by the second-stage analog-to-digital converter in the (n - 2)th cycle; (2) Reset stage: The lower levels of the second capacitor array are reset to the VCM common-mode voltage. At this time, the voltage signal on the upper plate of the second capacitor array is . Among them, is added back to the upper plate, introducing a reverse mismatch error; (3) Conversion stage: By performing voltage conversion, the most significant bit conversion code value and the least significant bit conversion code value are obtained, and is sent to the latch for storage. In the next cycle, after the first-stage analog-to-digital converter converts, it is transmitted to the lower plate of the feedback capacitor. In this stage, the voltage signal on the upper plate of the second capacitor array is . Among them, removal is equivalent to the first-order shaping of the mismatch error in the current cycle and the reverse mismatch error in the previous cycle.

[0074] To verify the effect of the analog-to-digital conversion method in the embodiment of the present invention, this method was verified by tape-out in a 55nm CMOS (Complementary Metal-Oxide-Semiconductor) process, realizing the design of a calibration-free high-precision ADC. At a power supply voltage of 1.2V and an operating frequency of 20MHz, the power consumption is 306.88uW, and the area is 0.0416mm 2, with a bandwidth of 156.25 kHz (64 times oversampling rate). This ADC does not require any calibration. The measured SNDR (Signal-to-Noise-and-Distortion Ratio) is 93.3 dB, and the SFDR (Spurious-Free Dynamic Range) is 112.8 dB. Without using this method, the SNDR and SFDR are attenuated to 76.4 dB and 80.6 dB respectively. By adjusting the reference voltage of the second stage to simulate the inter-stage gain change, it is measured that within the gain error range of -33% to +50%, the attenuation of the SNDR is less than 3 dB, which proves that this method has a very good shaping effect on the gain error. The final figure of merit FoMs of this ADC scheme is 180.4 dB, achieving the highest gain error tolerance range, as well as the highest precision and FoMs among all current gain error shaping schemes.

[0075] To implement the above embodiments, an analog-to-digital conversion device is further provided in an embodiment of the present invention.

[0076] Figure 6 It is a schematic structural diagram of the analog-to-digital conversion device provided in an embodiment of the present invention. This device is applied to a two-stage analog-to-digital converter, and the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. As Figure 6 shown, this device includes: a sampling module 610, a first reset module 620, a first conversion module 630, a second reset module 640, and a second conversion module 650.

[0077] In some embodiments, the sampling module 610 is configured to sample a first voltage signal to be converted based on a first-stage analog-to-digital converter. During the sampling process, the lower plates of the low-order capacitor array in the first-stage analog-to-digital converter are controlled to retain the conversion code values of the previous cycle. The first reset module 620 is configured to reset the lower plates of the first capacitor array in the first-stage analog-to-digital converter, and add the low-order voltage signal corresponding to the previous cycle to the upper plates of the first capacitor array to obtain a second voltage signal to be converted. The first conversion module 630 is configured to convert the second voltage signal to be converted based on the first-stage analog-to-digital converter to obtain a first conversion code value, and transmit the amplified voltage residue after conversion to the upper plates of the second capacitor array in the second-stage analog-to-digital converter. During the sampling process, the lower plates of the second capacitor array are controlled to retain the conversion code values of the previous cycle. The second reset module 640 is configured to reset the lower plates of the second capacitor array, and add the voltage signal corresponding to the previous cycle to the upper plates of the second capacitor array to obtain a third voltage signal to be converted. The second conversion module 650 is configured to convert the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and determine the converted digital signal based on the first conversion code value and the second conversion code value.

[0078] In some embodiments, the first capacitor array further includes a feedback capacitor. The first conversion module 630 is further configured to: after converting the second voltage signal to be converted, transfer the highest-bit conversion code value of the previous cycle of the second analog-to-digital converter to the lower plate of the feedback capacitor based on a latch; switch the feedback capacitor according to the high-bit conversion code value, and obtain the converted voltage residue after all the first capacitor arrays are switched.

[0079] In some embodiments, the sampling module 610 is further configured to: control the lower plates of the low-order capacitor array and the lower plates of the feedback capacitor to retain the conversion code values of their respective previous cycles. The first reset module 620 is further configured to: add the low-order voltage signal corresponding to the previous cycle and the voltage signal of the feedback capacitor in the previous cycle to the upper plates of the first capacitor array to obtain the second voltage signal to be converted.

[0080] In some embodiments, the sampling module 610 is further configured to: during the sampling process of the first voltage signal to be converted, determine the polarity of the first voltage signal to be converted; and switch the lower plates of the highest-bit capacitor array in the first-stage analog-to-digital converter based on the polarity of the first voltage signal to be converted.

[0081] As a possible implementation, the sampling module 610 is further configured to: if the first voltage signal to be converted is greater than 0, set the lower plate of the highest-order capacitor array to 1; if the first voltage signal to be converted is less than 0, set the lower plate of the highest-order capacitor array to -1.

[0082] In some embodiments, the first-stage analog-to-digital converter and the second-stage analog-to-digital converter are connected by an inter-stage integrator; the first conversion module 630 is further configured to: during the process of receiving the amplified voltage margin by the upper plate of the second capacitor array, control the upper plate of the second capacitor array to retain the voltage margin converted in the previous cycle.

[0083] It should be noted that the above explanations in the embodiments of the analog-to-digital conversion method can also be applied to the analog-to-digital conversion device of the embodiments of the present invention, and will not be repeated here.

[0084] Figure 7 FIG. shows a schematic structural diagram of an entity of a two-stage analog-to-digital converter. The two-stage analog-to-digital converter may include a first-stage analog-to-digital converter and a second-stage analog-to-digital converter, and its circuit is as Figure 5 shown. As Figure 7 shown, the two-stage analog-to-digital converter may include: a processor 710, a communication interface 720, a memory 730, and a communication bus 740. Among them, the processor 710, the communication interface 720, and the memory 730 complete mutual communication through the communication bus 740. The processor 710 may call a computer program in the memory 730 to execute the steps of the analog-to-digital conversion method.

[0085] For example, the method includes: sampling a first voltage signal to be converted based on a first-stage analog-to-digital converter, and during the sampling process, controlling the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle; resetting the lower plate of the first capacitor array in the first-stage analog-to-digital converter, and adding the corresponding low-order voltage signal of the previous cycle to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; converting the second voltage signal to be converted based on the first-stage analog-to-digital converter to obtain a first conversion code value, and transmitting the converted voltage margin to the upper plate of the second capacitor array in the second-stage analog-to-digital converter after amplification, and controlling the lower plate of the second capacitor array to retain the conversion code value of the previous cycle during the sampling process; resetting the lower plate of the second capacitor array, and adding the corresponding voltage signal of the previous cycle to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; converting the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and determining the converted digital signal based on the first conversion code value and the second conversion code value.

[0086] In addition, when the logical instructions in the above-mentioned memory 730 can be implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0087] On the other hand, an embodiment of the present invention also provides a computer program product. The computer program product includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the steps of the analog-to-digital conversion method provided in the above-mentioned various embodiments.

[0088] On the other hand, an embodiment of the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the analog-to-digital conversion method provided in the above-mentioned various embodiments are implemented.

[0089] The non-transitory computer-readable storage medium can be any available medium or data storage device accessible by the processor, including but not limited to magnetic memories (such as floppy disks, hard disks, magnetic tapes, magneto-optical discs (MO), etc.), optical memories (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor memories (such as ROM, EPROM, EEPROM, non-volatile memories (NANDFLASH), solid-state drives (SSD)).

[0090] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0091] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An analog-to-digital conversion method, characterized in that: Applied to a two-stage analog-to-digital converter, the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter; the method includes: Sampling the first voltage signal to be converted based on the first-stage analog-to-digital converter, and in the sampling process, controlling the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle; Resetting the lower plate of the first capacitor array in the first-stage analog-to-digital converter, and adding the low-order voltage signal corresponding to the previous cycle to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; Based on the first-stage analog-to-digital converter, the second voltage signal to be converted is converted to obtain a first conversion code value, and the converted voltage residual is amplified and transmitted to the upper plate of the second capacitor array in the second-stage analog-to-digital converter, and the lower plate of the second capacitor array is controlled to retain the conversion code value of the previous cycle during the sampling process; Resetting the lower plate of the second capacitor array, and adding the voltage signal corresponding to the previous cycle to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; The third voltage signal to be converted is converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and a converted digital signal is determined based on the first conversion code value and the second conversion code value.

2. The method according to claim 1, characterized in that The first capacitor array further includes a feedback capacitor; after converting the second voltage signal to be converted, the method further includes: Based on the latch, the highest bit conversion code value of the second analog-to-digital converter in the previous cycle is transferred to the lower plate of the feedback capacitor; The feedback capacitor is switched according to the high-order conversion code value, and after the first capacitor array is switched, the converted voltage margin is obtained.

3. The method according to claim 2, characterized in that The step of controlling the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle includes: Controlling the lower plate of the low-order capacitor array and the lower plate of the feedback capacitor to retain their respective conversion code values ​​of the previous cycle; The step of adding the low voltage signal corresponding to the previous cycle to the upper plate of the first capacitor array to obtain the second voltage signal to be converted includes: The low-order voltage signal corresponding to the previous cycle and the voltage signal of the feedback capacitor in the previous cycle are both added to the upper plate of the first capacitor array to obtain the second voltage signal to be converted.

4. The method according to claim 1, characterized in that: In the sampling process of the first voltage signal to be converted, the method further includes: Determining the polarity of the first voltage signal to be converted; Based on the polarity of the first voltage signal to be converted, the lower plate of the highest-order capacitor array in the first-stage analog-to-digital converter is switched.

5. The method according to claim 4, characterized in that The step of switching the lower plate of the highest-order capacitor array in the first-stage analog-to-digital converter based on the polarity of the first voltage signal to be converted includes: If the first voltage signal to be converted is greater than 0, the lower plate of the highest-order capacitor array is set to 1; If the first voltage signal to be converted is less than 0, the lower plate of the highest-order capacitor array is set to -1.

6. The method according to any one of claims 1 to 5, characterized in that The first-stage analog-to-digital converter and the second-stage analog-to-digital converter are connected via an interstage integrator; in the process of the upper plate of the second capacitor array receiving the amplified voltage margin, the method further includes: The upper plate of the second capacitor array is controlled to retain the voltage margin after the conversion of the previous cycle.

7. An analog-to-digital conversion device, characterized in that: Configured in a two-stage analog-to-digital converter, the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter; the device includes: A sampling module, used for sampling the first voltage signal to be converted based on the first-stage analog-to-digital converter, and in the sampling process, controlling the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle; A first reset module, used for resetting the lower plate of the first capacitor array in the first-stage analog-to-digital converter, and adding the low-bit voltage signal corresponding to the previous cycle to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; A first conversion module, configured to convert the second voltage signal to be converted based on the first-stage analog-to-digital converter to obtain a first conversion code value, and transmit the converted voltage margin to the upper plate of the second capacitor array in the second-stage analog-to-digital converter after amplification, and control the lower plate of the second capacitor array to retain the conversion code value of the previous cycle during the sampling process; A second reset module, used for resetting the lower plate of the second capacitor array, and adding the voltage signal corresponding to the previous cycle to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; The second conversion module is used to convert the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and determine the converted digital signal based on the first conversion code value and the second conversion code value.

8. A two-stage analog-to-digital converter, comprising a processor and a memory storing a computer program, characterized in that: When the processor executes the computer program, the analog-to-digital conversion method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the analog-to-digital conversion method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the analog-to-digital conversion method according to any one of claims 1 to 6 is implemented.

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