B time code efficient decoding system and method based on multi-frequency clock configuration

Abstract

The invention discloses a B time code efficient decoding system and method based on multi-frequency clock configuration, relates to the technical field of signal decoding, and is used for solving the problems of precision and stability of B time code decoding. According to the method, clock sources with different frequencies are identified and adapted, and a rising edge and a falling edge of a clock signal are detected by using global clock resources. By calculating the clock frequency, the duty ratio and the clock error, the input clock frequency is dynamically adjusted to ensure the stability of the clock. Characteristic data of stable and unstable clocks are determined, and the PLL is further adjusted to adapt to clock input signals of different frequencies. The method also preprocesses the B time code signal, and decodes the signal using a finite state machine. And finally, the time synchronization and the clock stability of the system are ensured by combining a time keeping circuit and a PPS dithering elimination circuit. The method has the advantages of high precision and high stability, and is suitable for a system needing high-precision clock synchronization.

Description

Technical Field

[0001] The present invention relates to the technical field of signal decoding, and more specifically, to an efficient B time code decoding system and method based on multi-frequency clock configuration. Background Art

[0002] In modern high-precision clock synchronization systems, B time code decoding is widely used in fields such as satellite navigation, communication, and precision measurement. With the continuous development of technology, the requirements for clock accuracy and stability are increasing day by day. Traditional clock decoding methods mainly target fixed-frequency clock signals. However, with the change of the system operating frequency, the prior art fails to effectively handle the adaptation of multi-frequency clock sources and the dynamic adjustment of clock errors. These methods often cannot guarantee accurate decoding in high-frequency or unstable frequency environments, resulting in error accumulation or synchronization failure, affecting the reliability and accuracy of the system.

[0003] In the prior art, although there are some methods to detect the clock frequency, most methods cannot comprehensively consider the frequency fluctuation, duty cycle change of the clock, and the dynamic error adjustment of the system.

[0004] In view of the above problems, the present invention proposes a solution. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art, embodiments of the present invention provide an efficient B time code decoding system and method based on multi-frequency clock configuration to solve the problems raised in the above background art.

[0006] To achieve the above object, the present invention provides the following technical solutions: In a preferred embodiment, it includes: Step 1: Identify and adapt clock sources of different frequencies, and classify them according to the clock frequency stability; Step 2: Preprocess the B time code signal according to the priority; Step 3: Maintain time accuracy and correct errors based on the FPGA timekeeping circuit; Step 4: Eliminate signal jitter based on the PPS debounce circuit of the FPGA.

[0007] In a preferred embodiment, in Step 1, receive the clock signal, generate a stable reference clock, and calculate the input clock frequency.

[0008] In a preferred embodiment, in step 1, the rising edge time, falling edge time and duty cycle deviation of the clock signal are detected; the rising and falling edge times and duty cycle deviation of the current clock frequency are weighted and summed to determine the clock error S of the current clock frequency. An error threshold Ys is set. If the clock error S of the current clock frequency is greater than or equal to the error threshold Ys, it indicates that the clock frequency belongs to an unstable clock frequency; if the clock error S of the current clock frequency is less than the error threshold Ys, it indicates that the clock frequency belongs to a stable clock frequency.

[0009] In a preferred embodiment, in step 1, the maximum allowable deviation threshold Eb between the clock frequency and the reference clock is defined; the time window width T1, that is, the stable time range required for B time code decoding, is defined, and the time error Es is set: the fluctuation amplitude Δf of the clock frequency and the standard deviation σ of the clock frequency are calculated; the clock frequency influence coefficient Ki is determined, and an influence threshold Yk is set. If the influence coefficient Ki is greater than or equal to the influence threshold Yk, the PLL expands the clock frequency adjustment amplitude; if the influence coefficient Ki is less than the influence threshold Yk, the PLL reduces the clock frequency adjustment amplitude.

[0010] In a preferred embodiment, in step 2, the matching degree between the B time code signal and the clock frequency and the envelope stability data are obtained, and the matching degree between the B time code signal and the clock frequency and the envelope stability data are weighted and summed to determine the priority P of the B time code signal. The B time code signals are processed from high to low according to the priority P of the B time code signal.

[0011] In a preferred embodiment, in step 2, the high-frequency noise of the B time code signal is removed; the key time information of the B time code signal is extracted; based on the threshold determination logic implemented by the FPGA, combined with the high-level duration and signal period obtained in step 1, a pulse high-level duration determination threshold is set; the B time code signal is decoded.

[0012] In a preferred embodiment, in step 3, the deviation between the decoded time and the clock is calculated. When the external time source is lost based on the FPGA, it automatically switches to the FPGA timekeeping circuit and maintains time synchronization; after the clock signal is restored, the decoded time is re-compared and the error is corrected.

[0013] In a preferred embodiment, in step 4, the PPS signal is obtained; the time deviation ΔTpps of consecutive PPS pulses is calculated, and a jitter deviation threshold Tp is set. When the time deviation ΔTpps is greater than or equal to the jitter deviation threshold Tp, stable time output is required.

[0014] In a preferred embodiment, it includes: a clock identification and adaptation module, a clock error calculation and adjustment module, a B time code signal preprocessing module, and a B time code decoding and correction module, with signal connections between the modules; The clock recognition and adaptation module is mainly used to recognize and adapt clock signals of different frequencies, generate a stable reference clock through the PLL inside the FPGA, and calculate the input clock frequency; The clock error calculation and adjustment module calculates the clock error and optimizes the clock frequency by dynamically adjusting the PLL configuration to ensure that the clock stability meets the decoding accuracy requirements; The B time code signal preprocessing module performs matching degree judgment and envelope stability analysis on the received B time code signal, and extracts key information through filtering and zero-crossing detection; The B time code decoding and correction module decodes the B time code using a finite state machine and corrects the decoding error through a timing circuit to ensure the time synchronization accuracy.

[0015] The present invention discloses an efficient B time code decoding system and method based on multi-frequency clock configuration, which relates to the technical field of signal decoding and is used to solve the problems of the accuracy and stability of B time code decoding; this method recognizes and adapts clock sources of different frequencies, and uses global clock resources to detect the rising and falling edges of clock signals. By calculating the clock frequency, duty cycle, and clock error, the input clock frequency is dynamically adjusted to ensure the clock stability. Determine the characteristic data of stable and unstable clocks, and further adjust the PLL to adapt to clock input signals of different frequencies. The method also preprocesses the B time code signal and decodes the signal using a finite state machine. Finally, combined with a timing circuit and a PPS debounce circuit to ensure the time synchronization and clock stability of the system. The present invention has the advantages of high precision and high stability, and is applicable to systems that require high-precision clock synchronization. Brief Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of the efficient B time code decoding system based on multi-frequency clock configuration of the present invention.

[0017] Figure 2 It is an operation flowchart of the efficient B time code decoding method based on multi-frequency clock configuration of the present invention. Detailed Embodiments

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. Embodiment

[0019] The present invention discloses an efficient B time code decoding method based on multi-frequency clock configuration, as Figure 2 shown, including: Step 1: Identify and adapt clock sources of different frequencies; Use the global clock pin GCLK as the external clock input port. If the clock signal is a single-ended signal LVCMOS, directly connect it to the GCLK pin; if the clock signal is a differential signal LVDS, use the IBUFDS differential input buffer to convert the differential signal into a single-ended signal and then connect it to the GCLK pin; After that, use the time window method to count the input clock cycles. The specific process is as follows: Generate a stable reference clock inside the FPGA through the internal PLL / MMCM of the FPGA. At the same time, create a counter inside the FPGA, count from 0 to 100000, and set a fixed time window T, which is determined by counting the 100MHz reference clock: T = 100000 clock cycles; Adopt a rising edge detection module. Within the time window T, when each rising edge of the input clock occurs, input the clock into the counter to detect the number of rising edges of the input clock signal and count the number of input clock pulses N; then, measure within the period T, and calculate the input clock frequency fin according to the number of input clock pulses N. The specific formula is: fin = N / T.

[0020] Store the identified clock frequency into the internal register of the FPGA.

[0021] After that, use a high-precision global clock counter based on the global clock resources of the FPGA to sample the input clock signal, use the double-edge trigger method to detect the rising edge time Trise and falling edge time Tfall of the clock signal respectively, and store the current count value as a timestamp; Calculate the period Tclk of the input clock signal: Tclk = Trise(i + 1) - Trise(i); Calculate the high-level time Thigh and low-level time Tlow: Thigh = Tfall(i) - Trise(i); Tlow = Trise(i + 1) - Tfall(i); Calculate the duty cycle D: D = (Thigh / Tclk) × 100%; Use K-means clustering to analyze the mean and standard deviation of the historical duty cycle data to determine the ideal duty cycle D1, and calculate the duty cycle deviation ΔD according to the ideal duty cycle and the current duty cycle: ΔD = |D - D1|; Determine the clock error S of the current clock frequency by weighted summing the rising and falling edge times and the duty cycle deviation of the current clock frequency. The specific formula is:

[0022] Among them, Qy represents the weight of the rising and falling edge times of the current clock frequency, Qz represents the weight of the current duty cycle deviation, Treise(i) represents the actual rising edge time of the input clock signal detected at the i-th sampling point, and Tideal-rise(i) represents the ideal rising edge time at the i-th sampling point; Set the error threshold Ys, and compare the clock error S of the current clock frequency with the stability score threshold Ys. If the clock error S of the current clock frequency is greater than or equal to the error threshold Ys, it indicates that the stability of this clock frequency is weak and it belongs to an unstable clock frequency; if the clock error S of the current clock frequency is less than the error threshold Ys, it indicates that the stability of this clock frequency is strong and it belongs to a stable clock frequency; Furthermore, clarify and quantify the accuracy requirements for B time code decoding: Step S1: Define the maximum allowable deviation threshold Eb between the input clock frequency and the reference clock frequency, and compare it with the maximum allowable deviation between the input clock frequency and the reference clock frequency during the decoding process: Eb = |fin - fre| ≤ Δfmax; Among them, fin represents the input clock frequency, fre represents the reference clock frequency, and Δfmax represents the maximum allowable deviation between the clock frequency and the reference; Step S2: Define the time window width T1, that is, the stable time range required for B time code decoding, and set the time error Es: Es = |Tw - Ts|; Among them, Tw represents the actual time window, and Ts represents the time synchronization accuracy required for B time code decoding.

[0023] Obtain the characteristic data of stable and unstable clock frequencies: Step S3: Calculate the fluctuation amplitude Δf of the clock frequency: Δf = max(fin) - min(fin); Step S4: Calculate the standard deviation σ of the clock frequency:

[0024] Among them, fi represents the clock frequency at each time point, μ represents the mean value of the clock frequency, and N represents the number of sampling points; Combine the accuracy requirements for B time code decoding with the characteristic data of stable and unstable clock frequencies to determine the influence coefficient: Ki = f(Eb, Es, S, Δf, σ), where f represents a comprehensive function; After that, use the influence coefficient Ki to adjust the configuration of the FPGA phase-locked loop (PLL) to dynamically adjust the input clock frequency. The specific steps are as follows: Step S5: Input the influence coefficient Ki into the PLL control module, set the influence threshold Yk. When the influence coefficient Ki is greater than or equal to the influence threshold Yk, the PLL will increase the clock frequency adjustment range; when the influence coefficient Ki is less than the influence threshold Yk, the PLL will decrease the clock frequency adjustment range; Finally, send a clock frequency adjustment completion signal to notify the B time code decoding module to use the new clock frequency parameters to adapt to the B time code signal with different clock frequencies.

[0025] Step 2: Preprocess the B time code signal; After receiving the B time code signal, determine the priority of the B time code signal according to the matching degree between the B time code and the clock frequency and the envelope stability of the B time code signal in Step 1. The specific process is as follows: Step B1: Obtain the matching degree data between the B time code and the clock frequency; Specifically, after receiving the B time code signal, according to the maximum allowable deviation threshold Eb between the clock frequency and the reference clock in Step 1, when the error threshold Eb is less than or equal to the maximum allowable deviation Δfmax, it indicates that the matching degree between the B time code and the clock frequency is high at this time; when the maximum allowable deviation threshold Eb between the clock frequency and the reference clock is greater than the maximum allowable deviation Δfmax, it indicates that the matching degree between the B time code and the clock frequency is low at this time; Step B2: Obtain the envelope stability data of the B time code signal; Specifically, perform Hilbert transform on the received B time code signal to obtain the analytical form of the B time code signal, and then calculate the envelope of the B time code signal; calculate the standard deviation Bb of the B time code signal envelope, which is recorded as the envelope stability data of the B time code signal; Step B3: Determine the priority P of the B time code signal by weighted summing the matching degree between the B time code and the clock frequency and the envelope stability data of the B time code signal. The specific basis is the formula:

[0026] where, w1 represents the weight of the matching degree between the B time code and the clock frequency, w2 represents the weight of the envelope stability of the B time code signal, and Bb(max) represents the maximum standard deviation of the envelope signal, which is used to normalize the envelope stability; Furthermore, process the B time code signals according to the priority P of the B time code signals from high to low; The specific processing process of the B time code signal is as follows: Use a second-order IIR filter to perform low-pass filtering on the B time code signal to remove high-frequency noise. The cut-off frequency is set to fc = 1.2×f baseband, where the baseband frequency is usually 1 kHz. The specific basis is the formula:

[0027] Adopt the zero-crossing detection circuit built in the FPGA, set the zero threshold. When the B time code signal is added or subtracted with the threshold and the result changes from negative to positive (or from positive to negative), record the time stamp and extract the key time information of the B time code signal; Next, perform normalization processing on the B time code signal to ensure that the signal amplitude range is fixed, which is convenient for FPGA processing; Since the symbol information of the B time code is distinguished by the high-level time, according to the threshold determination logic, combine the high-level duration and the signal period obtained in step 1 to set the pulse high-level duration determination threshold: Set the high-level time threshold range of symbol "1": T1,min ≤ Thigh ≤ T1,max; Set the high-level time threshold range of symbol "0": T0,min ≤ Thigh ≤ T0,max; Set the time threshold of the start code: Tstart,min ≤ Thigh ≤ Tstart,max; It should be noted that the threshold determination logic implemented based on the FPGA is as follows: After each measurement of Thigh, compare its value: If Thigh is within the range of symbol "1", store "1"; If Thigh falls within the range of symbol "0", store "0"; If Thigh falls within the range of the start code, store "start code"; If it exceeds all ranges, discard the data and trigger the error handling mechanism; After that, use a finite state machine (FSM) to decode the B time code signal, and the processing flow is as follows: IDLE state: Wait for the signal to enter the valid area; SYNC state: Detect the synchronization frame header; DECODE state: Parse 60-bit data and identify "0" / "1" according to the pulse width; CHECKSUM state: Calculate the CRC checksum, verify the data correctness, and if it passes, store it in the FPGA time register, otherwise discard it; Step 3: Maintain the time accuracy and correct the error based on the FPGA timing circuit; Calculate the deviation between the decoded time and the clock, specifically according to the formula: ΔT = Tdecoded - Tsystem; where, Tdecoded represents the system time obtained after decoding the B time code, and Tsystem represents the current FPGA internal system time.

[0028] Based on the FPGA, the stability of the external time source is judged, and the timekeeping switching logic is triggered. When the external time source is lost, it automatically switches to the FPGA timekeeping circuit, and a temperature-compensated crystal oscillator (TCXO) is used to maintain short-term time accuracy, provide a stable clock, and maintain time synchronization; After the GPS or OCXO clock signal is restored, the decoded time is compared again and the error is corrected; After that, the exponential moving average (EMA) algorithm is adopted to smoothly adjust the decoded time. Specifically, according to the formula: Tadj = α×Tnew + (1 - α)Told, where α represents the smoothing factor, Tnew represents the time value measured in the latest measurement, and Told represents the time value saved in the previous time.

[0029] Step 4: Eliminate signal jitter through the PPS debounce circuit based on the FPGA; Obtain the PPS signal through the dedicated PPS input port of the FPGA; Calculate the time deviation ΔTpps of consecutive multiple PPS pulses to judge whether there is a jitter phenomenon. Specifically, according to the formula: ΔTpps = Tpps(i) - Tpps(i - 1). Set the jitter deviation threshold Tp, and compare the time deviation ΔTpps with the jitter deviation threshold Tp. When the time deviation ΔTpps is greater than or equal to the jitter deviation threshold Tp, it indicates that there is a severe jitter phenomenon. At this time, after the input PPS signal is shaped by the buffer, the phase-locked loop (PLL) is used to track the phase of the PPS signal to stabilize the time output; and through time window filtering, the sudden deviation is eliminated; when the time deviation ΔTpps is less than the jitter deviation threshold Tp, it indicates that there is no severe jitter phenomenon.

[0030] The present invention also proposes an efficient decoding system for B time code based on multi-frequency clock configuration, as Figure 1 shown, including: a clock identification and adaptation module, a clock error calculation and adjustment module, a B time code signal preprocessing module, and a B time code decoding and correction module, with signal connections between the modules; The clock identification and adaptation module is mainly used to identify and adapt clock signals of different frequencies, generate a stable reference clock through the internal PLL of the FPGA, and calculate the input clock frequency; The clock error calculation and adjustment module calculates the clock error and optimizes the clock frequency by dynamically adjusting the PLL configuration to ensure that the clock stability meets the decoding accuracy requirements; The B time code signal preprocessing module performs matching degree judgment and envelope stability analysis on the received B time code signal, and extracts key information through filtering and zero-crossing detection; The B time code decoding and correction module decodes the B time code using a finite state machine and corrects the decoding error through a timekeeping circuit to ensure the time synchronization accuracy; The above formulas are all dimensionless and take their numerical values for calculation. The formulas are obtained by collecting a large amount of data for software simulation to get a formula closest to the actual situation. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0031] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product.

[0032] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application of the technical solution and the invention constraints. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0033] In addition, in each embodiment of this application, the functional modules can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module.

[0034] As described above, this is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0035] Finally: The above are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. Efficient decoding method of B time code based on multi-frequency clock configuration, It is characterized by; including: Step 1: Identify clock sources that are suitable for different frequencies and classify them according to clock frequency stability; Step 2: pre-process the B time code signal according to the priority level; Step 3: Maintain time accuracy and correct errors based on FPGA timing circuit; Step 4: FPGA-based PPS de-jitter circuit eliminates signal jitter.

2. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 1, characterized in that: In step 1, a clock signal is received, a stable reference clock is generated, and the input clock frequency is calculated.

3. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 2, characterized in that: In step 1, the rising edge time and the falling edge time and the duty cycle deviation of the clock signal are detected; The clock error S of the current clock frequency is determined by weighted summing of the rising and falling edge times and the duty cycle deviation of the current clock frequency, and an error threshold Ys is set. If the clock error S of the current clock frequency is greater than or equal to the error threshold Ys, it indicates that the clock frequency is an unstable clock frequency; if the clock error S of the current clock frequency is less than the error threshold Ys, it indicates that the clock frequency is a stable clock frequency.

4. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 3, characterized in that; In step 1, define the maximum allowable deviation threshold Eb between the clock frequency and the reference clock; define the time window width T1, that is, the stable time range required for B time code decoding, and set the time error Es: calculate the fluctuation amplitude Δf of the clock frequency and the standard deviation σ of the clock frequency; determine the clock frequency influence coefficient Ki, set the influence threshold Yk, if the influence coefficient Ki is greater than or equal to the influence threshold Yk, PLL increases the clock frequency adjustment amplitude; if the influence coefficient Ki is less than the influence threshold Yk, PLL reduces the clock frequency adjustment amplitude.

5. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 4 is characterized in that: In step 2, the matching degree and envelope stability data of the B time code signal and the clock frequency are obtained, and the priority P of the B time code signal is determined by weighted summation. The B time code signal is processed from high to low according to the priority P of the B time code signal.

6. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 5, characterized in that: In step 2, high-frequency noise of the B time code signal is removed; key time information of the B time code signal is extracted; based on the threshold judgment logic implemented by FPGA, the pulse high-level duration judgment threshold is set in combination with the high-level duration and signal period obtained in step 1; and the B time code signal is decoded.

7. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 6, characterized in that: In step 3, the deviation between the decoding time and the clock is calculated. When the external time source is lost based on the FPGA, it automatically switches to the FPGA timing circuit and maintains time synchronization; after the clock signal is restored, the decoding time is re-compared and the error is corrected.

8. The B time code efficient decoding method based on multi-frequency clock configuration according to claim 7, characterized in that; In step 4, a PPS signal is obtained; a time deviation ΔTpps of a plurality of consecutive PPS pulses is calculated, and a jitter deviation threshold Tp is set. When the time deviation ΔTpps is greater than or equal to the jitter deviation threshold Tp, a stable time output is required.

9. A B time code efficient decoding system based on a multi-frequency clock configuration, characterized in that: include: Clock identification and adaptation module, clock error calculation and adjustment module, B time code signal preprocessing module, B time code decoding and correction module, and signal connection between modules; The clock identification and adaptation module is mainly used to identify and adapt clock signals of different frequencies, generate a stable reference clock through the FPGA internal PLL, and calculate the input clock frequency; The clock error calculation and adjustment module calculates the clock error and optimizes the clock frequency by dynamically adjusting the PLL configuration to ensure that the clock stability meets the decoding accuracy requirements; The B time code signal preprocessing module performs matching judgment and envelope stability analysis on the received B time code signal, and extracts key information through filtering and zero-crossing detection; The B time code decoding and correction module uses a finite state machine to decode the B time code and corrects the decoding error through a timekeeping circuit to ensure time synchronization accuracy.

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